[FIXED] Reset issue in programming uart FSM.

verilog/gl/ghazi_top_dffram_csv.v

diff --git a/verilog/gl/ghazi_top_dffram_csv.v b/verilog/gl/ghazi_top_dffram_csv.v
index b793de5..d5392ed 100644
--- a/verilog/gl/ghazi_top_dffram_csv.v
+++ b/verilog/gl/ghazi_top_dffram_csv.v
Binary files differ

verilog/rtl/ghazi/iccm_controller.v

diff --git a/verilog/rtl/ghazi/iccm_controller.v b/verilog/rtl/ghazi/iccm_controller.v
index 41d95d4..e3c15b2 100644
--- a/verilog/rtl/ghazi/iccm_controller.v
+++ b/verilog/rtl/ghazi/iccm_controller.v
@@ -43,11 +43,14 @@
 		reset_d = reset_q;
 		ctrl_fsm_ns = ctrl_fsm_cs;
 		case (ctrl_fsm_cs)
-			RESET:
+			RESET: begin
+				we_d = 1'b0;
+				reset_d = 1'b0;
 				if (rx_dv_i)
 					ctrl_fsm_ns = LOAD;
 				else
 					ctrl_fsm_ns = RESET;
+			end
 			LOAD:
 				if (((byte_count == 2'b11) && (rx_byte_q2 != 8'h0f)) && (rx_byte_d != 8'hff)) begin
 					we_d = 1'b1;

verilog/rtl/ghazi/uart_rx_prog.v

diff --git a/verilog/rtl/ghazi/uart_rx_prog.v b/verilog/rtl/ghazi/uart_rx_prog.v
index b7ee5d1..1c8a8a2 100644
--- a/verilog/rtl/ghazi/uart_rx_prog.v
+++ b/verilog/rtl/ghazi/uart_rx_prog.v
@@ -36,10 +36,13 @@
    
    
   // Purpose: Control RX state machine
-  always @(posedge i_Clock)
+  always @(posedge i_Clock negedge rst_ni )
     begin
       if (!rst_ni) begin
         r_SM_Main <= s_IDLE;
+        r_Rx_DV       <= 1'b0;
+        r_Clock_Count <= 0;
+        r_Bit_Index   <= 0;
       end else begin       
       case (r_SM_Main)
         s_IDLE :