Removed unused power pins.

verilog/rtl/ghazi/ghazi_top_dffram_csv.v

diff --git a/verilog/rtl/ghazi/ghazi_top_dffram_csv.v b/verilog/rtl/ghazi/ghazi_top_dffram_csv.v
index 34be432..5c1130c 100644
--- a/verilog/rtl/ghazi/ghazi_top_dffram_csv.v
+++ b/verilog/rtl/ghazi/ghazi_top_dffram_csv.v
@@ -3,27 +3,13 @@
 
 module ghazi_top_dffram_csv (
 `ifdef USE_POWER_PINS
-    inout vdda1,	// User area 1 3.3V supply
-    inout vdda2,	// User area 2 3.3V supply
-    inout vssa1,	// User area 1 analog ground
-    inout vssa2,	// User area 2 analog ground
-    inout vccd1,	// User area 1 1.8V supply
-    inout vccd2,	// User area 2 1.8v supply
-    inout vssd1,	// User area 1 digital ground
-    inout vssd2,	// User area 2 digital ground
+    inout VPWR,	// User area 1 1.8V supply
+    inout VGND,	// User area 1 digital ground
 `endif
 
     // Wishbone Slave ports (WB MI A)
     input wb_clk_i,
     input wb_rst_i,
-    input wbs_stb_i,
-    input wbs_cyc_i,
-    input wbs_we_i,
-    input [3:0] wbs_sel_i,
-    input [31:0] wbs_dat_i,
-    input [31:0] wbs_adr_i,
-    output wbs_ack_o,
-    output [31:0] wbs_dat_o,
 
     // Logic Analyzer Signals
     input  [127:0] la_data_in,
@@ -155,8 +141,8 @@
 			ram_main_instr_rvalid <= ram_main_instr_req;
 	DFFRAM #(1) SRAMI(
 	`ifdef USE_POWER_PINS
-	        .VPWR(vccd1),
-	        .VGND(vssa1),
+	        .VPWR(VPWR),
+	        .VGND(VGND),
     	`endif
 		.CLK(wb_clk_i),
 		.WE(instr_WE),
@@ -176,8 +162,8 @@
 			ram_main_data_rvalid <= ram_main_data_req;
 	DFFRAM #(1) SRAMD(
 	`ifdef USE_POWER_PINS
-	        .VPWR(vccd1),
-	        .VGND(vssa1),
+	        .VPWR(VPWR),
+	        .VGND(VGND),
     	`endif
 		.CLK(wb_clk_i),
 		.WE(data_WE),

verilog/rtl/user_project_wrapper.v

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d26d18d..de74159 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -66,14 +66,8 @@
 
     ghazi_top_dffram_csv mprj (
     `ifdef USE_POWER_PINS
-	.vdda1(vdda1),	// User area 1 3.3V power
-	.vdda2(vdda2),	// User area 2 3.3V power
-	.vssa1(vssa1),	// User area 1 analog ground
-	.vssa2(vssa2),	// User area 2 analog ground
-	.vccd1(vccd1),	// User area 1 1.8V power
-	.vccd2(vccd2),	// User area 2 1.8V power
-	.vssd1(vssd1),	// User area 1 digital ground
-	.vssd2(vssd2),	// User area 2 digital ground
+	.VPWR(vccd1),	// User area 1 1.8V power
+	.VGND(vssd1),	// User area 1 digital ground
     `endif
 
 	// MGMT core clock and reset
@@ -81,17 +75,6 @@
     	.wb_clk_i(wb_clk_i),
     	.wb_rst_i(wb_rst_i),
 
-	// MGMT SoC Wishbone Slave
-
-	.wbs_cyc_i(wbs_cyc_i),
-	.wbs_stb_i(wbs_stb_i),
-	.wbs_we_i(wbs_we_i),
-	.wbs_sel_i(wbs_sel_i),
-	.wbs_adr_i(wbs_adr_i),
-	.wbs_dat_i(wbs_dat_i),
-	.wbs_ack_o(wbs_ack_o),
-	.wbs_dat_o(wbs_dat_o),
-
 	// Logic Analyzer
 
 	.la_data_in(la_data_in),