Merge tag 'mpw-one-b' of https://github.com/efabless/caravel
diff --git a/Makefile b/Makefile index fc74db5..845e638 100644 --- a/Makefile +++ b/Makefile
@@ -1,3 +1,5 @@ +<<<<<<< HEAD +======= # SPDX-FileCopyrightText: 2020 Efabless Corporation # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,14 +16,15 @@ # # SPDX-License-Identifier: Apache-2.0 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d # cannot commit files larger than 100 MB to GitHub FILE_SIZE_LIMIT_MB = 100 LARGE_FILES := $(shell find ./gds -type f -name "*.gds") LARGE_FILES += $(shell find . -type f -size +$(FILE_SIZE_LIMIT_MB)M -not -path "./.git/*" -not -path "./gds/*" -not -path "./openlane/*") -LARGE_FILES_GZ := $(addsuffix .gz, $(LARGE_FILES)) +LARGE_FILES_XZ := $(addsuffix .xz, $(LARGE_FILES)) -ARCHIVES := $(shell find . -type f -name "*.gz") +ARCHIVES := $(shell find . -type f -name "*.xz") ARCHIVE_SOURCES := $(basename $(ARCHIVES)) # PDK setup configs @@ -56,21 +59,21 @@ -$(LARGE_FILES_GZ): %.gz: % - @if ! [ $(suffix $<) == ".gz" ]; then\ - gzip -n --best $< > /dev/null &&\ +$(LARGE_FILES_XZ): %.xz: % + @if ! [ $(suffix $<) == ".xz" ]; then\ + xz -6 --threads=$(shell nproc) $< > /dev/null &&\ echo "$< -> $@";\ fi # This target compresses all files larger than $(FILE_SIZE_LIMIT_MB) MB .PHONY: compress -compress: $(LARGE_FILES_GZ) +compress: $(LARGE_FILES_XZ) @echo "Files larger than $(FILE_SIZE_LIMIT_MB) MBytes are compressed!" -$(ARCHIVE_SOURCES): %: %.gz - @gzip -d $< &&\ +$(ARCHIVE_SOURCES): %: %.xz + @xz --decompress $< &&\ echo "$< -> $@";\ .PHONY: uncompress @@ -99,13 +102,13 @@ mkdir -p ./spi/lvs/tmp sh ./spi/lvs/run_lvs.sh ./verilog/gl/$*.v ./spi/lvs/$*.spice $* mv -f ./spi/lvs/*{.out,.json,.log} ./spi/lvs/tmp 2> /dev/null || true - + .PHONY: help help: @$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$' - + ########################################################################### .PHONY: pdk pdk: skywater-pdk skywater-library open_pdks build-pdk
diff --git a/README.md b/README.md index 15727b1..89873d7 100644 --- a/README.md +++ b/README.md
@@ -1,3 +1,13 @@ +<<<<<<< HEAD +# Ghazi + +An SoC (System on a Chip) design for Google sponsored Open MPW shuttles for SKY130. + +<p align=”center”> +<img src="/doc/Ghazi-SoC.png" > +</p> + +======= <!--- # SPDX-FileCopyrightText: 2020 Efabless Corporation # @@ -15,6 +25,7 @@ # # SPDX-License-Identifier: Apache-2.0 --> +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d # CIIC Harness A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
diff --git a/def/ghazi_top_dffram_csv.def.xz b/def/ghazi_top_dffram_csv.def.xz new file mode 100644 index 0000000..bea359a --- /dev/null +++ b/def/ghazi_top_dffram_csv.def.xz Binary files differ
diff --git a/def/user_project_wrapper.def b/def/user_project_wrapper.def index e220776..2a63c0d 100644 --- a/def/user_project_wrapper.def +++ b/def/user_project_wrapper.def
@@ -2591,7 +2591,11 @@ TRACKS X 1700 DO 859 STEP 3400 LAYER met5 ; TRACKS Y 1700 DO 1035 STEP 3400 LAYER met5 ; +<<<<<<< HEAD +VIAS 4 ; +======= VIAS 7 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d - via2_FR + RECT met2 ( -140 -185 ) ( 140 185 ) + RECT via2 ( -100 -100 ) ( 100 100 ) @@ -2613,6 +2617,10 @@ + ENCLOSURE 1100 300 1100 310 + ROWCOL 2 1 ; +<<<<<<< HEAD +- via4_1600x3000 + +======= - via_3000x480 + VIARULE M1M2_PR @@ -2642,6 +2650,7 @@ ; - via4_1600x3000 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + VIARULE M4M5_PR + CUTSIZE 800 800 + LAYERS met4 via4 met5 @@ -2652,10 +2661,17 @@ END VIAS COMPONENTS 1 ; +<<<<<<< HEAD +- mprj ghazi_top_dffram_csv + FIXED ( 310000 260000 ) N ; +END COMPONENTS + +PINS 640 ; +======= - mprj user_proj_example + FIXED ( 1175000 1700000 ) N ; END COMPONENTS PINS 982 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d - analog_io[0] + NET analog_io[0] + DIRECTION INOUT + USE SIGNAL + LAYER met3 ( -3600 -600 ) ( 3600 600 ) + PLACED ( 2921200 29580 ) N ; @@ -4564,6 +4580,40 @@ - wbs_we_i + NET wbs_we_i + DIRECTION INPUT + USE SIGNAL + LAYER met2 ( -280 -3600 ) ( 280 3600 ) + PLACED ( 32430 -1200 ) N ; +<<<<<<< HEAD +- vccd1 + NET vccd1 + DIRECTION INPUT + USE SIGNAL + + LAYER met5 ( -1469790 -1500 ) ( 1469790 1500 ) + + FIXED ( 1459810 -3120 ) N + SPECIAL ; +- vssd1 + NET vssd1 + DIRECTION INPUT + USE SIGNAL + + LAYER met5 ( -1474590 -1500 ) ( 1474590 1500 ) + + FIXED ( 1459810 -7920 ) N + SPECIAL ; +- vccd2 + NET vccd2 + DIRECTION INPUT + USE SIGNAL + + LAYER met5 ( -1479390 -1500 ) ( 1479390 1500 ) + + FIXED ( 1459810 -12720 ) N + SPECIAL ; +- vssd2 + NET vssd2 + DIRECTION INPUT + USE SIGNAL + + LAYER met5 ( -1484190 -1500 ) ( 1484190 1500 ) + + FIXED ( 1459810 -17520 ) N + SPECIAL ; +END PINS + +SPECIALNETS 4 ; +- vccd1 ( PIN vccd1 ) + + ROUTED met4 0 + SHAPE STRIPE ( 331840 3070880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2890880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2710880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2530880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2350880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2170880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1990880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1810880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1630880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1450880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1270880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1090880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 910880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 730880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 550880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 370880 ) via4_1600x3000 +======= - vccd1 + NET vccd1 + DIRECTION INOUT + USE POWER + LAYER met4 ( -1500 -1769160 ) ( 1500 1769160 ) + FIXED ( 2885520 1759840 ) N + SPECIAL ; @@ -35504,6 +35554,7 @@ NEW met3 0 + SHAPE STRIPE ( 185520 10880 ) via3_3000x480 NEW met2 0 + SHAPE STRIPE ( 185520 10880 ) via2_3000x480 NEW met1 0 + SHAPE STRIPE ( 185520 10880 ) via_3000x480 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d NEW met4 0 + SHAPE STRIPE ( 2928100 3522800 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 2885520 3522800 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 2705520 3522800 ) via4_3000x3000 @@ -35523,6 +35574,167 @@ NEW met4 0 + SHAPE STRIPE ( 185520 3522800 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 5520 3522800 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( -8480 3522800 ) via4_3000x3000 +<<<<<<< HEAD + NEW met4 0 + SHAPE STRIPE ( 2928100 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2525520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2345520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2165520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1985520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1805520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1625520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1445520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1265520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1085520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 905520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 725520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 545520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 365520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 3430880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 3250880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 3250880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 3250880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 3250880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 3250880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 3250880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 3070880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 3070880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 3070880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 3070880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 3070880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 3070880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 2890880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 2890880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 2890880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 2890880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 2890880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 2890880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 2710880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 2710880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 2710880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 2710880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 2710880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 2710880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 2530880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 2530880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 2530880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 2530880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 2530880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 2530880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 2350880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 2350880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 2350880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 2350880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 2350880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 2350880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 2170880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 2170880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 2170880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 2170880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 2170880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 2170880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 1990880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 1990880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 1990880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 1990880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 1990880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 1990880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 1810880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 1810880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 1810880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 1810880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 1810880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 1810880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 1630880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 1630880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 1630880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 1630880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 1630880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 1630880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 1450880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 1450880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 1450880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 1450880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 1450880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 1450880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 1270880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 1270880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 1270880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 1270880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 1270880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 1270880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 1090880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 1090880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 1090880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 1090880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 1090880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 1090880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 910880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 910880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 910880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 910880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 910880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 910880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 730880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 730880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 730880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 730880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 730880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 730880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 550880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 550880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 550880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 550880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 550880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 550880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 370880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 370880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 370880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 370880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 370880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 370880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2525520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2345520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2165520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1985520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1805520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1625520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1445520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1265520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1085520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 905520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 725520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 545520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 365520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 190880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2928100 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2885520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2705520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2525520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2345520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2165520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1985520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1805520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1625520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1445520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1265520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1085520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 905520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 725520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 545520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 365520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 185520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 5520 10880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -8480 10880 ) via4_3000x3000 +======= NEW met4 0 + SHAPE STRIPE ( 2928100 3430640 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 2885520 3430640 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 2705520 3430640 ) via4_3000x3000 @@ -35894,6 +36106,7 @@ NEW met4 0 + SHAPE STRIPE ( 185520 10640 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 5520 10640 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( -8480 10640 ) via4_3000x3000 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d NEW met4 0 + SHAPE STRIPE ( 2928100 -3120 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 2885520 -3120 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( 2705520 -3120 ) via4_3000x3000 @@ -35914,6 +36127,831 @@ NEW met4 0 + SHAPE STRIPE ( 5520 -3120 ) via4_3000x3000 NEW met4 0 + SHAPE STRIPE ( -8480 -3120 ) via4_3000x3000 NEW met5 3000 + SHAPE STRIPE ( -9980 3522800 ) ( 2929600 3522800 ) +<<<<<<< HEAD + NEW met5 3000 + SHAPE STRIPE ( -14780 3430880 ) ( 2934400 3430880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 3250880 ) ( 2934400 3250880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 3070880 ) ( 2934400 3070880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2890880 ) ( 2934400 2890880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2710880 ) ( 2934400 2710880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2530880 ) ( 2934400 2530880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2350880 ) ( 2934400 2350880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2170880 ) ( 2934400 2170880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1990880 ) ( 2934400 1990880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1810880 ) ( 2934400 1810880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1630880 ) ( 2934400 1630880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1450880 ) ( 2934400 1450880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1270880 ) ( 2934400 1270880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1090880 ) ( 2934400 1090880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 910880 ) ( 2934400 910880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 730880 ) ( 2934400 730880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 550880 ) ( 2934400 550880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 370880 ) ( 2934400 370880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 190880 ) ( 2934400 190880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 10880 ) ( 2934400 10880 ) + NEW met5 3000 + SHAPE STRIPE ( -9980 -3120 ) ( 2929600 -3120 ) + NEW met4 3000 + SHAPE STRIPE ( 2885520 -9420 ) ( 2885520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2705520 -9420 ) ( 2705520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2525520 3260000 ) ( 2525520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2345520 3260000 ) ( 2345520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2165520 3260000 ) ( 2165520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1985520 3260000 ) ( 1985520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1805520 3260000 ) ( 1805520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1625520 3260000 ) ( 1625520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1445520 3260000 ) ( 1445520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1265520 3260000 ) ( 1265520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1085520 3260000 ) ( 1085520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 905520 3260000 ) ( 905520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 725520 3260000 ) ( 725520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 545520 3260000 ) ( 545520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 365520 3260000 ) ( 365520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 185520 -9420 ) ( 185520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 5520 -9420 ) ( 5520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2928100 -4620 ) ( 2928100 3524300 ) + NEW met4 3000 + SHAPE STRIPE ( -8480 -4620 ) ( -8480 3524300 ) + NEW met4 3000 + SHAPE STRIPE ( 2525520 -9420 ) ( 2525520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2345520 -9420 ) ( 2345520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2165520 -9420 ) ( 2165520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1985520 -9420 ) ( 1985520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1805520 -9420 ) ( 1805520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1625520 -9420 ) ( 1625520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1445520 -9420 ) ( 1445520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1265520 -9420 ) ( 1265520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1085520 -9420 ) ( 1085520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 905520 -9420 ) ( 905520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 725520 -9420 ) ( 725520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 545520 -9420 ) ( 545520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 365520 -9420 ) ( 365520 260000 ) + + USE POWER ; +- vssd1 ( PIN vssd1 ) + + ROUTED met4 0 + SHAPE STRIPE ( 408640 3160880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2980880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2800880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2620880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2440880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2260880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2080880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1900880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1720880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1540880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1360880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1180880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1000880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 820880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 640880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 460880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 280880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2435520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2255520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2075520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1895520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1715520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1535520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1355520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1175520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 995520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 815520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 635520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 455520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 3527600 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2435520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2255520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2075520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1895520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1715520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1535520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1355520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1175520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 995520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 815520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 635520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 455520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 3340880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 3160880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 3160880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 3160880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 3160880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 3160880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 3160880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 2980880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 2980880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 2980880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 2980880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 2980880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 2980880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 2800880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 2800880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 2800880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 2800880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 2800880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 2800880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 2620880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 2620880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 2620880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 2620880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 2620880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 2620880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 2440880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 2440880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 2440880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 2440880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 2440880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 2440880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 2260880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 2260880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 2260880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 2260880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 2260880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 2260880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 2080880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 2080880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 2080880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 2080880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 2080880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 2080880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 1900880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 1900880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 1900880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 1900880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 1900880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 1900880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 1720880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 1720880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 1720880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 1720880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 1720880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 1720880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 1540880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 1540880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 1540880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 1540880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 1540880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 1540880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 1360880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 1360880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 1360880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 1360880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 1360880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 1360880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 1180880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 1180880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 1180880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 1180880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 1180880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 1180880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 1000880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 1000880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 1000880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 1000880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 1000880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 1000880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 820880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 820880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 820880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 820880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 820880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 820880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 640880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 640880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 640880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 640880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 640880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 640880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 460880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 460880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 460880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 460880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 460880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 460880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 280880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 280880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 280880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 280880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 280880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 280880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2435520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2255520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2075520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1895520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1715520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1535520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1355520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1175520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 995520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 815520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 635520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 455520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 100880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2932900 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2795520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2615520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2435520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2255520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2075520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1895520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1715520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1535520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1355520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1175520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 995520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 815520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 635520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 455520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 275520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 95520 -7920 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -13280 -7920 ) via4_3000x3000 + NEW met5 3000 + SHAPE STRIPE ( -14780 3527600 ) ( 2934400 3527600 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 3340880 ) ( 2934400 3340880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 3160880 ) ( 2934400 3160880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2980880 ) ( 2934400 2980880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2800880 ) ( 2934400 2800880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2620880 ) ( 2934400 2620880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2440880 ) ( 2934400 2440880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2260880 ) ( 2934400 2260880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 2080880 ) ( 2934400 2080880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1900880 ) ( 2934400 1900880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1720880 ) ( 2934400 1720880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1540880 ) ( 2934400 1540880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1360880 ) ( 2934400 1360880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1180880 ) ( 2934400 1180880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 1000880 ) ( 2934400 1000880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 820880 ) ( 2934400 820880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 640880 ) ( 2934400 640880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 460880 ) ( 2934400 460880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 280880 ) ( 2934400 280880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 100880 ) ( 2934400 100880 ) + NEW met5 3000 + SHAPE STRIPE ( -14780 -7920 ) ( 2934400 -7920 ) + NEW met4 3000 + SHAPE STRIPE ( 2932900 -9420 ) ( 2932900 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2795520 -9420 ) ( 2795520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2615520 -9420 ) ( 2615520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2435520 3260000 ) ( 2435520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2255520 3260000 ) ( 2255520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2075520 3260000 ) ( 2075520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1895520 3260000 ) ( 1895520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1715520 3260000 ) ( 1715520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1535520 3260000 ) ( 1535520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1355520 3260000 ) ( 1355520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 1175520 3260000 ) ( 1175520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 995520 3260000 ) ( 995520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 815520 3260000 ) ( 815520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 635520 3260000 ) ( 635520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 455520 3260000 ) ( 455520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 275520 -9420 ) ( 275520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 95520 -9420 ) ( 95520 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( -13280 -9420 ) ( -13280 3529100 ) + NEW met4 3000 + SHAPE STRIPE ( 2435520 -9420 ) ( 2435520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2255520 -9420 ) ( 2255520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2075520 -9420 ) ( 2075520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1895520 -9420 ) ( 1895520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1715520 -9420 ) ( 1715520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1535520 -9420 ) ( 1535520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1355520 -9420 ) ( 1355520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1175520 -9420 ) ( 1175520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 995520 -9420 ) ( 995520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 815520 -9420 ) ( 815520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 635520 -9420 ) ( 635520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 455520 -9420 ) ( 455520 260000 ) + + USE GROUND ; +- vccd2 ( PIN vccd2 ) + + ROUTED met4 0 + SHAPE STRIPE ( 331840 3088880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2908880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2728880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2548880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2368880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2188880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 2008880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1828880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1648880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1468880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1288880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 1108880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 928880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 748880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 568880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 331840 388880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2543520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2363520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2183520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2003520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1823520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1643520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1463520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1283520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1103520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 923520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 743520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 563520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 383520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 3532400 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2543520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2363520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2183520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2003520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1823520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1643520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1463520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1283520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1103520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 923520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 743520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 563520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 383520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 3448880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2543520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2363520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2183520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2003520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1823520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1643520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1463520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1283520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1103520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 923520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 743520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 563520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 383520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 3268880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 3088880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 3088880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 3088880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 3088880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 3088880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 3088880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 2908880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 2908880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 2908880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 2908880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 2908880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 2908880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 2728880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 2728880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 2728880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 2728880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 2728880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 2728880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 2548880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 2548880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 2548880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 2548880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 2548880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 2548880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 2368880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 2368880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 2368880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 2368880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 2368880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 2368880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 2188880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 2188880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 2188880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 2188880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 2188880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 2188880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 2008880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 2008880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 2008880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 2008880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 2008880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 2008880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 1828880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 1828880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 1828880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 1828880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 1828880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 1828880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 1648880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 1648880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 1648880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 1648880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 1648880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 1648880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 1468880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 1468880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 1468880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 1468880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 1468880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 1468880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 1288880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 1288880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 1288880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 1288880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 1288880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 1288880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 1108880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 1108880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 1108880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 1108880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 1108880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 1108880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 928880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 928880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 928880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 928880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 928880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 928880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 748880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 748880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 748880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 748880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 748880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 748880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 568880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 568880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 568880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 568880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 568880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 568880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 388880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 388880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 388880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 388880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 388880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 388880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2543520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2363520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2183520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2003520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1823520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1643520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1463520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1283520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1103520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 923520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 743520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 563520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 383520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 208880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2543520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2363520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2183520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2003520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1823520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1643520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1463520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1283520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1103520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 923520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 743520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 563520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 383520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 28880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2937700 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2903520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2723520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2543520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2363520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2183520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2003520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1823520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1643520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1463520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1283520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1103520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 923520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 743520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 563520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 383520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 203520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 23520 -12720 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -18080 -12720 ) via4_3000x3000 + NEW met5 3000 + SHAPE STRIPE ( -19580 3532400 ) ( 2939200 3532400 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 3448880 ) ( 2944000 3448880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 3268880 ) ( 2944000 3268880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 3088880 ) ( 2944000 3088880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2908880 ) ( 2944000 2908880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2728880 ) ( 2944000 2728880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2548880 ) ( 2944000 2548880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2368880 ) ( 2944000 2368880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2188880 ) ( 2944000 2188880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2008880 ) ( 2944000 2008880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1828880 ) ( 2944000 1828880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1648880 ) ( 2944000 1648880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1468880 ) ( 2944000 1468880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1288880 ) ( 2944000 1288880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1108880 ) ( 2944000 1108880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 928880 ) ( 2944000 928880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 748880 ) ( 2944000 748880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 568880 ) ( 2944000 568880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 388880 ) ( 2944000 388880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 208880 ) ( 2944000 208880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 28880 ) ( 2944000 28880 ) + NEW met5 3000 + SHAPE STRIPE ( -19580 -12720 ) ( 2939200 -12720 ) + NEW met4 3000 + SHAPE STRIPE ( 2903520 -19020 ) ( 2903520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2723520 -19020 ) ( 2723520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2543520 3260000 ) ( 2543520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2363520 3260000 ) ( 2363520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2183520 3260000 ) ( 2183520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2003520 3260000 ) ( 2003520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1823520 3260000 ) ( 1823520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1643520 3260000 ) ( 1643520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1463520 3260000 ) ( 1463520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1283520 3260000 ) ( 1283520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1103520 3260000 ) ( 1103520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 923520 3260000 ) ( 923520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 743520 3260000 ) ( 743520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 563520 3260000 ) ( 563520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 383520 3260000 ) ( 383520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 203520 -19020 ) ( 203520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 23520 -19020 ) ( 23520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2937700 -14220 ) ( 2937700 3533900 ) + NEW met4 3000 + SHAPE STRIPE ( -18080 -14220 ) ( -18080 3533900 ) + NEW met4 3000 + SHAPE STRIPE ( 2543520 -19020 ) ( 2543520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2363520 -19020 ) ( 2363520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2183520 -19020 ) ( 2183520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2003520 -19020 ) ( 2003520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1823520 -19020 ) ( 1823520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1643520 -19020 ) ( 1643520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1463520 -19020 ) ( 1463520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1283520 -19020 ) ( 1283520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1103520 -19020 ) ( 1103520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 923520 -19020 ) ( 923520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 743520 -19020 ) ( 743520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 563520 -19020 ) ( 563520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 383520 -19020 ) ( 383520 260000 ) + + USE POWER ; +- vssd2 ( PIN vssd2 ) + + ROUTED met4 0 + SHAPE STRIPE ( 408640 3178880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2998880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2818880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2638880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2458880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2278880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 2098880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1918880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1738880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1558880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1378880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1198880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 1018880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 838880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 658880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 478880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 408640 298880 ) via4_1600x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2453520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2273520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2093520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1913520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1733520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1553520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1373520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1193520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1013520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 833520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 653520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 473520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 3537200 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2453520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2273520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2093520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1913520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1733520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1553520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1373520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1193520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1013520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 833520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 653520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 473520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 3358880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 3178880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 3178880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 3178880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 3178880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 3178880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 3178880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 2998880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 2998880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 2998880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 2998880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 2998880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 2998880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 2818880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 2818880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 2818880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 2818880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 2818880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 2818880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 2638880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 2638880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 2638880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 2638880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 2638880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 2638880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 2458880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 2458880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 2458880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 2458880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 2458880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 2458880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 2278880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 2278880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 2278880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 2278880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 2278880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 2278880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 2098880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 2098880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 2098880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 2098880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 2098880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 2098880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 1918880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 1918880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 1918880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 1918880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 1918880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 1918880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 1738880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 1738880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 1738880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 1738880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 1738880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 1738880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 1558880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 1558880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 1558880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 1558880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 1558880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 1558880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 1378880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 1378880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 1378880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 1378880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 1378880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 1378880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 1198880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 1198880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 1198880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 1198880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 1198880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 1198880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 1018880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 1018880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 1018880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 1018880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 1018880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 1018880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 838880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 838880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 838880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 838880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 838880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 838880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 658880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 658880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 658880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 658880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 658880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 658880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 478880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 478880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 478880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 478880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 478880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 478880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 298880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 298880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 298880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 298880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 298880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 298880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2453520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2273520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2093520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1913520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1733520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1553520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1373520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1193520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1013520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 833520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 653520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 473520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 118880 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2942500 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2813520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2633520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2453520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2273520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 2093520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1913520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1733520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1553520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1373520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1193520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 1013520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 833520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 653520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 473520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 293520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( 113520 -17520 ) via4_3000x3000 + NEW met4 0 + SHAPE STRIPE ( -22880 -17520 ) via4_3000x3000 + NEW met5 3000 + SHAPE STRIPE ( -24380 3537200 ) ( 2944000 3537200 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 3358880 ) ( 2944000 3358880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 3178880 ) ( 2944000 3178880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2998880 ) ( 2944000 2998880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2818880 ) ( 2944000 2818880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2638880 ) ( 2944000 2638880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2458880 ) ( 2944000 2458880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2278880 ) ( 2944000 2278880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 2098880 ) ( 2944000 2098880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1918880 ) ( 2944000 1918880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1738880 ) ( 2944000 1738880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1558880 ) ( 2944000 1558880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1378880 ) ( 2944000 1378880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1198880 ) ( 2944000 1198880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 1018880 ) ( 2944000 1018880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 838880 ) ( 2944000 838880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 658880 ) ( 2944000 658880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 478880 ) ( 2944000 478880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 298880 ) ( 2944000 298880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 118880 ) ( 2944000 118880 ) + NEW met5 3000 + SHAPE STRIPE ( -24380 -17520 ) ( 2944000 -17520 ) + NEW met4 3000 + SHAPE STRIPE ( 2942500 -19020 ) ( 2942500 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2813520 -19020 ) ( 2813520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2633520 -19020 ) ( 2633520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2453520 3260000 ) ( 2453520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2273520 3260000 ) ( 2273520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2093520 3260000 ) ( 2093520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1913520 3260000 ) ( 1913520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1733520 3260000 ) ( 1733520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1553520 3260000 ) ( 1553520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1373520 3260000 ) ( 1373520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1193520 3260000 ) ( 1193520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 1013520 3260000 ) ( 1013520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 833520 3260000 ) ( 833520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 653520 3260000 ) ( 653520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 473520 3260000 ) ( 473520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 293520 -19020 ) ( 293520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 113520 -19020 ) ( 113520 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( -22880 -19020 ) ( -22880 3538700 ) + NEW met4 3000 + SHAPE STRIPE ( 2453520 -19020 ) ( 2453520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2273520 -19020 ) ( 2273520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 2093520 -19020 ) ( 2093520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1913520 -19020 ) ( 1913520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1733520 -19020 ) ( 1733520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1553520 -19020 ) ( 1553520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1373520 -19020 ) ( 1373520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1193520 -19020 ) ( 1193520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 1013520 -19020 ) ( 1013520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 833520 -19020 ) ( 833520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 653520 -19020 ) ( 653520 260000 ) + NEW met4 3000 + SHAPE STRIPE ( 473520 -19020 ) ( 473520 260000 ) +======= NEW met5 3000 + SHAPE STRIPE ( -14680 3430640 ) ( 2934300 3430640 ) NEW met5 3000 + SHAPE STRIPE ( -14680 3250640 ) ( 2934300 3250640 ) NEW met5 3000 + SHAPE STRIPE ( -14680 3070640 ) ( 2934300 3070640 ) @@ -67391,6 +68429,7 @@ NEW met1 480 + SHAPE FOLLOWPIN ( 5520 24480 ) ( 2914100 24480 ) NEW met1 480 + SHAPE FOLLOWPIN ( 5520 19040 ) ( 2914100 19040 ) NEW met1 480 + SHAPE FOLLOWPIN ( 5520 13600 ) ( 2914100 13600 ) +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE GROUND ; - vccd2 ( PIN vccd2 ) + ROUTED met4 0 + SHAPE STRIPE ( 1660410 2188880 ) via4_1600x3000 @@ -70078,6 +71117,262 @@ - analog_io[9] ( PIN analog_io[9] ) + USE SIGNAL ; - io_in[0] ( PIN io_in[0] ) ( mprj io_in[0] ) +<<<<<<< HEAD + + ROUTED met3 ( 2609580 293420 0 ) ( 2619470 293420 ) + NEW met2 ( 2899150 88060 ) ( 2899150 89590 ) + NEW met3 ( 2899150 88060 ) ( 2917780 88060 0 ) + NEW met2 ( 2619470 89590 ) ( 2619470 293420 ) + NEW met1 ( 2619470 89590 ) ( 2899150 89590 ) + NEW met1 ( 2619470 89590 ) M1M2_PR + NEW met2 ( 2619470 293420 ) via2_FR + NEW met1 ( 2899150 89590 ) M1M2_PR + NEW met2 ( 2899150 88060 ) via2_FR ++ USE SIGNAL ; +- io_in[10] ( PIN io_in[10] ) ( mprj io_in[10] ) + + ROUTED met3 ( 2901450 2434060 ) ( 2917780 2434060 0 ) + NEW met3 ( 2609580 2293300 0 ) ( 2621770 2293300 ) + NEW met2 ( 2621770 2293300 ) ( 2621770 2297550 ) + NEW met2 ( 2901450 2297550 ) ( 2901450 2434060 ) + NEW met1 ( 2621770 2297550 ) ( 2901450 2297550 ) + NEW met2 ( 2901450 2434060 ) via2_FR + NEW met2 ( 2621770 2293300 ) via2_FR + NEW met1 ( 2621770 2297550 ) M1M2_PR + NEW met1 ( 2901450 2297550 ) M1M2_PR ++ USE SIGNAL ; +- io_in[11] ( PIN io_in[11] ) ( mprj io_in[11] ) + + ROUTED met3 ( 2609580 2493220 0 ) ( 2618550 2493220 ) + NEW met2 ( 2618550 2493220 ) ( 2618550 2497470 ) + NEW met3 ( 2901450 2669340 ) ( 2917780 2669340 0 ) + NEW met2 ( 2901450 2497470 ) ( 2901450 2669340 ) + NEW met1 ( 2618550 2497470 ) ( 2901450 2497470 ) + NEW met2 ( 2618550 2493220 ) via2_FR + NEW met1 ( 2618550 2497470 ) M1M2_PR + NEW met1 ( 2901450 2497470 ) M1M2_PR + NEW met2 ( 2901450 2669340 ) via2_FR ++ USE SIGNAL ; +- io_in[12] ( PIN io_in[12] ) ( mprj io_in[12] ) + + ROUTED met3 ( 2609580 2693140 0 ) ( 2618550 2693140 ) + NEW met2 ( 2618550 2693140 ) ( 2618550 2697730 ) + NEW met3 ( 2901450 2903940 ) ( 2917780 2903940 0 ) + NEW met2 ( 2901450 2697730 ) ( 2901450 2903940 ) + NEW met1 ( 2618550 2697730 ) ( 2901450 2697730 ) + NEW met2 ( 2618550 2693140 ) via2_FR + NEW met1 ( 2618550 2697730 ) M1M2_PR + NEW met1 ( 2901450 2697730 ) M1M2_PR + NEW met2 ( 2901450 2903940 ) via2_FR ++ USE SIGNAL ; +- io_in[13] ( PIN io_in[13] ) ( mprj io_in[13] ) + + ROUTED met3 ( 2609580 2893060 0 ) ( 2621770 2893060 ) + NEW met2 ( 2621770 2893060 ) ( 2621770 2897990 ) + NEW met3 ( 2901910 3138540 ) ( 2917780 3138540 0 ) + NEW met2 ( 2901910 2897990 ) ( 2901910 3138540 ) + NEW met1 ( 2621770 2897990 ) ( 2901910 2897990 ) + NEW met2 ( 2621770 2893060 ) via2_FR + NEW met1 ( 2621770 2897990 ) M1M2_PR + NEW met1 ( 2901910 2897990 ) M1M2_PR + NEW met2 ( 2901910 3138540 ) via2_FR ++ USE SIGNAL ; +- io_in[14] ( PIN io_in[14] ) ( mprj io_in[14] ) + + ROUTED met3 ( 2609580 3092980 0 ) ( 2621770 3092980 ) + NEW met2 ( 2621770 3092980 ) ( 2621770 3097910 ) + NEW met3 ( 2901450 3373140 ) ( 2917780 3373140 0 ) + NEW met2 ( 2901450 3097910 ) ( 2901450 3373140 ) + NEW met1 ( 2621770 3097910 ) ( 2901450 3097910 ) + NEW met2 ( 2621770 3092980 ) via2_FR + NEW met1 ( 2621770 3097910 ) M1M2_PR + NEW met1 ( 2901450 3097910 ) M1M2_PR + NEW met2 ( 2901450 3373140 ) via2_FR ++ USE SIGNAL ; +- io_in[15] ( PIN io_in[15] ) ( mprj io_in[15] ) + + ROUTED met2 ( 2798410 3502170 ) ( 2798410 3517980 0 ) + NEW met1 ( 2567030 3276410 ) ( 2573470 3276410 ) + NEW met1 ( 2573470 3502170 ) ( 2798410 3502170 ) + NEW met2 ( 2567030 3259580 0 ) ( 2567030 3276410 ) + NEW met2 ( 2573470 3276410 ) ( 2573470 3502170 ) + NEW met1 ( 2798410 3502170 ) M1M2_PR + NEW met1 ( 2567030 3276410 ) M1M2_PR + NEW met1 ( 2573470 3276410 ) M1M2_PR + NEW met1 ( 2573470 3502170 ) M1M2_PR ++ USE SIGNAL ; +- io_in[16] ( PIN io_in[16] ) ( mprj io_in[16] ) + + ROUTED met1 ( 2311730 3277430 ) ( 2318170 3277430 ) + NEW met2 ( 2311730 3259580 0 ) ( 2311730 3277430 ) + NEW met2 ( 2318170 3277430 ) ( 2318170 3502170 ) + NEW met1 ( 2318170 3502170 ) ( 2474110 3502170 ) + NEW met2 ( 2474110 3502170 ) ( 2474110 3517980 0 ) + NEW met1 ( 2311730 3277430 ) M1M2_PR + NEW met1 ( 2318170 3277430 ) M1M2_PR + NEW met1 ( 2318170 3502170 ) M1M2_PR + NEW met1 ( 2474110 3502170 ) M1M2_PR ++ USE SIGNAL ; +- io_in[17] ( PIN io_in[17] ) ( mprj io_in[17] ) + + ROUTED met2 ( 2055970 3259580 0 ) ( 2055970 3502170 ) + NEW met2 ( 2149350 3502170 ) ( 2149350 3517980 0 ) + NEW met1 ( 2055970 3502170 ) ( 2149350 3502170 ) + NEW met1 ( 2055970 3502170 ) M1M2_PR + NEW met1 ( 2149350 3502170 ) M1M2_PR ++ USE SIGNAL ; +- io_in[18] ( PIN io_in[18] ) ( mprj io_in[18] ) + + ROUTED met2 ( 1825050 3498430 ) ( 1825050 3517980 0 ) + NEW met1 ( 1800670 3498430 ) ( 1825050 3498430 ) + NEW met2 ( 1800670 3259580 0 ) ( 1800670 3498430 ) + NEW met1 ( 1825050 3498430 ) M1M2_PR + NEW met1 ( 1800670 3498430 ) M1M2_PR ++ USE SIGNAL ; +- io_in[19] ( PIN io_in[19] ) ( mprj io_in[19] ) + + ROUTED met2 ( 1544910 3259580 0 ) ( 1544910 3270630 ) + NEW met1 ( 1503970 3270630 ) ( 1544910 3270630 ) + NEW met1 ( 1500750 3498430 ) ( 1503970 3498430 ) + NEW met2 ( 1503970 3270630 ) ( 1503970 3498430 ) + NEW met2 ( 1500750 3498430 ) ( 1500750 3517980 0 ) + NEW met1 ( 1544910 3270630 ) M1M2_PR + NEW met1 ( 1503970 3270630 ) M1M2_PR + NEW met1 ( 1500750 3498430 ) M1M2_PR + NEW met1 ( 1503970 3498430 ) M1M2_PR ++ USE SIGNAL ; +- io_in[1] ( PIN io_in[1] ) ( mprj io_in[1] ) + + ROUTED met3 ( 2609580 493340 0 ) ( 2619470 493340 ) + NEW met2 ( 2899150 322660 ) ( 2899150 324190 ) + NEW met3 ( 2899150 322660 ) ( 2917780 322660 0 ) + NEW met2 ( 2619470 324190 ) ( 2619470 493340 ) + NEW met1 ( 2619470 324190 ) ( 2899150 324190 ) + NEW met1 ( 2619470 324190 ) M1M2_PR + NEW met2 ( 2619470 493340 ) via2_FR + NEW met1 ( 2899150 324190 ) M1M2_PR + NEW met2 ( 2899150 322660 ) via2_FR ++ USE SIGNAL ; +- io_in[20] ( PIN io_in[20] ) ( mprj io_in[20] ) + + ROUTED met1 ( 1175990 3498430 ) ( 1179670 3498430 ) + NEW met2 ( 1179670 3274030 ) ( 1179670 3498430 ) + NEW met2 ( 1175990 3498430 ) ( 1175990 3517980 0 ) + NEW met2 ( 1289610 3259580 0 ) ( 1289610 3274030 ) + NEW met1 ( 1179670 3274030 ) ( 1289610 3274030 ) + NEW met1 ( 1179670 3274030 ) M1M2_PR + NEW met1 ( 1175990 3498430 ) M1M2_PR + NEW met1 ( 1179670 3498430 ) M1M2_PR + NEW met1 ( 1289610 3274030 ) M1M2_PR ++ USE SIGNAL ; +- io_in[21] ( PIN io_in[21] ) ( mprj io_in[21] ) + + ROUTED met1 ( 851690 3501150 ) ( 855370 3501150 ) + NEW met1 ( 855370 3274370 ) ( 1033850 3274370 ) + NEW met2 ( 855370 3274370 ) ( 855370 3501150 ) + NEW met2 ( 851690 3501150 ) ( 851690 3517980 0 ) + NEW met2 ( 1033850 3259580 0 ) ( 1033850 3274370 ) + NEW met1 ( 855370 3274370 ) M1M2_PR + NEW met1 ( 851690 3501150 ) M1M2_PR + NEW met1 ( 855370 3501150 ) M1M2_PR + NEW met1 ( 1033850 3274370 ) M1M2_PR ++ USE SIGNAL ; +- io_in[22] ( PIN io_in[22] ) ( mprj io_in[22] ) + + ROUTED met2 ( 778090 3259580 0 ) ( 778090 3274370 ) + NEW met1 ( 527390 3498430 ) ( 531070 3498430 ) + NEW met1 ( 531070 3274370 ) ( 778090 3274370 ) + NEW met2 ( 531070 3274370 ) ( 531070 3498430 ) + NEW met2 ( 527390 3498430 ) ( 527390 3517980 0 ) + NEW met1 ( 778090 3274370 ) M1M2_PR + NEW met1 ( 531070 3274370 ) M1M2_PR + NEW met1 ( 527390 3498430 ) M1M2_PR + NEW met1 ( 531070 3498430 ) M1M2_PR ++ USE SIGNAL ; +- io_in[23] ( PIN io_in[23] ) ( mprj io_in[23] ) + + ROUTED met1 ( 202630 3501830 ) ( 206770 3501830 ) + NEW met2 ( 206770 3274370 ) ( 206770 3501830 ) + NEW met2 ( 202630 3501830 ) ( 202630 3517980 0 ) + NEW met2 ( 522790 3259580 0 ) ( 522790 3274370 ) + NEW met1 ( 206770 3274370 ) ( 522790 3274370 ) + NEW met1 ( 206770 3274370 ) M1M2_PR + NEW met1 ( 202630 3501830 ) M1M2_PR + NEW met1 ( 206770 3501830 ) M1M2_PR + NEW met1 ( 522790 3274370 ) M1M2_PR ++ USE SIGNAL ; +- io_in[24] ( PIN io_in[24] ) ( mprj io_in[24] ) + + ROUTED met2 ( 296930 3223540 ) ( 296930 3229150 ) + NEW met3 ( 296930 3223540 ) ( 310500 3223540 0 ) + NEW met1 ( 18170 3229150 ) ( 296930 3229150 ) + NEW met3 ( 2300 3411220 0 ) ( 18170 3411220 ) + NEW met2 ( 18170 3229150 ) ( 18170 3411220 ) + NEW met1 ( 18170 3229150 ) M1M2_PR + NEW met1 ( 296930 3229150 ) M1M2_PR + NEW met2 ( 296930 3223540 ) via2_FR + NEW met2 ( 18170 3411220 ) via2_FR ++ USE SIGNAL ; +- io_in[25] ( PIN io_in[25] ) ( mprj io_in[25] ) + + ROUTED met3 ( 2300 3124260 0 ) ( 18170 3124260 ) + NEW met2 ( 296930 3009340 ) ( 296930 3015290 ) + NEW met3 ( 296930 3009340 ) ( 310500 3009340 0 ) + NEW met2 ( 18170 3015290 ) ( 18170 3124260 ) + NEW met1 ( 18170 3015290 ) ( 296930 3015290 ) + NEW met1 ( 18170 3015290 ) M1M2_PR + NEW met2 ( 18170 3124260 ) via2_FR + NEW met1 ( 296930 3015290 ) M1M2_PR + NEW met2 ( 296930 3009340 ) via2_FR ++ USE SIGNAL ; +- io_in[26] ( PIN io_in[26] ) ( mprj io_in[26] ) + + ROUTED met2 ( 296930 2795140 ) ( 296930 2801090 ) + NEW met3 ( 296930 2795140 ) ( 310500 2795140 0 ) + NEW met3 ( 2300 2836620 0 ) ( 17250 2836620 ) + NEW met2 ( 17250 2801090 ) ( 17250 2836620 ) + NEW met1 ( 17250 2801090 ) ( 296930 2801090 ) + NEW met1 ( 17250 2801090 ) M1M2_PR + NEW met1 ( 296930 2801090 ) M1M2_PR + NEW met2 ( 296930 2795140 ) via2_FR + NEW met2 ( 17250 2836620 ) via2_FR ++ USE SIGNAL ; +- io_in[27] ( PIN io_in[27] ) ( mprj io_in[27] ) + + ROUTED met3 ( 2300 2549660 0 ) ( 17250 2549660 ) + NEW met2 ( 17250 2549660 ) ( 17250 2580770 ) + NEW met2 ( 296930 2580770 ) ( 296930 2580940 ) + NEW met3 ( 296930 2580940 ) ( 310500 2580940 0 ) + NEW met1 ( 17250 2580770 ) ( 296930 2580770 ) + NEW met2 ( 17250 2549660 ) via2_FR + NEW met1 ( 17250 2580770 ) M1M2_PR + NEW met1 ( 296930 2580770 ) M1M2_PR + NEW met2 ( 296930 2580940 ) via2_FR ++ USE SIGNAL ; +- io_in[28] ( PIN io_in[28] ) ( mprj io_in[28] ) + + ROUTED met3 ( 2300 2262020 0 ) ( 17250 2262020 ) + NEW met2 ( 17250 2262020 ) ( 17250 2366910 ) + NEW met2 ( 296930 2366740 ) ( 296930 2366910 ) + NEW met3 ( 296930 2366740 ) ( 310500 2366740 0 ) + NEW met1 ( 17250 2366910 ) ( 296930 2366910 ) + NEW met2 ( 17250 2262020 ) via2_FR + NEW met1 ( 17250 2366910 ) M1M2_PR + NEW met1 ( 296930 2366910 ) M1M2_PR + NEW met2 ( 296930 2366740 ) via2_FR ++ USE SIGNAL ; +- io_in[29] ( PIN io_in[29] ) ( mprj io_in[29] ) + + ROUTED met2 ( 296930 2145910 ) ( 296930 2152540 ) + NEW met3 ( 296930 2152540 ) ( 310500 2152540 0 ) + NEW met3 ( 2300 1975060 0 ) ( 17710 1975060 ) + NEW met2 ( 17710 1975060 ) ( 17710 2145910 ) + NEW met1 ( 17710 2145910 ) ( 296930 2145910 ) + NEW met1 ( 17710 2145910 ) M1M2_PR + NEW met1 ( 296930 2145910 ) M1M2_PR + NEW met2 ( 296930 2152540 ) via2_FR + NEW met2 ( 17710 1975060 ) via2_FR ++ USE SIGNAL ; +- io_in[2] ( PIN io_in[2] ) ( mprj io_in[2] ) + + ROUTED met3 ( 2609580 693260 0 ) ( 2619470 693260 ) + NEW met2 ( 2619470 558790 ) ( 2619470 693260 ) + NEW met2 ( 2899150 557260 ) ( 2899150 558790 ) + NEW met3 ( 2899150 557260 ) ( 2917780 557260 0 ) + NEW met1 ( 2619470 558790 ) ( 2899150 558790 ) + NEW met2 ( 2619470 693260 ) via2_FR + NEW met1 ( 2619470 558790 ) M1M2_PR + NEW met1 ( 2899150 558790 ) M1M2_PR + NEW met2 ( 2899150 557260 ) via2_FR ++ USE SIGNAL ; +- io_in[30] ( PIN io_in[30] ) ( mprj io_in[30] ) + + ROUTED met3 ( 300150 1938340 ) ( 310500 1938340 0 ) + NEW met3 ( 2300 1687420 0 ) ( 18170 1687420 ) + NEW met2 ( 18170 1687420 ) ( 18170 1690310 ) + NEW met2 ( 300150 1690310 ) ( 300150 1938340 ) + NEW met1 ( 18170 1690310 ) ( 300150 1690310 ) + NEW met2 ( 300150 1938340 ) via2_FR + NEW met2 ( 18170 1687420 ) via2_FR + NEW met1 ( 18170 1690310 ) M1M2_PR + NEW met1 ( 300150 1690310 ) M1M2_PR +======= + ROUTED met3 ( 2015260 83300 ) ( 2015260 84660 ) NEW met3 ( 2111860 83300 ) ( 2111860 84660 ) NEW met3 ( 2401660 83300 ) ( 2401660 86020 ) @@ -70824,10 +72119,108 @@ NEW met1 ( 14490 1690310 ) M1M2_PR NEW met1 ( 31510 1690310 ) M1M2_PR NEW met1 ( 1650250 2305370 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - io_in[31] ( PIN io_in[31] ) ( mprj io_in[31] ) + ROUTED met3 ( 2300 1471860 0 ) ( 15410 1471860 ) NEW met2 ( 15410 1471860 ) ( 15410 1476450 ) +<<<<<<< HEAD + NEW met3 ( 301070 1723460 ) ( 310500 1723460 0 ) + NEW met2 ( 301070 1476450 ) ( 301070 1723460 ) + NEW met1 ( 15410 1476450 ) ( 301070 1476450 ) + NEW met2 ( 15410 1471860 ) via2_FR + NEW met1 ( 15410 1476450 ) M1M2_PR + NEW met1 ( 301070 1476450 ) M1M2_PR + NEW met2 ( 301070 1723460 ) via2_FR ++ USE SIGNAL ; +- io_in[32] ( PIN io_in[32] ) ( mprj io_in[32] ) + + ROUTED met3 ( 2300 1256300 0 ) ( 15870 1256300 ) + NEW met2 ( 15870 1256300 ) ( 15870 1262590 ) + NEW met3 ( 300610 1509260 ) ( 310500 1509260 0 ) + NEW met2 ( 300610 1262590 ) ( 300610 1509260 ) + NEW met1 ( 15870 1262590 ) ( 300610 1262590 ) + NEW met2 ( 15870 1256300 ) via2_FR + NEW met1 ( 15870 1262590 ) M1M2_PR + NEW met1 ( 300610 1262590 ) M1M2_PR + NEW met2 ( 300610 1509260 ) via2_FR ++ USE SIGNAL ; +- io_in[33] ( PIN io_in[33] ) ( mprj io_in[33] ) + + ROUTED met3 ( 2300 1040740 0 ) ( 15870 1040740 ) + NEW met2 ( 15870 1040740 ) ( 15870 1041590 ) + NEW met3 ( 300150 1295060 ) ( 310500 1295060 0 ) + NEW met2 ( 300150 1041590 ) ( 300150 1295060 ) + NEW met1 ( 15870 1041590 ) ( 300150 1041590 ) + NEW met2 ( 15870 1040740 ) via2_FR + NEW met1 ( 15870 1041590 ) M1M2_PR + NEW met1 ( 300150 1041590 ) M1M2_PR + NEW met2 ( 300150 1295060 ) via2_FR ++ USE SIGNAL ; +- io_in[34] ( PIN io_in[34] ) ( mprj io_in[34] ) + + ROUTED met3 ( 300610 1080860 ) ( 310500 1080860 0 ) + NEW met3 ( 2300 825180 0 ) ( 17250 825180 ) + NEW met2 ( 17250 825180 ) ( 17250 827730 ) + NEW met2 ( 300610 827730 ) ( 300610 1080860 ) + NEW met1 ( 17250 827730 ) ( 300610 827730 ) + NEW met2 ( 300610 1080860 ) via2_FR + NEW met2 ( 17250 825180 ) via2_FR + NEW met1 ( 17250 827730 ) M1M2_PR + NEW met1 ( 300610 827730 ) M1M2_PR ++ USE SIGNAL ; +- io_in[35] ( PIN io_in[35] ) ( mprj io_in[35] ) + + ROUTED met3 ( 2300 610300 0 ) ( 14950 610300 ) + NEW met2 ( 14950 610300 ) ( 14950 613870 ) + NEW met3 ( 300150 866660 ) ( 310500 866660 0 ) + NEW met2 ( 300150 613870 ) ( 300150 866660 ) + NEW met1 ( 14950 613870 ) ( 300150 613870 ) + NEW met2 ( 14950 610300 ) via2_FR + NEW met1 ( 14950 613870 ) M1M2_PR + NEW met1 ( 300150 613870 ) M1M2_PR + NEW met2 ( 300150 866660 ) via2_FR ++ USE SIGNAL ; +- io_in[36] ( PIN io_in[36] ) ( mprj io_in[36] ) + + ROUTED met3 ( 2300 394740 0 ) ( 15410 394740 ) + NEW met2 ( 15410 394740 ) ( 15410 400010 ) + NEW met3 ( 300610 652460 ) ( 310500 652460 0 ) + NEW met2 ( 300610 400010 ) ( 300610 652460 ) + NEW met1 ( 15410 400010 ) ( 300610 400010 ) + NEW met2 ( 15410 394740 ) via2_FR + NEW met1 ( 15410 400010 ) M1M2_PR + NEW met1 ( 300610 400010 ) M1M2_PR + NEW met2 ( 300610 652460 ) via2_FR ++ USE SIGNAL ; +- io_in[37] ( PIN io_in[37] ) ( mprj io_in[37] ) + + ROUTED met3 ( 2300 179180 0 ) ( 16790 179180 ) + NEW met2 ( 16790 179180 ) ( 16790 179350 ) + NEW met3 ( 300150 438260 ) ( 310500 438260 0 ) + NEW met2 ( 300150 179350 ) ( 300150 438260 ) + NEW met1 ( 16790 179350 ) ( 300150 179350 ) + NEW met2 ( 16790 179180 ) via2_FR + NEW met1 ( 16790 179350 ) M1M2_PR + NEW met1 ( 300150 179350 ) M1M2_PR + NEW met2 ( 300150 438260 ) via2_FR ++ USE SIGNAL ; +- io_in[3] ( PIN io_in[3] ) ( mprj io_in[3] ) + + ROUTED met3 ( 2609580 893180 0 ) ( 2619470 893180 ) + NEW met2 ( 2899150 791860 ) ( 2899150 793390 ) + NEW met3 ( 2899150 791860 ) ( 2917780 791860 0 ) + NEW met2 ( 2619470 793390 ) ( 2619470 893180 ) + NEW met1 ( 2619470 793390 ) ( 2899150 793390 ) + NEW met1 ( 2619470 793390 ) M1M2_PR + NEW met2 ( 2619470 893180 ) via2_FR + NEW met1 ( 2899150 793390 ) M1M2_PR + NEW met2 ( 2899150 791860 ) via2_FR ++ USE SIGNAL ; +- io_in[4] ( PIN io_in[4] ) ( mprj io_in[4] ) + + ROUTED met3 ( 2609580 1093100 0 ) ( 2619470 1093100 ) + NEW met2 ( 2619470 1027990 ) ( 2619470 1093100 ) + NEW met2 ( 2899150 1026460 ) ( 2899150 1027990 ) + NEW met3 ( 2899150 1026460 ) ( 2917780 1026460 0 ) + NEW met1 ( 2619470 1027990 ) ( 2899150 1027990 ) + NEW met2 ( 2619470 1093100 ) via2_FR + NEW met1 ( 2619470 1027990 ) M1M2_PR + NEW met1 ( 2899150 1027990 ) M1M2_PR + NEW met2 ( 2899150 1026460 ) via2_FR +======= NEW met2 ( 1163110 1476450 ) ( 1163110 2300610 ) NEW met2 ( 1665890 2299420 0 ) ( 1665890 2300610 ) NEW met1 ( 15410 1476450 ) ( 1163110 1476450 ) @@ -71126,10 +72519,119 @@ NEW met1 ( 1337910 1022210 ) M1M2_PR NEW met2 ( 1337910 1023060 ) via2_FR NEW met3 ( 1241540 2298060 ) RECT ( 0 -150 390 150 ) +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - io_in[5] ( PIN io_in[5] ) ( mprj io_in[5] ) + ROUTED met2 ( 2899150 1261060 ) ( 2899150 1262590 ) NEW met3 ( 2899150 1261060 ) ( 2917780 1261060 0 ) +<<<<<<< HEAD + NEW met3 ( 2609580 1293020 0 ) ( 2618550 1293020 ) + NEW met2 ( 2618550 1262590 ) ( 2618550 1293020 ) + NEW met1 ( 2618550 1262590 ) ( 2899150 1262590 ) + NEW met1 ( 2618550 1262590 ) M1M2_PR + NEW met1 ( 2899150 1262590 ) M1M2_PR + NEW met2 ( 2899150 1261060 ) via2_FR + NEW met2 ( 2618550 1293020 ) via2_FR ++ USE SIGNAL ; +- io_in[6] ( PIN io_in[6] ) ( mprj io_in[6] ) + + ROUTED met3 ( 2609580 1492940 0 ) ( 2621770 1492940 ) + NEW met2 ( 2621770 1492940 ) ( 2621770 1493790 ) + NEW met2 ( 2900990 1493790 ) ( 2900990 1495660 ) + NEW met3 ( 2900990 1495660 ) ( 2917780 1495660 0 ) + NEW met1 ( 2621770 1493790 ) ( 2900990 1493790 ) + NEW met2 ( 2621770 1492940 ) via2_FR + NEW met1 ( 2621770 1493790 ) M1M2_PR + NEW met1 ( 2900990 1493790 ) M1M2_PR + NEW met2 ( 2900990 1495660 ) via2_FR ++ USE SIGNAL ; +- io_in[7] ( PIN io_in[7] ) ( mprj io_in[7] ) + + ROUTED met2 ( 2900990 1725330 ) ( 2900990 1730260 ) + NEW met3 ( 2900990 1730260 ) ( 2917780 1730260 0 ) + NEW met3 ( 2609580 1692860 0 ) ( 2619010 1692860 ) + NEW met2 ( 2619010 1692860 ) ( 2619010 1725330 ) + NEW met1 ( 2619010 1725330 ) ( 2900990 1725330 ) + NEW met1 ( 2619010 1725330 ) M1M2_PR + NEW met1 ( 2900990 1725330 ) M1M2_PR + NEW met2 ( 2900990 1730260 ) via2_FR + NEW met2 ( 2619010 1692860 ) via2_FR ++ USE SIGNAL ; +- io_in[8] ( PIN io_in[8] ) ( mprj io_in[8] ) + + ROUTED met2 ( 2900990 1959930 ) ( 2900990 1964860 ) + NEW met3 ( 2900990 1964860 ) ( 2917780 1964860 0 ) + NEW met3 ( 2609580 1893460 0 ) ( 2618550 1893460 ) + NEW met2 ( 2618550 1893460 ) ( 2618550 1959930 ) + NEW met1 ( 2618550 1959930 ) ( 2900990 1959930 ) + NEW met1 ( 2618550 1959930 ) M1M2_PR + NEW met1 ( 2900990 1959930 ) M1M2_PR + NEW met2 ( 2900990 1964860 ) via2_FR + NEW met2 ( 2618550 1893460 ) via2_FR ++ USE SIGNAL ; +- io_in[9] ( PIN io_in[9] ) ( mprj io_in[9] ) + + ROUTED met3 ( 2609580 2093380 0 ) ( 2618550 2093380 ) + NEW met2 ( 2618550 2093380 ) ( 2618550 2194530 ) + NEW met2 ( 2900990 2194530 ) ( 2900990 2199460 ) + NEW met3 ( 2900990 2199460 ) ( 2917780 2199460 0 ) + NEW met1 ( 2618550 2194530 ) ( 2900990 2194530 ) + NEW met2 ( 2618550 2093380 ) via2_FR + NEW met1 ( 2618550 2194530 ) M1M2_PR + NEW met1 ( 2900990 2194530 ) M1M2_PR + NEW met2 ( 2900990 2199460 ) via2_FR ++ USE SIGNAL ; +- io_oeb[0] ( PIN io_oeb[0] ) ( mprj io_oeb[0] ) + + ROUTED met2 ( 2900990 205020 ) ( 2900990 206890 ) + NEW met3 ( 2900990 205020 ) ( 2917780 205020 0 ) + NEW met3 ( 2609580 426700 0 ) ( 2618550 426700 ) + NEW met2 ( 2618550 206890 ) ( 2618550 426700 ) + NEW met1 ( 2618550 206890 ) ( 2900990 206890 ) + NEW met1 ( 2618550 206890 ) M1M2_PR + NEW met1 ( 2900990 206890 ) M1M2_PR + NEW met2 ( 2900990 205020 ) via2_FR + NEW met2 ( 2618550 426700 ) via2_FR ++ USE SIGNAL ; +- io_oeb[10] ( PIN io_oeb[10] ) ( mprj io_oeb[10] ) + + ROUTED met3 ( 2609580 2426580 0 ) ( 2619010 2426580 ) + NEW met2 ( 2619010 2426580 ) ( 2619010 2546430 ) + NEW met2 ( 2900990 2546430 ) ( 2900990 2551700 ) + NEW met3 ( 2900990 2551700 ) ( 2917780 2551700 0 ) + NEW met1 ( 2619010 2546430 ) ( 2900990 2546430 ) + NEW met2 ( 2619010 2426580 ) via2_FR + NEW met1 ( 2619010 2546430 ) M1M2_PR + NEW met1 ( 2900990 2546430 ) M1M2_PR + NEW met2 ( 2900990 2551700 ) via2_FR ++ USE SIGNAL ; +- io_oeb[11] ( PIN io_oeb[11] ) ( mprj io_oeb[11] ) + + ROUTED met3 ( 2609580 2626500 0 ) ( 2619010 2626500 ) + NEW met2 ( 2619010 2626500 ) ( 2619010 2781030 ) + NEW met2 ( 2900990 2781030 ) ( 2900990 2786300 ) + NEW met3 ( 2900990 2786300 ) ( 2917780 2786300 0 ) + NEW met1 ( 2619010 2781030 ) ( 2900990 2781030 ) + NEW met2 ( 2619010 2626500 ) via2_FR + NEW met1 ( 2619010 2781030 ) M1M2_PR + NEW met1 ( 2900990 2781030 ) M1M2_PR + NEW met2 ( 2900990 2786300 ) via2_FR ++ USE SIGNAL ; +- io_oeb[12] ( PIN io_oeb[12] ) ( mprj io_oeb[12] ) + + ROUTED met3 ( 2609580 2826420 0 ) ( 2615790 2826420 ) + NEW met2 ( 2615790 2826420 ) ( 2615790 2828970 ) + NEW met3 ( 2902370 3020900 ) ( 2917780 3020900 0 ) + NEW met2 ( 2902370 2828970 ) ( 2902370 3020900 ) + NEW met1 ( 2615790 2828970 ) ( 2902370 2828970 ) + NEW met2 ( 2615790 2826420 ) via2_FR + NEW met1 ( 2615790 2828970 ) M1M2_PR + NEW met1 ( 2902370 2828970 ) M1M2_PR + NEW met2 ( 2902370 3020900 ) via2_FR ++ USE SIGNAL ; +- io_oeb[13] ( PIN io_oeb[13] ) ( mprj io_oeb[13] ) + + ROUTED met3 ( 2609580 3026340 0 ) ( 2615790 3026340 ) + NEW met2 ( 2615790 3026340 ) ( 2615790 3028890 ) + NEW met3 ( 2902370 3255500 ) ( 2917780 3255500 0 ) + NEW met2 ( 2902370 3028890 ) ( 2902370 3255500 ) + NEW met1 ( 2615790 3028890 ) ( 2902370 3028890 ) + NEW met2 ( 2615790 3026340 ) via2_FR + NEW met1 ( 2615790 3028890 ) M1M2_PR + NEW met1 ( 2902370 3028890 ) M1M2_PR + NEW met2 ( 2902370 3255500 ) via2_FR +======= NEW met2 ( 1255110 2299420 ) ( 1255570 2299420 0 ) NEW met2 ( 1255110 2299420 ) ( 1255110 2299930 ) NEW met1 ( 1790550 1262590 ) ( 2899150 1262590 ) @@ -71384,10 +72886,454 @@ NEW met1 ( 1393570 3250910 ) M1M2_PR NEW met1 ( 1388970 2311490 ) M1M2_PR NEW met1 ( 1393570 2311490 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - io_oeb[14] ( PIN io_oeb[14] ) ( mprj io_oeb[14] ) + ROUTED met2 ( 2900990 3484830 ) ( 2900990 3490100 ) NEW met3 ( 2900990 3490100 ) ( 2917780 3490100 0 ) +<<<<<<< HEAD + NEW met3 ( 2609580 3226260 0 ) ( 2619010 3226260 ) + NEW met2 ( 2619010 3226260 ) ( 2619010 3484830 ) + NEW met1 ( 2619010 3484830 ) ( 2900990 3484830 ) + NEW met1 ( 2619010 3484830 ) M1M2_PR + NEW met1 ( 2900990 3484830 ) M1M2_PR + NEW met2 ( 2900990 3490100 ) via2_FR + NEW met2 ( 2619010 3226260 ) via2_FR ++ USE SIGNAL ; +- io_oeb[15] ( PIN io_oeb[15] ) ( mprj io_oeb[15] ) + + ROUTED met2 ( 2636030 3501490 ) ( 2636030 3517980 0 ) + NEW met1 ( 2396830 3277430 ) ( 2400970 3277430 ) + NEW met1 ( 2400970 3501490 ) ( 2636030 3501490 ) + NEW met2 ( 2396830 3259580 0 ) ( 2396830 3277430 ) + NEW met2 ( 2400970 3277430 ) ( 2400970 3501490 ) + NEW met1 ( 2636030 3501490 ) M1M2_PR + NEW met1 ( 2396830 3277430 ) M1M2_PR + NEW met1 ( 2400970 3277430 ) M1M2_PR + NEW met1 ( 2400970 3501490 ) M1M2_PR ++ USE SIGNAL ; +- io_oeb[16] ( PIN io_oeb[16] ) ( mprj io_oeb[16] ) + + ROUTED met1 ( 2141070 3277430 ) ( 2145670 3277430 ) + NEW met2 ( 2141070 3259580 0 ) ( 2141070 3277430 ) + NEW met2 ( 2145670 3277430 ) ( 2145670 3501490 ) + NEW met2 ( 2311730 3501490 ) ( 2311730 3517980 0 ) + NEW met1 ( 2145670 3501490 ) ( 2311730 3501490 ) + NEW met1 ( 2141070 3277430 ) M1M2_PR + NEW met1 ( 2145670 3277430 ) M1M2_PR + NEW met1 ( 2145670 3501490 ) M1M2_PR + NEW met1 ( 2311730 3501490 ) M1M2_PR ++ USE SIGNAL ; +- io_oeb[17] ( PIN io_oeb[17] ) ( mprj io_oeb[17] ) + + ROUTED met1 ( 1885770 3277430 ) ( 1890370 3277430 ) + NEW met1 ( 1890370 3501490 ) ( 1987430 3501490 ) + NEW met2 ( 1885770 3259580 0 ) ( 1885770 3277430 ) + NEW met2 ( 1890370 3277430 ) ( 1890370 3501490 ) + NEW met2 ( 1987430 3501490 ) ( 1987430 3517980 0 ) + NEW met1 ( 1885770 3277430 ) M1M2_PR + NEW met1 ( 1890370 3277430 ) M1M2_PR + NEW met1 ( 1890370 3501490 ) M1M2_PR + NEW met1 ( 1987430 3501490 ) M1M2_PR ++ USE SIGNAL ; +- io_oeb[18] ( PIN io_oeb[18] ) ( mprj io_oeb[18] ) + + ROUTED met1 ( 1630010 3275730 ) ( 1635070 3275730 ) + NEW met1 ( 1635070 3498430 ) ( 1662670 3498430 ) + NEW met2 ( 1630010 3259580 0 ) ( 1630010 3275730 ) + NEW met2 ( 1635070 3275730 ) ( 1635070 3498430 ) + NEW met2 ( 1662670 3498430 ) ( 1662670 3517980 0 ) + NEW met1 ( 1630010 3275730 ) M1M2_PR + NEW met1 ( 1635070 3275730 ) M1M2_PR + NEW met1 ( 1635070 3498430 ) M1M2_PR + NEW met1 ( 1662670 3498430 ) M1M2_PR ++ USE SIGNAL ; +- io_oeb[19] ( PIN io_oeb[19] ) ( mprj io_oeb[19] ) + + ROUTED met2 ( 1374710 3259580 0 ) ( 1374710 3274030 ) + NEW met1 ( 1338370 3274030 ) ( 1374710 3274030 ) + NEW met2 ( 1338370 3274030 ) ( 1338370 3517980 0 ) + NEW met1 ( 1374710 3274030 ) M1M2_PR + NEW met1 ( 1338370 3274030 ) M1M2_PR ++ USE SIGNAL ; +- io_oeb[1] ( PIN io_oeb[1] ) ( mprj io_oeb[1] ) + + ROUTED met3 ( 2609580 626620 0 ) ( 2618550 626620 ) + NEW met2 ( 2618550 441490 ) ( 2618550 626620 ) + NEW met2 ( 2900990 439620 ) ( 2900990 441490 ) + NEW met3 ( 2900990 439620 ) ( 2917780 439620 0 ) + NEW met1 ( 2618550 441490 ) ( 2900990 441490 ) + NEW met1 ( 2618550 441490 ) M1M2_PR + NEW met2 ( 2618550 626620 ) via2_FR + NEW met1 ( 2900990 441490 ) M1M2_PR + NEW met2 ( 2900990 439620 ) via2_FR ++ USE SIGNAL ; +- io_oeb[20] ( PIN io_oeb[20] ) ( mprj io_oeb[20] ) + + ROUTED met2 ( 1014070 3274030 ) ( 1014070 3517980 0 ) + NEW met2 ( 1118950 3259580 0 ) ( 1118950 3274030 ) + NEW met1 ( 1014070 3274030 ) ( 1118950 3274030 ) + NEW met1 ( 1014070 3274030 ) M1M2_PR + NEW met1 ( 1118950 3274030 ) M1M2_PR ++ USE SIGNAL ; +- io_oeb[21] ( PIN io_oeb[21] ) ( mprj io_oeb[21] ) + + ROUTED met2 ( 688850 3318740 ) ( 689770 3318740 ) + NEW met2 ( 688850 3274710 ) ( 688850 3318740 ) + NEW met1 ( 688850 3367530 ) ( 689770 3367530 ) + NEW met2 ( 689770 3318740 ) ( 689770 3367530 ) + NEW met2 ( 863650 3259580 0 ) ( 863650 3274710 ) + NEW met1 ( 688850 3274710 ) ( 863650 3274710 ) + NEW met1 ( 688850 3491290 ) ( 689770 3491290 ) + NEW met2 ( 688850 3517300 ) ( 689310 3517300 ) + NEW met2 ( 689310 3517300 ) ( 689310 3517980 0 ) + NEW met2 ( 688850 3491290 ) ( 688850 3517300 ) + NEW met1 ( 688850 3394730 ) ( 688850 3395070 ) + NEW met1 ( 688850 3395070 ) ( 689310 3395070 ) + NEW met2 ( 688850 3367530 ) ( 688850 3394730 ) + NEW li1 ( 689310 3429410 ) ( 689310 3477350 ) + NEW met1 ( 689310 3477350 ) ( 689770 3477350 ) + NEW met2 ( 689310 3395070 ) ( 689310 3429410 ) + NEW met2 ( 689770 3477350 ) ( 689770 3491290 ) + NEW met1 ( 688850 3274710 ) M1M2_PR + NEW met1 ( 689770 3367530 ) M1M2_PR + NEW met1 ( 688850 3367530 ) M1M2_PR + NEW met1 ( 863650 3274710 ) M1M2_PR + NEW met1 ( 688850 3491290 ) M1M2_PR + NEW met1 ( 689770 3491290 ) M1M2_PR + NEW met1 ( 688850 3394730 ) M1M2_PR + NEW met1 ( 689310 3395070 ) M1M2_PR + NEW li1 ( 689310 3429410 ) L1M1_PR_MR + NEW met1 ( 689310 3429410 ) M1M2_PR + NEW li1 ( 689310 3477350 ) L1M1_PR_MR + NEW met1 ( 689770 3477350 ) M1M2_PR + NEW met1 ( 689310 3429410 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- io_oeb[22] ( PIN io_oeb[22] ) ( mprj io_oeb[22] ) + + ROUTED met2 ( 607890 3259580 0 ) ( 607890 3274710 ) + NEW met1 ( 364090 3274710 ) ( 607890 3274710 ) + NEW met1 ( 363630 3346450 ) ( 364550 3346450 ) + NEW met2 ( 363630 3491460 ) ( 364090 3491460 ) + NEW met2 ( 364090 3491460 ) ( 364090 3517300 ) + NEW met2 ( 364090 3517300 ) ( 365010 3517300 ) + NEW met2 ( 365010 3517300 ) ( 365010 3517980 0 ) + NEW li1 ( 364090 3284570 ) ( 364090 3332510 ) + NEW met1 ( 364090 3332510 ) ( 364550 3332510 ) + NEW met2 ( 364090 3274710 ) ( 364090 3284570 ) + NEW met2 ( 364550 3332510 ) ( 364550 3346450 ) + NEW met1 ( 362710 3415470 ) ( 363630 3415470 ) + NEW li1 ( 363630 3394390 ) ( 363630 3415470 ) + NEW met2 ( 363630 3346450 ) ( 363630 3394390 ) + NEW li1 ( 362710 3416150 ) ( 362710 3463750 ) + NEW met1 ( 362710 3463750 ) ( 363630 3463750 ) + NEW met2 ( 362710 3415470 ) ( 362710 3416150 ) + NEW met2 ( 363630 3463750 ) ( 363630 3491460 ) + NEW met1 ( 607890 3274710 ) M1M2_PR + NEW met1 ( 364090 3274710 ) M1M2_PR + NEW met1 ( 363630 3346450 ) M1M2_PR + NEW met1 ( 364550 3346450 ) M1M2_PR + NEW li1 ( 364090 3284570 ) L1M1_PR_MR + NEW met1 ( 364090 3284570 ) M1M2_PR + NEW li1 ( 364090 3332510 ) L1M1_PR_MR + NEW met1 ( 364550 3332510 ) M1M2_PR + NEW met1 ( 362710 3415470 ) M1M2_PR + NEW li1 ( 363630 3415470 ) L1M1_PR_MR + NEW li1 ( 363630 3394390 ) L1M1_PR_MR + NEW met1 ( 363630 3394390 ) M1M2_PR + NEW li1 ( 362710 3416150 ) L1M1_PR_MR + NEW met1 ( 362710 3416150 ) M1M2_PR + NEW li1 ( 362710 3463750 ) L1M1_PR_MR + NEW met1 ( 363630 3463750 ) M1M2_PR + NEW met1 ( 364090 3284570 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 363630 3394390 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 362710 3416150 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- io_oeb[23] ( PIN io_oeb[23] ) ( mprj io_oeb[23] ) + + ROUTED met2 ( 40250 3318740 ) ( 41170 3318740 ) + NEW met2 ( 40250 3274710 ) ( 40250 3318740 ) + NEW met1 ( 40250 3367530 ) ( 41170 3367530 ) + NEW met2 ( 41170 3318740 ) ( 41170 3367530 ) + NEW met2 ( 352590 3259580 0 ) ( 352590 3274710 ) + NEW met1 ( 40250 3274710 ) ( 352590 3274710 ) + NEW met1 ( 40250 3491290 ) ( 41170 3491290 ) + NEW met2 ( 40250 3517300 ) ( 40710 3517300 ) + NEW met2 ( 40710 3517300 ) ( 40710 3517980 0 ) + NEW met2 ( 40250 3491290 ) ( 40250 3517300 ) + NEW met1 ( 40250 3394730 ) ( 40250 3395070 ) + NEW met1 ( 40250 3395070 ) ( 40710 3395070 ) + NEW met2 ( 40250 3367530 ) ( 40250 3394730 ) + NEW li1 ( 40710 3429410 ) ( 40710 3477350 ) + NEW met1 ( 40710 3477350 ) ( 41170 3477350 ) + NEW met2 ( 40710 3395070 ) ( 40710 3429410 ) + NEW met2 ( 41170 3477350 ) ( 41170 3491290 ) + NEW met1 ( 40250 3274710 ) M1M2_PR + NEW met1 ( 41170 3367530 ) M1M2_PR + NEW met1 ( 40250 3367530 ) M1M2_PR + NEW met1 ( 352590 3274710 ) M1M2_PR + NEW met1 ( 40250 3491290 ) M1M2_PR + NEW met1 ( 41170 3491290 ) M1M2_PR + NEW met1 ( 40250 3394730 ) M1M2_PR + NEW met1 ( 40710 3395070 ) M1M2_PR + NEW li1 ( 40710 3429410 ) L1M1_PR_MR + NEW met1 ( 40710 3429410 ) M1M2_PR + NEW li1 ( 40710 3477350 ) L1M1_PR_MR + NEW met1 ( 41170 3477350 ) M1M2_PR + NEW met1 ( 40710 3429410 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- io_oeb[24] ( PIN io_oeb[24] ) ( mprj io_oeb[24] ) + + ROUTED met2 ( 296930 3080740 ) ( 296930 3083970 ) + NEW met3 ( 296930 3080740 ) ( 310500 3080740 0 ) + NEW met3 ( 2300 3267740 0 ) ( 17710 3267740 ) + NEW met2 ( 17710 3083970 ) ( 17710 3267740 ) + NEW met1 ( 17710 3083970 ) ( 296930 3083970 ) + NEW met1 ( 17710 3083970 ) M1M2_PR + NEW met1 ( 296930 3083970 ) M1M2_PR + NEW met2 ( 296930 3080740 ) via2_FR + NEW met2 ( 17710 3267740 ) via2_FR ++ USE SIGNAL ; +- io_oeb[25] ( PIN io_oeb[25] ) ( mprj io_oeb[25] ) + + ROUTED met3 ( 2300 2980100 0 ) ( 17710 2980100 ) + NEW met2 ( 17710 2870110 ) ( 17710 2980100 ) + NEW met2 ( 296930 2866540 ) ( 296930 2870110 ) + NEW met3 ( 296930 2866540 ) ( 310500 2866540 0 ) + NEW met1 ( 17710 2870110 ) ( 296930 2870110 ) + NEW met1 ( 17710 2870110 ) M1M2_PR + NEW met2 ( 17710 2980100 ) via2_FR + NEW met1 ( 296930 2870110 ) M1M2_PR + NEW met2 ( 296930 2866540 ) via2_FR ++ USE SIGNAL ; +- io_oeb[26] ( PIN io_oeb[26] ) ( mprj io_oeb[26] ) + + ROUTED met3 ( 2300 2693140 0 ) ( 17250 2693140 ) + NEW met2 ( 17250 2656250 ) ( 17250 2693140 ) + NEW met2 ( 296930 2652340 ) ( 296930 2656250 ) + NEW met3 ( 296930 2652340 ) ( 310500 2652340 0 ) + NEW met1 ( 17250 2656250 ) ( 296930 2656250 ) + NEW met2 ( 17250 2693140 ) via2_FR + NEW met1 ( 17250 2656250 ) M1M2_PR + NEW met1 ( 296930 2656250 ) M1M2_PR + NEW met2 ( 296930 2652340 ) via2_FR ++ USE SIGNAL ; +- io_oeb[27] ( PIN io_oeb[27] ) ( mprj io_oeb[27] ) + + ROUTED met3 ( 2300 2405500 0 ) ( 17250 2405500 ) + NEW met2 ( 17250 2405500 ) ( 17250 2435930 ) + NEW met2 ( 296930 2435930 ) ( 296930 2438140 ) + NEW met3 ( 296930 2438140 ) ( 310500 2438140 0 ) + NEW met1 ( 17250 2435930 ) ( 296930 2435930 ) + NEW met2 ( 17250 2405500 ) via2_FR + NEW met1 ( 17250 2435930 ) M1M2_PR + NEW met1 ( 296930 2435930 ) M1M2_PR + NEW met2 ( 296930 2438140 ) via2_FR ++ USE SIGNAL ; +- io_oeb[28] ( PIN io_oeb[28] ) ( mprj io_oeb[28] ) + + ROUTED met3 ( 2300 2118540 0 ) ( 17250 2118540 ) + NEW met2 ( 296930 2222070 ) ( 296930 2223940 ) + NEW met3 ( 296930 2223940 ) ( 310500 2223940 0 ) + NEW met2 ( 17250 2118540 ) ( 17250 2222070 ) + NEW met1 ( 17250 2222070 ) ( 296930 2222070 ) + NEW met2 ( 17250 2118540 ) via2_FR + NEW met1 ( 17250 2222070 ) M1M2_PR + NEW met1 ( 296930 2222070 ) M1M2_PR + NEW met2 ( 296930 2223940 ) via2_FR ++ USE SIGNAL ; +- io_oeb[29] ( PIN io_oeb[29] ) ( mprj io_oeb[29] ) + + ROUTED met3 ( 2300 1830900 0 ) ( 18170 1830900 ) + NEW met2 ( 18170 1830900 ) ( 18170 2008210 ) + NEW met2 ( 296930 2008210 ) ( 296930 2009740 ) + NEW met3 ( 296930 2009740 ) ( 310500 2009740 0 ) + NEW met1 ( 18170 2008210 ) ( 296930 2008210 ) + NEW met2 ( 18170 1830900 ) via2_FR + NEW met1 ( 18170 2008210 ) M1M2_PR + NEW met1 ( 296930 2008210 ) M1M2_PR + NEW met2 ( 296930 2009740 ) via2_FR ++ USE SIGNAL ; +- io_oeb[2] ( PIN io_oeb[2] ) ( mprj io_oeb[2] ) + + ROUTED met2 ( 2900990 674220 ) ( 2900990 676090 ) + NEW met3 ( 2900990 674220 ) ( 2917780 674220 0 ) + NEW met3 ( 2609580 826540 0 ) ( 2618550 826540 ) + NEW met2 ( 2618550 676090 ) ( 2618550 826540 ) + NEW met1 ( 2618550 676090 ) ( 2900990 676090 ) + NEW met1 ( 2618550 676090 ) M1M2_PR + NEW met1 ( 2900990 676090 ) M1M2_PR + NEW met2 ( 2900990 674220 ) via2_FR + NEW met2 ( 2618550 826540 ) via2_FR ++ USE SIGNAL ; +- io_oeb[30] ( PIN io_oeb[30] ) ( mprj io_oeb[30] ) + + ROUTED met3 ( 2300 1543940 0 ) ( 17250 1543940 ) + NEW met2 ( 17250 1543940 ) ( 17250 1794010 ) + NEW met2 ( 296930 1794010 ) ( 296930 1795540 ) + NEW met3 ( 296930 1795540 ) ( 310500 1795540 0 ) + NEW met1 ( 17250 1794010 ) ( 296930 1794010 ) + NEW met2 ( 17250 1543940 ) via2_FR + NEW met1 ( 17250 1794010 ) M1M2_PR + NEW met1 ( 296930 1794010 ) M1M2_PR + NEW met2 ( 296930 1795540 ) via2_FR ++ USE SIGNAL ; +- io_oeb[31] ( PIN io_oeb[31] ) ( mprj io_oeb[31] ) + + ROUTED met3 ( 2300 1328380 0 ) ( 18630 1328380 ) + NEW met2 ( 18630 1328380 ) ( 18630 1580150 ) + NEW met2 ( 296930 1580150 ) ( 296930 1580660 ) + NEW met3 ( 296930 1580660 ) ( 310500 1580660 0 ) + NEW met1 ( 18630 1580150 ) ( 296930 1580150 ) + NEW met2 ( 18630 1328380 ) via2_FR + NEW met1 ( 18630 1580150 ) M1M2_PR + NEW met1 ( 296930 1580150 ) M1M2_PR + NEW met2 ( 296930 1580660 ) via2_FR ++ USE SIGNAL ; +- io_oeb[32] ( PIN io_oeb[32] ) ( mprj io_oeb[32] ) + + ROUTED met2 ( 296930 1366290 ) ( 296930 1366460 ) + NEW met3 ( 296930 1366460 ) ( 310500 1366460 0 ) + NEW met3 ( 2300 1112820 0 ) ( 18170 1112820 ) + NEW met2 ( 18170 1112820 ) ( 18170 1366290 ) + NEW met1 ( 18170 1366290 ) ( 296930 1366290 ) + NEW met1 ( 18170 1366290 ) M1M2_PR + NEW met1 ( 296930 1366290 ) M1M2_PR + NEW met2 ( 296930 1366460 ) via2_FR + NEW met2 ( 18170 1112820 ) via2_FR ++ USE SIGNAL ; +- io_oeb[33] ( PIN io_oeb[33] ) ( mprj io_oeb[33] ) + + ROUTED met3 ( 2300 897260 0 ) ( 18630 897260 ) + NEW met2 ( 296930 1145630 ) ( 296930 1152260 ) + NEW met3 ( 296930 1152260 ) ( 310500 1152260 0 ) + NEW met2 ( 18630 897260 ) ( 18630 1145630 ) + NEW met1 ( 18630 1145630 ) ( 296930 1145630 ) + NEW met2 ( 18630 897260 ) via2_FR + NEW met1 ( 18630 1145630 ) M1M2_PR + NEW met1 ( 296930 1145630 ) M1M2_PR + NEW met2 ( 296930 1152260 ) via2_FR ++ USE SIGNAL ; +- io_oeb[34] ( PIN io_oeb[34] ) ( mprj io_oeb[34] ) + + ROUTED met3 ( 2300 681700 0 ) ( 18170 681700 ) + NEW met2 ( 18170 681700 ) ( 18170 931770 ) + NEW met2 ( 296930 931770 ) ( 296930 938060 ) + NEW met3 ( 296930 938060 ) ( 310500 938060 0 ) + NEW met1 ( 18170 931770 ) ( 296930 931770 ) + NEW met2 ( 18170 681700 ) via2_FR + NEW met1 ( 18170 931770 ) M1M2_PR + NEW met1 ( 296930 931770 ) M1M2_PR + NEW met2 ( 296930 938060 ) via2_FR ++ USE SIGNAL ; +- io_oeb[35] ( PIN io_oeb[35] ) ( mprj io_oeb[35] ) + + ROUTED met3 ( 2300 466140 0 ) ( 18630 466140 ) + NEW met2 ( 18630 466140 ) ( 18630 717910 ) + NEW met2 ( 296930 717910 ) ( 296930 723860 ) + NEW met3 ( 296930 723860 ) ( 310500 723860 0 ) + NEW met1 ( 18630 717910 ) ( 296930 717910 ) + NEW met2 ( 18630 466140 ) via2_FR + NEW met1 ( 18630 717910 ) M1M2_PR + NEW met1 ( 296930 717910 ) M1M2_PR + NEW met2 ( 296930 723860 ) via2_FR ++ USE SIGNAL ; +- io_oeb[36] ( PIN io_oeb[36] ) ( mprj io_oeb[36] ) + + ROUTED met2 ( 296930 503710 ) ( 296930 509660 ) + NEW met3 ( 296930 509660 ) ( 310500 509660 0 ) + NEW met3 ( 2300 250580 0 ) ( 18170 250580 ) + NEW met2 ( 18170 250580 ) ( 18170 503710 ) + NEW met1 ( 18170 503710 ) ( 296930 503710 ) + NEW met1 ( 18170 503710 ) M1M2_PR + NEW met1 ( 296930 503710 ) M1M2_PR + NEW met2 ( 296930 509660 ) via2_FR + NEW met2 ( 18170 250580 ) via2_FR ++ USE SIGNAL ; +- io_oeb[37] ( PIN io_oeb[37] ) ( mprj io_oeb[37] ) + + ROUTED met2 ( 296930 289850 ) ( 296930 295460 ) + NEW met3 ( 296930 295460 ) ( 310500 295460 0 ) + NEW met3 ( 2300 35700 0 ) ( 17710 35700 ) + NEW met2 ( 17710 35700 ) ( 17710 289850 ) + NEW met1 ( 17710 289850 ) ( 296930 289850 ) + NEW met1 ( 17710 289850 ) M1M2_PR + NEW met1 ( 296930 289850 ) M1M2_PR + NEW met2 ( 296930 295460 ) via2_FR + NEW met2 ( 17710 35700 ) via2_FR ++ USE SIGNAL ; +- io_oeb[3] ( PIN io_oeb[3] ) ( mprj io_oeb[3] ) + + ROUTED met3 ( 2609580 1026460 0 ) ( 2618550 1026460 ) + NEW met2 ( 2618550 910690 ) ( 2618550 1026460 ) + NEW met2 ( 2900990 909500 ) ( 2900990 910690 ) + NEW met3 ( 2900990 909500 ) ( 2917780 909500 0 ) + NEW met1 ( 2618550 910690 ) ( 2900990 910690 ) + NEW met1 ( 2618550 910690 ) M1M2_PR + NEW met2 ( 2618550 1026460 ) via2_FR + NEW met1 ( 2900990 910690 ) M1M2_PR + NEW met2 ( 2900990 909500 ) via2_FR ++ USE SIGNAL ; +- io_oeb[4] ( PIN io_oeb[4] ) ( mprj io_oeb[4] ) + + ROUTED met3 ( 2609580 1226380 0 ) ( 2618550 1226380 ) + NEW met2 ( 2618550 1145290 ) ( 2618550 1226380 ) + NEW met2 ( 2900990 1144100 ) ( 2900990 1145290 ) + NEW met3 ( 2900990 1144100 ) ( 2917780 1144100 0 ) + NEW met1 ( 2618550 1145290 ) ( 2900990 1145290 ) + NEW met1 ( 2618550 1145290 ) M1M2_PR + NEW met2 ( 2618550 1226380 ) via2_FR + NEW met1 ( 2900990 1145290 ) M1M2_PR + NEW met2 ( 2900990 1144100 ) via2_FR ++ USE SIGNAL ; +- io_oeb[5] ( PIN io_oeb[5] ) ( mprj io_oeb[5] ) + + ROUTED met2 ( 2900990 1378700 ) ( 2900990 1379890 ) + NEW met3 ( 2900990 1378700 ) ( 2917780 1378700 0 ) + NEW met3 ( 2609580 1426300 0 ) ( 2618550 1426300 ) + NEW met2 ( 2618550 1379890 ) ( 2618550 1426300 ) + NEW met1 ( 2618550 1379890 ) ( 2900990 1379890 ) + NEW met1 ( 2618550 1379890 ) M1M2_PR + NEW met1 ( 2900990 1379890 ) M1M2_PR + NEW met2 ( 2900990 1378700 ) via2_FR + NEW met2 ( 2618550 1426300 ) via2_FR ++ USE SIGNAL ; +- io_oeb[6] ( PIN io_oeb[6] ) ( mprj io_oeb[6] ) + + ROUTED met3 ( 2609580 1626220 0 ) ( 2621770 1626220 ) + NEW met2 ( 2621770 1614490 ) ( 2621770 1626220 ) + NEW met2 ( 2900990 1613300 ) ( 2900990 1614490 ) + NEW met3 ( 2900990 1613300 ) ( 2917780 1613300 0 ) + NEW met1 ( 2621770 1614490 ) ( 2900990 1614490 ) + NEW met2 ( 2621770 1626220 ) via2_FR + NEW met1 ( 2621770 1614490 ) M1M2_PR + NEW met1 ( 2900990 1614490 ) M1M2_PR + NEW met2 ( 2900990 1613300 ) via2_FR ++ USE SIGNAL ; +- io_oeb[7] ( PIN io_oeb[7] ) ( mprj io_oeb[7] ) + + ROUTED met3 ( 2609580 1826820 0 ) ( 2621310 1826820 ) + NEW met2 ( 2621310 1826820 ) ( 2621310 1842630 ) + NEW met2 ( 2900990 1842630 ) ( 2900990 1847900 ) + NEW met3 ( 2900990 1847900 ) ( 2917780 1847900 0 ) + NEW met1 ( 2621310 1842630 ) ( 2900990 1842630 ) + NEW met2 ( 2621310 1826820 ) via2_FR + NEW met1 ( 2621310 1842630 ) M1M2_PR + NEW met1 ( 2900990 1842630 ) M1M2_PR + NEW met2 ( 2900990 1847900 ) via2_FR ++ USE SIGNAL ; +- io_oeb[8] ( PIN io_oeb[8] ) ( mprj io_oeb[8] ) + + ROUTED met3 ( 2609580 2026740 0 ) ( 2618550 2026740 ) + NEW met2 ( 2618550 2026740 ) ( 2618550 2077230 ) + NEW met2 ( 2900990 2077230 ) ( 2900990 2082500 ) + NEW met3 ( 2900990 2082500 ) ( 2917780 2082500 0 ) + NEW met1 ( 2618550 2077230 ) ( 2900990 2077230 ) + NEW met2 ( 2618550 2026740 ) via2_FR + NEW met1 ( 2618550 2077230 ) M1M2_PR + NEW met1 ( 2900990 2077230 ) M1M2_PR + NEW met2 ( 2900990 2082500 ) via2_FR ++ USE SIGNAL ; +- io_oeb[9] ( PIN io_oeb[9] ) ( mprj io_oeb[9] ) + + ROUTED met3 ( 2609580 2226660 0 ) ( 2618550 2226660 ) + NEW met2 ( 2900990 2311830 ) ( 2900990 2317100 ) + NEW met3 ( 2900990 2317100 ) ( 2917780 2317100 0 ) + NEW met2 ( 2618550 2226660 ) ( 2618550 2311830 ) + NEW met1 ( 2618550 2311830 ) ( 2900990 2311830 ) + NEW met2 ( 2618550 2226660 ) via2_FR + NEW met1 ( 2618550 2311830 ) M1M2_PR + NEW met1 ( 2900990 2311830 ) M1M2_PR + NEW met2 ( 2900990 2317100 ) via2_FR ++ USE SIGNAL ; +- io_out[0] ( PIN io_out[0] ) ( mprj io_out[0] ) + + ROUTED met3 ( 2609580 360060 0 ) ( 2619010 360060 ) + NEW met2 ( 2619010 151470 ) ( 2619010 360060 ) + NEW met2 ( 2900990 146540 ) ( 2900990 151470 ) + NEW met3 ( 2900990 146540 ) ( 2917780 146540 0 ) + NEW met1 ( 2619010 151470 ) ( 2900990 151470 ) + NEW met1 ( 2619010 151470 ) M1M2_PR + NEW met2 ( 2619010 360060 ) via2_FR + NEW met1 ( 2900990 151470 ) M1M2_PR + NEW met2 ( 2900990 146540 ) via2_FR ++ USE SIGNAL ; +- io_out[10] ( PIN io_out[10] ) ( mprj io_out[10] ) + + ROUTED met3 ( 2609580 2359940 0 ) ( 2618550 2359940 ) + NEW met2 ( 2618550 2359940 ) ( 2618550 2491010 ) + NEW met2 ( 2900990 2491010 ) ( 2900990 2493220 ) + NEW met3 ( 2900990 2493220 ) ( 2917780 2493220 0 ) + NEW met1 ( 2618550 2491010 ) ( 2900990 2491010 ) + NEW met2 ( 2618550 2359940 ) via2_FR + NEW met1 ( 2618550 2491010 ) M1M2_PR +======= NEW met1 ( 1407370 3484830 ) ( 2900990 3484830 ) NEW met2 ( 1402770 2299420 0 ) ( 1404610 2299420 ) NEW met2 ( 1404610 2299420 ) ( 1404610 2300100 ) @@ -72521,10 +74467,35 @@ NEW met2 ( 1344810 2299420 ) ( 1344810 2491010 ) NEW met1 ( 1344810 2491010 ) ( 2900990 2491010 ) NEW met1 ( 1344810 2491010 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d NEW met1 ( 2900990 2491010 ) M1M2_PR NEW met2 ( 2900990 2493220 ) via2_FR + USE SIGNAL ; - io_out[11] ( PIN io_out[11] ) ( mprj io_out[11] ) +<<<<<<< HEAD + + ROUTED met2 ( 2617630 2691100 ) ( 2618550 2691100 ) + NEW met2 ( 2617630 2691100 ) ( 2617630 2725610 ) + NEW met2 ( 2900990 2725610 ) ( 2900990 2727820 ) + NEW met3 ( 2900990 2727820 ) ( 2917780 2727820 0 ) + NEW met3 ( 2609580 2559860 0 ) ( 2618550 2559860 ) + NEW met2 ( 2618550 2559860 ) ( 2618550 2691100 ) + NEW met1 ( 2617630 2725610 ) ( 2900990 2725610 ) + NEW met1 ( 2617630 2725610 ) M1M2_PR + NEW met1 ( 2900990 2725610 ) M1M2_PR + NEW met2 ( 2900990 2727820 ) via2_FR + NEW met2 ( 2618550 2559860 ) via2_FR ++ USE SIGNAL ; +- io_out[12] ( PIN io_out[12] ) ( mprj io_out[12] ) + + ROUTED met3 ( 2609580 2759780 0 ) ( 2618550 2759780 ) + NEW met2 ( 2618550 2759780 ) ( 2618550 2960210 ) + NEW met2 ( 2899150 2960210 ) ( 2899150 2962420 ) + NEW met3 ( 2899150 2962420 ) ( 2917780 2962420 0 ) + NEW met1 ( 2618550 2960210 ) ( 2899150 2960210 ) + NEW met2 ( 2618550 2759780 ) via2_FR + NEW met1 ( 2618550 2960210 ) M1M2_PR + NEW met1 ( 2899150 2960210 ) M1M2_PR + NEW met2 ( 2899150 2962420 ) via2_FR +======= + ROUTED met2 ( 2900990 2725950 ) ( 2900990 2727820 ) NEW met3 ( 2900990 2727820 ) ( 2917780 2727820 0 ) NEW met2 ( 1360910 2299420 0 ) ( 1360910 2313190 ) @@ -72548,10 +74519,739 @@ NEW met1 ( 1379770 2960210 ) M1M2_PR NEW met1 ( 2900990 2960210 ) M1M2_PR NEW met2 ( 2900990 2962420 ) via2_FR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - io_out[13] ( PIN io_out[13] ) ( mprj io_out[13] ) + ROUTED met2 ( 2900990 3194810 ) ( 2900990 3197020 ) NEW met3 ( 2900990 3197020 ) ( 2917780 3197020 0 ) +<<<<<<< HEAD + NEW met3 ( 2609580 2959700 0 ) ( 2619010 2959700 ) + NEW met2 ( 2619010 2959700 ) ( 2619010 3194810 ) + NEW met1 ( 2619010 3194810 ) ( 2900990 3194810 ) + NEW met1 ( 2619010 3194810 ) M1M2_PR + NEW met1 ( 2900990 3194810 ) M1M2_PR + NEW met2 ( 2900990 3197020 ) via2_FR + NEW met2 ( 2619010 2959700 ) via2_FR ++ USE SIGNAL ; +- io_out[14] ( PIN io_out[14] ) ( mprj io_out[14] ) + + ROUTED met3 ( 2609580 3159620 0 ) ( 2618550 3159620 ) + NEW met2 ( 2618550 3159620 ) ( 2618550 3429410 ) + NEW met2 ( 2900990 3429410 ) ( 2900990 3431620 ) + NEW met3 ( 2900990 3431620 ) ( 2917780 3431620 0 ) + NEW met1 ( 2618550 3429410 ) ( 2900990 3429410 ) + NEW met2 ( 2618550 3159620 ) via2_FR + NEW met1 ( 2618550 3429410 ) M1M2_PR + NEW met1 ( 2900990 3429410 ) M1M2_PR + NEW met2 ( 2900990 3431620 ) via2_FR ++ USE SIGNAL ; +- io_out[15] ( PIN io_out[15] ) ( mprj io_out[15] ) + + ROUTED met2 ( 2717450 3501830 ) ( 2717450 3517980 0 ) + NEW met1 ( 2483770 3501830 ) ( 2717450 3501830 ) + NEW met2 ( 2481930 3259580 0 ) ( 2483770 3259580 ) + NEW met2 ( 2483770 3259580 ) ( 2483770 3501830 ) + NEW met1 ( 2717450 3501830 ) M1M2_PR + NEW met1 ( 2483770 3501830 ) M1M2_PR ++ USE SIGNAL ; +- io_out[16] ( PIN io_out[16] ) ( mprj io_out[16] ) + + ROUTED met2 ( 2226630 3259580 0 ) ( 2228470 3259580 ) + NEW met2 ( 2228470 3259580 ) ( 2228470 3501830 ) + NEW met1 ( 2228470 3501830 ) ( 2392690 3501830 ) + NEW met2 ( 2392690 3501830 ) ( 2392690 3517980 0 ) + NEW met1 ( 2228470 3501830 ) M1M2_PR + NEW met1 ( 2392690 3501830 ) M1M2_PR ++ USE SIGNAL ; +- io_out[17] ( PIN io_out[17] ) ( mprj io_out[17] ) + + ROUTED met1 ( 1973170 3501830 ) ( 2068390 3501830 ) + NEW met2 ( 1970870 3258900 0 ) ( 1973170 3258900 ) + NEW met2 ( 1973170 3258900 ) ( 1973170 3501830 ) + NEW met2 ( 2068390 3501830 ) ( 2068390 3517980 0 ) + NEW met1 ( 1973170 3501830 ) M1M2_PR + NEW met1 ( 2068390 3501830 ) M1M2_PR ++ USE SIGNAL ; +- io_out[18] ( PIN io_out[18] ) ( mprj io_out[18] ) + + ROUTED met2 ( 1744090 3501490 ) ( 1744090 3517980 0 ) + NEW met1 ( 1717870 3501490 ) ( 1744090 3501490 ) + NEW met2 ( 1715110 3258900 0 ) ( 1717870 3258900 ) + NEW met2 ( 1717870 3258900 ) ( 1717870 3501490 ) + NEW met1 ( 1744090 3501490 ) M1M2_PR + NEW met1 ( 1717870 3501490 ) M1M2_PR ++ USE SIGNAL ; +- io_out[19] ( PIN io_out[19] ) ( mprj io_out[19] ) + + ROUTED met2 ( 1459810 3259580 0 ) ( 1459810 3274030 ) + NEW met2 ( 1420250 3318740 ) ( 1421170 3318740 ) + NEW met2 ( 1420250 3274030 ) ( 1420250 3318740 ) + NEW met1 ( 1420250 3274030 ) ( 1459810 3274030 ) + NEW met1 ( 1420250 3367530 ) ( 1421170 3367530 ) + NEW met2 ( 1421170 3318740 ) ( 1421170 3367530 ) + NEW met1 ( 1419790 3443010 ) ( 1420710 3443010 ) + NEW li1 ( 1420250 3381130 ) ( 1420250 3429070 ) + NEW met1 ( 1420250 3429070 ) ( 1420710 3429070 ) + NEW met2 ( 1420250 3367530 ) ( 1420250 3381130 ) + NEW met2 ( 1420710 3429070 ) ( 1420710 3443010 ) + NEW met1 ( 1419330 3477690 ) ( 1419790 3477690 ) + NEW met2 ( 1419330 3477690 ) ( 1419330 3517980 0 ) + NEW met2 ( 1419790 3443010 ) ( 1419790 3477690 ) + NEW met1 ( 1459810 3274030 ) M1M2_PR + NEW met1 ( 1420250 3274030 ) M1M2_PR + NEW met1 ( 1421170 3367530 ) M1M2_PR + NEW met1 ( 1420250 3367530 ) M1M2_PR + NEW met1 ( 1419790 3443010 ) M1M2_PR + NEW met1 ( 1420710 3443010 ) M1M2_PR + NEW li1 ( 1420250 3381130 ) L1M1_PR_MR + NEW met1 ( 1420250 3381130 ) M1M2_PR + NEW li1 ( 1420250 3429070 ) L1M1_PR_MR + NEW met1 ( 1420710 3429070 ) M1M2_PR + NEW met1 ( 1419790 3477690 ) M1M2_PR + NEW met1 ( 1419330 3477690 ) M1M2_PR + NEW met1 ( 1420250 3381130 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- io_out[1] ( PIN io_out[1] ) ( mprj io_out[1] ) + + ROUTED met2 ( 2900990 381140 ) ( 2900990 386070 ) + NEW met3 ( 2900990 381140 ) ( 2917780 381140 0 ) + NEW met3 ( 2609580 559980 0 ) ( 2619010 559980 ) + NEW met2 ( 2619010 386070 ) ( 2619010 559980 ) + NEW met1 ( 2619010 386070 ) ( 2900990 386070 ) + NEW met1 ( 2619010 386070 ) M1M2_PR + NEW met1 ( 2900990 386070 ) M1M2_PR + NEW met2 ( 2900990 381140 ) via2_FR + NEW met2 ( 2619010 559980 ) via2_FR ++ USE SIGNAL ; +- io_out[20] ( PIN io_out[20] ) ( mprj io_out[20] ) + + ROUTED met2 ( 1204050 3259580 0 ) ( 1204050 3274370 ) + NEW met1 ( 1095490 3274370 ) ( 1204050 3274370 ) + NEW met1 ( 1095030 3346450 ) ( 1095950 3346450 ) + NEW li1 ( 1095490 3284570 ) ( 1095490 3332510 ) + NEW met1 ( 1095490 3332510 ) ( 1095950 3332510 ) + NEW met2 ( 1095490 3274370 ) ( 1095490 3284570 ) + NEW met2 ( 1095950 3332510 ) ( 1095950 3346450 ) + NEW met1 ( 1095030 3394730 ) ( 1095030 3395070 ) + NEW met1 ( 1095030 3395070 ) ( 1095490 3395070 ) + NEW met2 ( 1095030 3346450 ) ( 1095030 3394730 ) + NEW met2 ( 1095950 3477860 ) ( 1096410 3477860 ) + NEW met3 ( 1096410 3477860 ) ( 1097100 3477860 ) + NEW met3 ( 1097100 3477860 ) ( 1097100 3478540 ) + NEW met3 ( 1094570 3478540 ) ( 1097100 3478540 ) + NEW met2 ( 1094570 3478540 ) ( 1094570 3517300 ) + NEW met2 ( 1094570 3517300 ) ( 1095030 3517300 ) + NEW met2 ( 1095030 3517300 ) ( 1095030 3517980 0 ) + NEW li1 ( 1095490 3429410 ) ( 1095490 3477350 ) + NEW met1 ( 1095490 3477350 ) ( 1095950 3477350 ) + NEW met2 ( 1095490 3395070 ) ( 1095490 3429410 ) + NEW met2 ( 1095950 3477350 ) ( 1095950 3477860 ) + NEW met1 ( 1204050 3274370 ) M1M2_PR + NEW met1 ( 1095490 3274370 ) M1M2_PR + NEW met1 ( 1095030 3346450 ) M1M2_PR + NEW met1 ( 1095950 3346450 ) M1M2_PR + NEW li1 ( 1095490 3284570 ) L1M1_PR_MR + NEW met1 ( 1095490 3284570 ) M1M2_PR + NEW li1 ( 1095490 3332510 ) L1M1_PR_MR + NEW met1 ( 1095950 3332510 ) M1M2_PR + NEW met1 ( 1095030 3394730 ) M1M2_PR + NEW met1 ( 1095490 3395070 ) M1M2_PR + NEW met2 ( 1096410 3477860 ) via2_FR + NEW met2 ( 1094570 3478540 ) via2_FR + NEW li1 ( 1095490 3429410 ) L1M1_PR_MR + NEW met1 ( 1095490 3429410 ) M1M2_PR + NEW li1 ( 1095490 3477350 ) L1M1_PR_MR + NEW met1 ( 1095950 3477350 ) M1M2_PR + NEW met1 ( 1095490 3284570 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 1095490 3429410 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- io_out[21] ( PIN io_out[21] ) ( mprj io_out[21] ) + + ROUTED met2 ( 771650 3318740 ) ( 772570 3318740 ) + NEW met2 ( 771650 3274030 ) ( 771650 3318740 ) + NEW met1 ( 771650 3367530 ) ( 772570 3367530 ) + NEW met2 ( 772570 3318740 ) ( 772570 3367530 ) + NEW met1 ( 771650 3274030 ) ( 948750 3274030 ) + NEW met2 ( 948750 3259580 0 ) ( 948750 3274030 ) + NEW met1 ( 771190 3443010 ) ( 772110 3443010 ) + NEW li1 ( 771650 3381130 ) ( 771650 3429070 ) + NEW met1 ( 771650 3429070 ) ( 772110 3429070 ) + NEW met2 ( 771650 3367530 ) ( 771650 3381130 ) + NEW met2 ( 772110 3429070 ) ( 772110 3443010 ) + NEW met1 ( 770730 3477690 ) ( 771190 3477690 ) + NEW met2 ( 770730 3477690 ) ( 770730 3517980 0 ) + NEW met2 ( 771190 3443010 ) ( 771190 3477690 ) + NEW met1 ( 771650 3274030 ) M1M2_PR + NEW met1 ( 772570 3367530 ) M1M2_PR + NEW met1 ( 771650 3367530 ) M1M2_PR + NEW met1 ( 948750 3274030 ) M1M2_PR + NEW met1 ( 771190 3443010 ) M1M2_PR + NEW met1 ( 772110 3443010 ) M1M2_PR + NEW li1 ( 771650 3381130 ) L1M1_PR_MR + NEW met1 ( 771650 3381130 ) M1M2_PR + NEW li1 ( 771650 3429070 ) L1M1_PR_MR + NEW met1 ( 772110 3429070 ) M1M2_PR + NEW met1 ( 771190 3477690 ) M1M2_PR + NEW met1 ( 770730 3477690 ) M1M2_PR + NEW met1 ( 771650 3381130 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- io_out[22] ( PIN io_out[22] ) ( mprj io_out[22] ) + + ROUTED met2 ( 692990 3259580 0 ) ( 692990 3274030 ) + NEW met1 ( 445970 3498430 ) ( 448270 3498430 ) + NEW met1 ( 448270 3274030 ) ( 692990 3274030 ) + NEW met2 ( 448270 3274030 ) ( 448270 3498430 ) + NEW met2 ( 445970 3498430 ) ( 445970 3517980 0 ) + NEW met1 ( 692990 3274030 ) M1M2_PR + NEW met1 ( 448270 3274030 ) M1M2_PR + NEW met1 ( 445970 3498430 ) M1M2_PR + NEW met1 ( 448270 3498430 ) M1M2_PR ++ USE SIGNAL ; +- io_out[23] ( PIN io_out[23] ) ( mprj io_out[23] ) + + ROUTED met1 ( 121670 3498430 ) ( 123970 3498430 ) + NEW met2 ( 123970 3274030 ) ( 123970 3498430 ) + NEW met2 ( 121670 3498430 ) ( 121670 3517980 0 ) + NEW met2 ( 437690 3259580 0 ) ( 437690 3274030 ) + NEW met1 ( 123970 3274030 ) ( 437690 3274030 ) + NEW met1 ( 123970 3274030 ) M1M2_PR + NEW met1 ( 121670 3498430 ) M1M2_PR + NEW met1 ( 123970 3498430 ) M1M2_PR + NEW met1 ( 437690 3274030 ) M1M2_PR ++ USE SIGNAL ; +- io_out[24] ( PIN io_out[24] ) ( mprj io_out[24] ) + + ROUTED met3 ( 2300 3339820 0 ) ( 17250 3339820 ) + NEW met2 ( 17250 3152990 ) ( 17250 3339820 ) + NEW met2 ( 296930 3152140 ) ( 296930 3152990 ) + NEW met3 ( 296930 3152140 ) ( 310500 3152140 0 ) + NEW met1 ( 17250 3152990 ) ( 296930 3152990 ) + NEW met1 ( 17250 3152990 ) M1M2_PR + NEW met2 ( 17250 3339820 ) via2_FR + NEW met1 ( 296930 3152990 ) M1M2_PR + NEW met2 ( 296930 3152140 ) via2_FR ++ USE SIGNAL ; +- io_out[25] ( PIN io_out[25] ) ( mprj io_out[25] ) + + ROUTED met3 ( 2300 3052180 0 ) ( 17250 3052180 ) + NEW met2 ( 17250 2939130 ) ( 17250 3052180 ) + NEW met2 ( 296930 2937940 ) ( 296930 2939130 ) + NEW met3 ( 296930 2937940 ) ( 310500 2937940 0 ) + NEW met1 ( 17250 2939130 ) ( 296930 2939130 ) + NEW met1 ( 17250 2939130 ) M1M2_PR + NEW met2 ( 17250 3052180 ) via2_FR + NEW met1 ( 296930 2939130 ) M1M2_PR + NEW met2 ( 296930 2937940 ) via2_FR ++ USE SIGNAL ; +- io_out[26] ( PIN io_out[26] ) ( mprj io_out[26] ) + + ROUTED met2 ( 296930 2723740 ) ( 296930 2725270 ) + NEW met3 ( 296930 2723740 ) ( 310500 2723740 0 ) + NEW met3 ( 2300 2765220 0 ) ( 17250 2765220 ) + NEW met2 ( 17250 2725270 ) ( 17250 2765220 ) + NEW met1 ( 17250 2725270 ) ( 296930 2725270 ) + NEW met1 ( 17250 2725270 ) M1M2_PR + NEW met1 ( 296930 2725270 ) M1M2_PR + NEW met2 ( 296930 2723740 ) via2_FR + NEW met2 ( 17250 2765220 ) via2_FR ++ USE SIGNAL ; +- io_out[27] ( PIN io_out[27] ) ( mprj io_out[27] ) + + ROUTED met2 ( 296930 2504950 ) ( 296930 2509540 ) + NEW met3 ( 296930 2509540 ) ( 310500 2509540 0 ) + NEW met3 ( 2300 2477580 0 ) ( 16790 2477580 ) + NEW met2 ( 16790 2477580 ) ( 16790 2504950 ) + NEW met1 ( 16790 2504950 ) ( 296930 2504950 ) + NEW met1 ( 16790 2504950 ) M1M2_PR + NEW met1 ( 296930 2504950 ) M1M2_PR + NEW met2 ( 296930 2509540 ) via2_FR + NEW met2 ( 16790 2477580 ) via2_FR ++ USE SIGNAL ; +- io_out[28] ( PIN io_out[28] ) ( mprj io_out[28] ) + + ROUTED met3 ( 2300 2189940 0 ) ( 17710 2189940 ) + NEW met2 ( 17710 2189940 ) ( 17710 2291090 ) + NEW met2 ( 296930 2291090 ) ( 296930 2295340 ) + NEW met3 ( 296930 2295340 ) ( 310500 2295340 0 ) + NEW met1 ( 17710 2291090 ) ( 296930 2291090 ) + NEW met2 ( 17710 2189940 ) via2_FR + NEW met1 ( 17710 2291090 ) M1M2_PR + NEW met1 ( 296930 2291090 ) M1M2_PR + NEW met2 ( 296930 2295340 ) via2_FR ++ USE SIGNAL ; +- io_out[29] ( PIN io_out[29] ) ( mprj io_out[29] ) + + ROUTED met3 ( 2300 1902980 0 ) ( 17250 1902980 ) + NEW met2 ( 17250 1902980 ) ( 17250 2077230 ) + NEW met2 ( 296930 2077230 ) ( 296930 2081140 ) + NEW met3 ( 296930 2081140 ) ( 310500 2081140 0 ) + NEW met1 ( 17250 2077230 ) ( 296930 2077230 ) + NEW met2 ( 17250 1902980 ) via2_FR + NEW met1 ( 17250 2077230 ) M1M2_PR + NEW met1 ( 296930 2077230 ) M1M2_PR + NEW met2 ( 296930 2081140 ) via2_FR ++ USE SIGNAL ; +- io_out[2] ( PIN io_out[2] ) ( mprj io_out[2] ) + + ROUTED met3 ( 2609580 759900 0 ) ( 2619010 759900 ) + NEW met2 ( 2619010 620670 ) ( 2619010 759900 ) + NEW met2 ( 2900990 615740 ) ( 2900990 620670 ) + NEW met3 ( 2900990 615740 ) ( 2917780 615740 0 ) + NEW met1 ( 2619010 620670 ) ( 2900990 620670 ) + NEW met2 ( 2619010 759900 ) via2_FR + NEW met1 ( 2619010 620670 ) M1M2_PR + NEW met1 ( 2900990 620670 ) M1M2_PR + NEW met2 ( 2900990 615740 ) via2_FR ++ USE SIGNAL ; +- io_out[30] ( PIN io_out[30] ) ( mprj io_out[30] ) + + ROUTED met2 ( 296930 1863030 ) ( 296930 1866940 ) + NEW met3 ( 296930 1866940 ) ( 310500 1866940 0 ) + NEW met3 ( 2300 1615340 0 ) ( 17710 1615340 ) + NEW met2 ( 17710 1615340 ) ( 17710 1863030 ) + NEW met1 ( 17710 1863030 ) ( 296930 1863030 ) + NEW met1 ( 17710 1863030 ) M1M2_PR + NEW met1 ( 296930 1863030 ) M1M2_PR + NEW met2 ( 296930 1866940 ) via2_FR + NEW met2 ( 17710 1615340 ) via2_FR ++ USE SIGNAL ; +- io_out[31] ( PIN io_out[31] ) ( mprj io_out[31] ) + + ROUTED met2 ( 296930 1649170 ) ( 296930 1652060 ) + NEW met3 ( 296930 1652060 ) ( 310500 1652060 0 ) + NEW met3 ( 2300 1400460 0 ) ( 18170 1400460 ) + NEW met2 ( 18170 1400460 ) ( 18170 1649170 ) + NEW met1 ( 18170 1649170 ) ( 296930 1649170 ) + NEW met1 ( 18170 1649170 ) M1M2_PR + NEW met1 ( 296930 1649170 ) M1M2_PR + NEW met2 ( 296930 1652060 ) via2_FR + NEW met2 ( 18170 1400460 ) via2_FR ++ USE SIGNAL ; +- io_out[32] ( PIN io_out[32] ) ( mprj io_out[32] ) + + ROUTED met3 ( 2300 1184900 0 ) ( 17710 1184900 ) + NEW met2 ( 296930 1435310 ) ( 296930 1437860 ) + NEW met3 ( 296930 1437860 ) ( 310500 1437860 0 ) + NEW met2 ( 17710 1184900 ) ( 17710 1435310 ) + NEW met1 ( 17710 1435310 ) ( 296930 1435310 ) + NEW met2 ( 17710 1184900 ) via2_FR + NEW met1 ( 17710 1435310 ) M1M2_PR + NEW met1 ( 296930 1435310 ) M1M2_PR + NEW met2 ( 296930 1437860 ) via2_FR ++ USE SIGNAL ; +- io_out[33] ( PIN io_out[33] ) ( mprj io_out[33] ) + + ROUTED met3 ( 2300 969340 0 ) ( 17250 969340 ) + NEW met2 ( 17250 969340 ) ( 17250 1221450 ) + NEW met2 ( 296930 1221450 ) ( 296930 1223660 ) + NEW met3 ( 296930 1223660 ) ( 310500 1223660 0 ) + NEW met1 ( 17250 1221450 ) ( 296930 1221450 ) + NEW met2 ( 17250 969340 ) via2_FR + NEW met1 ( 17250 1221450 ) M1M2_PR + NEW met1 ( 296930 1221450 ) M1M2_PR + NEW met2 ( 296930 1223660 ) via2_FR ++ USE SIGNAL ; +- io_out[34] ( PIN io_out[34] ) ( mprj io_out[34] ) + + ROUTED met3 ( 2300 753780 0 ) ( 17710 753780 ) + NEW met2 ( 17710 753780 ) ( 17710 1007590 ) + NEW met2 ( 296930 1007590 ) ( 296930 1009460 ) + NEW met3 ( 296930 1009460 ) ( 310500 1009460 0 ) + NEW met1 ( 17710 1007590 ) ( 296930 1007590 ) + NEW met2 ( 17710 753780 ) via2_FR + NEW met1 ( 17710 1007590 ) M1M2_PR + NEW met1 ( 296930 1007590 ) M1M2_PR + NEW met2 ( 296930 1009460 ) via2_FR ++ USE SIGNAL ; +- io_out[35] ( PIN io_out[35] ) ( mprj io_out[35] ) + + ROUTED met2 ( 296930 793730 ) ( 296930 795260 ) + NEW met3 ( 296930 795260 ) ( 310500 795260 0 ) + NEW met3 ( 2300 538220 0 ) ( 17250 538220 ) + NEW met2 ( 17250 538220 ) ( 17250 793730 ) + NEW met1 ( 17250 793730 ) ( 296930 793730 ) + NEW met1 ( 17250 793730 ) M1M2_PR + NEW met1 ( 296930 793730 ) M1M2_PR + NEW met2 ( 296930 795260 ) via2_FR + NEW met2 ( 17250 538220 ) via2_FR ++ USE SIGNAL ; +- io_out[36] ( PIN io_out[36] ) ( mprj io_out[36] ) + + ROUTED met3 ( 2300 322660 0 ) ( 17710 322660 ) + NEW met2 ( 296930 579870 ) ( 296930 581060 ) + NEW met3 ( 296930 581060 ) ( 310500 581060 0 ) + NEW met2 ( 17710 322660 ) ( 17710 579870 ) + NEW met1 ( 17710 579870 ) ( 296930 579870 ) + NEW met2 ( 17710 322660 ) via2_FR + NEW met1 ( 17710 579870 ) M1M2_PR + NEW met1 ( 296930 579870 ) M1M2_PR + NEW met2 ( 296930 581060 ) via2_FR ++ USE SIGNAL ; +- io_out[37] ( PIN io_out[37] ) ( mprj io_out[37] ) + + ROUTED met3 ( 2300 107100 0 ) ( 17250 107100 ) + NEW met2 ( 17250 107100 ) ( 17250 366010 ) + NEW met2 ( 296930 366010 ) ( 296930 366860 ) + NEW met3 ( 296930 366860 ) ( 310500 366860 0 ) + NEW met1 ( 17250 366010 ) ( 296930 366010 ) + NEW met2 ( 17250 107100 ) via2_FR + NEW met1 ( 17250 366010 ) M1M2_PR + NEW met1 ( 296930 366010 ) M1M2_PR + NEW met2 ( 296930 366860 ) via2_FR ++ USE SIGNAL ; +- io_out[3] ( PIN io_out[3] ) ( mprj io_out[3] ) + + ROUTED met3 ( 2609580 959820 0 ) ( 2619010 959820 ) + NEW met2 ( 2619010 855270 ) ( 2619010 959820 ) + NEW met2 ( 2900990 850340 ) ( 2900990 855270 ) + NEW met3 ( 2900990 850340 ) ( 2917780 850340 0 ) + NEW met1 ( 2619010 855270 ) ( 2900990 855270 ) + NEW met2 ( 2619010 959820 ) via2_FR + NEW met1 ( 2619010 855270 ) M1M2_PR + NEW met1 ( 2900990 855270 ) M1M2_PR + NEW met2 ( 2900990 850340 ) via2_FR ++ USE SIGNAL ; +- io_out[4] ( PIN io_out[4] ) ( mprj io_out[4] ) + + ROUTED met3 ( 2609580 1159740 0 ) ( 2619010 1159740 ) + NEW met2 ( 2900990 1084940 ) ( 2900990 1089870 ) + NEW met3 ( 2900990 1084940 ) ( 2917780 1084940 0 ) + NEW met2 ( 2619010 1089870 ) ( 2619010 1159740 ) + NEW met1 ( 2619010 1089870 ) ( 2900990 1089870 ) + NEW met1 ( 2619010 1089870 ) M1M2_PR + NEW met2 ( 2619010 1159740 ) via2_FR + NEW met1 ( 2900990 1089870 ) M1M2_PR + NEW met2 ( 2900990 1084940 ) via2_FR ++ USE SIGNAL ; +- io_out[5] ( PIN io_out[5] ) ( mprj io_out[5] ) + + ROUTED met3 ( 2609580 1359660 0 ) ( 2618550 1359660 ) + NEW met2 ( 2618550 1324470 ) ( 2618550 1359660 ) + NEW met2 ( 2900990 1319540 ) ( 2900990 1324470 ) + NEW met3 ( 2900990 1319540 ) ( 2917780 1319540 0 ) + NEW met1 ( 2618550 1324470 ) ( 2900990 1324470 ) + NEW met2 ( 2618550 1359660 ) via2_FR + NEW met1 ( 2618550 1324470 ) M1M2_PR + NEW met1 ( 2900990 1324470 ) M1M2_PR + NEW met2 ( 2900990 1319540 ) via2_FR ++ USE SIGNAL ; +- io_out[6] ( PIN io_out[6] ) ( mprj io_out[6] ) + + ROUTED met3 ( 2609580 1559580 0 ) ( 2621770 1559580 ) + NEW met2 ( 2621770 1559070 ) ( 2621770 1559580 ) + NEW met2 ( 2900990 1554140 ) ( 2900990 1559070 ) + NEW met3 ( 2900990 1554140 ) ( 2917780 1554140 0 ) + NEW met1 ( 2621770 1559070 ) ( 2900990 1559070 ) + NEW met2 ( 2621770 1559580 ) via2_FR + NEW met1 ( 2621770 1559070 ) M1M2_PR + NEW met1 ( 2900990 1559070 ) M1M2_PR + NEW met2 ( 2900990 1554140 ) via2_FR ++ USE SIGNAL ; +- io_out[7] ( PIN io_out[7] ) ( mprj io_out[7] ) + + ROUTED met3 ( 2609580 1759500 0 ) ( 2618550 1759500 ) + NEW met2 ( 2618550 1759500 ) ( 2618550 1787210 ) + NEW met2 ( 2900990 1787210 ) ( 2900990 1789420 ) + NEW met3 ( 2900990 1789420 ) ( 2917780 1789420 0 ) + NEW met1 ( 2618550 1787210 ) ( 2900990 1787210 ) + NEW met2 ( 2618550 1759500 ) via2_FR + NEW met1 ( 2618550 1787210 ) M1M2_PR + NEW met1 ( 2900990 1787210 ) M1M2_PR + NEW met2 ( 2900990 1789420 ) via2_FR ++ USE SIGNAL ; +- io_out[8] ( PIN io_out[8] ) ( mprj io_out[8] ) + + ROUTED met3 ( 2609580 1960100 0 ) ( 2619010 1960100 ) + NEW met2 ( 2900990 2021810 ) ( 2900990 2024020 ) + NEW met3 ( 2900990 2024020 ) ( 2917780 2024020 0 ) + NEW met2 ( 2619010 1960100 ) ( 2619010 2021810 ) + NEW met1 ( 2619010 2021810 ) ( 2900990 2021810 ) + NEW met2 ( 2619010 1960100 ) via2_FR + NEW met1 ( 2619010 2021810 ) M1M2_PR + NEW met1 ( 2900990 2021810 ) M1M2_PR + NEW met2 ( 2900990 2024020 ) via2_FR ++ USE SIGNAL ; +- io_out[9] ( PIN io_out[9] ) ( mprj io_out[9] ) + + ROUTED met3 ( 2609580 2160020 0 ) ( 2619010 2160020 ) + NEW met2 ( 2619010 2160020 ) ( 2619010 2256410 ) + NEW met2 ( 2900990 2256410 ) ( 2900990 2258620 ) + NEW met3 ( 2900990 2258620 ) ( 2917780 2258620 0 ) + NEW met1 ( 2619010 2256410 ) ( 2900990 2256410 ) + NEW met2 ( 2619010 2160020 ) via2_FR + NEW met1 ( 2619010 2256410 ) M1M2_PR + NEW met1 ( 2900990 2256410 ) M1M2_PR + NEW met2 ( 2900990 2258620 ) via2_FR ++ USE SIGNAL ; +- la_data_in[0] ( PIN la_data_in[0] ) ( mprj la_data_in[0] ) + + ROUTED met2 ( 633190 2380 0 ) ( 633190 24310 ) + NEW met1 ( 330970 24310 ) ( 633190 24310 ) + NEW met1 ( 324530 243610 ) ( 330970 243610 ) + NEW met2 ( 324530 243610 ) ( 324530 260100 0 ) + NEW met2 ( 330970 24310 ) ( 330970 243610 ) + NEW met1 ( 330970 24310 ) M1M2_PR + NEW met1 ( 633190 24310 ) M1M2_PR + NEW met1 ( 330970 243610 ) M1M2_PR + NEW met1 ( 324530 243610 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[100] ( PIN la_data_in[100] ) ( mprj la_data_in[100] ) + + ROUTED met1 ( 2112090 241570 ) ( 2118070 241570 ) + NEW met2 ( 2112090 241570 ) ( 2112090 260100 0 ) + NEW met2 ( 2118070 37910 ) ( 2118070 241570 ) + NEW met2 ( 2417530 2380 0 ) ( 2417530 37910 ) + NEW met1 ( 2118070 37910 ) ( 2417530 37910 ) + NEW met1 ( 2118070 37910 ) M1M2_PR + NEW met1 ( 2118070 241570 ) M1M2_PR + NEW met1 ( 2112090 241570 ) M1M2_PR + NEW met1 ( 2417530 37910 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[101] ( PIN la_data_in[101] ) ( mprj la_data_in[101] ) + + ROUTED met2 ( 2435010 2380 0 ) ( 2435010 30770 ) + NEW met2 ( 2130030 260100 0 ) ( 2131870 260100 ) + NEW met2 ( 2131870 30770 ) ( 2131870 260100 ) + NEW met1 ( 2131870 30770 ) ( 2435010 30770 ) + NEW met1 ( 2131870 30770 ) M1M2_PR + NEW met1 ( 2435010 30770 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[102] ( PIN la_data_in[102] ) ( mprj la_data_in[102] ) + + ROUTED met1 ( 2147970 243950 ) ( 2152570 243950 ) + NEW met2 ( 2147970 243950 ) ( 2147970 260100 0 ) + NEW met2 ( 2452950 2380 0 ) ( 2452950 44710 ) + NEW met2 ( 2152570 44710 ) ( 2152570 243950 ) + NEW met1 ( 2152570 44710 ) ( 2452950 44710 ) + NEW met1 ( 2152570 243950 ) M1M2_PR + NEW met1 ( 2147970 243950 ) M1M2_PR + NEW met1 ( 2452950 44710 ) M1M2_PR + NEW met1 ( 2152570 44710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[103] ( PIN la_data_in[103] ) ( mprj la_data_in[103] ) + + ROUTED met2 ( 2470890 2380 0 ) ( 2470890 17340 ) + NEW met2 ( 2470430 17340 ) ( 2470890 17340 ) + NEW met2 ( 2166370 237830 ) ( 2166370 260100 ) + NEW met2 ( 2165910 260100 0 ) ( 2166370 260100 ) + NEW met1 ( 2166370 237830 ) ( 2470430 237830 ) + NEW met2 ( 2470430 17340 ) ( 2470430 237830 ) + NEW met1 ( 2166370 237830 ) M1M2_PR + NEW met1 ( 2470430 237830 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[104] ( PIN la_data_in[104] ) ( mprj la_data_in[104] ) + + ROUTED met2 ( 2488830 2380 0 ) ( 2488830 17340 ) + NEW met2 ( 2484230 17340 ) ( 2488830 17340 ) + NEW met2 ( 2183850 231030 ) ( 2183850 260100 0 ) + NEW met1 ( 2183850 231030 ) ( 2484230 231030 ) + NEW met2 ( 2484230 17340 ) ( 2484230 231030 ) + NEW met1 ( 2183850 231030 ) M1M2_PR + NEW met1 ( 2484230 231030 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[105] ( PIN la_data_in[105] ) ( mprj la_data_in[105] ) + + ROUTED met2 ( 2506310 2380 0 ) ( 2506310 4420 ) + NEW met2 ( 2504930 4420 ) ( 2506310 4420 ) + NEW met2 ( 2504930 4420 ) ( 2504930 51850 ) + NEW met1 ( 2201790 243950 ) ( 2207770 243950 ) + NEW met2 ( 2201790 243950 ) ( 2201790 260100 0 ) + NEW met2 ( 2207770 51850 ) ( 2207770 243950 ) + NEW met1 ( 2207770 51850 ) ( 2504930 51850 ) + NEW met1 ( 2504930 51850 ) M1M2_PR + NEW met1 ( 2207770 51850 ) M1M2_PR + NEW met1 ( 2207770 243950 ) M1M2_PR + NEW met1 ( 2201790 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[106] ( PIN la_data_in[106] ) ( mprj la_data_in[106] ) + + ROUTED met2 ( 2524250 2380 0 ) ( 2524250 16660 ) + NEW met2 ( 2518730 16660 ) ( 2524250 16660 ) + NEW met2 ( 2219730 260100 0 ) ( 2221570 260100 ) + NEW met2 ( 2221570 58650 ) ( 2221570 260100 ) + NEW met2 ( 2518730 16660 ) ( 2518730 58650 ) + NEW met1 ( 2221570 58650 ) ( 2518730 58650 ) + NEW met1 ( 2221570 58650 ) M1M2_PR + NEW met1 ( 2518730 58650 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[107] ( PIN la_data_in[107] ) ( mprj la_data_in[107] ) + + ROUTED met2 ( 2542190 2380 0 ) ( 2542190 16660 ) + NEW met2 ( 2539430 16660 ) ( 2542190 16660 ) + NEW met1 ( 2237210 243950 ) ( 2242270 243950 ) + NEW met2 ( 2237210 243950 ) ( 2237210 260100 0 ) + NEW met2 ( 2242270 65450 ) ( 2242270 243950 ) + NEW met2 ( 2539430 16660 ) ( 2539430 65450 ) + NEW met1 ( 2242270 65450 ) ( 2539430 65450 ) + NEW met1 ( 2242270 65450 ) M1M2_PR + NEW met1 ( 2242270 243950 ) M1M2_PR + NEW met1 ( 2237210 243950 ) M1M2_PR + NEW met1 ( 2539430 65450 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[108] ( PIN la_data_in[108] ) ( mprj la_data_in[108] ) + + ROUTED met2 ( 2255150 260100 0 ) ( 2256070 260100 ) + NEW met2 ( 2256070 224230 ) ( 2256070 260100 ) + NEW met1 ( 2256070 224230 ) ( 2560130 224230 ) + NEW met2 ( 2560130 2380 0 ) ( 2560130 224230 ) + NEW met1 ( 2256070 224230 ) M1M2_PR + NEW met1 ( 2560130 224230 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[109] ( PIN la_data_in[109] ) ( mprj la_data_in[109] ) + + ROUTED met2 ( 2578070 2380 0 ) ( 2578070 25330 ) + NEW met1 ( 2276770 25330 ) ( 2578070 25330 ) + NEW met2 ( 2273090 260100 0 ) ( 2276770 260100 ) + NEW met2 ( 2276770 25330 ) ( 2276770 260100 ) + NEW met1 ( 2276770 25330 ) M1M2_PR + NEW met1 ( 2578070 25330 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[10] ( PIN la_data_in[10] ) ( mprj la_data_in[10] ) + + ROUTED met2 ( 503010 260100 ) ( 503470 260100 0 ) + NEW met2 ( 503010 30770 ) ( 503010 260100 ) + NEW met2 ( 811670 2380 0 ) ( 811670 30770 ) + NEW met1 ( 503010 30770 ) ( 811670 30770 ) + NEW met1 ( 503010 30770 ) M1M2_PR + NEW met1 ( 811670 30770 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[110] ( PIN la_data_in[110] ) ( mprj la_data_in[110] ) + + ROUTED met2 ( 2595550 2380 0 ) ( 2595550 24310 ) + NEW met1 ( 2297470 24310 ) ( 2595550 24310 ) + NEW met1 ( 2291030 243950 ) ( 2297470 243950 ) + NEW met2 ( 2291030 243950 ) ( 2291030 260100 0 ) + NEW met2 ( 2297470 24310 ) ( 2297470 243950 ) + NEW met1 ( 2595550 24310 ) M1M2_PR + NEW met1 ( 2297470 24310 ) M1M2_PR + NEW met1 ( 2297470 243950 ) M1M2_PR + NEW met1 ( 2291030 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[111] ( PIN la_data_in[111] ) ( mprj la_data_in[111] ) + + ROUTED met2 ( 2613490 2380 0 ) ( 2613490 24650 ) + NEW met2 ( 2308970 260100 0 ) ( 2311270 260100 ) + NEW met2 ( 2311270 24650 ) ( 2311270 260100 ) + NEW met1 ( 2311270 24650 ) ( 2613490 24650 ) + NEW met1 ( 2311270 24650 ) M1M2_PR + NEW met1 ( 2613490 24650 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[112] ( PIN la_data_in[112] ) ( mprj la_data_in[112] ) + + ROUTED met2 ( 2631430 2380 0 ) ( 2631430 24990 ) + NEW met1 ( 2326910 243950 ) ( 2331970 243950 ) + NEW met2 ( 2326910 243950 ) ( 2326910 260100 0 ) + NEW met2 ( 2331970 24990 ) ( 2331970 243950 ) + NEW met1 ( 2331970 24990 ) ( 2631430 24990 ) + NEW met1 ( 2331970 24990 ) M1M2_PR + NEW met1 ( 2631430 24990 ) M1M2_PR + NEW met1 ( 2331970 243950 ) M1M2_PR + NEW met1 ( 2326910 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[113] ( PIN la_data_in[113] ) ( mprj la_data_in[113] ) + + ROUTED met2 ( 2344850 260100 0 ) ( 2345770 260100 ) + NEW met2 ( 2345770 72250 ) ( 2345770 260100 ) + NEW met2 ( 2649370 2380 0 ) ( 2649370 18870 ) + NEW met1 ( 2643390 18870 ) ( 2649370 18870 ) + NEW met1 ( 2345770 72250 ) ( 2643390 72250 ) + NEW met2 ( 2643390 18870 ) ( 2643390 72250 ) + NEW met1 ( 2345770 72250 ) M1M2_PR + NEW met1 ( 2649370 18870 ) M1M2_PR + NEW met1 ( 2643390 18870 ) M1M2_PR + NEW met1 ( 2643390 72250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[114] ( PIN la_data_in[114] ) ( mprj la_data_in[114] ) + + ROUTED met2 ( 2667310 2380 0 ) ( 2667310 17340 ) + NEW met2 ( 2663630 17340 ) ( 2667310 17340 ) + NEW met1 ( 2370150 217090 ) ( 2663630 217090 ) + NEW met1 ( 2362330 243610 ) ( 2370150 243610 ) + NEW met2 ( 2362330 243610 ) ( 2362330 260100 0 ) + NEW met2 ( 2370150 217090 ) ( 2370150 243610 ) + NEW met2 ( 2663630 17340 ) ( 2663630 217090 ) + NEW met1 ( 2370150 217090 ) M1M2_PR + NEW met1 ( 2663630 217090 ) M1M2_PR + NEW met1 ( 2370150 243610 ) M1M2_PR + NEW met1 ( 2362330 243610 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[115] ( PIN la_data_in[115] ) ( mprj la_data_in[115] ) + + ROUTED met2 ( 2684790 2380 0 ) ( 2684790 23970 ) + NEW met1 ( 2380270 23970 ) ( 2684790 23970 ) + NEW met2 ( 2380270 23970 ) ( 2380270 260100 0 ) + NEW met1 ( 2380270 23970 ) M1M2_PR + NEW met1 ( 2684790 23970 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[116] ( PIN la_data_in[116] ) ( mprj la_data_in[116] ) + + ROUTED met2 ( 2702730 2380 0 ) ( 2702730 26690 ) + NEW met1 ( 2400970 26690 ) ( 2702730 26690 ) + NEW met2 ( 2398210 260100 0 ) ( 2400970 260100 ) + NEW met2 ( 2400970 26690 ) ( 2400970 260100 ) + NEW met1 ( 2702730 26690 ) M1M2_PR + NEW met1 ( 2400970 26690 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[117] ( PIN la_data_in[117] ) ( mprj la_data_in[117] ) + + ROUTED met2 ( 2720670 2380 0 ) ( 2720670 26350 ) + NEW met1 ( 2416150 243950 ) ( 2421670 243950 ) + NEW met2 ( 2416150 243950 ) ( 2416150 260100 0 ) + NEW met2 ( 2421670 26350 ) ( 2421670 243950 ) + NEW met1 ( 2421670 26350 ) ( 2720670 26350 ) + NEW met1 ( 2421670 26350 ) M1M2_PR + NEW met1 ( 2720670 26350 ) M1M2_PR + NEW met1 ( 2421670 243950 ) M1M2_PR + NEW met1 ( 2416150 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[118] ( PIN la_data_in[118] ) ( mprj la_data_in[118] ) + + ROUTED met2 ( 2738610 2380 0 ) ( 2738610 26010 ) + NEW met2 ( 2434090 260100 0 ) ( 2435470 260100 ) + NEW met2 ( 2435470 26010 ) ( 2435470 260100 ) + NEW met1 ( 2435470 26010 ) ( 2738610 26010 ) + NEW met1 ( 2435470 26010 ) M1M2_PR + NEW met1 ( 2738610 26010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[119] ( PIN la_data_in[119] ) ( mprj la_data_in[119] ) + + ROUTED met2 ( 2756090 2380 0 ) ( 2756090 17340 ) + NEW met2 ( 2753330 17340 ) ( 2756090 17340 ) + NEW met2 ( 2452030 238170 ) ( 2452030 260100 0 ) + NEW met1 ( 2452030 238170 ) ( 2753330 238170 ) + NEW met2 ( 2753330 17340 ) ( 2753330 238170 ) + NEW met1 ( 2452030 238170 ) M1M2_PR + NEW met1 ( 2753330 238170 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[11] ( PIN la_data_in[11] ) ( mprj la_data_in[11] ) + + ROUTED met2 ( 521410 260100 0 ) ( 524170 260100 ) + NEW met2 ( 524170 38250 ) ( 524170 260100 ) + NEW met1 ( 524170 38250 ) ( 829610 38250 ) + NEW met2 ( 829610 2380 0 ) ( 829610 38250 ) + NEW met1 ( 524170 38250 ) M1M2_PR + NEW met1 ( 829610 38250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[120] ( PIN la_data_in[120] ) ( mprj la_data_in[120] ) + + ROUTED met1 ( 2469510 210290 ) ( 2774030 210290 ) + NEW met2 ( 2469510 260100 ) ( 2469970 260100 0 ) + NEW met2 ( 2469510 210290 ) ( 2469510 260100 ) + NEW met2 ( 2774030 2380 0 ) ( 2774030 210290 ) + NEW met1 ( 2469510 210290 ) M1M2_PR + NEW met1 ( 2774030 210290 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[121] ( PIN la_data_in[121] ) ( mprj la_data_in[121] ) + + ROUTED met2 ( 2791970 2380 0 ) ( 2791970 2890 ) + NEW met1 ( 2787830 2890 ) ( 2791970 2890 ) + NEW met2 ( 2787830 2890 ) ( 2787830 231030 ) + NEW met2 ( 2487450 231030 ) ( 2487450 260100 0 ) + NEW met1 ( 2487450 231030 ) ( 2787830 231030 ) + NEW met1 ( 2791970 2890 ) M1M2_PR + NEW met1 ( 2787830 2890 ) M1M2_PR + NEW met1 ( 2787830 231030 ) M1M2_PR + NEW met1 ( 2487450 231030 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[122] ( PIN la_data_in[122] ) ( mprj la_data_in[122] ) + + ROUTED met2 ( 2809910 2380 0 ) ( 2809910 30770 ) + NEW met1 ( 2505390 243950 ) ( 2511370 243950 ) + NEW met2 ( 2505390 243950 ) ( 2505390 260100 0 ) + NEW met2 ( 2511370 30770 ) ( 2511370 243950 ) + NEW met1 ( 2511370 30770 ) ( 2809910 30770 ) + NEW met1 ( 2511370 30770 ) M1M2_PR + NEW met1 ( 2809910 30770 ) M1M2_PR + NEW met1 ( 2511370 243950 ) M1M2_PR + NEW met1 ( 2505390 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[123] ( PIN la_data_in[123] ) ( mprj la_data_in[123] ) + + ROUTED met2 ( 2827850 2380 0 ) ( 2827850 2890 ) + NEW met1 ( 2822330 2890 ) ( 2827850 2890 ) + NEW met2 ( 2523330 260100 0 ) ( 2525170 260100 ) + NEW met2 ( 2525170 79390 ) ( 2525170 260100 ) + NEW met2 ( 2822330 2890 ) ( 2822330 79390 ) + NEW met1 ( 2525170 79390 ) ( 2822330 79390 ) + NEW met1 ( 2827850 2890 ) M1M2_PR + NEW met1 ( 2822330 2890 ) M1M2_PR + NEW met1 ( 2525170 79390 ) M1M2_PR + NEW met1 ( 2822330 79390 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[124] ( PIN la_data_in[124] ) ( mprj la_data_in[124] ) + + ROUTED met1 ( 2541270 243950 ) ( 2545870 243950 ) + NEW met2 ( 2541270 243950 ) ( 2541270 260100 0 ) + NEW met2 ( 2545870 224570 ) ( 2545870 243950 ) + NEW met2 ( 2845330 2380 0 ) ( 2845330 6460 ) + NEW met2 ( 2843030 6460 ) ( 2845330 6460 ) + NEW met1 ( 2545870 224570 ) ( 2843030 224570 ) + NEW met2 ( 2843030 6460 ) ( 2843030 224570 ) + NEW met1 ( 2545870 224570 ) M1M2_PR + NEW met1 ( 2545870 243950 ) M1M2_PR + NEW met1 ( 2541270 243950 ) M1M2_PR + NEW met1 ( 2843030 224570 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[125] ( PIN la_data_in[125] ) ( mprj la_data_in[125] ) + + ROUTED met2 ( 2863270 2380 0 ) ( 2863270 17510 ) + NEW met1 ( 2857290 17510 ) ( 2863270 17510 ) + NEW met1 ( 2559210 196690 ) ( 2857290 196690 ) + NEW met2 ( 2559210 196690 ) ( 2559210 260100 0 ) + NEW met2 ( 2857290 17510 ) ( 2857290 196690 ) + NEW met1 ( 2559210 196690 ) M1M2_PR + NEW met1 ( 2863270 17510 ) M1M2_PR + NEW met1 ( 2857290 17510 ) M1M2_PR + NEW met1 ( 2857290 196690 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[126] ( PIN la_data_in[126] ) ( mprj la_data_in[126] ) + + ROUTED met2 ( 2881210 2380 0 ) ( 2881210 17340 ) + NEW met2 ( 2877530 17340 ) ( 2881210 17340 ) + NEW met2 ( 2577150 260100 0 ) ( 2580370 260100 ) + NEW met2 ( 2580370 51510 ) ( 2580370 260100 ) + NEW met1 ( 2580370 51510 ) ( 2877530 51510 ) + NEW met2 ( 2877530 17340 ) ( 2877530 51510 ) + NEW met1 ( 2580370 51510 ) M1M2_PR + NEW met1 ( 2877530 51510 ) M1M2_PR +======= NEW met2 ( 1392190 2299420 0 ) ( 1393110 2299420 ) NEW met2 ( 1393110 2299420 ) ( 1393110 3194810 ) NEW met1 ( 1393110 3194810 ) ( 2900990 3194810 ) @@ -74816,10 +77516,679 @@ NEW met1 ( 1776750 879750 ) M1M2_PR NEW met1 ( 1776750 1684870 ) M1M2_PR NEW met1 ( 1767550 1684870 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - la_data_in[127] ( PIN la_data_in[127] ) ( mprj la_data_in[127] ) + ROUTED met2 ( 2899150 2380 0 ) ( 2899150 17510 ) NEW met1 ( 2894550 17510 ) ( 2899150 17510 ) +<<<<<<< HEAD + NEW met1 ( 2595090 243950 ) ( 2600610 243950 ) + NEW met2 ( 2595090 243950 ) ( 2595090 260100 0 ) + NEW met2 ( 2600610 189550 ) ( 2600610 243950 ) + NEW met2 ( 2894550 17510 ) ( 2894550 189550 ) + NEW met1 ( 2600610 189550 ) ( 2894550 189550 ) + NEW met1 ( 2600610 189550 ) M1M2_PR + NEW met1 ( 2899150 17510 ) M1M2_PR + NEW met1 ( 2894550 17510 ) M1M2_PR + NEW met1 ( 2894550 189550 ) M1M2_PR + NEW met1 ( 2600610 243950 ) M1M2_PR + NEW met1 ( 2595090 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[12] ( PIN la_data_in[12] ) ( mprj la_data_in[12] ) + + ROUTED met1 ( 539350 243950 ) ( 544870 243950 ) + NEW met2 ( 539350 243950 ) ( 539350 260100 0 ) + NEW met2 ( 544870 44710 ) ( 544870 243950 ) + NEW met1 ( 544870 44710 ) ( 847090 44710 ) + NEW met2 ( 847090 2380 0 ) ( 847090 44710 ) + NEW met1 ( 544870 44710 ) M1M2_PR + NEW met1 ( 544870 243950 ) M1M2_PR + NEW met1 ( 539350 243950 ) M1M2_PR + NEW met1 ( 847090 44710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[13] ( PIN la_data_in[13] ) ( mprj la_data_in[13] ) + + ROUTED met2 ( 865030 2380 0 ) ( 865030 16660 ) + NEW met2 ( 862730 16660 ) ( 865030 16660 ) + NEW met2 ( 862730 16660 ) ( 862730 51510 ) + NEW met2 ( 557290 260100 0 ) ( 558670 260100 ) + NEW met2 ( 558670 51510 ) ( 558670 260100 ) + NEW met1 ( 558670 51510 ) ( 862730 51510 ) + NEW met1 ( 862730 51510 ) M1M2_PR + NEW met1 ( 558670 51510 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[14] ( PIN la_data_in[14] ) ( mprj la_data_in[14] ) + + ROUTED met2 ( 882970 2380 0 ) ( 882970 16490 ) + NEW met1 ( 876990 16490 ) ( 882970 16490 ) + NEW met1 ( 574770 243950 ) ( 579370 243950 ) + NEW met2 ( 574770 243950 ) ( 574770 260100 0 ) + NEW met2 ( 579370 58650 ) ( 579370 243950 ) + NEW met2 ( 876990 16490 ) ( 876990 58650 ) + NEW met1 ( 579370 58650 ) ( 876990 58650 ) + NEW met1 ( 882970 16490 ) M1M2_PR + NEW met1 ( 876990 16490 ) M1M2_PR + NEW met1 ( 579370 58650 ) M1M2_PR + NEW met1 ( 579370 243950 ) M1M2_PR + NEW met1 ( 574770 243950 ) M1M2_PR + NEW met1 ( 876990 58650 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[15] ( PIN la_data_in[15] ) ( mprj la_data_in[15] ) + + ROUTED met2 ( 900910 2380 0 ) ( 900910 16660 ) + NEW met2 ( 897230 16660 ) ( 900910 16660 ) + NEW met2 ( 592710 65450 ) ( 592710 260100 0 ) + NEW met2 ( 897230 16660 ) ( 897230 65450 ) + NEW met1 ( 592710 65450 ) ( 897230 65450 ) + NEW met1 ( 592710 65450 ) M1M2_PR + NEW met1 ( 897230 65450 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[16] ( PIN la_data_in[16] ) ( mprj la_data_in[16] ) + + ROUTED met2 ( 610650 260100 0 ) ( 613870 260100 ) + NEW met2 ( 613870 72250 ) ( 613870 260100 ) + NEW met2 ( 918850 2380 0 ) ( 918850 17340 ) + NEW met2 ( 918390 17340 ) ( 918850 17340 ) + NEW met1 ( 613870 72250 ) ( 918390 72250 ) + NEW met2 ( 918390 17340 ) ( 918390 72250 ) + NEW met1 ( 613870 72250 ) M1M2_PR + NEW met1 ( 918390 72250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[17] ( PIN la_data_in[17] ) ( mprj la_data_in[17] ) + + ROUTED met2 ( 936330 2380 0 ) ( 936330 16660 ) + NEW met2 ( 931730 16660 ) ( 936330 16660 ) + NEW met1 ( 628590 243270 ) ( 634570 243270 ) + NEW met2 ( 628590 243270 ) ( 628590 260100 0 ) + NEW met2 ( 634570 79730 ) ( 634570 243270 ) + NEW met1 ( 634570 79730 ) ( 931730 79730 ) + NEW met2 ( 931730 16660 ) ( 931730 79730 ) + NEW met1 ( 634570 79730 ) M1M2_PR + NEW met1 ( 634570 243270 ) M1M2_PR + NEW met1 ( 628590 243270 ) M1M2_PR + NEW met1 ( 931730 79730 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[18] ( PIN la_data_in[18] ) ( mprj la_data_in[18] ) + + ROUTED met2 ( 954270 2380 0 ) ( 954270 16660 ) + NEW met2 ( 952430 16660 ) ( 954270 16660 ) + NEW met2 ( 952430 16660 ) ( 952430 86190 ) + NEW met1 ( 648370 86190 ) ( 952430 86190 ) + NEW met2 ( 646530 260100 0 ) ( 648370 260100 ) + NEW met2 ( 648370 86190 ) ( 648370 260100 ) + NEW met1 ( 952430 86190 ) M1M2_PR + NEW met1 ( 648370 86190 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[19] ( PIN la_data_in[19] ) ( mprj la_data_in[19] ) + + ROUTED met2 ( 972210 2380 0 ) ( 972210 24650 ) + NEW met1 ( 664470 243950 ) ( 669070 243950 ) + NEW met2 ( 664470 243950 ) ( 664470 260100 0 ) + NEW met2 ( 669070 24650 ) ( 669070 243950 ) + NEW met1 ( 669070 24650 ) ( 972210 24650 ) + NEW met1 ( 669070 24650 ) M1M2_PR + NEW met1 ( 972210 24650 ) M1M2_PR + NEW met1 ( 669070 243950 ) M1M2_PR + NEW met1 ( 664470 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[1] ( PIN la_data_in[1] ) ( mprj la_data_in[1] ) + + ROUTED met2 ( 651130 2380 0 ) ( 651130 23970 ) + NEW met1 ( 344770 23970 ) ( 651130 23970 ) + NEW met2 ( 342470 260100 0 ) ( 344770 260100 ) + NEW met2 ( 344770 23970 ) ( 344770 260100 ) + NEW met1 ( 344770 23970 ) M1M2_PR + NEW met1 ( 651130 23970 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[20] ( PIN la_data_in[20] ) ( mprj la_data_in[20] ) + + ROUTED met2 ( 990150 2380 0 ) ( 990150 16660 ) + NEW met2 ( 986930 16660 ) ( 990150 16660 ) + NEW met2 ( 682870 237830 ) ( 682870 260100 ) + NEW met2 ( 682410 260100 0 ) ( 682870 260100 ) + NEW met2 ( 986930 16660 ) ( 986930 237830 ) + NEW met1 ( 682870 237830 ) ( 986930 237830 ) + NEW met1 ( 682870 237830 ) M1M2_PR + NEW met1 ( 986930 237830 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[21] ( PIN la_data_in[21] ) ( mprj la_data_in[21] ) + + ROUTED met2 ( 699890 260100 0 ) ( 703570 260100 ) + NEW met2 ( 703570 92990 ) ( 703570 260100 ) + NEW met2 ( 1007630 2380 0 ) ( 1007630 17340 ) + NEW met2 ( 1007630 17340 ) ( 1008090 17340 ) + NEW met1 ( 703570 92990 ) ( 1008090 92990 ) + NEW met2 ( 1008090 17340 ) ( 1008090 92990 ) + NEW met1 ( 703570 92990 ) M1M2_PR + NEW met1 ( 1008090 92990 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[22] ( PIN la_data_in[22] ) ( mprj la_data_in[22] ) + + ROUTED met2 ( 1025570 2380 0 ) ( 1025570 16660 ) + NEW met2 ( 1021430 16660 ) ( 1025570 16660 ) + NEW met1 ( 724270 99790 ) ( 1021430 99790 ) + NEW met1 ( 717830 242590 ) ( 724270 242590 ) + NEW met2 ( 717830 242590 ) ( 717830 260100 0 ) + NEW met2 ( 724270 99790 ) ( 724270 242590 ) + NEW met2 ( 1021430 16660 ) ( 1021430 99790 ) + NEW met1 ( 724270 99790 ) M1M2_PR + NEW met1 ( 1021430 99790 ) M1M2_PR + NEW met1 ( 724270 242590 ) M1M2_PR + NEW met1 ( 717830 242590 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[23] ( PIN la_data_in[23] ) ( mprj la_data_in[23] ) + + ROUTED met2 ( 1043510 2380 0 ) ( 1043510 16660 ) + NEW met2 ( 1042130 16660 ) ( 1043510 16660 ) + NEW met1 ( 738070 106930 ) ( 1042130 106930 ) + NEW met2 ( 735770 260100 0 ) ( 738070 260100 ) + NEW met2 ( 738070 106930 ) ( 738070 260100 ) + NEW met2 ( 1042130 16660 ) ( 1042130 106930 ) + NEW met1 ( 738070 106930 ) M1M2_PR + NEW met1 ( 1042130 106930 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[24] ( PIN la_data_in[24] ) ( mprj la_data_in[24] ) + + ROUTED met2 ( 1061450 2380 0 ) ( 1061450 16660 ) + NEW met2 ( 1055930 16660 ) ( 1061450 16660 ) + NEW met2 ( 1055930 16660 ) ( 1055930 113730 ) + NEW met1 ( 758770 113730 ) ( 1055930 113730 ) + NEW met1 ( 753710 243950 ) ( 758770 243950 ) + NEW met2 ( 753710 243950 ) ( 753710 260100 0 ) + NEW met2 ( 758770 113730 ) ( 758770 243950 ) + NEW met1 ( 1055930 113730 ) M1M2_PR + NEW met1 ( 758770 113730 ) M1M2_PR + NEW met1 ( 758770 243950 ) M1M2_PR + NEW met1 ( 753710 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[25] ( PIN la_data_in[25] ) ( mprj la_data_in[25] ) + + ROUTED met2 ( 1079390 2380 0 ) ( 1079390 16660 ) + NEW met2 ( 1076630 16660 ) ( 1079390 16660 ) + NEW met2 ( 771650 260100 0 ) ( 772570 260100 ) + NEW met2 ( 772570 120530 ) ( 772570 260100 ) + NEW met2 ( 1076630 16660 ) ( 1076630 120530 ) + NEW met1 ( 772570 120530 ) ( 1076630 120530 ) + NEW met1 ( 772570 120530 ) M1M2_PR + NEW met1 ( 1076630 120530 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[26] ( PIN la_data_in[26] ) ( mprj la_data_in[26] ) + + ROUTED met2 ( 1096870 2380 0 ) ( 1096870 17850 ) + NEW met1 ( 1090890 17850 ) ( 1096870 17850 ) + NEW met1 ( 789590 243950 ) ( 793270 243950 ) + NEW met2 ( 789590 243950 ) ( 789590 260100 0 ) + NEW met2 ( 793270 127670 ) ( 793270 243950 ) + NEW met2 ( 1090890 17850 ) ( 1090890 127670 ) + NEW met1 ( 793270 127670 ) ( 1090890 127670 ) + NEW met1 ( 793270 127670 ) M1M2_PR + NEW met1 ( 1096870 17850 ) M1M2_PR + NEW met1 ( 1090890 17850 ) M1M2_PR + NEW met1 ( 1090890 127670 ) M1M2_PR + NEW met1 ( 793270 243950 ) M1M2_PR + NEW met1 ( 789590 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[27] ( PIN la_data_in[27] ) ( mprj la_data_in[27] ) + + ROUTED met2 ( 1114810 2380 0 ) ( 1114810 31450 ) + NEW met1 ( 813970 31450 ) ( 1114810 31450 ) + NEW met1 ( 807530 243950 ) ( 813970 243950 ) + NEW met2 ( 807530 243950 ) ( 807530 260100 0 ) + NEW met2 ( 813970 31450 ) ( 813970 243950 ) + NEW met1 ( 813970 31450 ) M1M2_PR + NEW met1 ( 1114810 31450 ) M1M2_PR + NEW met1 ( 813970 243950 ) M1M2_PR + NEW met1 ( 807530 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[28] ( PIN la_data_in[28] ) ( mprj la_data_in[28] ) + + ROUTED met2 ( 1132750 2380 0 ) ( 1132750 16660 ) + NEW met2 ( 1131830 16660 ) ( 1132750 16660 ) + NEW met2 ( 825010 260100 0 ) ( 827770 260100 ) + NEW met2 ( 827770 134470 ) ( 827770 260100 ) + NEW met1 ( 827770 134470 ) ( 1131830 134470 ) + NEW met2 ( 1131830 16660 ) ( 1131830 134470 ) + NEW met1 ( 827770 134470 ) M1M2_PR + NEW met1 ( 1131830 134470 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[29] ( PIN la_data_in[29] ) ( mprj la_data_in[29] ) + + ROUTED met2 ( 1150690 2380 0 ) ( 1150690 38250 ) + NEW met1 ( 842950 243950 ) ( 848470 243950 ) + NEW met2 ( 842950 243950 ) ( 842950 260100 0 ) + NEW met2 ( 848470 38250 ) ( 848470 243950 ) + NEW met1 ( 848470 38250 ) ( 1150690 38250 ) + NEW met1 ( 1150690 38250 ) M1M2_PR + NEW met1 ( 848470 38250 ) M1M2_PR + NEW met1 ( 848470 243950 ) M1M2_PR + NEW met1 ( 842950 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[2] ( PIN la_data_in[2] ) ( mprj la_data_in[2] ) + + ROUTED met2 ( 669070 2380 0 ) ( 669070 20230 ) + NEW met1 ( 663090 20230 ) ( 669070 20230 ) + NEW met2 ( 663090 20230 ) ( 663090 92990 ) + NEW met1 ( 365470 92990 ) ( 663090 92990 ) + NEW met1 ( 360410 243950 ) ( 365470 243950 ) + NEW met2 ( 360410 243950 ) ( 360410 260100 0 ) + NEW met2 ( 365470 92990 ) ( 365470 243950 ) + NEW met1 ( 669070 20230 ) M1M2_PR + NEW met1 ( 663090 20230 ) M1M2_PR + NEW met1 ( 663090 92990 ) M1M2_PR + NEW met1 ( 365470 92990 ) M1M2_PR + NEW met1 ( 365470 243950 ) M1M2_PR + NEW met1 ( 360410 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[30] ( PIN la_data_in[30] ) ( mprj la_data_in[30] ) + + ROUTED met2 ( 860890 260100 0 ) ( 862270 260100 ) + NEW met2 ( 862270 44710 ) ( 862270 260100 ) + NEW met2 ( 1168630 2380 0 ) ( 1168630 44710 ) + NEW met1 ( 862270 44710 ) ( 1168630 44710 ) + NEW met1 ( 862270 44710 ) M1M2_PR + NEW met1 ( 1168630 44710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[31] ( PIN la_data_in[31] ) ( mprj la_data_in[31] ) + + ROUTED met2 ( 1186110 2380 0 ) ( 1186110 17850 ) + NEW met1 ( 1180590 17850 ) ( 1186110 17850 ) + NEW met1 ( 878830 243950 ) ( 882970 243950 ) + NEW met2 ( 878830 243950 ) ( 878830 260100 0 ) + NEW met2 ( 882970 51850 ) ( 882970 243950 ) + NEW met2 ( 1180590 17850 ) ( 1180590 51850 ) + NEW met1 ( 882970 51850 ) ( 1180590 51850 ) + NEW met1 ( 1186110 17850 ) M1M2_PR + NEW met1 ( 1180590 17850 ) M1M2_PR + NEW met1 ( 882970 51850 ) M1M2_PR + NEW met1 ( 882970 243950 ) M1M2_PR + NEW met1 ( 878830 243950 ) M1M2_PR + NEW met1 ( 1180590 51850 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[32] ( PIN la_data_in[32] ) ( mprj la_data_in[32] ) + + ROUTED met2 ( 896310 260100 ) ( 896770 260100 0 ) + NEW met2 ( 896310 58650 ) ( 896310 260100 ) + NEW met2 ( 1204050 2380 0 ) ( 1204050 16660 ) + NEW met2 ( 1200830 16660 ) ( 1204050 16660 ) + NEW met1 ( 896310 58650 ) ( 1200830 58650 ) + NEW met2 ( 1200830 16660 ) ( 1200830 58650 ) + NEW met1 ( 896310 58650 ) M1M2_PR + NEW met1 ( 1200830 58650 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[33] ( PIN la_data_in[33] ) ( mprj la_data_in[33] ) + + ROUTED met2 ( 914710 260100 0 ) ( 917470 260100 ) + NEW met2 ( 917470 65450 ) ( 917470 260100 ) + NEW met1 ( 917470 65450 ) ( 1221990 65450 ) + NEW met2 ( 1221990 2380 0 ) ( 1221990 65450 ) + NEW met1 ( 917470 65450 ) M1M2_PR + NEW met1 ( 1221990 65450 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[34] ( PIN la_data_in[34] ) ( mprj la_data_in[34] ) + + ROUTED met2 ( 1239930 2380 0 ) ( 1239930 16660 ) + NEW met2 ( 1235330 16660 ) ( 1239930 16660 ) + NEW met1 ( 932650 243950 ) ( 938170 243950 ) + NEW met2 ( 932650 243950 ) ( 932650 260100 0 ) + NEW met2 ( 938170 72250 ) ( 938170 243950 ) + NEW met1 ( 938170 72250 ) ( 1235330 72250 ) + NEW met2 ( 1235330 16660 ) ( 1235330 72250 ) + NEW met1 ( 938170 72250 ) M1M2_PR + NEW met1 ( 938170 243950 ) M1M2_PR + NEW met1 ( 932650 243950 ) M1M2_PR + NEW met1 ( 1235330 72250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[35] ( PIN la_data_in[35] ) ( mprj la_data_in[35] ) + + ROUTED met2 ( 1257410 2380 0 ) ( 1257410 23970 ) + NEW met1 ( 951970 23970 ) ( 1257410 23970 ) + NEW met2 ( 950590 260100 0 ) ( 951970 260100 ) + NEW met2 ( 951970 23970 ) ( 951970 260100 ) + NEW met1 ( 1257410 23970 ) M1M2_PR + NEW met1 ( 951970 23970 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[36] ( PIN la_data_in[36] ) ( mprj la_data_in[36] ) + + ROUTED met2 ( 1275350 2380 0 ) ( 1275350 16660 ) + NEW met2 ( 1269830 16660 ) ( 1275350 16660 ) + NEW met1 ( 968070 243950 ) ( 972670 243950 ) + NEW met2 ( 968070 243950 ) ( 968070 260100 0 ) + NEW met2 ( 972670 79390 ) ( 972670 243950 ) + NEW met2 ( 1269830 16660 ) ( 1269830 79390 ) + NEW met1 ( 972670 79390 ) ( 1269830 79390 ) + NEW met1 ( 972670 79390 ) M1M2_PR + NEW met1 ( 972670 243950 ) M1M2_PR + NEW met1 ( 968070 243950 ) M1M2_PR + NEW met1 ( 1269830 79390 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[37] ( PIN la_data_in[37] ) ( mprj la_data_in[37] ) + + ROUTED met2 ( 986010 86190 ) ( 986010 260100 0 ) + NEW met2 ( 1293290 2380 0 ) ( 1293290 17340 ) + NEW met2 ( 1290530 17340 ) ( 1293290 17340 ) + NEW met1 ( 986010 86190 ) ( 1290530 86190 ) + NEW met2 ( 1290530 17340 ) ( 1290530 86190 ) + NEW met1 ( 986010 86190 ) M1M2_PR + NEW met1 ( 1290530 86190 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[38] ( PIN la_data_in[38] ) ( mprj la_data_in[38] ) + + ROUTED met2 ( 1311230 2380 0 ) ( 1311230 17340 ) + NEW met2 ( 1311230 17340 ) ( 1311690 17340 ) + NEW met2 ( 1003950 260100 0 ) ( 1007170 260100 ) + NEW met2 ( 1007170 141270 ) ( 1007170 260100 ) + NEW met1 ( 1007170 141270 ) ( 1311690 141270 ) + NEW met2 ( 1311690 17340 ) ( 1311690 141270 ) + NEW met1 ( 1007170 141270 ) M1M2_PR + NEW met1 ( 1311690 141270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[39] ( PIN la_data_in[39] ) ( mprj la_data_in[39] ) + + ROUTED met2 ( 1329170 2380 0 ) ( 1329170 17340 ) + NEW met2 ( 1325030 17340 ) ( 1329170 17340 ) + NEW met1 ( 1027870 99790 ) ( 1325030 99790 ) + NEW met1 ( 1021890 243950 ) ( 1027870 243950 ) + NEW met2 ( 1021890 243950 ) ( 1021890 260100 0 ) + NEW met2 ( 1027870 99790 ) ( 1027870 243950 ) + NEW met2 ( 1325030 17340 ) ( 1325030 99790 ) + NEW met1 ( 1027870 99790 ) M1M2_PR + NEW met1 ( 1325030 99790 ) M1M2_PR + NEW met1 ( 1027870 243950 ) M1M2_PR + NEW met1 ( 1021890 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[3] ( PIN la_data_in[3] ) ( mprj la_data_in[3] ) + + ROUTED met2 ( 686550 2380 0 ) ( 686550 16660 ) + NEW met2 ( 683330 16660 ) ( 686550 16660 ) + NEW met2 ( 378350 260100 0 ) ( 379270 260100 ) + NEW met2 ( 379270 99790 ) ( 379270 260100 ) + NEW met2 ( 683330 16660 ) ( 683330 99790 ) + NEW met1 ( 379270 99790 ) ( 683330 99790 ) + NEW met1 ( 379270 99790 ) M1M2_PR + NEW met1 ( 683330 99790 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[40] ( PIN la_data_in[40] ) ( mprj la_data_in[40] ) + + ROUTED met2 ( 1346650 2380 0 ) ( 1346650 17340 ) + NEW met2 ( 1345730 17340 ) ( 1346650 17340 ) + NEW met2 ( 1345730 17340 ) ( 1345730 92990 ) + NEW met1 ( 1041670 92990 ) ( 1345730 92990 ) + NEW met2 ( 1039830 260100 0 ) ( 1041670 260100 ) + NEW met2 ( 1041670 92990 ) ( 1041670 260100 ) + NEW met1 ( 1345730 92990 ) M1M2_PR + NEW met1 ( 1041670 92990 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[41] ( PIN la_data_in[41] ) ( mprj la_data_in[41] ) + + ROUTED met2 ( 1364590 2380 0 ) ( 1364590 17340 ) + NEW met2 ( 1359530 17340 ) ( 1364590 17340 ) + NEW met1 ( 1057770 243950 ) ( 1062370 243950 ) + NEW met2 ( 1057770 243950 ) ( 1057770 260100 0 ) + NEW met2 ( 1062370 106930 ) ( 1062370 243950 ) + NEW met2 ( 1359530 17340 ) ( 1359530 106930 ) + NEW met1 ( 1062370 106930 ) ( 1359530 106930 ) + NEW met1 ( 1062370 106930 ) M1M2_PR + NEW met1 ( 1359530 106930 ) M1M2_PR + NEW met1 ( 1062370 243950 ) M1M2_PR + NEW met1 ( 1057770 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[42] ( PIN la_data_in[42] ) ( mprj la_data_in[42] ) + + ROUTED met2 ( 1382530 2380 0 ) ( 1382530 17340 ) + NEW met2 ( 1380230 17340 ) ( 1382530 17340 ) + NEW met2 ( 1075710 113730 ) ( 1075710 260100 0 ) + NEW met2 ( 1380230 17340 ) ( 1380230 113730 ) + NEW met1 ( 1075710 113730 ) ( 1380230 113730 ) + NEW met1 ( 1075710 113730 ) M1M2_PR + NEW met1 ( 1380230 113730 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[43] ( PIN la_data_in[43] ) ( mprj la_data_in[43] ) + + ROUTED met1 ( 1093190 243950 ) ( 1096870 243950 ) + NEW met2 ( 1093190 243950 ) ( 1093190 260100 0 ) + NEW met2 ( 1096870 31110 ) ( 1096870 243950 ) + NEW met2 ( 1400010 30260 ) ( 1400010 31110 ) + NEW met2 ( 1400010 30260 ) ( 1400470 30260 ) + NEW met2 ( 1400470 2380 0 ) ( 1400470 30260 ) + NEW met1 ( 1096870 31110 ) ( 1400010 31110 ) + NEW met1 ( 1096870 31110 ) M1M2_PR + NEW met1 ( 1096870 243950 ) M1M2_PR + NEW met1 ( 1093190 243950 ) M1M2_PR + NEW met1 ( 1400010 31110 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[44] ( PIN la_data_in[44] ) ( mprj la_data_in[44] ) + + ROUTED met1 ( 1111130 243950 ) ( 1117570 243950 ) + NEW met2 ( 1111130 243950 ) ( 1111130 260100 0 ) + NEW met2 ( 1117570 37910 ) ( 1117570 243950 ) + NEW met1 ( 1117570 37910 ) ( 1418410 37910 ) + NEW met2 ( 1418410 2380 0 ) ( 1418410 37910 ) + NEW met1 ( 1117570 37910 ) M1M2_PR + NEW met1 ( 1117570 243950 ) M1M2_PR + NEW met1 ( 1111130 243950 ) M1M2_PR + NEW met1 ( 1418410 37910 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[45] ( PIN la_data_in[45] ) ( mprj la_data_in[45] ) + + ROUTED met2 ( 1435890 2380 0 ) ( 1435890 120530 ) + NEW met1 ( 1131370 120530 ) ( 1435890 120530 ) + NEW met2 ( 1129070 260100 0 ) ( 1131370 260100 ) + NEW met2 ( 1131370 120530 ) ( 1131370 260100 ) + NEW met1 ( 1435890 120530 ) M1M2_PR + NEW met1 ( 1131370 120530 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[46] ( PIN la_data_in[46] ) ( mprj la_data_in[46] ) + + ROUTED met1 ( 1147010 243950 ) ( 1152070 243950 ) + NEW met2 ( 1147010 243950 ) ( 1147010 260100 0 ) + NEW met2 ( 1152070 45050 ) ( 1152070 243950 ) + NEW met2 ( 1453830 2380 0 ) ( 1453830 45050 ) + NEW met1 ( 1152070 45050 ) ( 1453830 45050 ) + NEW met1 ( 1152070 45050 ) M1M2_PR + NEW met1 ( 1152070 243950 ) M1M2_PR + NEW met1 ( 1147010 243950 ) M1M2_PR + NEW met1 ( 1453830 45050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[47] ( PIN la_data_in[47] ) ( mprj la_data_in[47] ) + + ROUTED met2 ( 1471770 2380 0 ) ( 1471770 16660 ) + NEW met2 ( 1469930 16660 ) ( 1471770 16660 ) + NEW met2 ( 1164950 260100 0 ) ( 1165870 260100 ) + NEW met2 ( 1165870 51510 ) ( 1165870 260100 ) + NEW met2 ( 1469930 16660 ) ( 1469930 51510 ) + NEW met1 ( 1165870 51510 ) ( 1469930 51510 ) + NEW met1 ( 1165870 51510 ) M1M2_PR + NEW met1 ( 1469930 51510 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[48] ( PIN la_data_in[48] ) ( mprj la_data_in[48] ) + + ROUTED met2 ( 1182890 260100 0 ) ( 1186570 260100 ) + NEW met2 ( 1186570 128010 ) ( 1186570 260100 ) + NEW met2 ( 1489710 2380 0 ) ( 1489710 17340 ) + NEW met2 ( 1484190 17340 ) ( 1489710 17340 ) + NEW met1 ( 1186570 128010 ) ( 1484190 128010 ) + NEW met2 ( 1484190 17340 ) ( 1484190 128010 ) + NEW met1 ( 1186570 128010 ) M1M2_PR + NEW met1 ( 1484190 128010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[49] ( PIN la_data_in[49] ) ( mprj la_data_in[49] ) + + ROUTED met2 ( 1507190 2380 0 ) ( 1507190 17340 ) + NEW met2 ( 1504430 17340 ) ( 1507190 17340 ) + NEW met1 ( 1200830 241570 ) ( 1207270 241570 ) + NEW met2 ( 1200830 241570 ) ( 1200830 260100 0 ) + NEW met2 ( 1207270 58650 ) ( 1207270 241570 ) + NEW met1 ( 1207270 58650 ) ( 1504430 58650 ) + NEW met2 ( 1504430 17340 ) ( 1504430 58650 ) + NEW met1 ( 1207270 58650 ) M1M2_PR + NEW met1 ( 1207270 241570 ) M1M2_PR + NEW met1 ( 1200830 241570 ) M1M2_PR + NEW met1 ( 1504430 58650 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[4] ( PIN la_data_in[4] ) ( mprj la_data_in[4] ) + + ROUTED met2 ( 396290 260100 0 ) ( 399970 260100 ) + NEW met2 ( 399970 106930 ) ( 399970 260100 ) + NEW met2 ( 704490 2380 0 ) ( 704490 106930 ) + NEW met1 ( 399970 106930 ) ( 704490 106930 ) + NEW met1 ( 399970 106930 ) M1M2_PR + NEW met1 ( 704490 106930 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[50] ( PIN la_data_in[50] ) ( mprj la_data_in[50] ) + + ROUTED met2 ( 1525130 2380 0 ) ( 1525130 17340 ) + NEW met2 ( 1525130 17340 ) ( 1525590 17340 ) + NEW met2 ( 1218310 260100 0 ) ( 1221070 260100 ) + NEW met2 ( 1221070 134470 ) ( 1221070 260100 ) + NEW met1 ( 1221070 134470 ) ( 1525590 134470 ) + NEW met2 ( 1525590 17340 ) ( 1525590 134470 ) + NEW met1 ( 1221070 134470 ) M1M2_PR + NEW met1 ( 1525590 134470 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[51] ( PIN la_data_in[51] ) ( mprj la_data_in[51] ) + + ROUTED met2 ( 1543070 2380 0 ) ( 1543070 16660 ) + NEW met2 ( 1538930 16660 ) ( 1543070 16660 ) + NEW met2 ( 1538930 16660 ) ( 1538930 72250 ) + NEW met1 ( 1236250 243950 ) ( 1241770 243950 ) + NEW met2 ( 1236250 243950 ) ( 1236250 260100 0 ) + NEW met2 ( 1241770 72250 ) ( 1241770 243950 ) + NEW met1 ( 1241770 72250 ) ( 1538930 72250 ) + NEW met1 ( 1538930 72250 ) M1M2_PR + NEW met1 ( 1241770 72250 ) M1M2_PR + NEW met1 ( 1241770 243950 ) M1M2_PR + NEW met1 ( 1236250 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[52] ( PIN la_data_in[52] ) ( mprj la_data_in[52] ) + + ROUTED met2 ( 1561010 2380 0 ) ( 1561010 16660 ) + NEW met2 ( 1559630 16660 ) ( 1561010 16660 ) + NEW met2 ( 1254190 260100 0 ) ( 1255570 260100 ) + NEW met2 ( 1255570 65450 ) ( 1255570 260100 ) + NEW met2 ( 1559630 16660 ) ( 1559630 65450 ) + NEW met1 ( 1255570 65450 ) ( 1559630 65450 ) + NEW met1 ( 1255570 65450 ) M1M2_PR + NEW met1 ( 1559630 65450 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[53] ( PIN la_data_in[53] ) ( mprj la_data_in[53] ) + + ROUTED met2 ( 1578950 2380 0 ) ( 1578950 24310 ) + NEW met1 ( 1272130 243950 ) ( 1276270 243950 ) + NEW met2 ( 1272130 243950 ) ( 1272130 260100 0 ) + NEW met2 ( 1276270 24310 ) ( 1276270 243950 ) + NEW met1 ( 1276270 24310 ) ( 1578950 24310 ) + NEW met1 ( 1276270 24310 ) M1M2_PR + NEW met1 ( 1578950 24310 ) M1M2_PR + NEW met1 ( 1276270 243950 ) M1M2_PR + NEW met1 ( 1272130 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[54] ( PIN la_data_in[54] ) ( mprj la_data_in[54] ) + + ROUTED met2 ( 1289610 260100 ) ( 1290070 260100 0 ) + NEW met2 ( 1289610 79390 ) ( 1289610 260100 ) + NEW met2 ( 1596430 2380 0 ) ( 1596430 16660 ) + NEW met2 ( 1594130 16660 ) ( 1596430 16660 ) + NEW met1 ( 1289610 79390 ) ( 1594130 79390 ) + NEW met2 ( 1594130 16660 ) ( 1594130 79390 ) + NEW met1 ( 1289610 79390 ) M1M2_PR + NEW met1 ( 1594130 79390 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[55] ( PIN la_data_in[55] ) ( mprj la_data_in[55] ) + + ROUTED met1 ( 1310770 86190 ) ( 1608390 86190 ) + NEW met2 ( 1308010 260100 0 ) ( 1310770 260100 ) + NEW met2 ( 1310770 86190 ) ( 1310770 260100 ) + NEW met1 ( 1608390 38250 ) ( 1614370 38250 ) + NEW met2 ( 1608390 38250 ) ( 1608390 86190 ) + NEW met2 ( 1614370 2380 0 ) ( 1614370 38250 ) + NEW met1 ( 1310770 86190 ) M1M2_PR + NEW met1 ( 1608390 86190 ) M1M2_PR + NEW met1 ( 1608390 38250 ) M1M2_PR + NEW met1 ( 1614370 38250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[56] ( PIN la_data_in[56] ) ( mprj la_data_in[56] ) + + ROUTED met1 ( 1331470 99790 ) ( 1628630 99790 ) + NEW met1 ( 1325950 243950 ) ( 1331470 243950 ) + NEW met2 ( 1325950 243950 ) ( 1325950 260100 0 ) + NEW met2 ( 1331470 99790 ) ( 1331470 243950 ) + NEW met2 ( 1632310 2380 0 ) ( 1632310 47430 ) + NEW met1 ( 1632310 47430 ) ( 1632310 48110 ) + NEW met1 ( 1628630 62050 ) ( 1628630 62390 ) + NEW met1 ( 1628630 62050 ) ( 1632310 62050 ) + NEW met2 ( 1628630 62390 ) ( 1628630 99790 ) + NEW met2 ( 1632310 48110 ) ( 1632310 62050 ) + NEW met1 ( 1628630 99790 ) M1M2_PR + NEW met1 ( 1331470 99790 ) M1M2_PR + NEW met1 ( 1331470 243950 ) M1M2_PR + NEW met1 ( 1325950 243950 ) M1M2_PR + NEW met1 ( 1632310 47430 ) M1M2_PR + NEW met1 ( 1632310 48110 ) M1M2_PR + NEW met1 ( 1628630 62390 ) M1M2_PR + NEW met1 ( 1632310 62050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[57] ( PIN la_data_in[57] ) ( mprj la_data_in[57] ) + + ROUTED met2 ( 1343430 260100 0 ) ( 1345270 260100 ) + NEW met2 ( 1345270 93330 ) ( 1345270 260100 ) + NEW li1 ( 1650250 48450 ) ( 1650250 93330 ) + NEW met1 ( 1345270 93330 ) ( 1650250 93330 ) + NEW met2 ( 1650250 2380 0 ) ( 1650250 48450 ) + NEW met1 ( 1345270 93330 ) M1M2_PR + NEW li1 ( 1650250 93330 ) L1M1_PR_MR + NEW li1 ( 1650250 48450 ) L1M1_PR_MR + NEW met1 ( 1650250 48450 ) M1M2_PR + NEW met1 ( 1650250 48450 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- la_data_in[58] ( PIN la_data_in[58] ) ( mprj la_data_in[58] ) + + ROUTED met2 ( 1668190 2380 0 ) ( 1668190 16660 ) + NEW met2 ( 1663130 16660 ) ( 1668190 16660 ) + NEW met1 ( 1361370 243950 ) ( 1365970 243950 ) + NEW met2 ( 1361370 243950 ) ( 1361370 260100 0 ) + NEW met2 ( 1365970 106930 ) ( 1365970 243950 ) + NEW met2 ( 1663130 16660 ) ( 1663130 106930 ) + NEW met1 ( 1365970 106930 ) ( 1663130 106930 ) + NEW met1 ( 1365970 106930 ) M1M2_PR + NEW met1 ( 1663130 106930 ) M1M2_PR + NEW met1 ( 1365970 243950 ) M1M2_PR + NEW met1 ( 1361370 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[59] ( PIN la_data_in[59] ) ( mprj la_data_in[59] ) + + ROUTED met2 ( 1379770 237830 ) ( 1379770 260100 ) + NEW met2 ( 1379310 260100 0 ) ( 1379770 260100 ) + NEW met2 ( 1685670 2380 0 ) ( 1685670 17340 ) + NEW met2 ( 1683830 17340 ) ( 1685670 17340 ) + NEW met1 ( 1379770 237830 ) ( 1683830 237830 ) + NEW met2 ( 1683830 17340 ) ( 1683830 237830 ) + NEW met1 ( 1379770 237830 ) M1M2_PR + NEW met1 ( 1683830 237830 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[5] ( PIN la_data_in[5] ) ( mprj la_data_in[5] ) + + ROUTED met1 ( 414230 243270 ) ( 420210 243270 ) + NEW met2 ( 414230 243270 ) ( 414230 260100 0 ) + NEW met2 ( 420210 113730 ) ( 420210 243270 ) + NEW met2 ( 722430 2380 0 ) ( 722430 16660 ) + NEW met2 ( 717830 16660 ) ( 722430 16660 ) + NEW met1 ( 420210 113730 ) ( 717830 113730 ) + NEW met2 ( 717830 16660 ) ( 717830 113730 ) + NEW met1 ( 420210 113730 ) M1M2_PR + NEW met1 ( 420210 243270 ) M1M2_PR + NEW met1 ( 414230 243270 ) M1M2_PR + NEW met1 ( 717830 113730 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[60] ( PIN la_data_in[60] ) ( mprj la_data_in[60] ) + + ROUTED met2 ( 1703610 2380 0 ) ( 1703610 30770 ) + NEW met2 ( 1397250 260100 0 ) ( 1400470 260100 ) + NEW met2 ( 1400470 30770 ) ( 1400470 260100 ) + NEW met1 ( 1400470 30770 ) ( 1703610 30770 ) + NEW met1 ( 1400470 30770 ) M1M2_PR + NEW met1 ( 1703610 30770 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[61] ( PIN la_data_in[61] ) ( mprj la_data_in[61] ) + + ROUTED met1 ( 1415190 243950 ) ( 1421170 243950 ) + NEW met2 ( 1415190 243950 ) ( 1415190 260100 0 ) + NEW met2 ( 1421170 37910 ) ( 1421170 243950 ) + NEW met2 ( 1721550 2380 0 ) ( 1721550 37910 ) + NEW met1 ( 1421170 37910 ) ( 1721550 37910 ) + NEW met1 ( 1421170 37910 ) M1M2_PR + NEW met1 ( 1421170 243950 ) M1M2_PR + NEW met1 ( 1415190 243950 ) M1M2_PR + NEW met1 ( 1721550 37910 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[62] ( PIN la_data_in[62] ) ( mprj la_data_in[62] ) + + ROUTED met2 ( 1739490 2380 0 ) ( 1739490 113730 ) + NEW met1 ( 1434970 113730 ) ( 1739490 113730 ) + NEW met2 ( 1433130 260100 0 ) ( 1434970 260100 ) + NEW met2 ( 1434970 113730 ) ( 1434970 260100 ) + NEW met1 ( 1739490 113730 ) M1M2_PR + NEW met1 ( 1434970 113730 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[63] ( PIN la_data_in[63] ) ( mprj la_data_in[63] ) + + ROUTED met1 ( 1451070 243950 ) ( 1455670 243950 ) + NEW met2 ( 1451070 243950 ) ( 1451070 260100 0 ) + NEW met2 ( 1455670 44710 ) ( 1455670 243950 ) + NEW met2 ( 1756970 2380 0 ) ( 1756970 44710 ) + NEW met1 ( 1455670 44710 ) ( 1756970 44710 ) + NEW met1 ( 1455670 44710 ) M1M2_PR + NEW met1 ( 1455670 243950 ) M1M2_PR + NEW met1 ( 1451070 243950 ) M1M2_PR + NEW met1 ( 1756970 44710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[64] ( PIN la_data_in[64] ) ( mprj la_data_in[64] ) + + ROUTED met2 ( 1468550 231030 ) ( 1468550 260100 0 ) + NEW met2 ( 1774910 2380 0 ) ( 1774910 2890 ) + NEW met1 ( 1773530 2890 ) ( 1774910 2890 ) + NEW met1 ( 1468550 231030 ) ( 1773530 231030 ) + NEW met2 ( 1773530 2890 ) ( 1773530 231030 ) + NEW met1 ( 1468550 231030 ) M1M2_PR + NEW met1 ( 1774910 2890 ) M1M2_PR + NEW met1 ( 1773530 2890 ) M1M2_PR + NEW met1 ( 1773530 231030 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[65] ( PIN la_data_in[65] ) ( mprj la_data_in[65] ) + + ROUTED met2 ( 1792850 2380 0 ) ( 1792850 2890 ) + NEW met1 ( 1787790 2890 ) ( 1792850 2890 ) + NEW met2 ( 1787790 2890 ) ( 1787790 20060 ) + NEW met2 ( 1787330 20060 ) ( 1787790 20060 ) + NEW met2 ( 1486490 260100 0 ) ( 1490170 260100 ) + NEW met2 ( 1490170 51510 ) ( 1490170 260100 ) + NEW met2 ( 1787330 20060 ) ( 1787330 51510 ) + NEW met1 ( 1490170 51510 ) ( 1787330 51510 ) + NEW met1 ( 1792850 2890 ) M1M2_PR + NEW met1 ( 1787790 2890 ) M1M2_PR + NEW met1 ( 1490170 51510 ) M1M2_PR + NEW met1 ( 1787330 51510 ) M1M2_PR +======= NEW met2 ( 2894550 17510 ) ( 2894550 1666170 ) NEW met2 ( 1771230 1666170 ) ( 1771230 1700340 0 ) NEW met1 ( 1771230 1666170 ) ( 2894550 1666170 ) @@ -76996,10 +80365,710 @@ NEW met1 ( 1787330 2890 ) M1M2_PR NEW met1 ( 1544450 1611770 ) M1M2_PR NEW met1 ( 1787330 1611770 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - la_data_in[66] ( PIN la_data_in[66] ) ( mprj la_data_in[66] ) + ROUTED met2 ( 1810790 2380 0 ) ( 1810790 2890 ) NEW met1 ( 1808030 2890 ) ( 1810790 2890 ) +<<<<<<< HEAD + NEW met1 ( 1504430 243950 ) ( 1510870 243950 ) + NEW met2 ( 1504430 243950 ) ( 1504430 260100 0 ) + NEW met2 ( 1510870 58990 ) ( 1510870 243950 ) + NEW met2 ( 1808030 2890 ) ( 1808030 58990 ) + NEW met1 ( 1510870 58990 ) ( 1808030 58990 ) + NEW met1 ( 1810790 2890 ) M1M2_PR + NEW met1 ( 1808030 2890 ) M1M2_PR + NEW met1 ( 1510870 58990 ) M1M2_PR + NEW met1 ( 1510870 243950 ) M1M2_PR + NEW met1 ( 1504430 243950 ) M1M2_PR + NEW met1 ( 1808030 58990 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[67] ( PIN la_data_in[67] ) ( mprj la_data_in[67] ) + + ROUTED met2 ( 1828730 2380 0 ) ( 1828730 7140 ) + NEW met2 ( 1828730 7140 ) ( 1829190 7140 ) + NEW met2 ( 1829190 7140 ) ( 1829190 120530 ) + NEW met1 ( 1524670 120530 ) ( 1829190 120530 ) + NEW met2 ( 1522370 260100 0 ) ( 1524670 260100 ) + NEW met2 ( 1524670 120530 ) ( 1524670 260100 ) + NEW met1 ( 1829190 120530 ) M1M2_PR + NEW met1 ( 1524670 120530 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[68] ( PIN la_data_in[68] ) ( mprj la_data_in[68] ) + + ROUTED met2 ( 1846210 2380 0 ) ( 1846210 16660 ) + NEW met2 ( 1842530 16660 ) ( 1846210 16660 ) + NEW met1 ( 1540310 243950 ) ( 1545370 243950 ) + NEW met2 ( 1540310 243950 ) ( 1540310 260100 0 ) + NEW met2 ( 1545370 72250 ) ( 1545370 243950 ) + NEW met2 ( 1842530 16660 ) ( 1842530 72250 ) + NEW met1 ( 1545370 72250 ) ( 1842530 72250 ) + NEW met1 ( 1545370 72250 ) M1M2_PR + NEW met1 ( 1545370 243950 ) M1M2_PR + NEW met1 ( 1540310 243950 ) M1M2_PR + NEW met1 ( 1842530 72250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[69] ( PIN la_data_in[69] ) ( mprj la_data_in[69] ) + + ROUTED met2 ( 1558250 245650 ) ( 1558250 260100 0 ) + NEW met2 ( 1728450 31110 ) ( 1728450 245650 ) + NEW met1 ( 1558250 245650 ) ( 1728450 245650 ) + NEW met1 ( 1728450 31110 ) ( 1864150 31110 ) + NEW met2 ( 1864150 2380 0 ) ( 1864150 31110 ) + NEW met1 ( 1728450 31110 ) M1M2_PR + NEW met1 ( 1558250 245650 ) M1M2_PR + NEW met1 ( 1728450 245650 ) M1M2_PR + NEW met1 ( 1864150 31110 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[6] ( PIN la_data_in[6] ) ( mprj la_data_in[6] ) + + ROUTED met2 ( 740370 2380 0 ) ( 740370 16660 ) + NEW met2 ( 738530 16660 ) ( 740370 16660 ) + NEW met1 ( 434470 120530 ) ( 738530 120530 ) + NEW met2 ( 432170 260100 0 ) ( 434470 260100 ) + NEW met2 ( 434470 120530 ) ( 434470 260100 ) + NEW met2 ( 738530 16660 ) ( 738530 120530 ) + NEW met1 ( 434470 120530 ) M1M2_PR + NEW met1 ( 738530 120530 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[70] ( PIN la_data_in[70] ) ( mprj la_data_in[70] ) + + ROUTED met1 ( 1576190 243610 ) ( 1579870 243610 ) + NEW met2 ( 1576190 243610 ) ( 1576190 260100 0 ) + NEW met2 ( 1579870 65450 ) ( 1579870 243610 ) + NEW met1 ( 1579870 65450 ) ( 1877030 65450 ) + NEW met1 ( 1877030 62050 ) ( 1882090 62050 ) + NEW met2 ( 1877030 62050 ) ( 1877030 65450 ) + NEW met2 ( 1882090 2380 0 ) ( 1882090 62050 ) + NEW met1 ( 1579870 65450 ) M1M2_PR + NEW met1 ( 1579870 243610 ) M1M2_PR + NEW met1 ( 1576190 243610 ) M1M2_PR + NEW met1 ( 1877030 65450 ) M1M2_PR + NEW met1 ( 1877030 62050 ) M1M2_PR + NEW met1 ( 1882090 62050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[71] ( PIN la_data_in[71] ) ( mprj la_data_in[71] ) + + ROUTED met2 ( 1900030 2380 0 ) ( 1900030 16660 ) + NEW met2 ( 1897730 16660 ) ( 1900030 16660 ) + NEW met2 ( 1593210 260100 ) ( 1593670 260100 0 ) + NEW met2 ( 1593210 79730 ) ( 1593210 260100 ) + NEW met1 ( 1593210 79730 ) ( 1897730 79730 ) + NEW met2 ( 1897730 16660 ) ( 1897730 79730 ) + NEW met1 ( 1593210 79730 ) M1M2_PR + NEW met1 ( 1897730 79730 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[72] ( PIN la_data_in[72] ) ( mprj la_data_in[72] ) + + ROUTED met2 ( 1917970 2380 0 ) ( 1917970 17850 ) + NEW met1 ( 1911990 17850 ) ( 1917970 17850 ) + NEW met1 ( 1614370 86190 ) ( 1911990 86190 ) + NEW met2 ( 1611610 260100 0 ) ( 1614370 260100 ) + NEW met2 ( 1911990 17850 ) ( 1911990 86190 ) + NEW met2 ( 1614370 86190 ) ( 1614370 260100 ) + NEW met1 ( 1614370 86190 ) M1M2_PR + NEW met1 ( 1917970 17850 ) M1M2_PR + NEW met1 ( 1911990 17850 ) M1M2_PR + NEW met1 ( 1911990 86190 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[73] ( PIN la_data_in[73] ) ( mprj la_data_in[73] ) + + ROUTED met2 ( 1935450 2380 0 ) ( 1935450 2890 ) + NEW met1 ( 1932230 2890 ) ( 1935450 2890 ) + NEW met1 ( 1629550 243950 ) ( 1635070 243950 ) + NEW met2 ( 1629550 243950 ) ( 1629550 260100 0 ) + NEW met2 ( 1635070 99790 ) ( 1635070 243950 ) + NEW met2 ( 1932230 2890 ) ( 1932230 99790 ) + NEW met1 ( 1635070 99790 ) ( 1932230 99790 ) + NEW met1 ( 1635070 99790 ) M1M2_PR + NEW met1 ( 1935450 2890 ) M1M2_PR + NEW met1 ( 1932230 2890 ) M1M2_PR + NEW met1 ( 1932230 99790 ) M1M2_PR + NEW met1 ( 1635070 243950 ) M1M2_PR + NEW met1 ( 1629550 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[74] ( PIN la_data_in[74] ) ( mprj la_data_in[74] ) + + ROUTED met1 ( 1647490 243950 ) ( 1652550 243950 ) + NEW met2 ( 1647490 243950 ) ( 1647490 260100 0 ) + NEW met2 ( 1652550 92990 ) ( 1652550 243950 ) + NEW met1 ( 1652550 92990 ) ( 1953390 92990 ) + NEW met2 ( 1953390 2380 0 ) ( 1953390 92990 ) + NEW met1 ( 1652550 92990 ) M1M2_PR + NEW met1 ( 1953390 92990 ) M1M2_PR + NEW met1 ( 1652550 243950 ) M1M2_PR + NEW met1 ( 1647490 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[75] ( PIN la_data_in[75] ) ( mprj la_data_in[75] ) + + ROUTED met1 ( 1665430 243950 ) ( 1669570 243950 ) + NEW met2 ( 1665430 243950 ) ( 1665430 260100 0 ) + NEW met2 ( 1669570 106930 ) ( 1669570 243950 ) + NEW met1 ( 1669570 106930 ) ( 1966730 106930 ) + NEW met1 ( 1966730 62050 ) ( 1971330 62050 ) + NEW met2 ( 1966730 62050 ) ( 1966730 106930 ) + NEW met2 ( 1971330 2380 0 ) ( 1971330 62050 ) + NEW met1 ( 1669570 106930 ) M1M2_PR + NEW met1 ( 1669570 243950 ) M1M2_PR + NEW met1 ( 1665430 243950 ) M1M2_PR + NEW met1 ( 1966730 106930 ) M1M2_PR + NEW met1 ( 1966730 62050 ) M1M2_PR + NEW met1 ( 1971330 62050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[76] ( PIN la_data_in[76] ) ( mprj la_data_in[76] ) + + ROUTED met2 ( 1682910 260100 ) ( 1683370 260100 0 ) + NEW met2 ( 1682910 127670 ) ( 1682910 260100 ) + NEW met2 ( 1987890 96900 ) ( 1987890 127670 ) + NEW met2 ( 1987430 96900 ) ( 1987890 96900 ) + NEW met1 ( 1682910 127670 ) ( 1987890 127670 ) + NEW li1 ( 1987430 48450 ) ( 1987430 96390 ) + NEW met1 ( 1987430 48450 ) ( 1989270 48450 ) + NEW met2 ( 1987430 96390 ) ( 1987430 96900 ) + NEW met2 ( 1989270 2380 0 ) ( 1989270 48450 ) + NEW met1 ( 1682910 127670 ) M1M2_PR + NEW met1 ( 1987890 127670 ) M1M2_PR + NEW li1 ( 1987430 96390 ) L1M1_PR_MR + NEW met1 ( 1987430 96390 ) M1M2_PR + NEW li1 ( 1987430 48450 ) L1M1_PR_MR + NEW met1 ( 1989270 48450 ) M1M2_PR + NEW met1 ( 1987430 96390 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- la_data_in[77] ( PIN la_data_in[77] ) ( mprj la_data_in[77] ) + + ROUTED met2 ( 1701310 260100 0 ) ( 1704070 260100 ) + NEW met2 ( 1704070 38250 ) ( 1704070 260100 ) + NEW met2 ( 2006750 2380 0 ) ( 2006750 38250 ) + NEW met1 ( 1704070 38250 ) ( 2006750 38250 ) + NEW met1 ( 1704070 38250 ) M1M2_PR + NEW met1 ( 2006750 38250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[78] ( PIN la_data_in[78] ) ( mprj la_data_in[78] ) + + ROUTED met2 ( 2024690 2380 0 ) ( 2024690 16660 ) + NEW met2 ( 2021930 16660 ) ( 2024690 16660 ) + NEW met2 ( 2021930 16660 ) ( 2021930 134470 ) + NEW met1 ( 1718790 243950 ) ( 1724310 243950 ) + NEW met2 ( 1718790 243950 ) ( 1718790 260100 0 ) + NEW met2 ( 1724310 134470 ) ( 1724310 243950 ) + NEW met1 ( 1724310 134470 ) ( 2021930 134470 ) + NEW met1 ( 2021930 134470 ) M1M2_PR + NEW met1 ( 1724310 134470 ) M1M2_PR + NEW met1 ( 1724310 243950 ) M1M2_PR + NEW met1 ( 1718790 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[79] ( PIN la_data_in[79] ) ( mprj la_data_in[79] ) + + ROUTED met2 ( 1736730 237830 ) ( 1736730 260100 0 ) + NEW met1 ( 1736730 237830 ) ( 2042630 237830 ) + NEW met2 ( 2042630 2380 0 ) ( 2042630 237830 ) + NEW met1 ( 1736730 237830 ) M1M2_PR + NEW met1 ( 2042630 237830 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[7] ( PIN la_data_in[7] ) ( mprj la_data_in[7] ) + + ROUTED met2 ( 757850 2380 0 ) ( 757850 18870 ) + NEW met1 ( 752790 18870 ) ( 757850 18870 ) + NEW met1 ( 455170 127670 ) ( 752790 127670 ) + NEW met1 ( 449650 243950 ) ( 455170 243950 ) + NEW met2 ( 449650 243950 ) ( 449650 260100 0 ) + NEW met2 ( 455170 127670 ) ( 455170 243950 ) + NEW met2 ( 752790 18870 ) ( 752790 127670 ) + NEW met1 ( 455170 127670 ) M1M2_PR + NEW met1 ( 757850 18870 ) M1M2_PR + NEW met1 ( 752790 18870 ) M1M2_PR + NEW met1 ( 752790 127670 ) M1M2_PR + NEW met1 ( 455170 243950 ) M1M2_PR + NEW met1 ( 449650 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[80] ( PIN la_data_in[80] ) ( mprj la_data_in[80] ) + + ROUTED met1 ( 1754670 243950 ) ( 1759270 243950 ) + NEW met2 ( 1754670 243950 ) ( 1754670 260100 0 ) + NEW met2 ( 1759270 44710 ) ( 1759270 243950 ) + NEW met1 ( 1759270 44710 ) ( 2060570 44710 ) + NEW met2 ( 2060570 2380 0 ) ( 2060570 44710 ) + NEW met1 ( 1759270 44710 ) M1M2_PR + NEW met1 ( 1759270 243950 ) M1M2_PR + NEW met1 ( 1754670 243950 ) M1M2_PR + NEW met1 ( 2060570 44710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[81] ( PIN la_data_in[81] ) ( mprj la_data_in[81] ) + + ROUTED met2 ( 1772610 244970 ) ( 1772610 260100 0 ) + NEW met2 ( 1838850 51510 ) ( 1838850 244970 ) + NEW met2 ( 2078510 2380 0 ) ( 2078510 4420 ) + NEW met2 ( 2077130 4420 ) ( 2078510 4420 ) + NEW met1 ( 1772610 244970 ) ( 1838850 244970 ) + NEW met1 ( 1838850 51510 ) ( 2077130 51510 ) + NEW met2 ( 2077130 4420 ) ( 2077130 51510 ) + NEW met1 ( 1772610 244970 ) M1M2_PR + NEW met1 ( 1838850 51510 ) M1M2_PR + NEW met1 ( 1838850 244970 ) M1M2_PR + NEW met1 ( 2077130 51510 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[82] ( PIN la_data_in[82] ) ( mprj la_data_in[82] ) + + ROUTED met2 ( 2095990 2380 0 ) ( 2095990 24990 ) + NEW met2 ( 1790550 260100 0 ) ( 1793770 260100 ) + NEW met2 ( 1793770 24990 ) ( 1793770 260100 ) + NEW met1 ( 1793770 24990 ) ( 2095990 24990 ) + NEW met1 ( 1793770 24990 ) M1M2_PR + NEW met1 ( 2095990 24990 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[83] ( PIN la_data_in[83] ) ( mprj la_data_in[83] ) + + ROUTED met2 ( 2113930 2380 0 ) ( 2113930 26350 ) + NEW met1 ( 1808490 243950 ) ( 1814470 243950 ) + NEW met2 ( 1808490 243950 ) ( 1808490 260100 0 ) + NEW met2 ( 1814470 26350 ) ( 1814470 243950 ) + NEW met1 ( 1814470 26350 ) ( 2113930 26350 ) + NEW met1 ( 2113930 26350 ) M1M2_PR + NEW met1 ( 1814470 26350 ) M1M2_PR + NEW met1 ( 1814470 243950 ) M1M2_PR + NEW met1 ( 1808490 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[84] ( PIN la_data_in[84] ) ( mprj la_data_in[84] ) + + ROUTED met2 ( 2131870 2380 0 ) ( 2131870 17510 ) + NEW met1 ( 2125430 17510 ) ( 2131870 17510 ) + NEW met2 ( 1826430 231030 ) ( 1826430 260100 0 ) + NEW met2 ( 2125430 17510 ) ( 2125430 231030 ) + NEW met1 ( 1826430 231030 ) ( 2125430 231030 ) + NEW met1 ( 2131870 17510 ) M1M2_PR + NEW met1 ( 2125430 17510 ) M1M2_PR + NEW met1 ( 1826430 231030 ) M1M2_PR + NEW met1 ( 2125430 231030 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[85] ( PIN la_data_in[85] ) ( mprj la_data_in[85] ) + + ROUTED met1 ( 1844370 241570 ) ( 1848970 241570 ) + NEW met2 ( 1844370 241570 ) ( 1844370 260100 0 ) + NEW met1 ( 1848970 26010 ) ( 2149810 26010 ) + NEW met2 ( 2149810 2380 0 ) ( 2149810 26010 ) + NEW met2 ( 1848970 26010 ) ( 1848970 241570 ) + NEW met1 ( 1848970 26010 ) M1M2_PR + NEW met1 ( 1848970 241570 ) M1M2_PR + NEW met1 ( 1844370 241570 ) M1M2_PR + NEW met1 ( 2149810 26010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[86] ( PIN la_data_in[86] ) ( mprj la_data_in[86] ) + + ROUTED met2 ( 1861850 260100 0 ) ( 1862770 260100 ) + NEW met1 ( 2014570 23290 ) ( 2014570 23630 ) + NEW met2 ( 1862770 23970 ) ( 1862770 260100 ) + NEW met1 ( 1932230 23290 ) ( 1932230 23630 ) + NEW li1 ( 1932230 23290 ) ( 1933150 23290 ) + NEW met1 ( 1933150 23290 ) ( 2014570 23290 ) + NEW met1 ( 2041710 23290 ) ( 2041710 23630 ) + NEW met1 ( 2014570 23630 ) ( 2041710 23630 ) + NEW met1 ( 2125430 23290 ) ( 2125430 23630 ) + NEW li1 ( 2125430 11730 ) ( 2125430 23290 ) + NEW met1 ( 2125430 11730 ) ( 2167750 11730 ) + NEW met2 ( 2167750 2380 0 ) ( 2167750 11730 ) + NEW li1 ( 1883930 23970 ) ( 1883930 24650 ) + NEW met1 ( 1883930 24650 ) ( 1931770 24650 ) + NEW li1 ( 1931770 23630 ) ( 1931770 24650 ) + NEW met1 ( 1862770 23970 ) ( 1883930 23970 ) + NEW met1 ( 1931770 23630 ) ( 1932230 23630 ) + NEW li1 ( 2077130 22610 ) ( 2077130 23290 ) + NEW met1 ( 2077130 22610 ) ( 2124970 22610 ) + NEW li1 ( 2124970 22610 ) ( 2124970 23630 ) + NEW met1 ( 2041710 23290 ) ( 2077130 23290 ) + NEW met1 ( 2124970 23630 ) ( 2125430 23630 ) + NEW met1 ( 1862770 23970 ) M1M2_PR + NEW li1 ( 1932230 23290 ) L1M1_PR_MR + NEW li1 ( 1933150 23290 ) L1M1_PR_MR + NEW li1 ( 2125430 23290 ) L1M1_PR_MR + NEW li1 ( 2125430 11730 ) L1M1_PR_MR + NEW met1 ( 2167750 11730 ) M1M2_PR + NEW li1 ( 1883930 23970 ) L1M1_PR_MR + NEW li1 ( 1883930 24650 ) L1M1_PR_MR + NEW li1 ( 1931770 24650 ) L1M1_PR_MR + NEW li1 ( 1931770 23630 ) L1M1_PR_MR + NEW li1 ( 2077130 23290 ) L1M1_PR_MR + NEW li1 ( 2077130 22610 ) L1M1_PR_MR + NEW li1 ( 2124970 22610 ) L1M1_PR_MR + NEW li1 ( 2124970 23630 ) L1M1_PR_MR ++ USE SIGNAL ; +- la_data_in[87] ( PIN la_data_in[87] ) ( mprj la_data_in[87] ) + + ROUTED met1 ( 1879790 243610 ) ( 1883470 243610 ) + NEW met2 ( 1879790 243610 ) ( 1879790 260100 0 ) + NEW met2 ( 1883470 58650 ) ( 1883470 243610 ) + NEW met1 ( 1883470 58650 ) ( 2185230 58650 ) + NEW met2 ( 2185230 2380 0 ) ( 2185230 58650 ) + NEW met1 ( 1883470 243610 ) M1M2_PR + NEW met1 ( 1879790 243610 ) M1M2_PR + NEW met1 ( 1883470 58650 ) M1M2_PR + NEW met1 ( 2185230 58650 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[88] ( PIN la_data_in[88] ) ( mprj la_data_in[88] ) + + ROUTED met2 ( 2203170 2380 0 ) ( 2203170 25330 ) + NEW met1 ( 1897730 243950 ) ( 1904170 243950 ) + NEW met2 ( 1897730 243950 ) ( 1897730 260100 0 ) + NEW met2 ( 1904170 25330 ) ( 1904170 243950 ) + NEW met1 ( 1904170 25330 ) ( 2203170 25330 ) + NEW met1 ( 1904170 25330 ) M1M2_PR + NEW met1 ( 2203170 25330 ) M1M2_PR + NEW met1 ( 1904170 243950 ) M1M2_PR + NEW met1 ( 1897730 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[89] ( PIN la_data_in[89] ) ( mprj la_data_in[89] ) + + ROUTED met2 ( 2221110 2380 0 ) ( 2221110 20570 ) + NEW met1 ( 2215590 20570 ) ( 2221110 20570 ) + NEW met2 ( 1921650 65450 ) ( 1921650 243270 ) + NEW met2 ( 2215590 20570 ) ( 2215590 65450 ) + NEW met2 ( 1915670 243270 ) ( 1915670 260100 0 ) + NEW met1 ( 1915670 243270 ) ( 1921650 243270 ) + NEW met1 ( 1921650 65450 ) ( 2215590 65450 ) + NEW met1 ( 2221110 20570 ) M1M2_PR + NEW met1 ( 2215590 20570 ) M1M2_PR + NEW met1 ( 1921650 65450 ) M1M2_PR + NEW met1 ( 1921650 243270 ) M1M2_PR + NEW met1 ( 2215590 65450 ) M1M2_PR + NEW met1 ( 1915670 243270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[8] ( PIN la_data_in[8] ) ( mprj la_data_in[8] ) + + ROUTED met2 ( 775790 2380 0 ) ( 775790 16660 ) + NEW met2 ( 773030 16660 ) ( 775790 16660 ) + NEW met2 ( 773030 16660 ) ( 773030 134470 ) + NEW met2 ( 467590 260100 0 ) ( 468970 260100 ) + NEW met2 ( 468970 134470 ) ( 468970 260100 ) + NEW met1 ( 468970 134470 ) ( 773030 134470 ) + NEW met1 ( 773030 134470 ) M1M2_PR + NEW met1 ( 468970 134470 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[90] ( PIN la_data_in[90] ) ( mprj la_data_in[90] ) + + ROUTED met2 ( 2239050 2380 0 ) ( 2239050 24650 ) + NEW met1 ( 1933610 243950 ) ( 1938670 243950 ) + NEW met2 ( 1933610 243950 ) ( 1933610 260100 0 ) + NEW met2 ( 1938670 24650 ) ( 1938670 243950 ) + NEW met1 ( 1938670 24650 ) ( 2239050 24650 ) + NEW met1 ( 1938670 24650 ) M1M2_PR + NEW met1 ( 2239050 24650 ) M1M2_PR + NEW met1 ( 1938670 243950 ) M1M2_PR + NEW met1 ( 1933610 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[91] ( PIN la_data_in[91] ) ( mprj la_data_in[91] ) + + ROUTED li1 ( 2015030 23290 ) ( 2015030 24310 ) + NEW li1 ( 2111630 24310 ) ( 2111630 24990 ) + NEW met1 ( 2208230 23630 ) ( 2208230 24310 ) + NEW met2 ( 1951550 260100 0 ) ( 1952470 260100 ) + NEW met2 ( 2256990 12580 ) ( 2256990 23630 ) + NEW met2 ( 2256530 12580 ) ( 2256990 12580 ) + NEW met2 ( 2256530 2380 0 ) ( 2256530 12580 ) + NEW met1 ( 2208230 23630 ) ( 2256990 23630 ) + NEW met2 ( 1952470 24310 ) ( 1952470 260100 ) + NEW met1 ( 1952470 24310 ) ( 2015030 24310 ) + NEW li1 ( 2141070 24310 ) ( 2141070 24990 ) + NEW met1 ( 2111630 24990 ) ( 2141070 24990 ) + NEW met1 ( 2141070 24310 ) ( 2208230 24310 ) + NEW li1 ( 2032050 23290 ) ( 2032050 24310 ) + NEW met1 ( 2015030 23290 ) ( 2032050 23290 ) + NEW met1 ( 2032050 24310 ) ( 2111630 24310 ) + NEW li1 ( 2015030 24310 ) L1M1_PR_MR + NEW li1 ( 2015030 23290 ) L1M1_PR_MR + NEW li1 ( 2111630 24310 ) L1M1_PR_MR + NEW li1 ( 2111630 24990 ) L1M1_PR_MR + NEW met1 ( 2256990 23630 ) M1M2_PR + NEW met1 ( 1952470 24310 ) M1M2_PR + NEW li1 ( 2141070 24990 ) L1M1_PR_MR + NEW li1 ( 2141070 24310 ) L1M1_PR_MR + NEW li1 ( 2032050 23290 ) L1M1_PR_MR + NEW li1 ( 2032050 24310 ) L1M1_PR_MR ++ USE SIGNAL ; +- la_data_in[92] ( PIN la_data_in[92] ) ( mprj la_data_in[92] ) + + ROUTED met2 ( 2274470 2380 0 ) ( 2274470 25670 ) + NEW met2 ( 1969490 260100 0 ) ( 1973170 260100 ) + NEW met1 ( 1973170 25670 ) ( 2274470 25670 ) + NEW met2 ( 1973170 25670 ) ( 1973170 260100 ) + NEW met1 ( 2274470 25670 ) M1M2_PR + NEW met1 ( 1973170 25670 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[93] ( PIN la_data_in[93] ) ( mprj la_data_in[93] ) + + ROUTED met2 ( 2292410 2380 0 ) ( 2292410 3060 ) + NEW met2 ( 2291030 3060 ) ( 2292410 3060 ) + NEW met1 ( 1986970 72250 ) ( 2291030 72250 ) + NEW met2 ( 2291030 3060 ) ( 2291030 72250 ) + NEW met2 ( 1986970 72250 ) ( 1986970 260100 0 ) + NEW met1 ( 1986970 72250 ) M1M2_PR + NEW met1 ( 2291030 72250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[94] ( PIN la_data_in[94] ) ( mprj la_data_in[94] ) + + ROUTED met2 ( 2310350 2380 0 ) ( 2310350 16660 ) + NEW met2 ( 2304830 16660 ) ( 2310350 16660 ) + NEW met2 ( 2304830 16660 ) ( 2304830 217090 ) + NEW met1 ( 2007670 217090 ) ( 2304830 217090 ) + NEW met2 ( 2004910 260100 0 ) ( 2007670 260100 ) + NEW met2 ( 2007670 217090 ) ( 2007670 260100 ) + NEW met1 ( 2304830 217090 ) M1M2_PR + NEW met1 ( 2007670 217090 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[95] ( PIN la_data_in[95] ) ( mprj la_data_in[95] ) + + ROUTED met2 ( 2328290 2380 0 ) ( 2328290 9180 ) + NEW met2 ( 2325530 9180 ) ( 2328290 9180 ) + NEW met1 ( 2022850 243270 ) ( 2028370 243270 ) + NEW met2 ( 2022850 243270 ) ( 2022850 260100 0 ) + NEW met2 ( 2028370 79390 ) ( 2028370 243270 ) + NEW met2 ( 2325530 9180 ) ( 2325530 79390 ) + NEW met1 ( 2028370 79390 ) ( 2325530 79390 ) + NEW met1 ( 2028370 79390 ) M1M2_PR + NEW met1 ( 2028370 243270 ) M1M2_PR + NEW met1 ( 2022850 243270 ) M1M2_PR + NEW met1 ( 2325530 79390 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[96] ( PIN la_data_in[96] ) ( mprj la_data_in[96] ) + + ROUTED met2 ( 2345770 2380 0 ) ( 2345770 18190 ) + NEW met1 ( 2339330 18190 ) ( 2345770 18190 ) + NEW met2 ( 2040790 260100 0 ) ( 2042170 260100 ) + NEW met2 ( 2042170 86190 ) ( 2042170 260100 ) + NEW met2 ( 2339330 18190 ) ( 2339330 86190 ) + NEW met1 ( 2042170 86190 ) ( 2339330 86190 ) + NEW met1 ( 2042170 86190 ) M1M2_PR + NEW met1 ( 2345770 18190 ) M1M2_PR + NEW met1 ( 2339330 18190 ) M1M2_PR + NEW met1 ( 2339330 86190 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[97] ( PIN la_data_in[97] ) ( mprj la_data_in[97] ) + + ROUTED met1 ( 2058730 242250 ) ( 2062870 242250 ) + NEW met2 ( 2058730 242250 ) ( 2058730 260100 0 ) + NEW met2 ( 2062870 92990 ) ( 2062870 242250 ) + NEW met2 ( 2363710 2380 0 ) ( 2363710 2890 ) + NEW met1 ( 2360030 2890 ) ( 2363710 2890 ) + NEW met1 ( 2062870 92990 ) ( 2360030 92990 ) + NEW met2 ( 2360030 2890 ) ( 2360030 92990 ) + NEW met1 ( 2062870 92990 ) M1M2_PR + NEW met1 ( 2062870 242250 ) M1M2_PR + NEW met1 ( 2058730 242250 ) M1M2_PR + NEW met1 ( 2363710 2890 ) M1M2_PR + NEW met1 ( 2360030 2890 ) M1M2_PR + NEW met1 ( 2360030 92990 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[98] ( PIN la_data_in[98] ) ( mprj la_data_in[98] ) + + ROUTED met2 ( 2381650 2380 0 ) ( 2381650 3060 ) + NEW met2 ( 2380730 3060 ) ( 2381650 3060 ) + NEW met1 ( 2076210 210290 ) ( 2380730 210290 ) + NEW met2 ( 2076210 260100 ) ( 2076670 260100 0 ) + NEW met2 ( 2076210 210290 ) ( 2076210 260100 ) + NEW met2 ( 2380730 3060 ) ( 2380730 210290 ) + NEW met1 ( 2076210 210290 ) M1M2_PR + NEW met1 ( 2380730 210290 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[99] ( PIN la_data_in[99] ) ( mprj la_data_in[99] ) + + ROUTED met2 ( 2399590 2380 0 ) ( 2399590 2890 ) + NEW met1 ( 2394530 2890 ) ( 2399590 2890 ) + NEW met1 ( 2097370 203490 ) ( 2394530 203490 ) + NEW met2 ( 2094610 260100 0 ) ( 2097370 260100 ) + NEW met2 ( 2097370 203490 ) ( 2097370 260100 ) + NEW met2 ( 2394530 2890 ) ( 2394530 203490 ) + NEW met1 ( 2097370 203490 ) M1M2_PR + NEW met1 ( 2399590 2890 ) M1M2_PR + NEW met1 ( 2394530 2890 ) M1M2_PR + NEW met1 ( 2394530 203490 ) M1M2_PR ++ USE SIGNAL ; +- la_data_in[9] ( PIN la_data_in[9] ) ( mprj la_data_in[9] ) + + ROUTED met2 ( 793730 2380 0 ) ( 793730 7820 ) + NEW met2 ( 793730 7820 ) ( 794190 7820 ) + NEW met1 ( 485530 243950 ) ( 489670 243950 ) + NEW met2 ( 485530 243950 ) ( 485530 260100 0 ) + NEW met2 ( 489670 141270 ) ( 489670 243950 ) + NEW met2 ( 794190 7820 ) ( 794190 141270 ) + NEW met1 ( 489670 141270 ) ( 794190 141270 ) + NEW met1 ( 489670 141270 ) M1M2_PR + NEW met1 ( 489670 243950 ) M1M2_PR + NEW met1 ( 485530 243950 ) M1M2_PR + NEW met1 ( 794190 141270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[0] ( PIN la_data_out[0] ) ( mprj la_data_out[0] ) + + ROUTED met2 ( 639170 2380 0 ) ( 639170 17340 ) + NEW met2 ( 635030 17340 ) ( 639170 17340 ) + NEW met1 ( 330510 243950 ) ( 334650 243950 ) + NEW met2 ( 330510 243950 ) ( 330510 260100 0 ) + NEW met2 ( 334650 79390 ) ( 334650 243950 ) + NEW met1 ( 334650 79390 ) ( 635030 79390 ) + NEW met2 ( 635030 17340 ) ( 635030 79390 ) + NEW met1 ( 334650 79390 ) M1M2_PR + NEW met1 ( 334650 243950 ) M1M2_PR + NEW met1 ( 330510 243950 ) M1M2_PR + NEW met1 ( 635030 79390 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[100] ( PIN la_data_out[100] ) ( mprj la_data_out[100] ) + + ROUTED met2 ( 2423050 2380 0 ) ( 2423050 17340 ) + NEW met2 ( 2422130 17340 ) ( 2423050 17340 ) + NEW met2 ( 2117610 260100 ) ( 2118070 260100 0 ) + NEW met2 ( 2117610 99790 ) ( 2117610 260100 ) + NEW met2 ( 2422130 17340 ) ( 2422130 99790 ) + NEW met1 ( 2117610 99790 ) ( 2422130 99790 ) + NEW met1 ( 2117610 99790 ) M1M2_PR + NEW met1 ( 2422130 99790 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[101] ( PIN la_data_out[101] ) ( mprj la_data_out[101] ) + + ROUTED met2 ( 2440990 2380 0 ) ( 2440990 17340 ) + NEW met2 ( 2435930 17340 ) ( 2440990 17340 ) + NEW met2 ( 2136010 260100 0 ) ( 2138770 260100 ) + NEW met2 ( 2138770 107270 ) ( 2138770 260100 ) + NEW met2 ( 2435930 17340 ) ( 2435930 107270 ) + NEW met1 ( 2138770 107270 ) ( 2435930 107270 ) + NEW met1 ( 2138770 107270 ) M1M2_PR + NEW met1 ( 2435930 107270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[102] ( PIN la_data_out[102] ) ( mprj la_data_out[102] ) + + ROUTED met1 ( 2153950 243950 ) ( 2159470 243950 ) + NEW met2 ( 2153950 243950 ) ( 2153950 260100 0 ) + NEW met2 ( 2159470 114070 ) ( 2159470 243950 ) + NEW met2 ( 2458930 2380 0 ) ( 2458930 17340 ) + NEW met2 ( 2456630 17340 ) ( 2458930 17340 ) + NEW met1 ( 2159470 114070 ) ( 2456630 114070 ) + NEW met2 ( 2456630 17340 ) ( 2456630 114070 ) + NEW met1 ( 2159470 114070 ) M1M2_PR + NEW met1 ( 2159470 243950 ) M1M2_PR + NEW met1 ( 2153950 243950 ) M1M2_PR + NEW met1 ( 2456630 114070 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[103] ( PIN la_data_out[103] ) ( mprj la_data_out[103] ) + + ROUTED met2 ( 2476870 2380 0 ) ( 2476870 17850 ) + NEW met1 ( 2470890 17850 ) ( 2476870 17850 ) + NEW met1 ( 2173270 120530 ) ( 2470890 120530 ) + NEW met2 ( 2171890 260100 0 ) ( 2173270 260100 ) + NEW met2 ( 2173270 120530 ) ( 2173270 260100 ) + NEW met2 ( 2470890 17850 ) ( 2470890 120530 ) + NEW met1 ( 2173270 120530 ) M1M2_PR + NEW met1 ( 2476870 17850 ) M1M2_PR + NEW met1 ( 2470890 17850 ) M1M2_PR + NEW met1 ( 2470890 120530 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[104] ( PIN la_data_out[104] ) ( mprj la_data_out[104] ) + + ROUTED met2 ( 2494810 2380 0 ) ( 2494810 17340 ) + NEW met2 ( 2491130 17340 ) ( 2494810 17340 ) + NEW met1 ( 2193970 128350 ) ( 2491130 128350 ) + NEW met1 ( 2189830 242250 ) ( 2193970 242250 ) + NEW met2 ( 2189830 242250 ) ( 2189830 260100 0 ) + NEW met2 ( 2193970 128350 ) ( 2193970 242250 ) + NEW met2 ( 2491130 17340 ) ( 2491130 128350 ) + NEW met1 ( 2193970 128350 ) M1M2_PR + NEW met1 ( 2491130 128350 ) M1M2_PR + NEW met1 ( 2193970 242250 ) M1M2_PR + NEW met1 ( 2189830 242250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[105] ( PIN la_data_out[105] ) ( mprj la_data_out[105] ) + + ROUTED met2 ( 2512290 2380 0 ) ( 2512290 148070 ) + NEW met2 ( 2207310 260100 ) ( 2207770 260100 0 ) + NEW met2 ( 2207310 148070 ) ( 2207310 260100 ) + NEW met1 ( 2207310 148070 ) ( 2512290 148070 ) + NEW met1 ( 2512290 148070 ) M1M2_PR + NEW met1 ( 2207310 148070 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[106] ( PIN la_data_out[106] ) ( mprj la_data_out[106] ) + + ROUTED met2 ( 2530230 2380 0 ) ( 2530230 16660 ) + NEW met2 ( 2525630 16660 ) ( 2530230 16660 ) + NEW met2 ( 2225710 260100 0 ) ( 2228470 260100 ) + NEW met2 ( 2228470 135150 ) ( 2228470 260100 ) + NEW met2 ( 2525630 16660 ) ( 2525630 135150 ) + NEW met1 ( 2228470 135150 ) ( 2525630 135150 ) + NEW met1 ( 2228470 135150 ) M1M2_PR + NEW met1 ( 2525630 135150 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[107] ( PIN la_data_out[107] ) ( mprj la_data_out[107] ) + + ROUTED met1 ( 2243190 243950 ) ( 2248710 243950 ) + NEW met2 ( 2243190 243950 ) ( 2243190 260100 0 ) + NEW met2 ( 2248710 141610 ) ( 2248710 243950 ) + NEW met2 ( 2548170 2380 0 ) ( 2548170 16660 ) + NEW met2 ( 2546330 16660 ) ( 2548170 16660 ) + NEW met1 ( 2248710 141610 ) ( 2546330 141610 ) + NEW met2 ( 2546330 16660 ) ( 2546330 141610 ) + NEW met1 ( 2248710 141610 ) M1M2_PR + NEW met1 ( 2248710 243950 ) M1M2_PR + NEW met1 ( 2243190 243950 ) M1M2_PR + NEW met1 ( 2546330 141610 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[108] ( PIN la_data_out[108] ) ( mprj la_data_out[108] ) + + ROUTED met2 ( 2566110 2380 0 ) ( 2566110 16660 ) + NEW met2 ( 2560590 16660 ) ( 2566110 16660 ) + NEW met2 ( 2261130 260100 0 ) ( 2262970 260100 ) + NEW met2 ( 2262970 155210 ) ( 2262970 260100 ) + NEW met1 ( 2262970 155210 ) ( 2560590 155210 ) + NEW met2 ( 2560590 16660 ) ( 2560590 155210 ) + NEW met1 ( 2262970 155210 ) M1M2_PR + NEW met1 ( 2560590 155210 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[109] ( PIN la_data_out[109] ) ( mprj la_data_out[109] ) + + ROUTED met2 ( 2584050 2380 0 ) ( 2584050 16660 ) + NEW met2 ( 2580830 16660 ) ( 2584050 16660 ) + NEW met1 ( 2279070 243950 ) ( 2283670 243950 ) + NEW met2 ( 2279070 243950 ) ( 2279070 260100 0 ) + NEW met2 ( 2283670 162010 ) ( 2283670 243950 ) + NEW met1 ( 2283670 162010 ) ( 2580830 162010 ) + NEW met2 ( 2580830 16660 ) ( 2580830 162010 ) + NEW met1 ( 2283670 162010 ) M1M2_PR + NEW met1 ( 2283670 243950 ) M1M2_PR + NEW met1 ( 2279070 243950 ) M1M2_PR + NEW met1 ( 2580830 162010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[10] ( PIN la_data_out[10] ) ( mprj la_data_out[10] ) + + ROUTED met2 ( 509450 260100 0 ) ( 510370 260100 ) + NEW met2 ( 510370 148070 ) ( 510370 260100 ) + NEW met2 ( 817650 2380 0 ) ( 817650 17340 ) + NEW met2 ( 814430 17340 ) ( 817650 17340 ) + NEW met1 ( 510370 148070 ) ( 814430 148070 ) + NEW met2 ( 814430 17340 ) ( 814430 148070 ) + NEW met1 ( 510370 148070 ) M1M2_PR + NEW met1 ( 814430 148070 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[110] ( PIN la_data_out[110] ) ( mprj la_data_out[110] ) + + ROUTED met2 ( 2601530 2380 0 ) ( 2601530 17340 ) + NEW met2 ( 2601530 17340 ) ( 2601990 17340 ) + NEW met2 ( 2601990 17340 ) ( 2601990 168810 ) + NEW met2 ( 2297010 168810 ) ( 2297010 260100 0 ) + NEW met1 ( 2297010 168810 ) ( 2601990 168810 ) + NEW met1 ( 2601990 168810 ) M1M2_PR + NEW met1 ( 2297010 168810 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[111] ( PIN la_data_out[111] ) ( mprj la_data_out[111] ) + + ROUTED met2 ( 2619470 2380 0 ) ( 2619470 25670 ) + NEW met2 ( 2314950 260100 0 ) ( 2318170 260100 ) + NEW met2 ( 2318170 25670 ) ( 2318170 260100 ) + NEW met1 ( 2318170 25670 ) ( 2619470 25670 ) + NEW met1 ( 2318170 25670 ) M1M2_PR + NEW met1 ( 2619470 25670 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[112] ( PIN la_data_out[112] ) ( mprj la_data_out[112] ) + + ROUTED met2 ( 2637410 2380 0 ) ( 2637410 16660 ) + NEW met2 ( 2636030 16660 ) ( 2637410 16660 ) + NEW met1 ( 2332890 243950 ) ( 2338870 243950 ) + NEW met2 ( 2332890 243950 ) ( 2332890 260100 0 ) + NEW met2 ( 2338870 175950 ) ( 2338870 243950 ) + NEW met2 ( 2636030 16660 ) ( 2636030 175950 ) + NEW met1 ( 2338870 175950 ) ( 2636030 175950 ) + NEW met1 ( 2338870 175950 ) M1M2_PR + NEW met1 ( 2338870 243950 ) M1M2_PR + NEW met1 ( 2332890 243950 ) M1M2_PR + NEW met1 ( 2636030 175950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[113] ( PIN la_data_out[113] ) ( mprj la_data_out[113] ) + + ROUTED met2 ( 2350830 260100 0 ) ( 2352670 260100 ) + NEW met2 ( 2352670 182750 ) ( 2352670 260100 ) + NEW met2 ( 2655350 2380 0 ) ( 2655350 17340 ) + NEW met2 ( 2649830 17340 ) ( 2655350 17340 ) + NEW met1 ( 2352670 182750 ) ( 2649830 182750 ) + NEW met2 ( 2649830 17340 ) ( 2649830 182750 ) + NEW met1 ( 2352670 182750 ) M1M2_PR + NEW met1 ( 2649830 182750 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[114] ( PIN la_data_out[114] ) ( mprj la_data_out[114] ) + + ROUTED met2 ( 2672830 2380 0 ) ( 2672830 17340 ) + NEW met2 ( 2670530 17340 ) ( 2672830 17340 ) + NEW met1 ( 2373370 92990 ) ( 2670530 92990 ) + NEW met1 ( 2368310 243950 ) ( 2373370 243950 ) + NEW met2 ( 2368310 243950 ) ( 2368310 260100 0 ) + NEW met2 ( 2373370 92990 ) ( 2373370 243950 ) + NEW met2 ( 2670530 17340 ) ( 2670530 92990 ) + NEW met1 ( 2373370 92990 ) M1M2_PR + NEW met1 ( 2670530 92990 ) M1M2_PR + NEW met1 ( 2373370 243950 ) M1M2_PR + NEW met1 ( 2368310 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[115] ( PIN la_data_out[115] ) ( mprj la_data_out[115] ) + + ROUTED met2 ( 2411550 38250 ) ( 2411550 248370 ) + NEW met2 ( 2386250 248370 ) ( 2386250 260100 0 ) + NEW met1 ( 2386250 248370 ) ( 2411550 248370 ) + NEW met1 ( 2411550 38250 ) ( 2690770 38250 ) + NEW met2 ( 2690770 2380 0 ) ( 2690770 38250 ) + NEW met1 ( 2411550 38250 ) M1M2_PR + NEW met1 ( 2411550 248370 ) M1M2_PR + NEW met1 ( 2386250 248370 ) M1M2_PR + NEW met1 ( 2690770 38250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[116] ( PIN la_data_out[116] ) ( mprj la_data_out[116] ) + + ROUTED met2 ( 2708710 2380 0 ) ( 2708710 17340 ) + NEW met2 ( 2705030 17340 ) ( 2708710 17340 ) + NEW met1 ( 2404190 243950 ) ( 2407870 243950 ) + NEW met2 ( 2404190 243950 ) ( 2404190 260100 0 ) + NEW met2 ( 2407870 100130 ) ( 2407870 243950 ) + NEW met2 ( 2705030 17340 ) ( 2705030 100130 ) + NEW met1 ( 2407870 100130 ) ( 2705030 100130 ) + NEW met1 ( 2407870 100130 ) M1M2_PR + NEW met1 ( 2705030 100130 ) M1M2_PR + NEW met1 ( 2407870 243950 ) M1M2_PR + NEW met1 ( 2404190 243950 ) M1M2_PR +======= NEW met2 ( 1546290 1700340 ) ( 1547210 1700340 0 ) NEW met2 ( 1546290 1654270 ) ( 1546290 1700340 ) NEW met2 ( 1808030 2890 ) ( 1808030 1654270 ) @@ -78103,10 +82172,32 @@ NEW met1 ( 1729830 1521330 ) M1M2_PR NEW met1 ( 1729830 1684190 ) M1M2_PR NEW met1 ( 1731670 1684190 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - la_data_out[117] ( PIN la_data_out[117] ) ( mprj la_data_out[117] ) + ROUTED met2 ( 2726650 2380 0 ) ( 2726650 17340 ) NEW met2 ( 2725730 17340 ) ( 2726650 17340 ) +<<<<<<< HEAD + NEW met1 ( 2422130 241570 ) ( 2428110 241570 ) + NEW met2 ( 2422130 241570 ) ( 2422130 260100 0 ) + NEW met2 ( 2428110 106930 ) ( 2428110 241570 ) + NEW met2 ( 2725730 17340 ) ( 2725730 106930 ) + NEW met1 ( 2428110 106930 ) ( 2725730 106930 ) + NEW met1 ( 2428110 106930 ) M1M2_PR + NEW met1 ( 2725730 106930 ) M1M2_PR + NEW met1 ( 2428110 241570 ) M1M2_PR + NEW met1 ( 2422130 241570 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[118] ( PIN la_data_out[118] ) ( mprj la_data_out[118] ) + + ROUTED met2 ( 2440070 260100 0 ) ( 2442370 260100 ) + NEW met2 ( 2442370 113730 ) ( 2442370 260100 ) + NEW met2 ( 2744590 2380 0 ) ( 2744590 17340 ) + NEW met2 ( 2739530 17340 ) ( 2744590 17340 ) + NEW met1 ( 2442370 113730 ) ( 2739530 113730 ) + NEW met2 ( 2739530 17340 ) ( 2739530 113730 ) + NEW met1 ( 2442370 113730 ) M1M2_PR + NEW met1 ( 2739530 113730 ) M1M2_PR +======= NEW met2 ( 1735350 1659710 ) ( 1735350 1700340 0 ) NEW met1 ( 1735350 1659710 ) ( 2725730 1659710 ) NEW met2 ( 2725730 17340 ) ( 2725730 1659710 ) @@ -78145,10 +82236,1004 @@ NEW met1 ( 1743170 1587290 ) M1M2_PR NEW met1 ( 1743170 1586610 ) RECT ( -355 -70 0 70 ) NEW met1 ( 1742250 1635230 ) RECT ( -355 -70 0 70 ) +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - la_data_out[119] ( PIN la_data_out[119] ) ( mprj la_data_out[119] ) + ROUTED met2 ( 2762070 2380 0 ) ( 2762070 17340 ) NEW met2 ( 2760230 17340 ) ( 2762070 17340 ) +<<<<<<< HEAD + NEW met1 ( 2463070 120870 ) ( 2760230 120870 ) + NEW met1 ( 2458010 243950 ) ( 2463070 243950 ) + NEW met2 ( 2458010 243950 ) ( 2458010 260100 0 ) + NEW met2 ( 2463070 120870 ) ( 2463070 243950 ) + NEW met2 ( 2760230 17340 ) ( 2760230 120870 ) + NEW met1 ( 2463070 120870 ) M1M2_PR + NEW met1 ( 2760230 120870 ) M1M2_PR + NEW met1 ( 2463070 243950 ) M1M2_PR + NEW met1 ( 2458010 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[11] ( PIN la_data_out[11] ) ( mprj la_data_out[11] ) + + ROUTED met1 ( 527390 243950 ) ( 531070 243950 ) + NEW met2 ( 527390 243950 ) ( 527390 260100 0 ) + NEW met2 ( 531070 155210 ) ( 531070 243950 ) + NEW met1 ( 531070 155210 ) ( 835590 155210 ) + NEW met2 ( 835590 2380 0 ) ( 835590 155210 ) + NEW met1 ( 531070 155210 ) M1M2_PR + NEW met1 ( 531070 243950 ) M1M2_PR + NEW met1 ( 527390 243950 ) M1M2_PR + NEW met1 ( 835590 155210 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[120] ( PIN la_data_out[120] ) ( mprj la_data_out[120] ) + + ROUTED met2 ( 2780010 2380 0 ) ( 2780010 17340 ) + NEW met2 ( 2774490 17340 ) ( 2780010 17340 ) + NEW met1 ( 2476870 127670 ) ( 2774490 127670 ) + NEW met2 ( 2475950 260100 0 ) ( 2476870 260100 ) + NEW met2 ( 2476870 127670 ) ( 2476870 260100 ) + NEW met2 ( 2774490 17340 ) ( 2774490 127670 ) + NEW met1 ( 2476870 127670 ) M1M2_PR + NEW met1 ( 2774490 127670 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[121] ( PIN la_data_out[121] ) ( mprj la_data_out[121] ) + + ROUTED met2 ( 2797950 2380 0 ) ( 2797950 44710 ) + NEW met1 ( 2493430 243950 ) ( 2497570 243950 ) + NEW met2 ( 2493430 243950 ) ( 2493430 260100 0 ) + NEW met2 ( 2497570 44710 ) ( 2497570 243950 ) + NEW met1 ( 2497570 44710 ) ( 2797950 44710 ) + NEW met1 ( 2797950 44710 ) M1M2_PR + NEW met1 ( 2497570 44710 ) M1M2_PR + NEW met1 ( 2497570 243950 ) M1M2_PR + NEW met1 ( 2493430 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[122] ( PIN la_data_out[122] ) ( mprj la_data_out[122] ) + + ROUTED met2 ( 2510910 260100 ) ( 2511370 260100 0 ) + NEW met2 ( 2510910 134470 ) ( 2510910 260100 ) + NEW met2 ( 2815890 2380 0 ) ( 2815890 134470 ) + NEW met1 ( 2510910 134470 ) ( 2815890 134470 ) + NEW met1 ( 2510910 134470 ) M1M2_PR + NEW met1 ( 2815890 134470 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[123] ( PIN la_data_out[123] ) ( mprj la_data_out[123] ) + + ROUTED met2 ( 2833830 2380 0 ) ( 2833830 2890 ) + NEW met1 ( 2829230 2890 ) ( 2833830 2890 ) + NEW met2 ( 2529310 260100 0 ) ( 2532070 260100 ) + NEW met2 ( 2532070 141270 ) ( 2532070 260100 ) + NEW met2 ( 2829230 2890 ) ( 2829230 141270 ) + NEW met1 ( 2532070 141270 ) ( 2829230 141270 ) + NEW met1 ( 2833830 2890 ) M1M2_PR + NEW met1 ( 2829230 2890 ) M1M2_PR + NEW met1 ( 2532070 141270 ) M1M2_PR + NEW met1 ( 2829230 141270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[124] ( PIN la_data_out[124] ) ( mprj la_data_out[124] ) + + ROUTED met2 ( 2851310 2380 0 ) ( 2851310 17340 ) + NEW met2 ( 2849930 17340 ) ( 2851310 17340 ) + NEW met1 ( 2547250 243950 ) ( 2552770 243950 ) + NEW met2 ( 2547250 243950 ) ( 2547250 260100 0 ) + NEW met2 ( 2552770 155550 ) ( 2552770 243950 ) + NEW met1 ( 2552770 155550 ) ( 2849930 155550 ) + NEW met2 ( 2849930 17340 ) ( 2849930 155550 ) + NEW met1 ( 2552770 155550 ) M1M2_PR + NEW met1 ( 2552770 243950 ) M1M2_PR + NEW met1 ( 2547250 243950 ) M1M2_PR + NEW met1 ( 2849930 155550 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[125] ( PIN la_data_out[125] ) ( mprj la_data_out[125] ) + + ROUTED met2 ( 2869250 2380 0 ) ( 2869250 18530 ) + NEW met1 ( 2566570 18530 ) ( 2869250 18530 ) + NEW met2 ( 2565190 260100 0 ) ( 2566570 260100 ) + NEW met2 ( 2566570 18530 ) ( 2566570 260100 ) + NEW met1 ( 2566570 18530 ) M1M2_PR + NEW met1 ( 2869250 18530 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[126] ( PIN la_data_out[126] ) ( mprj la_data_out[126] ) + + ROUTED met2 ( 2887190 2380 0 ) ( 2887190 17170 ) + NEW met1 ( 2587270 17170 ) ( 2887190 17170 ) + NEW met1 ( 2583130 243950 ) ( 2587270 243950 ) + NEW met2 ( 2583130 243950 ) ( 2583130 260100 0 ) + NEW met2 ( 2587270 17170 ) ( 2587270 243950 ) + NEW met1 ( 2887190 17170 ) M1M2_PR + NEW met1 ( 2587270 17170 ) M1M2_PR + NEW met1 ( 2587270 243950 ) M1M2_PR + NEW met1 ( 2583130 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[127] ( PIN la_data_out[127] ) ( mprj la_data_out[127] ) + + ROUTED met2 ( 2905130 2380 0 ) ( 2905130 16660 ) + NEW met2 ( 2601070 16660 ) ( 2601070 260100 0 ) + NEW met3 ( 2601070 16660 ) ( 2905130 16660 ) + NEW met2 ( 2601070 16660 ) via2_FR + NEW met2 ( 2905130 16660 ) via2_FR ++ USE SIGNAL ; +- la_data_out[12] ( PIN la_data_out[12] ) ( mprj la_data_out[12] ) + + ROUTED met2 ( 853070 2380 0 ) ( 853070 17340 ) + NEW met2 ( 848930 17340 ) ( 853070 17340 ) + NEW met1 ( 545330 243950 ) ( 551770 243950 ) + NEW met2 ( 545330 243950 ) ( 545330 260100 0 ) + NEW met2 ( 551770 162010 ) ( 551770 243950 ) + NEW met1 ( 551770 162010 ) ( 848930 162010 ) + NEW met2 ( 848930 17340 ) ( 848930 162010 ) + NEW met1 ( 551770 162010 ) M1M2_PR + NEW met1 ( 551770 243950 ) M1M2_PR + NEW met1 ( 545330 243950 ) M1M2_PR + NEW met1 ( 848930 162010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[13] ( PIN la_data_out[13] ) ( mprj la_data_out[13] ) + + ROUTED met2 ( 871010 2380 0 ) ( 871010 16660 ) + NEW met2 ( 869630 16660 ) ( 871010 16660 ) + NEW met2 ( 869630 16660 ) ( 869630 231370 ) + NEW met2 ( 563270 231370 ) ( 563270 260100 0 ) + NEW met1 ( 563270 231370 ) ( 869630 231370 ) + NEW met1 ( 869630 231370 ) M1M2_PR + NEW met1 ( 563270 231370 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[14] ( PIN la_data_out[14] ) ( mprj la_data_out[14] ) + + ROUTED met2 ( 888950 2380 0 ) ( 888950 16660 ) + NEW met2 ( 883430 16660 ) ( 888950 16660 ) + NEW met1 ( 580750 243950 ) ( 586270 243950 ) + NEW met2 ( 580750 243950 ) ( 580750 260100 0 ) + NEW met2 ( 586270 168810 ) ( 586270 243950 ) + NEW met2 ( 883430 16660 ) ( 883430 168810 ) + NEW met1 ( 586270 168810 ) ( 883430 168810 ) + NEW met1 ( 586270 168810 ) M1M2_PR + NEW met1 ( 586270 243950 ) M1M2_PR + NEW met1 ( 580750 243950 ) M1M2_PR + NEW met1 ( 883430 168810 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[15] ( PIN la_data_out[15] ) ( mprj la_data_out[15] ) + + ROUTED met2 ( 598690 260100 0 ) ( 600070 260100 ) + NEW met2 ( 600070 175950 ) ( 600070 260100 ) + NEW met2 ( 906890 2380 0 ) ( 906890 16660 ) + NEW met2 ( 904130 16660 ) ( 906890 16660 ) + NEW met1 ( 600070 175950 ) ( 904130 175950 ) + NEW met2 ( 904130 16660 ) ( 904130 175950 ) + NEW met1 ( 600070 175950 ) M1M2_PR + NEW met1 ( 904130 175950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[16] ( PIN la_data_out[16] ) ( mprj la_data_out[16] ) + + ROUTED met2 ( 924370 2380 0 ) ( 924370 17850 ) + NEW met1 ( 917930 17850 ) ( 924370 17850 ) + NEW met1 ( 620770 182750 ) ( 917930 182750 ) + NEW met1 ( 616630 243950 ) ( 620770 243950 ) + NEW met2 ( 616630 243950 ) ( 616630 260100 0 ) + NEW met2 ( 620770 182750 ) ( 620770 243950 ) + NEW met2 ( 917930 17850 ) ( 917930 182750 ) + NEW met1 ( 620770 182750 ) M1M2_PR + NEW met1 ( 924370 17850 ) M1M2_PR + NEW met1 ( 917930 17850 ) M1M2_PR + NEW met1 ( 917930 182750 ) M1M2_PR + NEW met1 ( 620770 243950 ) M1M2_PR + NEW met1 ( 616630 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[17] ( PIN la_data_out[17] ) ( mprj la_data_out[17] ) + + ROUTED met2 ( 942310 2380 0 ) ( 942310 16660 ) + NEW met2 ( 938630 16660 ) ( 942310 16660 ) + NEW met1 ( 634110 196690 ) ( 938630 196690 ) + NEW met2 ( 634110 260100 ) ( 634570 260100 0 ) + NEW met2 ( 634110 196690 ) ( 634110 260100 ) + NEW met2 ( 938630 16660 ) ( 938630 196690 ) + NEW met1 ( 634110 196690 ) M1M2_PR + NEW met1 ( 938630 196690 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[18] ( PIN la_data_out[18] ) ( mprj la_data_out[18] ) + + ROUTED met2 ( 960250 2380 0 ) ( 960250 16660 ) + NEW met2 ( 959330 16660 ) ( 960250 16660 ) + NEW met2 ( 959330 16660 ) ( 959330 224230 ) + NEW met1 ( 655270 224230 ) ( 959330 224230 ) + NEW met2 ( 652510 260100 0 ) ( 655270 260100 ) + NEW met2 ( 655270 224230 ) ( 655270 260100 ) + NEW met1 ( 959330 224230 ) M1M2_PR + NEW met1 ( 655270 224230 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[19] ( PIN la_data_out[19] ) ( mprj la_data_out[19] ) + + ROUTED met2 ( 978190 2380 0 ) ( 978190 16660 ) + NEW met2 ( 973130 16660 ) ( 978190 16660 ) + NEW met1 ( 670450 243950 ) ( 675970 243950 ) + NEW met2 ( 670450 243950 ) ( 670450 260100 0 ) + NEW met2 ( 675970 189550 ) ( 675970 243950 ) + NEW met2 ( 973130 16660 ) ( 973130 189550 ) + NEW met1 ( 675970 189550 ) ( 973130 189550 ) + NEW met1 ( 675970 189550 ) M1M2_PR + NEW met1 ( 973130 189550 ) M1M2_PR + NEW met1 ( 675970 243950 ) M1M2_PR + NEW met1 ( 670450 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[1] ( PIN la_data_out[1] ) ( mprj la_data_out[1] ) + + ROUTED met2 ( 657110 2380 0 ) ( 657110 17340 ) + NEW met2 ( 655730 17340 ) ( 657110 17340 ) + NEW met1 ( 351670 189550 ) ( 655730 189550 ) + NEW met2 ( 348450 260100 0 ) ( 351670 260100 ) + NEW met2 ( 351670 189550 ) ( 351670 260100 ) + NEW met2 ( 655730 17340 ) ( 655730 189550 ) + NEW met1 ( 351670 189550 ) M1M2_PR + NEW met1 ( 655730 189550 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[20] ( PIN la_data_out[20] ) ( mprj la_data_out[20] ) + + ROUTED met2 ( 688390 260100 0 ) ( 689770 260100 ) + NEW met2 ( 689770 37910 ) ( 689770 260100 ) + NEW met2 ( 996130 2380 0 ) ( 996130 37910 ) + NEW met1 ( 689770 37910 ) ( 996130 37910 ) + NEW met1 ( 689770 37910 ) M1M2_PR + NEW met1 ( 996130 37910 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[21] ( PIN la_data_out[21] ) ( mprj la_data_out[21] ) + + ROUTED met1 ( 705870 243950 ) ( 710470 243950 ) + NEW met2 ( 705870 243950 ) ( 705870 260100 0 ) + NEW met2 ( 710470 203830 ) ( 710470 243950 ) + NEW met2 ( 1013610 2380 0 ) ( 1013610 17850 ) + NEW met1 ( 1007630 17850 ) ( 1013610 17850 ) + NEW met1 ( 710470 203830 ) ( 1007630 203830 ) + NEW met2 ( 1007630 17850 ) ( 1007630 203830 ) + NEW met1 ( 710470 203830 ) M1M2_PR + NEW met1 ( 710470 243950 ) M1M2_PR + NEW met1 ( 705870 243950 ) M1M2_PR + NEW met1 ( 1013610 17850 ) M1M2_PR + NEW met1 ( 1007630 17850 ) M1M2_PR + NEW met1 ( 1007630 203830 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[22] ( PIN la_data_out[22] ) ( mprj la_data_out[22] ) + + ROUTED met2 ( 1031550 2380 0 ) ( 1031550 16660 ) + NEW met2 ( 1028330 16660 ) ( 1031550 16660 ) + NEW met1 ( 723810 210290 ) ( 1028330 210290 ) + NEW met2 ( 723810 210290 ) ( 723810 260100 0 ) + NEW met2 ( 1028330 16660 ) ( 1028330 210290 ) + NEW met1 ( 723810 210290 ) M1M2_PR + NEW met1 ( 1028330 210290 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[23] ( PIN la_data_out[23] ) ( mprj la_data_out[23] ) + + ROUTED met2 ( 1049490 2380 0 ) ( 1049490 217090 ) + NEW met1 ( 744970 217090 ) ( 1049490 217090 ) + NEW met2 ( 741750 260100 0 ) ( 744970 260100 ) + NEW met2 ( 744970 217090 ) ( 744970 260100 ) + NEW met1 ( 1049490 217090 ) M1M2_PR + NEW met1 ( 744970 217090 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[24] ( PIN la_data_out[24] ) ( mprj la_data_out[24] ) + + ROUTED met2 ( 1067430 2380 0 ) ( 1067430 16660 ) + NEW met2 ( 1062830 16660 ) ( 1067430 16660 ) + NEW met1 ( 759690 243950 ) ( 765210 243950 ) + NEW met2 ( 759690 243950 ) ( 759690 260100 0 ) + NEW met2 ( 765210 148410 ) ( 765210 243950 ) + NEW met2 ( 1062830 16660 ) ( 1062830 148410 ) + NEW met1 ( 765210 148410 ) ( 1062830 148410 ) + NEW met1 ( 765210 148410 ) M1M2_PR + NEW met1 ( 765210 243950 ) M1M2_PR + NEW met1 ( 759690 243950 ) M1M2_PR + NEW met1 ( 1062830 148410 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[25] ( PIN la_data_out[25] ) ( mprj la_data_out[25] ) + + ROUTED met2 ( 1085370 2380 0 ) ( 1085370 16660 ) + NEW met2 ( 1083530 16660 ) ( 1085370 16660 ) + NEW met2 ( 777630 260100 0 ) ( 779470 260100 ) + NEW met2 ( 779470 155550 ) ( 779470 260100 ) + NEW met2 ( 1083530 16660 ) ( 1083530 155550 ) + NEW met1 ( 779470 155550 ) ( 1083530 155550 ) + NEW met1 ( 779470 155550 ) M1M2_PR + NEW met1 ( 1083530 155550 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[26] ( PIN la_data_out[26] ) ( mprj la_data_out[26] ) + + ROUTED met1 ( 795570 243950 ) ( 800170 243950 ) + NEW met2 ( 795570 243950 ) ( 795570 260100 0 ) + NEW met2 ( 800170 162350 ) ( 800170 243950 ) + NEW met2 ( 1102850 2380 0 ) ( 1102850 16660 ) + NEW met2 ( 1097330 16660 ) ( 1102850 16660 ) + NEW met1 ( 800170 162350 ) ( 1097330 162350 ) + NEW met2 ( 1097330 16660 ) ( 1097330 162350 ) + NEW met1 ( 800170 162350 ) M1M2_PR + NEW met1 ( 800170 243950 ) M1M2_PR + NEW met1 ( 795570 243950 ) M1M2_PR + NEW met1 ( 1097330 162350 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[27] ( PIN la_data_out[27] ) ( mprj la_data_out[27] ) + + ROUTED met2 ( 1120790 2380 0 ) ( 1120790 16660 ) + NEW met2 ( 1118030 16660 ) ( 1120790 16660 ) + NEW met2 ( 813510 231030 ) ( 813510 260100 0 ) + NEW met1 ( 813510 231030 ) ( 1118030 231030 ) + NEW met2 ( 1118030 16660 ) ( 1118030 231030 ) + NEW met1 ( 813510 231030 ) M1M2_PR + NEW met1 ( 1118030 231030 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[28] ( PIN la_data_out[28] ) ( mprj la_data_out[28] ) + + ROUTED met2 ( 1138730 2380 0 ) ( 1138730 17340 ) + NEW met2 ( 1138730 17340 ) ( 1139190 17340 ) + NEW met1 ( 830990 242590 ) ( 838350 242590 ) + NEW met2 ( 830990 242590 ) ( 830990 260100 0 ) + NEW met2 ( 838350 169150 ) ( 838350 242590 ) + NEW met1 ( 838350 169150 ) ( 1139190 169150 ) + NEW met2 ( 1139190 17340 ) ( 1139190 169150 ) + NEW met1 ( 838350 169150 ) M1M2_PR + NEW met1 ( 838350 242590 ) M1M2_PR + NEW met1 ( 830990 242590 ) M1M2_PR + NEW met1 ( 1139190 169150 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[29] ( PIN la_data_out[29] ) ( mprj la_data_out[29] ) + + ROUTED met2 ( 1156670 2380 0 ) ( 1156670 17340 ) + NEW met2 ( 1152530 17340 ) ( 1156670 17340 ) + NEW met2 ( 1152530 17340 ) ( 1152530 176290 ) + NEW met1 ( 848930 243950 ) ( 854910 243950 ) + NEW met2 ( 848930 243950 ) ( 848930 260100 0 ) + NEW met2 ( 854910 176290 ) ( 854910 243950 ) + NEW met1 ( 854910 176290 ) ( 1152530 176290 ) + NEW met1 ( 1152530 176290 ) M1M2_PR + NEW met1 ( 854910 176290 ) M1M2_PR + NEW met1 ( 854910 243950 ) M1M2_PR + NEW met1 ( 848930 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[2] ( PIN la_data_out[2] ) ( mprj la_data_out[2] ) + + ROUTED met2 ( 674590 2380 0 ) ( 674590 16660 ) + NEW met2 ( 669530 16660 ) ( 674590 16660 ) + NEW met2 ( 669530 16660 ) ( 669530 203490 ) + NEW met1 ( 372370 203490 ) ( 669530 203490 ) + NEW met1 ( 366390 243950 ) ( 372370 243950 ) + NEW met2 ( 366390 243950 ) ( 366390 260100 0 ) + NEW met2 ( 372370 203490 ) ( 372370 243950 ) + NEW met1 ( 669530 203490 ) M1M2_PR + NEW met1 ( 372370 203490 ) M1M2_PR + NEW met1 ( 372370 243950 ) M1M2_PR + NEW met1 ( 366390 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[30] ( PIN la_data_out[30] ) ( mprj la_data_out[30] ) + + ROUTED met2 ( 1174150 2380 0 ) ( 1174150 24310 ) + NEW met2 ( 866870 260100 0 ) ( 869170 260100 ) + NEW met2 ( 869170 24310 ) ( 869170 260100 ) + NEW met1 ( 869170 24310 ) ( 1174150 24310 ) + NEW met1 ( 869170 24310 ) M1M2_PR + NEW met1 ( 1174150 24310 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[31] ( PIN la_data_out[31] ) ( mprj la_data_out[31] ) + + ROUTED met2 ( 1192090 2380 0 ) ( 1192090 17340 ) + NEW met2 ( 1187030 17340 ) ( 1192090 17340 ) + NEW met1 ( 884810 243950 ) ( 889870 243950 ) + NEW met2 ( 884810 243950 ) ( 884810 260100 0 ) + NEW met2 ( 889870 183430 ) ( 889870 243950 ) + NEW met2 ( 1187030 17340 ) ( 1187030 183430 ) + NEW met1 ( 889870 183430 ) ( 1187030 183430 ) + NEW met1 ( 889870 183430 ) M1M2_PR + NEW met1 ( 1187030 183430 ) M1M2_PR + NEW met1 ( 889870 243950 ) M1M2_PR + NEW met1 ( 884810 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[32] ( PIN la_data_out[32] ) ( mprj la_data_out[32] ) + + ROUTED met2 ( 902750 260100 0 ) ( 903670 260100 ) + NEW met2 ( 903670 197030 ) ( 903670 260100 ) + NEW met2 ( 1210030 2380 0 ) ( 1210030 16660 ) + NEW met2 ( 1207730 16660 ) ( 1210030 16660 ) + NEW met1 ( 903670 197030 ) ( 1207730 197030 ) + NEW met2 ( 1207730 16660 ) ( 1207730 197030 ) + NEW met1 ( 903670 197030 ) M1M2_PR + NEW met1 ( 1207730 197030 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[33] ( PIN la_data_out[33] ) ( mprj la_data_out[33] ) + + ROUTED met2 ( 1227970 2380 0 ) ( 1227970 17510 ) + NEW met1 ( 1221530 17510 ) ( 1227970 17510 ) + NEW met1 ( 924370 224910 ) ( 1221530 224910 ) + NEW met2 ( 920690 260100 0 ) ( 924370 260100 ) + NEW met2 ( 924370 224910 ) ( 924370 260100 ) + NEW met2 ( 1221530 17510 ) ( 1221530 224910 ) + NEW met1 ( 924370 224910 ) M1M2_PR + NEW met1 ( 1227970 17510 ) M1M2_PR + NEW met1 ( 1221530 17510 ) M1M2_PR + NEW met1 ( 1221530 224910 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[34] ( PIN la_data_out[34] ) ( mprj la_data_out[34] ) + + ROUTED met2 ( 1245910 2380 0 ) ( 1245910 16660 ) + NEW met2 ( 1242230 16660 ) ( 1245910 16660 ) + NEW met2 ( 1242230 16660 ) ( 1242230 189890 ) + NEW met1 ( 945070 189890 ) ( 1242230 189890 ) + NEW met1 ( 938630 243950 ) ( 945070 243950 ) + NEW met2 ( 938630 243950 ) ( 938630 260100 0 ) + NEW met2 ( 945070 189890 ) ( 945070 243950 ) + NEW met1 ( 1242230 189890 ) M1M2_PR + NEW met1 ( 945070 189890 ) M1M2_PR + NEW met1 ( 945070 243950 ) M1M2_PR + NEW met1 ( 938630 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[35] ( PIN la_data_out[35] ) ( mprj la_data_out[35] ) + + ROUTED met2 ( 956110 260100 0 ) ( 958870 260100 ) + NEW met2 ( 958870 148070 ) ( 958870 260100 ) + NEW met2 ( 1263390 2380 0 ) ( 1263390 148070 ) + NEW met1 ( 958870 148070 ) ( 1263390 148070 ) + NEW met1 ( 958870 148070 ) M1M2_PR + NEW met1 ( 1263390 148070 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[36] ( PIN la_data_out[36] ) ( mprj la_data_out[36] ) + + ROUTED met2 ( 1281330 2380 0 ) ( 1281330 16660 ) + NEW met2 ( 1276730 16660 ) ( 1281330 16660 ) + NEW met2 ( 974050 238170 ) ( 974050 260100 0 ) + NEW met2 ( 1276730 16660 ) ( 1276730 238170 ) + NEW met1 ( 974050 238170 ) ( 1276730 238170 ) + NEW met1 ( 974050 238170 ) M1M2_PR + NEW met1 ( 1276730 238170 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[37] ( PIN la_data_out[37] ) ( mprj la_data_out[37] ) + + ROUTED met2 ( 991990 260100 0 ) ( 993370 260100 ) + NEW met2 ( 993370 203490 ) ( 993370 260100 ) + NEW met2 ( 1299270 2380 0 ) ( 1299270 17340 ) + NEW met2 ( 1297430 17340 ) ( 1299270 17340 ) + NEW met1 ( 993370 203490 ) ( 1297430 203490 ) + NEW met2 ( 1297430 17340 ) ( 1297430 203490 ) + NEW met1 ( 993370 203490 ) M1M2_PR + NEW met1 ( 1297430 203490 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[38] ( PIN la_data_out[38] ) ( mprj la_data_out[38] ) + + ROUTED met2 ( 1317210 2380 0 ) ( 1317210 19550 ) + NEW met1 ( 1311230 19550 ) ( 1317210 19550 ) + NEW met1 ( 1014070 210630 ) ( 1311230 210630 ) + NEW met1 ( 1009930 243950 ) ( 1014070 243950 ) + NEW met2 ( 1009930 243950 ) ( 1009930 260100 0 ) + NEW met2 ( 1014070 210630 ) ( 1014070 243950 ) + NEW met2 ( 1311230 19550 ) ( 1311230 210630 ) + NEW met1 ( 1014070 210630 ) M1M2_PR + NEW met1 ( 1317210 19550 ) M1M2_PR + NEW met1 ( 1311230 19550 ) M1M2_PR + NEW met1 ( 1311230 210630 ) M1M2_PR + NEW met1 ( 1014070 243950 ) M1M2_PR + NEW met1 ( 1009930 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[39] ( PIN la_data_out[39] ) ( mprj la_data_out[39] ) + + ROUTED met2 ( 1335150 2380 0 ) ( 1335150 17340 ) + NEW met2 ( 1331930 17340 ) ( 1335150 17340 ) + NEW met2 ( 1027410 260100 ) ( 1027870 260100 0 ) + NEW met2 ( 1027410 155210 ) ( 1027410 260100 ) + NEW met1 ( 1027410 155210 ) ( 1331930 155210 ) + NEW met2 ( 1331930 17340 ) ( 1331930 155210 ) + NEW met1 ( 1027410 155210 ) M1M2_PR + NEW met1 ( 1331930 155210 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[3] ( PIN la_data_out[3] ) ( mprj la_data_out[3] ) + + ROUTED met2 ( 692530 2380 0 ) ( 692530 16660 ) + NEW met2 ( 690230 16660 ) ( 692530 16660 ) + NEW met2 ( 384330 238170 ) ( 384330 260100 0 ) + NEW met2 ( 690230 16660 ) ( 690230 238170 ) + NEW met1 ( 384330 238170 ) ( 690230 238170 ) + NEW met1 ( 384330 238170 ) M1M2_PR + NEW met1 ( 690230 238170 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[40] ( PIN la_data_out[40] ) ( mprj la_data_out[40] ) + + ROUTED met2 ( 1353090 15980 ) ( 1353090 30770 ) + NEW met2 ( 1352630 15980 ) ( 1353090 15980 ) + NEW met2 ( 1352630 2380 0 ) ( 1352630 15980 ) + NEW met1 ( 1048570 30770 ) ( 1353090 30770 ) + NEW met2 ( 1045810 260100 0 ) ( 1048570 260100 ) + NEW met2 ( 1048570 30770 ) ( 1048570 260100 ) + NEW met1 ( 1353090 30770 ) M1M2_PR + NEW met1 ( 1048570 30770 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[41] ( PIN la_data_out[41] ) ( mprj la_data_out[41] ) + + ROUTED met2 ( 1370570 2380 0 ) ( 1370570 17340 ) + NEW met2 ( 1366430 17340 ) ( 1370570 17340 ) + NEW met1 ( 1063750 243950 ) ( 1069270 243950 ) + NEW met2 ( 1063750 243950 ) ( 1063750 260100 0 ) + NEW met2 ( 1069270 217090 ) ( 1069270 243950 ) + NEW met2 ( 1366430 17340 ) ( 1366430 217090 ) + NEW met1 ( 1069270 217090 ) ( 1366430 217090 ) + NEW met1 ( 1069270 217090 ) M1M2_PR + NEW met1 ( 1366430 217090 ) M1M2_PR + NEW met1 ( 1069270 243950 ) M1M2_PR + NEW met1 ( 1063750 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[42] ( PIN la_data_out[42] ) ( mprj la_data_out[42] ) + + ROUTED met2 ( 1081230 260100 0 ) ( 1083070 260100 ) + NEW met2 ( 1083070 162010 ) ( 1083070 260100 ) + NEW met2 ( 1388510 2380 0 ) ( 1388510 16830 ) + NEW met2 ( 1387130 16830 ) ( 1388510 16830 ) + NEW met1 ( 1083070 162010 ) ( 1387130 162010 ) + NEW met2 ( 1387130 16830 ) ( 1387130 162010 ) + NEW met1 ( 1083070 162010 ) M1M2_PR + NEW met1 ( 1387130 162010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[43] ( PIN la_data_out[43] ) ( mprj la_data_out[43] ) + + ROUTED met2 ( 1406450 2380 0 ) ( 1406450 16830 ) + NEW met2 ( 1400930 16830 ) ( 1406450 16830 ) + NEW met2 ( 1099170 231710 ) ( 1099170 260100 0 ) + NEW met1 ( 1099170 231710 ) ( 1400930 231710 ) + NEW met2 ( 1400930 16830 ) ( 1400930 231710 ) + NEW met1 ( 1099170 231710 ) M1M2_PR + NEW met1 ( 1400930 231710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[44] ( PIN la_data_out[44] ) ( mprj la_data_out[44] ) + + ROUTED met2 ( 1423930 2380 0 ) ( 1423930 16830 ) + NEW met2 ( 1421630 16830 ) ( 1423930 16830 ) + NEW met2 ( 1117110 168810 ) ( 1117110 260100 0 ) + NEW met1 ( 1117110 168810 ) ( 1421630 168810 ) + NEW met2 ( 1421630 16830 ) ( 1421630 168810 ) + NEW met1 ( 1117110 168810 ) M1M2_PR + NEW met1 ( 1421630 168810 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[45] ( PIN la_data_out[45] ) ( mprj la_data_out[45] ) + + ROUTED met2 ( 1441870 2380 0 ) ( 1441870 16830 ) + NEW met1 ( 1435430 16830 ) ( 1441870 16830 ) + NEW met2 ( 1435430 16830 ) ( 1435430 176630 ) + NEW met2 ( 1135050 260100 0 ) ( 1138270 260100 ) + NEW met2 ( 1138270 176630 ) ( 1138270 260100 ) + NEW met1 ( 1138270 176630 ) ( 1435430 176630 ) + NEW met1 ( 1441870 16830 ) M1M2_PR + NEW met1 ( 1435430 16830 ) M1M2_PR + NEW met1 ( 1435430 176630 ) M1M2_PR + NEW met1 ( 1138270 176630 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[46] ( PIN la_data_out[46] ) ( mprj la_data_out[46] ) + + ROUTED met2 ( 1459810 2380 0 ) ( 1459810 16660 ) + NEW met2 ( 1456130 16660 ) ( 1459810 16660 ) + NEW met1 ( 1152990 243270 ) ( 1158510 243270 ) + NEW met2 ( 1152990 243270 ) ( 1152990 260100 0 ) + NEW met2 ( 1158510 183090 ) ( 1158510 243270 ) + NEW met2 ( 1456130 16660 ) ( 1456130 183090 ) + NEW met1 ( 1158510 183090 ) ( 1456130 183090 ) + NEW met1 ( 1158510 183090 ) M1M2_PR + NEW met1 ( 1456130 183090 ) M1M2_PR + NEW met1 ( 1158510 243270 ) M1M2_PR + NEW met1 ( 1152990 243270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[47] ( PIN la_data_out[47] ) ( mprj la_data_out[47] ) + + ROUTED met2 ( 1477750 2380 0 ) ( 1477750 17170 ) + NEW met2 ( 1476830 17170 ) ( 1477750 17170 ) + NEW met2 ( 1170930 260100 0 ) ( 1172770 260100 ) + NEW met2 ( 1172770 196690 ) ( 1172770 260100 ) + NEW met2 ( 1476830 17170 ) ( 1476830 196690 ) + NEW met1 ( 1172770 196690 ) ( 1476830 196690 ) + NEW met1 ( 1172770 196690 ) M1M2_PR + NEW met1 ( 1476830 196690 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[48] ( PIN la_data_out[48] ) ( mprj la_data_out[48] ) + + ROUTED met1 ( 1188870 243950 ) ( 1193470 243950 ) + NEW met2 ( 1188870 243950 ) ( 1188870 260100 0 ) + NEW met2 ( 1193470 224570 ) ( 1193470 243950 ) + NEW met2 ( 1495690 2380 0 ) ( 1495690 17340 ) + NEW met2 ( 1490630 17340 ) ( 1495690 17340 ) + NEW met1 ( 1193470 224570 ) ( 1490630 224570 ) + NEW met2 ( 1490630 17340 ) ( 1490630 224570 ) + NEW met1 ( 1193470 224570 ) M1M2_PR + NEW met1 ( 1193470 243950 ) M1M2_PR + NEW met1 ( 1188870 243950 ) M1M2_PR + NEW met1 ( 1490630 224570 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[49] ( PIN la_data_out[49] ) ( mprj la_data_out[49] ) + + ROUTED met2 ( 1513170 2380 0 ) ( 1513170 17340 ) + NEW met2 ( 1511330 17340 ) ( 1513170 17340 ) + NEW met1 ( 1206810 189550 ) ( 1511330 189550 ) + NEW met2 ( 1206810 189550 ) ( 1206810 260100 0 ) + NEW met2 ( 1511330 17340 ) ( 1511330 189550 ) + NEW met1 ( 1206810 189550 ) M1M2_PR + NEW met1 ( 1511330 189550 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[4] ( PIN la_data_out[4] ) ( mprj la_data_out[4] ) + + ROUTED met2 ( 710470 2380 0 ) ( 710470 19210 ) + NEW met1 ( 704030 19210 ) ( 710470 19210 ) + NEW met1 ( 402270 243950 ) ( 406870 243950 ) + NEW met2 ( 402270 243950 ) ( 402270 260100 0 ) + NEW met2 ( 406870 210290 ) ( 406870 243950 ) + NEW met2 ( 704030 19210 ) ( 704030 210290 ) + NEW met1 ( 406870 210290 ) ( 704030 210290 ) + NEW met1 ( 406870 210290 ) M1M2_PR + NEW met1 ( 710470 19210 ) M1M2_PR + NEW met1 ( 704030 19210 ) M1M2_PR + NEW met1 ( 704030 210290 ) M1M2_PR + NEW met1 ( 406870 243950 ) M1M2_PR + NEW met1 ( 402270 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[50] ( PIN la_data_out[50] ) ( mprj la_data_out[50] ) + + ROUTED met2 ( 1531110 2380 0 ) ( 1531110 17850 ) + NEW met1 ( 1525130 17850 ) ( 1531110 17850 ) + NEW met2 ( 1224290 260100 0 ) ( 1227970 260100 ) + NEW met2 ( 1227970 148750 ) ( 1227970 260100 ) + NEW met1 ( 1227970 148750 ) ( 1525130 148750 ) + NEW met2 ( 1525130 17850 ) ( 1525130 148750 ) + NEW met1 ( 1531110 17850 ) M1M2_PR + NEW met1 ( 1525130 17850 ) M1M2_PR + NEW met1 ( 1227970 148750 ) M1M2_PR + NEW met1 ( 1525130 148750 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[51] ( PIN la_data_out[51] ) ( mprj la_data_out[51] ) + + ROUTED met2 ( 1549050 2380 0 ) ( 1549050 16660 ) + NEW met2 ( 1545830 16660 ) ( 1549050 16660 ) + NEW met1 ( 1242230 243950 ) ( 1248210 243950 ) + NEW met2 ( 1242230 243950 ) ( 1242230 260100 0 ) + NEW met2 ( 1248210 203830 ) ( 1248210 243950 ) + NEW met2 ( 1545830 16660 ) ( 1545830 203830 ) + NEW met1 ( 1248210 203830 ) ( 1545830 203830 ) + NEW met1 ( 1248210 203830 ) M1M2_PR + NEW met1 ( 1545830 203830 ) M1M2_PR + NEW met1 ( 1248210 243950 ) M1M2_PR + NEW met1 ( 1242230 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[52] ( PIN la_data_out[52] ) ( mprj la_data_out[52] ) + + ROUTED met2 ( 1260170 260100 0 ) ( 1262470 260100 ) + NEW met2 ( 1262470 141610 ) ( 1262470 260100 ) + NEW met2 ( 1566990 2380 0 ) ( 1566990 141610 ) + NEW met1 ( 1262470 141610 ) ( 1566990 141610 ) + NEW met1 ( 1262470 141610 ) M1M2_PR + NEW met1 ( 1566990 141610 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[53] ( PIN la_data_out[53] ) ( mprj la_data_out[53] ) + + ROUTED met1 ( 1278110 243950 ) ( 1283170 243950 ) + NEW met2 ( 1278110 243950 ) ( 1278110 260100 0 ) + NEW met2 ( 1283170 210970 ) ( 1283170 243950 ) + NEW met2 ( 1584930 2380 0 ) ( 1584930 16660 ) + NEW met2 ( 1580330 16660 ) ( 1584930 16660 ) + NEW met1 ( 1283170 210970 ) ( 1580330 210970 ) + NEW met2 ( 1580330 16660 ) ( 1580330 210970 ) + NEW met1 ( 1283170 210970 ) M1M2_PR + NEW met1 ( 1283170 243950 ) M1M2_PR + NEW met1 ( 1278110 243950 ) M1M2_PR + NEW met1 ( 1580330 210970 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[54] ( PIN la_data_out[54] ) ( mprj la_data_out[54] ) + + ROUTED met2 ( 1602410 2380 0 ) ( 1602410 16660 ) + NEW met2 ( 1601030 16660 ) ( 1602410 16660 ) + NEW met2 ( 1296050 260100 0 ) ( 1296970 260100 ) + NEW met2 ( 1296970 155550 ) ( 1296970 260100 ) + NEW met1 ( 1296970 155550 ) ( 1601030 155550 ) + NEW met2 ( 1601030 16660 ) ( 1601030 155550 ) + NEW met1 ( 1296970 155550 ) M1M2_PR + NEW met1 ( 1601030 155550 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[55] ( PIN la_data_out[55] ) ( mprj la_data_out[55] ) + + ROUTED met1 ( 1313990 241570 ) ( 1317670 241570 ) + NEW met2 ( 1313990 241570 ) ( 1313990 260100 0 ) + NEW met2 ( 1317670 217430 ) ( 1317670 241570 ) + NEW met2 ( 1620350 2380 0 ) ( 1620350 47430 ) + NEW met1 ( 1620350 47430 ) ( 1620350 48110 ) + NEW met2 ( 1615290 193460 ) ( 1615290 217430 ) + NEW met2 ( 1614830 193460 ) ( 1615290 193460 ) + NEW met1 ( 1317670 217430 ) ( 1615290 217430 ) + NEW met1 ( 1614830 62050 ) ( 1614830 62390 ) + NEW met1 ( 1614830 62050 ) ( 1620350 62050 ) + NEW met2 ( 1614830 62390 ) ( 1614830 193460 ) + NEW met2 ( 1620350 48110 ) ( 1620350 62050 ) + NEW met1 ( 1317670 217430 ) M1M2_PR + NEW met1 ( 1317670 241570 ) M1M2_PR + NEW met1 ( 1313990 241570 ) M1M2_PR + NEW met1 ( 1620350 47430 ) M1M2_PR + NEW met1 ( 1620350 48110 ) M1M2_PR + NEW met1 ( 1615290 217430 ) M1M2_PR + NEW met1 ( 1614830 62390 ) M1M2_PR + NEW met1 ( 1620350 62050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[56] ( PIN la_data_out[56] ) ( mprj la_data_out[56] ) + + ROUTED met1 ( 1331930 243950 ) ( 1337910 243950 ) + NEW met2 ( 1331930 243950 ) ( 1331930 260100 0 ) + NEW met2 ( 1337910 162350 ) ( 1337910 243950 ) + NEW met1 ( 1337910 162350 ) ( 1635530 162350 ) + NEW met2 ( 1638290 2380 0 ) ( 1638290 47430 ) + NEW met1 ( 1638290 47430 ) ( 1638290 48110 ) + NEW met1 ( 1635530 61710 ) ( 1635530 62390 ) + NEW met1 ( 1635530 61710 ) ( 1638290 61710 ) + NEW met2 ( 1635530 62390 ) ( 1635530 162350 ) + NEW met2 ( 1638290 48110 ) ( 1638290 61710 ) + NEW met1 ( 1635530 162350 ) M1M2_PR + NEW met1 ( 1337910 162350 ) M1M2_PR + NEW met1 ( 1337910 243950 ) M1M2_PR + NEW met1 ( 1331930 243950 ) M1M2_PR + NEW met1 ( 1638290 47430 ) M1M2_PR + NEW met1 ( 1638290 48110 ) M1M2_PR + NEW met1 ( 1635530 62390 ) M1M2_PR + NEW met1 ( 1638290 61710 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[57] ( PIN la_data_out[57] ) ( mprj la_data_out[57] ) + + ROUTED met2 ( 1349410 260100 0 ) ( 1352170 260100 ) + NEW met2 ( 1352170 169150 ) ( 1352170 260100 ) + NEW met2 ( 1656230 2380 0 ) ( 1656230 169150 ) + NEW met1 ( 1352170 169150 ) ( 1656230 169150 ) + NEW met1 ( 1352170 169150 ) M1M2_PR + NEW met1 ( 1656230 169150 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[58] ( PIN la_data_out[58] ) ( mprj la_data_out[58] ) + + ROUTED met2 ( 1673710 2380 0 ) ( 1673710 16660 ) + NEW met2 ( 1670030 16660 ) ( 1673710 16660 ) + NEW met1 ( 1367350 243950 ) ( 1372870 243950 ) + NEW met2 ( 1367350 243950 ) ( 1367350 260100 0 ) + NEW met2 ( 1372870 175950 ) ( 1372870 243950 ) + NEW met2 ( 1670030 16660 ) ( 1670030 175950 ) + NEW met1 ( 1372870 175950 ) ( 1670030 175950 ) + NEW met1 ( 1372870 175950 ) M1M2_PR + NEW met1 ( 1372870 243950 ) M1M2_PR + NEW met1 ( 1367350 243950 ) M1M2_PR + NEW met1 ( 1670030 175950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[59] ( PIN la_data_out[59] ) ( mprj la_data_out[59] ) + + ROUTED met2 ( 1385290 260100 0 ) ( 1386670 260100 ) + NEW met2 ( 1386670 182750 ) ( 1386670 260100 ) + NEW met2 ( 1691650 2380 0 ) ( 1691650 17340 ) + NEW met2 ( 1690730 17340 ) ( 1691650 17340 ) + NEW met1 ( 1386670 182750 ) ( 1690730 182750 ) + NEW met2 ( 1690730 17340 ) ( 1690730 182750 ) + NEW met1 ( 1386670 182750 ) M1M2_PR + NEW met1 ( 1690730 182750 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[5] ( PIN la_data_out[5] ) ( mprj la_data_out[5] ) + + ROUTED met2 ( 420210 260100 0 ) ( 420670 260100 ) + NEW met2 ( 420670 18870 ) ( 420670 260100 ) + NEW met2 ( 728410 2380 0 ) ( 728410 18870 ) + NEW met1 ( 420670 18870 ) ( 728410 18870 ) + NEW met1 ( 420670 18870 ) M1M2_PR + NEW met1 ( 728410 18870 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[60] ( PIN la_data_out[60] ) ( mprj la_data_out[60] ) + + ROUTED met2 ( 1709590 2380 0 ) ( 1709590 17340 ) + NEW met2 ( 1704530 17340 ) ( 1709590 17340 ) + NEW met1 ( 1407370 197030 ) ( 1704530 197030 ) + NEW met1 ( 1403230 243950 ) ( 1407370 243950 ) + NEW met2 ( 1403230 243950 ) ( 1403230 260100 0 ) + NEW met2 ( 1407370 197030 ) ( 1407370 243950 ) + NEW met2 ( 1704530 17340 ) ( 1704530 197030 ) + NEW met1 ( 1407370 197030 ) M1M2_PR + NEW met1 ( 1704530 197030 ) M1M2_PR + NEW met1 ( 1407370 243950 ) M1M2_PR + NEW met1 ( 1403230 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[61] ( PIN la_data_out[61] ) ( mprj la_data_out[61] ) + + ROUTED met2 ( 1727530 2380 0 ) ( 1727530 17340 ) + NEW met2 ( 1725230 17340 ) ( 1727530 17340 ) + NEW met2 ( 1725230 17340 ) ( 1725230 224230 ) + NEW met1 ( 1420710 224230 ) ( 1725230 224230 ) + NEW met2 ( 1420710 260100 ) ( 1421170 260100 0 ) + NEW met2 ( 1420710 224230 ) ( 1420710 260100 ) + NEW met1 ( 1725230 224230 ) M1M2_PR + NEW met1 ( 1420710 224230 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[62] ( PIN la_data_out[62] ) ( mprj la_data_out[62] ) + + ROUTED met2 ( 1745470 2380 0 ) ( 1745470 18870 ) + NEW met1 ( 1739030 18870 ) ( 1745470 18870 ) + NEW met2 ( 1439110 260100 0 ) ( 1441870 260100 ) + NEW met2 ( 1441870 189890 ) ( 1441870 260100 ) + NEW met2 ( 1739030 18870 ) ( 1739030 189890 ) + NEW met1 ( 1441870 189890 ) ( 1739030 189890 ) + NEW met1 ( 1441870 189890 ) M1M2_PR + NEW met1 ( 1745470 18870 ) M1M2_PR + NEW met1 ( 1739030 18870 ) M1M2_PR + NEW met1 ( 1739030 189890 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[63] ( PIN la_data_out[63] ) ( mprj la_data_out[63] ) + + ROUTED met2 ( 1762950 2380 0 ) ( 1762950 17340 ) + NEW met2 ( 1759730 17340 ) ( 1762950 17340 ) + NEW met1 ( 1457050 243950 ) ( 1462570 243950 ) + NEW met2 ( 1457050 243950 ) ( 1457050 260100 0 ) + NEW met2 ( 1462570 148410 ) ( 1462570 243950 ) + NEW met2 ( 1759730 17340 ) ( 1759730 148410 ) + NEW met1 ( 1462570 148410 ) ( 1759730 148410 ) + NEW met1 ( 1462570 148410 ) M1M2_PR + NEW met1 ( 1462570 243950 ) M1M2_PR + NEW met1 ( 1457050 243950 ) M1M2_PR + NEW met1 ( 1759730 148410 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[64] ( PIN la_data_out[64] ) ( mprj la_data_out[64] ) + + ROUTED met2 ( 1474530 260100 0 ) ( 1476370 260100 ) + NEW met2 ( 1476370 23970 ) ( 1476370 260100 ) + NEW met2 ( 1780890 2380 0 ) ( 1780890 23970 ) + NEW met1 ( 1476370 23970 ) ( 1780890 23970 ) + NEW met1 ( 1476370 23970 ) M1M2_PR + NEW met1 ( 1780890 23970 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[65] ( PIN la_data_out[65] ) ( mprj la_data_out[65] ) + + ROUTED met2 ( 1798830 2380 0 ) ( 1798830 2890 ) + NEW met1 ( 1794230 2890 ) ( 1798830 2890 ) + NEW met1 ( 1497070 204170 ) ( 1794230 204170 ) + NEW met1 ( 1492470 243950 ) ( 1497070 243950 ) + NEW met2 ( 1492470 243950 ) ( 1492470 260100 0 ) + NEW met2 ( 1497070 204170 ) ( 1497070 243950 ) + NEW met2 ( 1794230 2890 ) ( 1794230 204170 ) + NEW met1 ( 1497070 204170 ) M1M2_PR + NEW met1 ( 1798830 2890 ) M1M2_PR + NEW met1 ( 1794230 2890 ) M1M2_PR + NEW met1 ( 1794230 204170 ) M1M2_PR + NEW met1 ( 1497070 243950 ) M1M2_PR + NEW met1 ( 1492470 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[66] ( PIN la_data_out[66] ) ( mprj la_data_out[66] ) + + ROUTED met2 ( 1816770 2380 0 ) ( 1816770 3060 ) + NEW met2 ( 1814930 3060 ) ( 1816770 3060 ) + NEW met2 ( 1510410 141270 ) ( 1510410 260100 0 ) + NEW met1 ( 1510410 141270 ) ( 1814930 141270 ) + NEW met2 ( 1814930 3060 ) ( 1814930 141270 ) + NEW met1 ( 1510410 141270 ) M1M2_PR + NEW met1 ( 1814930 141270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[67] ( PIN la_data_out[67] ) ( mprj la_data_out[67] ) + + ROUTED met2 ( 1834710 2380 0 ) ( 1834710 17170 ) + NEW met1 ( 1828730 17170 ) ( 1834710 17170 ) + NEW met2 ( 1828730 17170 ) ( 1828730 155890 ) + NEW met2 ( 1528350 260100 0 ) ( 1531570 260100 ) + NEW met2 ( 1531570 155890 ) ( 1531570 260100 ) + NEW met1 ( 1531570 155890 ) ( 1828730 155890 ) + NEW met1 ( 1834710 17170 ) M1M2_PR + NEW met1 ( 1828730 17170 ) M1M2_PR + NEW met1 ( 1828730 155890 ) M1M2_PR + NEW met1 ( 1531570 155890 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[68] ( PIN la_data_out[68] ) ( mprj la_data_out[68] ) + + ROUTED met1 ( 1546290 243950 ) ( 1551810 243950 ) + NEW met2 ( 1546290 243950 ) ( 1546290 260100 0 ) + NEW met2 ( 1551810 210290 ) ( 1551810 243950 ) + NEW met1 ( 1551810 210290 ) ( 1849430 210290 ) + NEW met2 ( 1852190 2380 0 ) ( 1852190 17170 ) + NEW met2 ( 1852190 17170 ) ( 1852650 17170 ) + NEW met2 ( 1849430 145180 ) ( 1849890 145180 ) + NEW met2 ( 1849890 145180 ) ( 1849890 192950 ) + NEW met1 ( 1849430 192950 ) ( 1849890 192950 ) + NEW met2 ( 1849430 192950 ) ( 1849430 210290 ) + NEW met1 ( 1849430 137870 ) ( 1852650 137870 ) + NEW met2 ( 1849430 137870 ) ( 1849430 145180 ) + NEW met2 ( 1852650 17170 ) ( 1852650 137870 ) + NEW met1 ( 1551810 210290 ) M1M2_PR + NEW met1 ( 1849430 210290 ) M1M2_PR + NEW met1 ( 1551810 243950 ) M1M2_PR + NEW met1 ( 1546290 243950 ) M1M2_PR + NEW met1 ( 1849890 192950 ) M1M2_PR + NEW met1 ( 1849430 192950 ) M1M2_PR + NEW met1 ( 1849430 137870 ) M1M2_PR + NEW met1 ( 1852650 137870 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[69] ( PIN la_data_out[69] ) ( mprj la_data_out[69] ) + + ROUTED met2 ( 1564230 260100 0 ) ( 1566070 260100 ) + NEW met2 ( 1566070 217090 ) ( 1566070 260100 ) + NEW met1 ( 1566070 217090 ) ( 1870590 217090 ) + NEW met2 ( 1870130 2380 0 ) ( 1870130 13770 ) + NEW met1 ( 1870130 13770 ) ( 1870130 14110 ) + NEW met1 ( 1870130 14110 ) ( 1870590 14110 ) + NEW met2 ( 1870590 14110 ) ( 1870590 217090 ) + NEW met1 ( 1566070 217090 ) M1M2_PR + NEW met1 ( 1870590 217090 ) M1M2_PR + NEW met1 ( 1870130 13770 ) M1M2_PR + NEW met1 ( 1870590 14110 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[6] ( PIN la_data_out[6] ) ( mprj la_data_out[6] ) + + ROUTED met2 ( 746350 2380 0 ) ( 746350 17510 ) + NEW met1 ( 441370 17510 ) ( 746350 17510 ) + NEW met2 ( 438150 260100 0 ) ( 441370 260100 ) + NEW met2 ( 441370 17510 ) ( 441370 260100 ) + NEW met1 ( 441370 17510 ) M1M2_PR + NEW met1 ( 746350 17510 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[70] ( PIN la_data_out[70] ) ( mprj la_data_out[70] ) + + ROUTED met1 ( 1582170 243950 ) ( 1586770 243950 ) + NEW met2 ( 1582170 243950 ) ( 1582170 260100 0 ) + NEW met2 ( 1586770 162690 ) ( 1586770 243950 ) + NEW met1 ( 1586770 162690 ) ( 1883930 162690 ) + NEW met1 ( 1883930 62050 ) ( 1888070 62050 ) + NEW met2 ( 1883930 62050 ) ( 1883930 162690 ) + NEW met2 ( 1888070 2380 0 ) ( 1888070 62050 ) + NEW met1 ( 1586770 162690 ) M1M2_PR + NEW met1 ( 1586770 243950 ) M1M2_PR + NEW met1 ( 1582170 243950 ) M1M2_PR + NEW met1 ( 1883930 162690 ) M1M2_PR + NEW met1 ( 1883930 62050 ) M1M2_PR + NEW met1 ( 1888070 62050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[71] ( PIN la_data_out[71] ) ( mprj la_data_out[71] ) + + ROUTED met2 ( 1906010 2380 0 ) ( 1906010 16660 ) + NEW met2 ( 1904630 16660 ) ( 1906010 16660 ) + NEW met2 ( 1599650 260100 0 ) ( 1600570 260100 ) + NEW met2 ( 1600570 168810 ) ( 1600570 260100 ) + NEW met1 ( 1600570 168810 ) ( 1904630 168810 ) + NEW met2 ( 1904630 16660 ) ( 1904630 168810 ) + NEW met1 ( 1600570 168810 ) M1M2_PR + NEW met1 ( 1904630 168810 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[72] ( PIN la_data_out[72] ) ( mprj la_data_out[72] ) + + ROUTED met2 ( 1923490 2380 0 ) ( 1923490 2890 ) + NEW met1 ( 1918430 2890 ) ( 1923490 2890 ) + NEW met2 ( 1918430 2890 ) ( 1918430 176630 ) + NEW met1 ( 1617590 243950 ) ( 1621270 243950 ) + NEW met2 ( 1617590 243950 ) ( 1617590 260100 0 ) + NEW met2 ( 1621270 176630 ) ( 1621270 243950 ) + NEW met1 ( 1621270 176630 ) ( 1918430 176630 ) + NEW met1 ( 1923490 2890 ) M1M2_PR + NEW met1 ( 1918430 2890 ) M1M2_PR + NEW met1 ( 1918430 176630 ) M1M2_PR + NEW met1 ( 1621270 176630 ) M1M2_PR + NEW met1 ( 1621270 243950 ) M1M2_PR + NEW met1 ( 1617590 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[73] ( PIN la_data_out[73] ) ( mprj la_data_out[73] ) + + ROUTED met2 ( 1941430 2380 0 ) ( 1941430 2890 ) + NEW met1 ( 1939130 2890 ) ( 1941430 2890 ) + NEW met1 ( 1635530 243950 ) ( 1641510 243950 ) + NEW met2 ( 1635530 243950 ) ( 1635530 260100 0 ) + NEW met2 ( 1641510 183090 ) ( 1641510 243950 ) + NEW met2 ( 1939130 2890 ) ( 1939130 183090 ) + NEW met1 ( 1641510 183090 ) ( 1939130 183090 ) + NEW met1 ( 1641510 183090 ) M1M2_PR + NEW met1 ( 1941430 2890 ) M1M2_PR + NEW met1 ( 1939130 2890 ) M1M2_PR + NEW met1 ( 1939130 183090 ) M1M2_PR + NEW met1 ( 1641510 243950 ) M1M2_PR + NEW met1 ( 1635530 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[74] ( PIN la_data_out[74] ) ( mprj la_data_out[74] ) + + ROUTED met2 ( 1653470 260100 0 ) ( 1655770 260100 ) + NEW met2 ( 1655770 197370 ) ( 1655770 260100 ) + NEW met1 ( 1655770 197370 ) ( 1952930 197370 ) + NEW met1 ( 1952930 37910 ) ( 1959370 37910 ) + NEW met2 ( 1952930 37910 ) ( 1952930 197370 ) + NEW met2 ( 1959370 2380 0 ) ( 1959370 37910 ) + NEW met1 ( 1655770 197370 ) M1M2_PR + NEW met1 ( 1952930 197370 ) M1M2_PR + NEW met1 ( 1952930 37910 ) M1M2_PR + NEW met1 ( 1959370 37910 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[75] ( PIN la_data_out[75] ) ( mprj la_data_out[75] ) + + ROUTED met1 ( 1671410 243950 ) ( 1676470 243950 ) + NEW met2 ( 1671410 243950 ) ( 1671410 260100 0 ) + NEW met2 ( 1676470 114070 ) ( 1676470 243950 ) + NEW met2 ( 1974090 96900 ) ( 1974090 114070 ) + NEW met2 ( 1973630 96900 ) ( 1974090 96900 ) + NEW met1 ( 1676470 114070 ) ( 1974090 114070 ) + NEW li1 ( 1973630 48450 ) ( 1973630 96390 ) + NEW met1 ( 1973630 48450 ) ( 1977310 48450 ) + NEW met2 ( 1973630 96390 ) ( 1973630 96900 ) + NEW met2 ( 1977310 2380 0 ) ( 1977310 48450 ) + NEW met1 ( 1676470 114070 ) M1M2_PR + NEW met1 ( 1676470 243950 ) M1M2_PR + NEW met1 ( 1671410 243950 ) M1M2_PR + NEW met1 ( 1974090 114070 ) M1M2_PR + NEW li1 ( 1973630 96390 ) L1M1_PR_MR + NEW met1 ( 1973630 96390 ) M1M2_PR + NEW li1 ( 1973630 48450 ) L1M1_PR_MR + NEW met1 ( 1977310 48450 ) M1M2_PR + NEW met1 ( 1973630 96390 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- la_data_out[76] ( PIN la_data_out[76] ) ( mprj la_data_out[76] ) + + ROUTED met2 ( 1995250 2380 0 ) ( 1995250 16660 ) + NEW met2 ( 1994330 16660 ) ( 1995250 16660 ) + NEW met1 ( 1690270 224570 ) ( 1994330 224570 ) + NEW met2 ( 1689350 260100 0 ) ( 1690270 260100 ) + NEW met2 ( 1690270 224570 ) ( 1690270 260100 ) + NEW met2 ( 1994330 16660 ) ( 1994330 224570 ) + NEW met1 ( 1690270 224570 ) M1M2_PR + NEW met1 ( 1994330 224570 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[77] ( PIN la_data_out[77] ) ( mprj la_data_out[77] ) + + ROUTED met2 ( 2012730 2380 0 ) ( 2012730 16660 ) + NEW met2 ( 2008130 16660 ) ( 2012730 16660 ) + NEW met1 ( 1710970 189550 ) ( 2008130 189550 ) + NEW met2 ( 1707290 260100 0 ) ( 1710970 260100 ) + NEW met2 ( 1710970 189550 ) ( 1710970 260100 ) + NEW met2 ( 2008130 16660 ) ( 2008130 189550 ) + NEW met1 ( 1710970 189550 ) M1M2_PR + NEW met1 ( 2008130 189550 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[78] ( PIN la_data_out[78] ) ( mprj la_data_out[78] ) + + ROUTED met2 ( 2030670 2380 0 ) ( 2030670 30770 ) + NEW met2 ( 1724770 30770 ) ( 1724770 260100 0 ) + NEW met1 ( 1724770 30770 ) ( 2030670 30770 ) + NEW met1 ( 2030670 30770 ) M1M2_PR + NEW met1 ( 1724770 30770 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[79] ( PIN la_data_out[79] ) ( mprj la_data_out[79] ) + + ROUTED met2 ( 1742710 260100 0 ) ( 1745470 260100 ) + NEW met2 ( 1745470 148070 ) ( 1745470 260100 ) + NEW met1 ( 1745470 148070 ) ( 2043090 148070 ) + NEW met1 ( 2043090 62050 ) ( 2048610 62050 ) + NEW met2 ( 2043090 62050 ) ( 2043090 148070 ) + NEW met2 ( 2048610 2380 0 ) ( 2048610 62050 ) + NEW met1 ( 1745470 148070 ) M1M2_PR + NEW met1 ( 2043090 148070 ) M1M2_PR + NEW met1 ( 2043090 62050 ) M1M2_PR + NEW met1 ( 2048610 62050 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[7] ( PIN la_data_out[7] ) ( mprj la_data_out[7] ) + + ROUTED met2 ( 763830 2380 0 ) ( 763830 19890 ) + NEW met1 ( 461610 19890 ) ( 763830 19890 ) + NEW met1 ( 455630 243950 ) ( 461610 243950 ) + NEW met2 ( 455630 243950 ) ( 455630 260100 0 ) + NEW met2 ( 461610 19890 ) ( 461610 243950 ) + NEW met1 ( 763830 19890 ) M1M2_PR + NEW met1 ( 461610 19890 ) M1M2_PR + NEW met1 ( 461610 243950 ) M1M2_PR + NEW met1 ( 455630 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[80] ( PIN la_data_out[80] ) ( mprj la_data_out[80] ) + + ROUTED met1 ( 1760650 243950 ) ( 1766170 243950 ) + NEW met2 ( 1760650 243950 ) ( 1760650 260100 0 ) + NEW met2 ( 1766170 141610 ) ( 1766170 243950 ) + NEW met1 ( 1766170 141610 ) ( 2063330 141610 ) + NEW met1 ( 2063330 62050 ) ( 2066550 62050 ) + NEW met2 ( 2063330 62050 ) ( 2063330 141610 ) + NEW met2 ( 2066550 2380 0 ) ( 2066550 62050 ) + NEW met1 ( 1766170 141610 ) M1M2_PR + NEW met1 ( 1766170 243950 ) M1M2_PR + NEW met1 ( 1760650 243950 ) M1M2_PR + NEW met1 ( 2063330 141610 ) M1M2_PR +======= NEW met2 ( 1742710 1700340 0 ) ( 1743630 1700340 ) NEW met2 ( 1743630 1500590 ) ( 1743630 1700340 ) NEW met1 ( 1743630 1500590 ) ( 2760230 1500590 ) @@ -80060,10 +85145,405 @@ NEW met2 ( 2063330 62050 ) ( 2063330 1487330 ) NEW met1 ( 1599190 1487330 ) M1M2_PR NEW met1 ( 2063330 1487330 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d NEW met1 ( 2063330 62050 ) M1M2_PR NEW met1 ( 2066550 62050 ) M1M2_PR + USE SIGNAL ; - la_data_out[81] ( PIN la_data_out[81] ) ( mprj la_data_out[81] ) +<<<<<<< HEAD + + ROUTED met1 ( 1779970 203490 ) ( 2084490 203490 ) + NEW met2 ( 1778590 260100 0 ) ( 1779970 260100 ) + NEW met2 ( 1779970 203490 ) ( 1779970 260100 ) + NEW met2 ( 2084490 2380 0 ) ( 2084490 203490 ) + NEW met1 ( 1779970 203490 ) M1M2_PR + NEW met1 ( 2084490 203490 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[82] ( PIN la_data_out[82] ) ( mprj la_data_out[82] ) + + ROUTED met2 ( 2101970 2380 0 ) ( 2101970 16660 ) + NEW met2 ( 2097830 16660 ) ( 2101970 16660 ) + NEW met1 ( 1800670 120870 ) ( 2097830 120870 ) + NEW met1 ( 1796530 243950 ) ( 1800670 243950 ) + NEW met2 ( 1796530 243950 ) ( 1796530 260100 0 ) + NEW met2 ( 1800670 120870 ) ( 1800670 243950 ) + NEW met2 ( 2097830 16660 ) ( 2097830 120870 ) + NEW met1 ( 1800670 120870 ) M1M2_PR + NEW met1 ( 2097830 120870 ) M1M2_PR + NEW met1 ( 1800670 243950 ) M1M2_PR + NEW met1 ( 1796530 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[83] ( PIN la_data_out[83] ) ( mprj la_data_out[83] ) + + ROUTED met2 ( 2119910 2380 0 ) ( 2119910 16660 ) + NEW met2 ( 2118530 16660 ) ( 2119910 16660 ) + NEW met2 ( 2118530 16660 ) ( 2118530 155210 ) + NEW met2 ( 1814010 260100 ) ( 1814470 260100 0 ) + NEW met2 ( 1814010 155210 ) ( 1814010 260100 ) + NEW met1 ( 1814010 155210 ) ( 2118530 155210 ) + NEW met1 ( 2118530 155210 ) M1M2_PR + NEW met1 ( 1814010 155210 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[84] ( PIN la_data_out[84] ) ( mprj la_data_out[84] ) + + ROUTED met2 ( 2137850 2380 0 ) ( 2137850 16660 ) + NEW met2 ( 2132330 16660 ) ( 2137850 16660 ) + NEW met2 ( 1832410 260100 0 ) ( 1835170 260100 ) + NEW met2 ( 1835170 162010 ) ( 1835170 260100 ) + NEW met2 ( 2132330 16660 ) ( 2132330 162010 ) + NEW met1 ( 1835170 162010 ) ( 2132330 162010 ) + NEW met1 ( 1835170 162010 ) M1M2_PR + NEW met1 ( 2132330 162010 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[85] ( PIN la_data_out[85] ) ( mprj la_data_out[85] ) + + ROUTED met1 ( 1849890 243950 ) ( 1859550 243950 ) + NEW met2 ( 1849890 243950 ) ( 1849890 260100 0 ) + NEW met2 ( 1859550 169150 ) ( 1859550 243950 ) + NEW met1 ( 1859550 169150 ) ( 2153030 169150 ) + NEW met2 ( 2155790 2380 0 ) ( 2155790 2890 ) + NEW li1 ( 2155790 2890 ) ( 2155790 48110 ) + NEW met1 ( 2153030 48110 ) ( 2155790 48110 ) + NEW met2 ( 2153030 48110 ) ( 2153030 169150 ) + NEW met1 ( 1859550 169150 ) M1M2_PR + NEW met1 ( 1859550 243950 ) M1M2_PR + NEW met1 ( 1849890 243950 ) M1M2_PR + NEW met1 ( 2153030 169150 ) M1M2_PR + NEW li1 ( 2155790 2890 ) L1M1_PR_MR + NEW met1 ( 2155790 2890 ) M1M2_PR + NEW li1 ( 2155790 48110 ) L1M1_PR_MR + NEW met1 ( 2153030 48110 ) M1M2_PR + NEW met1 ( 2155790 2890 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- la_data_out[86] ( PIN la_data_out[86] ) ( mprj la_data_out[86] ) + + ROUTED met2 ( 1867830 260100 0 ) ( 1869670 260100 ) + NEW met2 ( 1869670 176290 ) ( 1869670 260100 ) + NEW met1 ( 1869670 176290 ) ( 2166830 176290 ) + NEW met1 ( 2166830 38250 ) ( 2173270 38250 ) + NEW met2 ( 2166830 38250 ) ( 2166830 176290 ) + NEW met2 ( 2173270 2380 0 ) ( 2173270 38250 ) + NEW met1 ( 1869670 176290 ) M1M2_PR + NEW met1 ( 2166830 176290 ) M1M2_PR + NEW met1 ( 2166830 38250 ) M1M2_PR + NEW met1 ( 2173270 38250 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[87] ( PIN la_data_out[87] ) ( mprj la_data_out[87] ) + + ROUTED met2 ( 2191210 2380 0 ) ( 2191210 16660 ) + NEW met2 ( 2187530 16660 ) ( 2191210 16660 ) + NEW met1 ( 1890370 182750 ) ( 2187530 182750 ) + NEW met1 ( 1885770 243950 ) ( 1890370 243950 ) + NEW met2 ( 1885770 243950 ) ( 1885770 260100 0 ) + NEW met2 ( 1890370 182750 ) ( 1890370 243950 ) + NEW met2 ( 2187530 16660 ) ( 2187530 182750 ) + NEW met1 ( 1890370 182750 ) M1M2_PR + NEW met1 ( 2187530 182750 ) M1M2_PR + NEW met1 ( 1890370 243950 ) M1M2_PR + NEW met1 ( 1885770 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[88] ( PIN la_data_out[88] ) ( mprj la_data_out[88] ) + + ROUTED met2 ( 2209150 2380 0 ) ( 2209150 16660 ) + NEW met2 ( 2208230 16660 ) ( 2209150 16660 ) + NEW met2 ( 2208230 16660 ) ( 2208230 196690 ) + NEW met1 ( 1903710 196690 ) ( 2208230 196690 ) + NEW met2 ( 1903710 196690 ) ( 1903710 260100 0 ) + NEW met1 ( 2208230 196690 ) M1M2_PR + NEW met1 ( 1903710 196690 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[89] ( PIN la_data_out[89] ) ( mprj la_data_out[89] ) + + ROUTED met2 ( 2227090 2380 0 ) ( 2227090 16660 ) + NEW met2 ( 2222030 16660 ) ( 2227090 16660 ) + NEW met2 ( 1921650 260100 0 ) ( 1924870 260100 ) + NEW met2 ( 1924870 224230 ) ( 1924870 260100 ) + NEW met2 ( 2222030 16660 ) ( 2222030 224230 ) + NEW met1 ( 1924870 224230 ) ( 2222030 224230 ) + NEW met1 ( 1924870 224230 ) M1M2_PR + NEW met1 ( 2222030 224230 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[8] ( PIN la_data_out[8] ) ( mprj la_data_out[8] ) + + ROUTED met2 ( 781770 2380 0 ) ( 781770 17170 ) + NEW met2 ( 473570 260100 0 ) ( 475870 260100 ) + NEW met2 ( 475870 17170 ) ( 475870 260100 ) + NEW met1 ( 475870 17170 ) ( 781770 17170 ) + NEW met1 ( 475870 17170 ) M1M2_PR + NEW met1 ( 781770 17170 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[90] ( PIN la_data_out[90] ) ( mprj la_data_out[90] ) + + ROUTED met2 ( 2245030 2380 0 ) ( 2245030 16660 ) + NEW met2 ( 2242730 16660 ) ( 2245030 16660 ) + NEW met1 ( 1939590 243270 ) ( 1945570 243270 ) + NEW met2 ( 1939590 243270 ) ( 1939590 260100 0 ) + NEW met2 ( 1945570 189890 ) ( 1945570 243270 ) + NEW met2 ( 2242730 16660 ) ( 2242730 189890 ) + NEW met1 ( 1945570 189890 ) ( 2242730 189890 ) + NEW met1 ( 1945570 189890 ) M1M2_PR + NEW met1 ( 2242730 189890 ) M1M2_PR + NEW met1 ( 1945570 243270 ) M1M2_PR + NEW met1 ( 1939590 243270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[91] ( PIN la_data_out[91] ) ( mprj la_data_out[91] ) + + ROUTED met2 ( 1957530 260100 0 ) ( 1959370 260100 ) + NEW met2 ( 1959370 134810 ) ( 1959370 260100 ) + NEW met2 ( 2262510 2380 0 ) ( 2262510 18190 ) + NEW met1 ( 2256530 18190 ) ( 2262510 18190 ) + NEW met1 ( 1959370 134810 ) ( 2256530 134810 ) + NEW met2 ( 2256530 18190 ) ( 2256530 134810 ) + NEW met1 ( 1959370 134810 ) M1M2_PR + NEW met1 ( 2262510 18190 ) M1M2_PR + NEW met1 ( 2256530 18190 ) M1M2_PR + NEW met1 ( 2256530 134810 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[92] ( PIN la_data_out[92] ) ( mprj la_data_out[92] ) + + ROUTED met2 ( 2280450 2380 0 ) ( 2280450 2890 ) + NEW met1 ( 2277230 2890 ) ( 2280450 2890 ) + NEW met1 ( 1980070 128010 ) ( 2277230 128010 ) + NEW met1 ( 1975010 243950 ) ( 1980070 243950 ) + NEW met2 ( 1975010 243950 ) ( 1975010 260100 0 ) + NEW met2 ( 1980070 128010 ) ( 1980070 243950 ) + NEW met2 ( 2277230 2890 ) ( 2277230 128010 ) + NEW met1 ( 1980070 128010 ) M1M2_PR + NEW met1 ( 2280450 2890 ) M1M2_PR + NEW met1 ( 2277230 2890 ) M1M2_PR + NEW met1 ( 2277230 128010 ) M1M2_PR + NEW met1 ( 1980070 243950 ) M1M2_PR + NEW met1 ( 1975010 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[93] ( PIN la_data_out[93] ) ( mprj la_data_out[93] ) + + ROUTED met2 ( 1992950 260100 0 ) ( 1993870 260100 ) + NEW met2 ( 1993870 141270 ) ( 1993870 260100 ) + NEW met1 ( 1993870 141270 ) ( 2298390 141270 ) + NEW met2 ( 2298390 2380 0 ) ( 2298390 141270 ) + NEW met1 ( 1993870 141270 ) M1M2_PR + NEW met1 ( 2298390 141270 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[94] ( PIN la_data_out[94] ) ( mprj la_data_out[94] ) + + ROUTED met2 ( 2316330 2380 0 ) ( 2316330 16660 ) + NEW met2 ( 2311730 16660 ) ( 2316330 16660 ) + NEW met2 ( 2311730 16660 ) ( 2311730 148410 ) + NEW met2 ( 2010890 260100 0 ) ( 2014570 260100 ) + NEW met2 ( 2014570 148410 ) ( 2014570 260100 ) + NEW met1 ( 2014570 148410 ) ( 2311730 148410 ) + NEW met1 ( 2311730 148410 ) M1M2_PR + NEW met1 ( 2014570 148410 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[95] ( PIN la_data_out[95] ) ( mprj la_data_out[95] ) + + ROUTED met2 ( 2334270 2380 0 ) ( 2334270 16660 ) + NEW met2 ( 2332430 16660 ) ( 2334270 16660 ) + NEW met1 ( 2028830 243950 ) ( 2034810 243950 ) + NEW met2 ( 2028830 243950 ) ( 2028830 260100 0 ) + NEW met2 ( 2034810 175950 ) ( 2034810 243950 ) + NEW met2 ( 2332430 16660 ) ( 2332430 175950 ) + NEW met1 ( 2034810 175950 ) ( 2332430 175950 ) + NEW met1 ( 2034810 175950 ) M1M2_PR + NEW met1 ( 2034810 243950 ) M1M2_PR + NEW met1 ( 2028830 243950 ) M1M2_PR + NEW met1 ( 2332430 175950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[96] ( PIN la_data_out[96] ) ( mprj la_data_out[96] ) + + ROUTED met2 ( 2351750 2380 0 ) ( 2351750 16660 ) + NEW met2 ( 2346230 16660 ) ( 2351750 16660 ) + NEW met2 ( 2046770 260100 0 ) ( 2049070 260100 ) + NEW met2 ( 2049070 183090 ) ( 2049070 260100 ) + NEW met2 ( 2346230 16660 ) ( 2346230 183090 ) + NEW met1 ( 2049070 183090 ) ( 2346230 183090 ) + NEW met1 ( 2049070 183090 ) M1M2_PR + NEW met1 ( 2346230 183090 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[97] ( PIN la_data_out[97] ) ( mprj la_data_out[97] ) + + ROUTED met2 ( 2369690 2380 0 ) ( 2369690 2890 ) + NEW met1 ( 2366930 2890 ) ( 2369690 2890 ) + NEW met1 ( 2064710 243950 ) ( 2069770 243950 ) + NEW met2 ( 2064710 243950 ) ( 2064710 260100 0 ) + NEW met2 ( 2069770 162350 ) ( 2069770 243950 ) + NEW met1 ( 2069770 162350 ) ( 2366930 162350 ) + NEW met2 ( 2366930 2890 ) ( 2366930 162350 ) + NEW met1 ( 2369690 2890 ) M1M2_PR + NEW met1 ( 2366930 2890 ) M1M2_PR + NEW met1 ( 2069770 162350 ) M1M2_PR + NEW met1 ( 2069770 243950 ) M1M2_PR + NEW met1 ( 2064710 243950 ) M1M2_PR + NEW met1 ( 2366930 162350 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[98] ( PIN la_data_out[98] ) ( mprj la_data_out[98] ) + + ROUTED met2 ( 2387630 2380 0 ) ( 2387630 3060 ) + NEW met2 ( 2387630 3060 ) ( 2388090 3060 ) + NEW met2 ( 2082650 260100 0 ) ( 2083570 260100 ) + NEW met2 ( 2388090 3060 ) ( 2388090 51510 ) + NEW met2 ( 2083570 51510 ) ( 2083570 260100 ) + NEW met1 ( 2083570 51510 ) ( 2388090 51510 ) + NEW met1 ( 2388090 51510 ) M1M2_PR + NEW met1 ( 2083570 51510 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[99] ( PIN la_data_out[99] ) ( mprj la_data_out[99] ) + + ROUTED met2 ( 2405570 2380 0 ) ( 2405570 17340 ) + NEW met2 ( 2401430 17340 ) ( 2405570 17340 ) + NEW met2 ( 2401430 17340 ) ( 2401430 197030 ) + NEW met1 ( 2104270 197030 ) ( 2401430 197030 ) + NEW met1 ( 2100590 243950 ) ( 2104270 243950 ) + NEW met2 ( 2100590 243950 ) ( 2100590 260100 0 ) + NEW met2 ( 2104270 197030 ) ( 2104270 243950 ) + NEW met1 ( 2401430 197030 ) M1M2_PR + NEW met1 ( 2104270 197030 ) M1M2_PR + NEW met1 ( 2104270 243950 ) M1M2_PR + NEW met1 ( 2100590 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_data_out[9] ( PIN la_data_out[9] ) ( mprj la_data_out[9] ) + + ROUTED met2 ( 799710 2380 0 ) ( 799710 15470 ) + NEW met1 ( 491510 243950 ) ( 496570 243950 ) + NEW met2 ( 491510 243950 ) ( 491510 260100 0 ) + NEW met2 ( 496570 15470 ) ( 496570 243950 ) + NEW met1 ( 496570 15470 ) ( 799710 15470 ) + NEW met1 ( 496570 15470 ) M1M2_PR + NEW met1 ( 799710 15470 ) M1M2_PR + NEW met1 ( 496570 243950 ) M1M2_PR + NEW met1 ( 491510 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[0] ( PIN la_oen[0] ) ( mprj la_oen[0] ) + + ROUTED met2 ( 645150 2380 0 ) ( 645150 17340 ) + NEW met2 ( 642390 17340 ) ( 645150 17340 ) + NEW met2 ( 336490 245310 ) ( 336490 260100 0 ) + NEW met1 ( 336490 245310 ) ( 642390 245310 ) + NEW met2 ( 642390 17340 ) ( 642390 245310 ) + NEW met1 ( 336490 245310 ) M1M2_PR + NEW met1 ( 642390 245310 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[100] ( PIN la_oen[100] ) ( mprj la_oen[100] ) + + ROUTED met2 ( 2124050 260100 0 ) ( 2124970 260100 ) + NEW met2 ( 2124970 189550 ) ( 2124970 260100 ) + NEW met2 ( 2429030 2380 0 ) ( 2429030 189550 ) + NEW met1 ( 2124970 189550 ) ( 2429030 189550 ) + NEW met1 ( 2124970 189550 ) M1M2_PR + NEW met1 ( 2429030 189550 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[101] ( PIN la_oen[101] ) ( mprj la_oen[101] ) + + ROUTED met2 ( 2446970 2380 0 ) ( 2446970 17510 ) + NEW met1 ( 2141990 243950 ) ( 2145670 243950 ) + NEW met2 ( 2141990 243950 ) ( 2141990 260100 0 ) + NEW met2 ( 2145670 17510 ) ( 2145670 243950 ) + NEW met1 ( 2145670 17510 ) ( 2446970 17510 ) + NEW met1 ( 2446970 17510 ) M1M2_PR + NEW met1 ( 2145670 243950 ) M1M2_PR + NEW met1 ( 2141990 243950 ) M1M2_PR + NEW met1 ( 2145670 17510 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[102] ( PIN la_oen[102] ) ( mprj la_oen[102] ) + + ROUTED met2 ( 2464910 2380 0 ) ( 2464910 15470 ) + NEW met1 ( 2159930 243950 ) ( 2165910 243950 ) + NEW met2 ( 2159930 243950 ) ( 2159930 260100 0 ) + NEW met2 ( 2165910 15470 ) ( 2165910 243950 ) + NEW met1 ( 2165910 15470 ) ( 2464910 15470 ) + NEW met1 ( 2464910 15470 ) M1M2_PR + NEW met1 ( 2165910 243950 ) M1M2_PR + NEW met1 ( 2159930 243950 ) M1M2_PR + NEW met1 ( 2165910 15470 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[103] ( PIN la_oen[103] ) ( mprj la_oen[103] ) + + ROUTED met2 ( 2482850 2380 0 ) ( 2482850 16830 ) + NEW met2 ( 2177870 260100 0 ) ( 2180170 260100 ) + NEW met2 ( 2180170 16830 ) ( 2180170 260100 ) + NEW met1 ( 2180170 16830 ) ( 2482850 16830 ) + NEW met1 ( 2482850 16830 ) M1M2_PR + NEW met1 ( 2180170 16830 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[104] ( PIN la_oen[104] ) ( mprj la_oen[104] ) + + ROUTED met2 ( 2500790 2380 0 ) ( 2500790 17170 ) + NEW met1 ( 2200870 17170 ) ( 2500790 17170 ) + NEW met1 ( 2195810 243950 ) ( 2200870 243950 ) + NEW met2 ( 2195810 243950 ) ( 2195810 260100 0 ) + NEW met2 ( 2200870 17170 ) ( 2200870 243950 ) + NEW met1 ( 2500790 17170 ) M1M2_PR + NEW met1 ( 2200870 17170 ) M1M2_PR + NEW met1 ( 2200870 243950 ) M1M2_PR + NEW met1 ( 2195810 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[105] ( PIN la_oen[105] ) ( mprj la_oen[105] ) + + ROUTED met2 ( 2518270 2380 0 ) ( 2518270 15810 ) + NEW met2 ( 2213750 260100 0 ) ( 2214670 260100 ) + NEW met2 ( 2214670 15810 ) ( 2214670 260100 ) + NEW met1 ( 2214670 15810 ) ( 2518270 15810 ) + NEW met1 ( 2214670 15810 ) M1M2_PR + NEW met1 ( 2518270 15810 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[106] ( PIN la_oen[106] ) ( mprj la_oen[106] ) + + ROUTED met2 ( 2536210 2380 0 ) ( 2536210 20570 ) + NEW met1 ( 2231230 243950 ) ( 2235370 243950 ) + NEW met2 ( 2231230 243950 ) ( 2231230 260100 0 ) + NEW met2 ( 2235370 20570 ) ( 2235370 243950 ) + NEW met1 ( 2235370 20570 ) ( 2536210 20570 ) + NEW met1 ( 2235370 20570 ) M1M2_PR + NEW met1 ( 2536210 20570 ) M1M2_PR + NEW met1 ( 2235370 243950 ) M1M2_PR + NEW met1 ( 2231230 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[107] ( PIN la_oen[107] ) ( mprj la_oen[107] ) + + ROUTED met2 ( 2249170 17340 ) ( 2249170 260100 0 ) + NEW met2 ( 2554150 2380 0 ) ( 2554150 17340 ) + NEW met3 ( 2249170 17340 ) ( 2554150 17340 ) + NEW met2 ( 2249170 17340 ) via2_FR + NEW met2 ( 2554150 17340 ) via2_FR ++ USE SIGNAL ; +- la_oen[108] ( PIN la_oen[108] ) ( mprj la_oen[108] ) + + ROUTED met2 ( 2572090 2380 0 ) ( 2572090 16490 ) + NEW met1 ( 2269870 16490 ) ( 2572090 16490 ) + NEW met2 ( 2267110 260100 0 ) ( 2269870 260100 ) + NEW met2 ( 2269870 16490 ) ( 2269870 260100 ) + NEW met1 ( 2269870 16490 ) M1M2_PR + NEW met1 ( 2572090 16490 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[109] ( PIN la_oen[109] ) ( mprj la_oen[109] ) + + ROUTED met2 ( 2589570 2380 0 ) ( 2589570 16150 ) + NEW met1 ( 2290570 16150 ) ( 2589570 16150 ) + NEW met1 ( 2285050 243950 ) ( 2290570 243950 ) + NEW met2 ( 2285050 243950 ) ( 2285050 260100 0 ) + NEW met2 ( 2290570 16150 ) ( 2290570 243950 ) + NEW met1 ( 2290570 16150 ) M1M2_PR + NEW met1 ( 2589570 16150 ) M1M2_PR + NEW met1 ( 2290570 243950 ) M1M2_PR + NEW met1 ( 2285050 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[10] ( PIN la_oen[10] ) ( mprj la_oen[10] ) + + ROUTED met2 ( 515430 246330 ) ( 515430 260100 0 ) + NEW met2 ( 823630 2380 0 ) ( 823630 17340 ) + NEW met2 ( 821790 17340 ) ( 823630 17340 ) + NEW met1 ( 515430 246330 ) ( 821790 246330 ) + NEW met2 ( 821790 17340 ) ( 821790 246330 ) + NEW met1 ( 515430 246330 ) M1M2_PR + NEW met1 ( 821790 246330 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[110] ( PIN la_oen[110] ) ( mprj la_oen[110] ) + + ROUTED met2 ( 2607510 2380 0 ) ( 2607510 19890 ) + NEW met1 ( 2304370 19890 ) ( 2607510 19890 ) + NEW met2 ( 2302990 260100 0 ) ( 2304370 260100 ) + NEW met2 ( 2304370 19890 ) ( 2304370 260100 ) + NEW met1 ( 2607510 19890 ) M1M2_PR + NEW met1 ( 2304370 19890 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[111] ( PIN la_oen[111] ) ( mprj la_oen[111] ) + + ROUTED met2 ( 2625450 2380 0 ) ( 2625450 19550 ) + NEW met1 ( 2320930 243950 ) ( 2325070 243950 ) + NEW met2 ( 2320930 243950 ) ( 2320930 260100 0 ) + NEW met2 ( 2325070 19550 ) ( 2325070 243950 ) + NEW met1 ( 2325070 19550 ) ( 2625450 19550 ) + NEW met1 ( 2325070 19550 ) M1M2_PR + NEW met1 ( 2625450 19550 ) M1M2_PR + NEW met1 ( 2325070 243950 ) M1M2_PR + NEW met1 ( 2320930 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[112] ( PIN la_oen[112] ) ( mprj la_oen[112] ) + + ROUTED met2 ( 2338870 244970 ) ( 2338870 260100 0 ) + NEW met2 ( 2643390 2380 0 ) ( 2643390 17340 ) + NEW met2 ( 2642930 17340 ) ( 2643390 17340 ) + NEW met1 ( 2338870 244970 ) ( 2642930 244970 ) + NEW met2 ( 2642930 17340 ) ( 2642930 244970 ) + NEW met1 ( 2338870 244970 ) M1M2_PR + NEW met1 ( 2642930 244970 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[113] ( PIN la_oen[113] ) ( mprj la_oen[113] ) + + ROUTED li1 ( 2642930 15810 ) ( 2642930 18870 ) + NEW met1 ( 2642930 15810 ) ( 2661330 15810 ) + NEW met2 ( 2661330 2380 0 ) ( 2661330 15810 ) + NEW met1 ( 2359570 18870 ) ( 2642930 18870 ) + NEW met2 ( 2356810 260100 0 ) ( 2359570 260100 ) + NEW met2 ( 2359570 18870 ) ( 2359570 260100 ) + NEW met1 ( 2359570 18870 ) M1M2_PR + NEW li1 ( 2642930 18870 ) L1M1_PR_MR + NEW li1 ( 2642930 15810 ) L1M1_PR_MR + NEW met1 ( 2661330 15810 ) M1M2_PR +======= + ROUTED met2 ( 1618510 1591710 ) ( 1618510 1688610 ) NEW met2 ( 1603330 1688610 ) ( 1603330 1700340 0 ) NEW met1 ( 1603330 1688610 ) ( 1618510 1688610 ) @@ -80792,10 +86272,26 @@ NEW met1 ( 1722470 1569950 ) M1M2_PR NEW met1 ( 1722010 1642370 ) M1M2_PR NEW met1 ( 1722470 1642370 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - la_oen[114] ( PIN la_oen[114] ) ( mprj la_oen[114] ) + ROUTED met2 ( 2678810 2380 0 ) ( 2678810 17340 ) NEW met2 ( 2677430 17340 ) ( 2678810 17340 ) +<<<<<<< HEAD + NEW met2 ( 2374290 245990 ) ( 2374290 260100 0 ) + NEW met1 ( 2374290 245990 ) ( 2677430 245990 ) + NEW met2 ( 2677430 17340 ) ( 2677430 245990 ) + NEW met1 ( 2374290 245990 ) M1M2_PR + NEW met1 ( 2677430 245990 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[115] ( PIN la_oen[115] ) ( mprj la_oen[115] ) + + ROUTED met2 ( 2696750 2380 0 ) ( 2696750 18190 ) + NEW met1 ( 2394070 18190 ) ( 2696750 18190 ) + NEW met2 ( 2392230 260100 0 ) ( 2394070 260100 ) + NEW met2 ( 2394070 18190 ) ( 2394070 260100 ) + NEW met1 ( 2696750 18190 ) M1M2_PR + NEW met1 ( 2394070 18190 ) M1M2_PR +======= NEW met1 ( 1725230 1635910 ) ( 1730290 1635910 ) NEW met2 ( 1730290 1383290 ) ( 1730290 1635910 ) NEW met2 ( 1725230 1700340 ) ( 1725690 1700340 0 ) @@ -80820,10 +86316,1152 @@ NEW met1 ( 1730750 1369690 ) ( 2691230 1369690 ) NEW met1 ( 2691230 1369690 ) M1M2_PR NEW met1 ( 1730750 1369690 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - la_oen[116] ( PIN la_oen[116] ) ( mprj la_oen[116] ) + ROUTED met2 ( 2714690 2380 0 ) ( 2714690 17340 ) NEW met2 ( 2711930 17340 ) ( 2714690 17340 ) +<<<<<<< HEAD + NEW met2 ( 2410170 245650 ) ( 2410170 260100 0 ) + NEW met2 ( 2711930 17340 ) ( 2711930 245650 ) + NEW met1 ( 2410170 245650 ) ( 2711930 245650 ) + NEW met1 ( 2410170 245650 ) M1M2_PR + NEW met1 ( 2711930 245650 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[117] ( PIN la_oen[117] ) ( mprj la_oen[117] ) + + ROUTED met2 ( 2732630 2380 0 ) ( 2732630 18020 ) + NEW met2 ( 2428110 260100 0 ) ( 2428570 260100 ) + NEW met2 ( 2428570 18020 ) ( 2428570 260100 ) + NEW met3 ( 2428570 18020 ) ( 2732630 18020 ) + NEW met2 ( 2428570 18020 ) via2_FR + NEW met2 ( 2732630 18020 ) via2_FR ++ USE SIGNAL ; +- la_oen[118] ( PIN la_oen[118] ) ( mprj la_oen[118] ) + + ROUTED met2 ( 2446050 245310 ) ( 2446050 260100 0 ) + NEW met2 ( 2750570 2380 0 ) ( 2750570 17340 ) + NEW met2 ( 2746430 17340 ) ( 2750570 17340 ) + NEW met1 ( 2446050 245310 ) ( 2746430 245310 ) + NEW met2 ( 2746430 17340 ) ( 2746430 245310 ) + NEW met1 ( 2446050 245310 ) M1M2_PR + NEW met1 ( 2746430 245310 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[119] ( PIN la_oen[119] ) ( mprj la_oen[119] ) + + ROUTED met2 ( 2768050 2380 0 ) ( 2768050 17510 ) + NEW met1 ( 2469970 17510 ) ( 2768050 17510 ) + NEW met1 ( 2463990 243950 ) ( 2469970 243950 ) + NEW met2 ( 2463990 243950 ) ( 2463990 260100 0 ) + NEW met2 ( 2469970 17510 ) ( 2469970 243950 ) + NEW met1 ( 2469970 17510 ) M1M2_PR + NEW met1 ( 2768050 17510 ) M1M2_PR + NEW met1 ( 2469970 243950 ) M1M2_PR + NEW met1 ( 2463990 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[11] ( PIN la_oen[11] ) ( mprj la_oen[11] ) + + ROUTED met2 ( 841110 2380 0 ) ( 841110 16150 ) + NEW met1 ( 537970 16150 ) ( 841110 16150 ) + NEW met1 ( 533370 243950 ) ( 537970 243950 ) + NEW met2 ( 533370 243950 ) ( 533370 260100 0 ) + NEW met2 ( 537970 16150 ) ( 537970 243950 ) + NEW met1 ( 537970 16150 ) M1M2_PR + NEW met1 ( 841110 16150 ) M1M2_PR + NEW met1 ( 537970 243950 ) M1M2_PR + NEW met1 ( 533370 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[120] ( PIN la_oen[120] ) ( mprj la_oen[120] ) + + ROUTED met2 ( 2785990 2380 0 ) ( 2785990 17850 ) + NEW met1 ( 2483770 17850 ) ( 2785990 17850 ) + NEW met2 ( 2481930 260100 0 ) ( 2483770 260100 ) + NEW met2 ( 2483770 17850 ) ( 2483770 260100 ) + NEW met1 ( 2483770 17850 ) M1M2_PR + NEW met1 ( 2785990 17850 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[121] ( PIN la_oen[121] ) ( mprj la_oen[121] ) + + ROUTED met2 ( 2803930 2380 0 ) ( 2803930 19210 ) + NEW met1 ( 2499410 243950 ) ( 2504470 243950 ) + NEW met2 ( 2499410 243950 ) ( 2499410 260100 0 ) + NEW met2 ( 2504470 19210 ) ( 2504470 243950 ) + NEW met1 ( 2504470 19210 ) ( 2803930 19210 ) + NEW met1 ( 2504470 19210 ) M1M2_PR + NEW met1 ( 2803930 19210 ) M1M2_PR + NEW met1 ( 2504470 243950 ) M1M2_PR + NEW met1 ( 2499410 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[122] ( PIN la_oen[122] ) ( mprj la_oen[122] ) + + ROUTED met2 ( 2821870 2380 0 ) ( 2821870 20230 ) + NEW met2 ( 2517350 260100 0 ) ( 2518270 260100 ) + NEW met2 ( 2518270 20230 ) ( 2518270 260100 ) + NEW met1 ( 2518270 20230 ) ( 2821870 20230 ) + NEW met1 ( 2518270 20230 ) M1M2_PR + NEW met1 ( 2821870 20230 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[123] ( PIN la_oen[123] ) ( mprj la_oen[123] ) + + ROUTED met2 ( 2535290 260100 0 ) ( 2538970 260100 ) + NEW met2 ( 2538970 20570 ) ( 2538970 260100 ) + NEW met2 ( 2839350 2380 0 ) ( 2839350 20570 ) + NEW met1 ( 2538970 20570 ) ( 2839350 20570 ) + NEW met1 ( 2538970 20570 ) M1M2_PR + NEW met1 ( 2839350 20570 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[124] ( PIN la_oen[124] ) ( mprj la_oen[124] ) + + ROUTED met2 ( 2857290 2380 0 ) ( 2857290 16830 ) + NEW met1 ( 2559670 16830 ) ( 2857290 16830 ) + NEW met1 ( 2553230 242590 ) ( 2559670 242590 ) + NEW met2 ( 2553230 242590 ) ( 2553230 260100 0 ) + NEW met2 ( 2559670 16830 ) ( 2559670 242590 ) + NEW met1 ( 2559670 16830 ) M1M2_PR + NEW met1 ( 2857290 16830 ) M1M2_PR + NEW met1 ( 2559670 242590 ) M1M2_PR + NEW met1 ( 2553230 242590 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[125] ( PIN la_oen[125] ) ( mprj la_oen[125] ) + + ROUTED met2 ( 2875230 2380 0 ) ( 2875230 16490 ) + NEW met1 ( 2573470 16490 ) ( 2875230 16490 ) + NEW met2 ( 2571170 260100 0 ) ( 2573470 260100 ) + NEW met2 ( 2573470 16490 ) ( 2573470 260100 ) + NEW met1 ( 2573470 16490 ) M1M2_PR + NEW met1 ( 2875230 16490 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[126] ( PIN la_oen[126] ) ( mprj la_oen[126] ) + + ROUTED met2 ( 2893170 2380 0 ) ( 2893170 16150 ) + NEW met1 ( 2594170 16150 ) ( 2893170 16150 ) + NEW met1 ( 2589110 243950 ) ( 2594170 243950 ) + NEW met2 ( 2589110 243950 ) ( 2589110 260100 0 ) + NEW met2 ( 2594170 16150 ) ( 2594170 243950 ) + NEW met1 ( 2893170 16150 ) M1M2_PR + NEW met1 ( 2594170 16150 ) M1M2_PR + NEW met1 ( 2594170 243950 ) M1M2_PR + NEW met1 ( 2589110 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[127] ( PIN la_oen[127] ) ( mprj la_oen[127] ) + + ROUTED met2 ( 2911110 2380 0 ) ( 2911110 19890 ) + NEW met2 ( 2607050 260100 0 ) ( 2607970 260100 ) + NEW met2 ( 2607970 19890 ) ( 2607970 260100 ) + NEW met1 ( 2607970 19890 ) ( 2911110 19890 ) + NEW met1 ( 2607970 19890 ) M1M2_PR + NEW met1 ( 2911110 19890 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[12] ( PIN la_oen[12] ) ( mprj la_oen[12] ) + + ROUTED met2 ( 859050 2380 0 ) ( 859050 16660 ) + NEW met2 ( 856290 16660 ) ( 859050 16660 ) + NEW met2 ( 856290 16660 ) ( 856290 247010 ) + NEW met2 ( 551310 247010 ) ( 551310 260100 0 ) + NEW met1 ( 551310 247010 ) ( 856290 247010 ) + NEW met1 ( 856290 247010 ) M1M2_PR + NEW met1 ( 551310 247010 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[13] ( PIN la_oen[13] ) ( mprj la_oen[13] ) + + ROUTED met2 ( 876530 15980 ) ( 876530 18530 ) + NEW met2 ( 876530 15980 ) ( 876990 15980 ) + NEW met2 ( 876990 2380 0 ) ( 876990 15980 ) + NEW met1 ( 568790 243950 ) ( 572470 243950 ) + NEW met2 ( 568790 243950 ) ( 568790 260100 0 ) + NEW met2 ( 572470 18530 ) ( 572470 243950 ) + NEW met1 ( 572470 18530 ) ( 876530 18530 ) + NEW met1 ( 572470 18530 ) M1M2_PR + NEW met1 ( 876530 18530 ) M1M2_PR + NEW met1 ( 572470 243950 ) M1M2_PR + NEW met1 ( 568790 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[14] ( PIN la_oen[14] ) ( mprj la_oen[14] ) + + ROUTED met1 ( 865030 16150 ) ( 865030 16490 ) + NEW met1 ( 865030 16150 ) ( 894930 16150 ) + NEW met2 ( 894930 2380 0 ) ( 894930 16150 ) + NEW met1 ( 586730 243950 ) ( 593170 243950 ) + NEW met2 ( 586730 243950 ) ( 586730 260100 0 ) + NEW met2 ( 593170 16490 ) ( 593170 243950 ) + NEW met1 ( 593170 16490 ) ( 865030 16490 ) + NEW met1 ( 593170 16490 ) M1M2_PR + NEW met1 ( 894930 16150 ) M1M2_PR + NEW met1 ( 593170 243950 ) M1M2_PR + NEW met1 ( 586730 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[15] ( PIN la_oen[15] ) ( mprj la_oen[15] ) + + ROUTED met2 ( 604670 260100 0 ) ( 606970 260100 ) + NEW met2 ( 606970 18190 ) ( 606970 260100 ) + NEW met2 ( 912870 2380 0 ) ( 912870 18190 ) + NEW met1 ( 606970 18190 ) ( 912870 18190 ) + NEW met1 ( 606970 18190 ) M1M2_PR + NEW met1 ( 912870 18190 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[16] ( PIN la_oen[16] ) ( mprj la_oen[16] ) + + ROUTED met2 ( 930350 2380 0 ) ( 930350 16830 ) + NEW met1 ( 627670 16830 ) ( 930350 16830 ) + NEW met1 ( 622610 243950 ) ( 627670 243950 ) + NEW met2 ( 622610 243950 ) ( 622610 260100 0 ) + NEW met2 ( 627670 16830 ) ( 627670 243950 ) + NEW met1 ( 627670 16830 ) M1M2_PR + NEW met1 ( 930350 16830 ) M1M2_PR + NEW met1 ( 627670 243950 ) M1M2_PR + NEW met1 ( 622610 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[17] ( PIN la_oen[17] ) ( mprj la_oen[17] ) + + ROUTED met1 ( 917470 17850 ) ( 917470 18190 ) + NEW met1 ( 917470 18190 ) ( 948290 18190 ) + NEW met2 ( 948290 2380 0 ) ( 948290 18190 ) + NEW met1 ( 641470 17850 ) ( 917470 17850 ) + NEW met2 ( 640550 260100 0 ) ( 641470 260100 ) + NEW met2 ( 641470 17850 ) ( 641470 260100 ) + NEW met1 ( 641470 17850 ) M1M2_PR + NEW met1 ( 948290 18190 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[18] ( PIN la_oen[18] ) ( mprj la_oen[18] ) + + ROUTED met2 ( 966230 2380 0 ) ( 966230 16660 ) + NEW met2 ( 966230 16660 ) ( 967150 16660 ) + NEW met2 ( 967150 16660 ) ( 967150 245310 ) + NEW met2 ( 658490 245310 ) ( 658490 260100 0 ) + NEW met1 ( 658490 245310 ) ( 967150 245310 ) + NEW met1 ( 967150 245310 ) M1M2_PR + NEW met1 ( 658490 245310 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[19] ( PIN la_oen[19] ) ( mprj la_oen[19] ) + + ROUTED met2 ( 984170 2380 0 ) ( 984170 19550 ) + NEW met1 ( 676430 242590 ) ( 682410 242590 ) + NEW met2 ( 676430 242590 ) ( 676430 260100 0 ) + NEW met2 ( 682410 19550 ) ( 682410 242590 ) + NEW met1 ( 682410 19550 ) ( 984170 19550 ) + NEW met1 ( 682410 19550 ) M1M2_PR + NEW met1 ( 984170 19550 ) M1M2_PR + NEW met1 ( 682410 242590 ) M1M2_PR + NEW met1 ( 676430 242590 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[1] ( PIN la_oen[1] ) ( mprj la_oen[1] ) + + ROUTED met2 ( 662630 18700 ) ( 662630 19550 ) + NEW met2 ( 662630 18700 ) ( 663090 18700 ) + NEW met2 ( 663090 2380 0 ) ( 663090 18700 ) + NEW met1 ( 358570 19550 ) ( 662630 19550 ) + NEW met1 ( 354430 243950 ) ( 358570 243950 ) + NEW met2 ( 354430 243950 ) ( 354430 260100 0 ) + NEW met2 ( 358570 19550 ) ( 358570 243950 ) + NEW met1 ( 662630 19550 ) M1M2_PR + NEW met1 ( 358570 19550 ) M1M2_PR + NEW met1 ( 358570 243950 ) M1M2_PR + NEW met1 ( 354430 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[20] ( PIN la_oen[20] ) ( mprj la_oen[20] ) + + ROUTED met2 ( 694370 245650 ) ( 694370 260100 0 ) + NEW met2 ( 1002110 2380 0 ) ( 1002110 16660 ) + NEW met2 ( 1001190 16660 ) ( 1002110 16660 ) + NEW met1 ( 694370 245650 ) ( 1001190 245650 ) + NEW met2 ( 1001190 16660 ) ( 1001190 245650 ) + NEW met1 ( 694370 245650 ) M1M2_PR + NEW met1 ( 1001190 245650 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[21] ( PIN la_oen[21] ) ( mprj la_oen[21] ) + + ROUTED met2 ( 1019590 2380 0 ) ( 1019590 20570 ) + NEW met1 ( 717370 20570 ) ( 1019590 20570 ) + NEW met1 ( 711850 243950 ) ( 717370 243950 ) + NEW met2 ( 711850 243950 ) ( 711850 260100 0 ) + NEW met2 ( 717370 20570 ) ( 717370 243950 ) + NEW met1 ( 717370 20570 ) M1M2_PR + NEW met1 ( 1019590 20570 ) M1M2_PR + NEW met1 ( 717370 243950 ) M1M2_PR + NEW met1 ( 711850 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[22] ( PIN la_oen[22] ) ( mprj la_oen[22] ) + + ROUTED met2 ( 1037530 2380 0 ) ( 1037530 16660 ) + NEW met2 ( 1035690 16660 ) ( 1037530 16660 ) + NEW met2 ( 729790 245990 ) ( 729790 260100 0 ) + NEW met1 ( 729790 245990 ) ( 1035690 245990 ) + NEW met2 ( 1035690 16660 ) ( 1035690 245990 ) + NEW met1 ( 729790 245990 ) M1M2_PR + NEW met1 ( 1035690 245990 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[23] ( PIN la_oen[23] ) ( mprj la_oen[23] ) + + ROUTED met2 ( 1055470 2380 0 ) ( 1055470 20230 ) + NEW met1 ( 751870 20230 ) ( 1055470 20230 ) + NEW met1 ( 747730 243950 ) ( 751870 243950 ) + NEW met2 ( 747730 243950 ) ( 747730 260100 0 ) + NEW met2 ( 751870 20230 ) ( 751870 243950 ) + NEW met1 ( 1055470 20230 ) M1M2_PR + NEW met1 ( 751870 20230 ) M1M2_PR + NEW met1 ( 751870 243950 ) M1M2_PR + NEW met1 ( 747730 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[24] ( PIN la_oen[24] ) ( mprj la_oen[24] ) + + ROUTED met2 ( 1073410 2380 0 ) ( 1073410 18870 ) + NEW met2 ( 765670 18870 ) ( 765670 260100 0 ) + NEW met1 ( 765670 18870 ) ( 1073410 18870 ) + NEW met1 ( 765670 18870 ) M1M2_PR + NEW met1 ( 1073410 18870 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[25] ( PIN la_oen[25] ) ( mprj la_oen[25] ) + + ROUTED met2 ( 1090430 17340 ) ( 1090430 19210 ) + NEW met2 ( 1090430 17340 ) ( 1090890 17340 ) + NEW met2 ( 1090890 2380 0 ) ( 1090890 17340 ) + NEW met2 ( 783610 260100 0 ) ( 786370 260100 ) + NEW met2 ( 786370 19210 ) ( 786370 260100 ) + NEW met1 ( 786370 19210 ) ( 1090430 19210 ) + NEW met1 ( 786370 19210 ) M1M2_PR + NEW met1 ( 1090430 19210 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[26] ( PIN la_oen[26] ) ( mprj la_oen[26] ) + + ROUTED met1 ( 801550 243950 ) ( 807070 243950 ) + NEW met2 ( 801550 243950 ) ( 801550 260100 0 ) + NEW met2 ( 807070 19890 ) ( 807070 243950 ) + NEW met2 ( 1108830 2380 0 ) ( 1108830 19890 ) + NEW met1 ( 807070 19890 ) ( 1108830 19890 ) + NEW met1 ( 807070 19890 ) M1M2_PR + NEW met1 ( 807070 243950 ) M1M2_PR + NEW met1 ( 801550 243950 ) M1M2_PR + NEW met1 ( 1108830 19890 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[27] ( PIN la_oen[27] ) ( mprj la_oen[27] ) + + ROUTED met2 ( 1126770 2380 0 ) ( 1126770 17170 ) + NEW met1 ( 820870 17170 ) ( 1126770 17170 ) + NEW met2 ( 819490 260100 0 ) ( 820870 260100 ) + NEW met2 ( 820870 17170 ) ( 820870 260100 ) + NEW met1 ( 820870 17170 ) M1M2_PR + NEW met1 ( 1126770 17170 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[28] ( PIN la_oen[28] ) ( mprj la_oen[28] ) + + ROUTED met2 ( 1144710 2380 0 ) ( 1144710 16660 ) + NEW met2 ( 1139650 16660 ) ( 1144710 16660 ) + NEW met2 ( 836970 247350 ) ( 836970 260100 0 ) + NEW met1 ( 836970 247350 ) ( 1139650 247350 ) + NEW met2 ( 1139650 16660 ) ( 1139650 247350 ) + NEW met1 ( 836970 247350 ) M1M2_PR + NEW met1 ( 1139650 247350 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[29] ( PIN la_oen[29] ) ( mprj la_oen[29] ) + + ROUTED met2 ( 1162650 2380 0 ) ( 1162650 17510 ) + NEW met1 ( 855370 17510 ) ( 1162650 17510 ) + NEW met2 ( 854910 260100 0 ) ( 855370 260100 ) + NEW met2 ( 855370 17510 ) ( 855370 260100 ) + NEW met1 ( 1162650 17510 ) M1M2_PR + NEW met1 ( 855370 17510 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[2] ( PIN la_oen[2] ) ( mprj la_oen[2] ) + + ROUTED met2 ( 680570 2380 0 ) ( 680570 16660 ) + NEW met2 ( 677350 16660 ) ( 680570 16660 ) + NEW met2 ( 677350 16660 ) ( 677350 245650 ) + NEW met2 ( 372370 245650 ) ( 372370 260100 0 ) + NEW met1 ( 372370 245650 ) ( 677350 245650 ) + NEW met1 ( 677350 245650 ) M1M2_PR + NEW met1 ( 372370 245650 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[30] ( PIN la_oen[30] ) ( mprj la_oen[30] ) + + ROUTED met2 ( 1180130 2380 0 ) ( 1180130 17340 ) + NEW met2 ( 1180130 17340 ) ( 1181050 17340 ) + NEW met2 ( 872850 246330 ) ( 872850 260100 0 ) + NEW met2 ( 1181050 17340 ) ( 1181050 246330 ) + NEW met1 ( 872850 246330 ) ( 1181050 246330 ) + NEW met1 ( 872850 246330 ) M1M2_PR + NEW met1 ( 1181050 246330 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[31] ( PIN la_oen[31] ) ( mprj la_oen[31] ) + + ROUTED met1 ( 890790 243950 ) ( 896770 243950 ) + NEW met2 ( 890790 243950 ) ( 890790 260100 0 ) + NEW met2 ( 896770 15470 ) ( 896770 243950 ) + NEW met2 ( 1198070 2380 0 ) ( 1198070 15470 ) + NEW met1 ( 896770 15470 ) ( 1198070 15470 ) + NEW met1 ( 896770 15470 ) M1M2_PR + NEW met1 ( 896770 243950 ) M1M2_PR + NEW met1 ( 890790 243950 ) M1M2_PR + NEW met1 ( 1198070 15470 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[32] ( PIN la_oen[32] ) ( mprj la_oen[32] ) + + ROUTED met2 ( 1216010 2380 0 ) ( 1216010 16660 ) + NEW met2 ( 1215090 16660 ) ( 1216010 16660 ) + NEW met2 ( 908730 244970 ) ( 908730 260100 0 ) + NEW met1 ( 908730 244970 ) ( 1215090 244970 ) + NEW met2 ( 1215090 16660 ) ( 1215090 244970 ) + NEW met1 ( 908730 244970 ) M1M2_PR + NEW met1 ( 1215090 244970 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[33] ( PIN la_oen[33] ) ( mprj la_oen[33] ) + + ROUTED met2 ( 1233950 2380 0 ) ( 1233950 15130 ) + NEW met1 ( 931270 15130 ) ( 1233950 15130 ) + NEW met1 ( 926670 243950 ) ( 931270 243950 ) + NEW met2 ( 926670 243950 ) ( 926670 260100 0 ) + NEW met2 ( 931270 15130 ) ( 931270 243950 ) + NEW met1 ( 931270 15130 ) M1M2_PR + NEW met1 ( 1233950 15130 ) M1M2_PR + NEW met1 ( 931270 243950 ) M1M2_PR + NEW met1 ( 926670 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[34] ( PIN la_oen[34] ) ( mprj la_oen[34] ) + + ROUTED met2 ( 1251890 2380 0 ) ( 1251890 16660 ) + NEW met2 ( 1249590 16660 ) ( 1251890 16660 ) + NEW met2 ( 1249590 16660 ) ( 1249590 246670 ) + NEW met2 ( 944610 246670 ) ( 944610 260100 0 ) + NEW met1 ( 944610 246670 ) ( 1249590 246670 ) + NEW met1 ( 1249590 246670 ) M1M2_PR + NEW met1 ( 944610 246670 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[35] ( PIN la_oen[35] ) ( mprj la_oen[35] ) + + ROUTED met2 ( 1269370 2380 0 ) ( 1269370 15810 ) + NEW met2 ( 962090 260100 0 ) ( 965770 260100 ) + NEW met2 ( 965770 15810 ) ( 965770 260100 ) + NEW met1 ( 965770 15810 ) ( 1269370 15810 ) + NEW met1 ( 965770 15810 ) M1M2_PR + NEW met1 ( 1269370 15810 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[36] ( PIN la_oen[36] ) ( mprj la_oen[36] ) + + ROUTED met2 ( 1287310 2380 0 ) ( 1287310 16150 ) + NEW met1 ( 980030 243270 ) ( 986470 243270 ) + NEW met2 ( 980030 243270 ) ( 980030 260100 0 ) + NEW met2 ( 986470 16150 ) ( 986470 243270 ) + NEW met1 ( 986470 16150 ) ( 1287310 16150 ) + NEW met1 ( 986470 16150 ) M1M2_PR + NEW met1 ( 1287310 16150 ) M1M2_PR + NEW met1 ( 986470 243270 ) M1M2_PR + NEW met1 ( 980030 243270 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[37] ( PIN la_oen[37] ) ( mprj la_oen[37] ) + + ROUTED met2 ( 997970 260100 0 ) ( 1000270 260100 ) + NEW met2 ( 1000270 19550 ) ( 1000270 260100 ) + NEW met2 ( 1305250 2380 0 ) ( 1305250 19550 ) + NEW met1 ( 1000270 19550 ) ( 1305250 19550 ) + NEW met1 ( 1000270 19550 ) M1M2_PR + NEW met1 ( 1305250 19550 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[38] ( PIN la_oen[38] ) ( mprj la_oen[38] ) + + ROUTED met2 ( 1323190 2380 0 ) ( 1323190 16490 ) + NEW met1 ( 1020970 16490 ) ( 1323190 16490 ) + NEW met1 ( 1015910 243950 ) ( 1020970 243950 ) + NEW met2 ( 1015910 243950 ) ( 1015910 260100 0 ) + NEW met2 ( 1020970 16490 ) ( 1020970 243950 ) + NEW met1 ( 1020970 16490 ) M1M2_PR + NEW met1 ( 1323190 16490 ) M1M2_PR + NEW met1 ( 1020970 243950 ) M1M2_PR + NEW met1 ( 1015910 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[39] ( PIN la_oen[39] ) ( mprj la_oen[39] ) + + ROUTED met2 ( 1340670 2380 0 ) ( 1340670 18530 ) + NEW met1 ( 1034770 18530 ) ( 1340670 18530 ) + NEW met2 ( 1033850 260100 0 ) ( 1034770 260100 ) + NEW met2 ( 1034770 18530 ) ( 1034770 260100 ) + NEW met1 ( 1340670 18530 ) M1M2_PR + NEW met1 ( 1034770 18530 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[3] ( PIN la_oen[3] ) ( mprj la_oen[3] ) + + ROUTED met1 ( 663090 19210 ) ( 663090 19550 ) + NEW met1 ( 663090 19550 ) ( 669530 19550 ) + NEW met1 ( 669530 19210 ) ( 669530 19550 ) + NEW met1 ( 669530 19210 ) ( 698510 19210 ) + NEW met2 ( 698510 2380 0 ) ( 698510 19210 ) + NEW met2 ( 390310 260100 0 ) ( 393070 260100 ) + NEW met2 ( 393070 19210 ) ( 393070 260100 ) + NEW met1 ( 393070 19210 ) ( 663090 19210 ) + NEW met1 ( 393070 19210 ) M1M2_PR + NEW met1 ( 698510 19210 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[40] ( PIN la_oen[40] ) ( mprj la_oen[40] ) + + ROUTED met2 ( 1358610 2380 0 ) ( 1358610 16830 ) + NEW met1 ( 1352630 16830 ) ( 1358610 16830 ) + NEW met2 ( 1051790 245990 ) ( 1051790 260100 0 ) + NEW met2 ( 1352630 16830 ) ( 1352630 245990 ) + NEW met1 ( 1051790 245990 ) ( 1352630 245990 ) + NEW met1 ( 1358610 16830 ) M1M2_PR + NEW met1 ( 1352630 16830 ) M1M2_PR + NEW met1 ( 1051790 245990 ) M1M2_PR + NEW met1 ( 1352630 245990 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[41] ( PIN la_oen[41] ) ( mprj la_oen[41] ) + + ROUTED met1 ( 1338830 16150 ) ( 1338830 16830 ) + NEW met1 ( 1338830 16150 ) ( 1376550 16150 ) + NEW met2 ( 1376550 2380 0 ) ( 1376550 16150 ) + NEW met1 ( 1069730 243950 ) ( 1076170 243950 ) + NEW met2 ( 1069730 243950 ) ( 1069730 260100 0 ) + NEW met2 ( 1076170 16830 ) ( 1076170 243950 ) + NEW met1 ( 1076170 16830 ) ( 1338830 16830 ) + NEW met1 ( 1076170 16830 ) M1M2_PR + NEW met1 ( 1376550 16150 ) M1M2_PR + NEW met1 ( 1076170 243950 ) M1M2_PR + NEW met1 ( 1069730 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[42] ( PIN la_oen[42] ) ( mprj la_oen[42] ) + + ROUTED met2 ( 1087210 245310 ) ( 1087210 260100 0 ) + NEW met2 ( 1394490 2380 0 ) ( 1394490 17340 ) + NEW met2 ( 1394490 17340 ) ( 1394950 17340 ) + NEW met1 ( 1087210 245310 ) ( 1394950 245310 ) + NEW met2 ( 1394950 17340 ) ( 1394950 245310 ) + NEW met1 ( 1087210 245310 ) M1M2_PR + NEW met1 ( 1394950 245310 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[43] ( PIN la_oen[43] ) ( mprj la_oen[43] ) + + ROUTED met2 ( 1412430 2380 0 ) ( 1412430 18870 ) + NEW met1 ( 1110670 18870 ) ( 1412430 18870 ) + NEW met1 ( 1105150 243950 ) ( 1110670 243950 ) + NEW met2 ( 1105150 243950 ) ( 1105150 260100 0 ) + NEW met2 ( 1110670 18870 ) ( 1110670 243950 ) + NEW met1 ( 1110670 18870 ) M1M2_PR + NEW met1 ( 1412430 18870 ) M1M2_PR + NEW met1 ( 1110670 243950 ) M1M2_PR + NEW met1 ( 1105150 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[44] ( PIN la_oen[44] ) ( mprj la_oen[44] ) + + ROUTED met2 ( 1429910 2380 0 ) ( 1429910 16830 ) + NEW met2 ( 1428990 16830 ) ( 1429910 16830 ) + NEW met2 ( 1123090 245650 ) ( 1123090 260100 0 ) + NEW met1 ( 1123090 245650 ) ( 1428990 245650 ) + NEW met2 ( 1428990 16830 ) ( 1428990 245650 ) + NEW met1 ( 1123090 245650 ) M1M2_PR + NEW met1 ( 1428990 245650 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[45] ( PIN la_oen[45] ) ( mprj la_oen[45] ) + + ROUTED met2 ( 1447850 2380 0 ) ( 1447850 19210 ) + NEW met1 ( 1145170 19210 ) ( 1447850 19210 ) + NEW met1 ( 1141030 243950 ) ( 1145170 243950 ) + NEW met2 ( 1141030 243950 ) ( 1141030 260100 0 ) + NEW met2 ( 1145170 19210 ) ( 1145170 243950 ) + NEW met1 ( 1447850 19210 ) M1M2_PR + NEW met1 ( 1145170 19210 ) M1M2_PR + NEW met1 ( 1145170 243950 ) M1M2_PR + NEW met1 ( 1141030 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[46] ( PIN la_oen[46] ) ( mprj la_oen[46] ) + + ROUTED met2 ( 1465790 2380 0 ) ( 1465790 18190 ) + NEW met2 ( 1158970 18190 ) ( 1158970 260100 0 ) + NEW met1 ( 1158970 18190 ) ( 1465790 18190 ) + NEW met1 ( 1158970 18190 ) M1M2_PR + NEW met1 ( 1465790 18190 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[47] ( PIN la_oen[47] ) ( mprj la_oen[47] ) + + ROUTED met2 ( 1176910 260100 0 ) ( 1179670 260100 ) + NEW met2 ( 1179670 17170 ) ( 1179670 260100 ) + NEW met2 ( 1483730 2380 0 ) ( 1483730 17170 ) + NEW met1 ( 1179670 17170 ) ( 1483730 17170 ) + NEW met1 ( 1179670 17170 ) M1M2_PR + NEW met1 ( 1483730 17170 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[48] ( PIN la_oen[48] ) ( mprj la_oen[48] ) + + ROUTED met2 ( 1501670 2380 0 ) ( 1501670 20570 ) + NEW met1 ( 1200370 20570 ) ( 1501670 20570 ) + NEW met1 ( 1194850 243610 ) ( 1200370 243610 ) + NEW met2 ( 1194850 243610 ) ( 1194850 260100 0 ) + NEW met2 ( 1200370 20570 ) ( 1200370 243610 ) + NEW met1 ( 1200370 20570 ) M1M2_PR + NEW met1 ( 1501670 20570 ) M1M2_PR + NEW met1 ( 1200370 243610 ) M1M2_PR + NEW met1 ( 1194850 243610 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[49] ( PIN la_oen[49] ) ( mprj la_oen[49] ) + + ROUTED met2 ( 1519150 2380 0 ) ( 1519150 17850 ) + NEW met1 ( 1214170 17850 ) ( 1519150 17850 ) + NEW met2 ( 1212330 260100 0 ) ( 1214170 260100 ) + NEW met2 ( 1214170 17850 ) ( 1214170 260100 ) + NEW met1 ( 1214170 17850 ) M1M2_PR + NEW met1 ( 1519150 17850 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[4] ( PIN la_oen[4] ) ( mprj la_oen[4] ) + + ROUTED met2 ( 408250 245990 ) ( 408250 260100 0 ) + NEW met2 ( 716450 2380 0 ) ( 716450 16660 ) + NEW met2 ( 711390 16660 ) ( 716450 16660 ) + NEW met1 ( 408250 245990 ) ( 711390 245990 ) + NEW met2 ( 711390 16660 ) ( 711390 245990 ) + NEW met1 ( 408250 245990 ) M1M2_PR + NEW met1 ( 711390 245990 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[50] ( PIN la_oen[50] ) ( mprj la_oen[50] ) + + ROUTED met2 ( 1537090 2380 0 ) ( 1537090 19890 ) + NEW met1 ( 1234870 19890 ) ( 1537090 19890 ) + NEW met1 ( 1230270 243950 ) ( 1234870 243950 ) + NEW met2 ( 1230270 243950 ) ( 1230270 260100 0 ) + NEW met2 ( 1234870 19890 ) ( 1234870 243950 ) + NEW met1 ( 1537090 19890 ) M1M2_PR + NEW met1 ( 1234870 19890 ) M1M2_PR + NEW met1 ( 1234870 243950 ) M1M2_PR + NEW met1 ( 1230270 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[51] ( PIN la_oen[51] ) ( mprj la_oen[51] ) + + ROUTED met2 ( 1555030 2380 0 ) ( 1555030 17510 ) + NEW met2 ( 1248210 260100 0 ) ( 1248670 260100 ) + NEW met2 ( 1248670 17510 ) ( 1248670 260100 ) + NEW met1 ( 1248670 17510 ) ( 1555030 17510 ) + NEW met1 ( 1248670 17510 ) M1M2_PR + NEW met1 ( 1555030 17510 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[52] ( PIN la_oen[52] ) ( mprj la_oen[52] ) + + ROUTED met2 ( 1572970 2380 0 ) ( 1572970 16660 ) + NEW met2 ( 1567450 16660 ) ( 1572970 16660 ) + NEW met2 ( 1266150 246330 ) ( 1266150 260100 0 ) + NEW met2 ( 1567450 16660 ) ( 1567450 246330 ) + NEW met1 ( 1266150 246330 ) ( 1567450 246330 ) + NEW met1 ( 1266150 246330 ) M1M2_PR + NEW met1 ( 1567450 246330 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[53] ( PIN la_oen[53] ) ( mprj la_oen[53] ) + + ROUTED met1 ( 1284090 243950 ) ( 1290070 243950 ) + NEW met2 ( 1284090 243950 ) ( 1284090 260100 0 ) + NEW met2 ( 1290070 20230 ) ( 1290070 243950 ) + NEW met2 ( 1590450 2380 0 ) ( 1590450 20230 ) + NEW met1 ( 1290070 20230 ) ( 1590450 20230 ) + NEW met1 ( 1290070 20230 ) M1M2_PR + NEW met1 ( 1290070 243950 ) M1M2_PR + NEW met1 ( 1284090 243950 ) M1M2_PR + NEW met1 ( 1590450 20230 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[54] ( PIN la_oen[54] ) ( mprj la_oen[54] ) + + ROUTED met2 ( 1302030 244970 ) ( 1302030 260100 0 ) + NEW met1 ( 1302030 244970 ) ( 1608850 244970 ) + NEW met2 ( 1608390 37740 ) ( 1608850 37740 ) + NEW met2 ( 1608390 2380 0 ) ( 1608390 37740 ) + NEW met2 ( 1608850 37740 ) ( 1608850 244970 ) + NEW met1 ( 1302030 244970 ) M1M2_PR + NEW met1 ( 1608850 244970 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[55] ( PIN la_oen[55] ) ( mprj la_oen[55] ) + + ROUTED met1 ( 1319970 243950 ) ( 1324570 243950 ) + NEW met2 ( 1319970 243950 ) ( 1319970 260100 0 ) + NEW met2 ( 1324570 38250 ) ( 1324570 243950 ) + NEW met1 ( 1607930 38250 ) ( 1607930 38590 ) + NEW met1 ( 1607930 38590 ) ( 1626330 38590 ) + NEW met1 ( 1324570 38250 ) ( 1607930 38250 ) + NEW met2 ( 1626330 2380 0 ) ( 1626330 38590 ) + NEW met1 ( 1324570 38250 ) M1M2_PR + NEW met1 ( 1324570 243950 ) M1M2_PR + NEW met1 ( 1319970 243950 ) M1M2_PR + NEW met1 ( 1626330 38590 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[56] ( PIN la_oen[56] ) ( mprj la_oen[56] ) + + ROUTED met2 ( 1337450 260100 0 ) ( 1338370 260100 ) + NEW met2 ( 1338370 127670 ) ( 1338370 260100 ) + NEW met2 ( 1644270 2380 0 ) ( 1644270 2890 ) + NEW met1 ( 1644270 2890 ) ( 1644730 2890 ) + NEW met2 ( 1644730 2890 ) ( 1644730 47940 ) + NEW met2 ( 1644270 47940 ) ( 1644730 47940 ) + NEW met2 ( 1642890 96900 ) ( 1642890 127670 ) + NEW met2 ( 1642430 96900 ) ( 1642890 96900 ) + NEW met1 ( 1338370 127670 ) ( 1642890 127670 ) + NEW li1 ( 1642430 48450 ) ( 1642430 96390 ) + NEW met1 ( 1642430 48450 ) ( 1644270 48450 ) + NEW met2 ( 1642430 96390 ) ( 1642430 96900 ) + NEW met2 ( 1644270 47940 ) ( 1644270 48450 ) + NEW met1 ( 1338370 127670 ) M1M2_PR + NEW met1 ( 1644270 2890 ) M1M2_PR + NEW met1 ( 1644730 2890 ) M1M2_PR + NEW met1 ( 1642890 127670 ) M1M2_PR + NEW li1 ( 1642430 96390 ) L1M1_PR_MR + NEW met1 ( 1642430 96390 ) M1M2_PR + NEW li1 ( 1642430 48450 ) L1M1_PR_MR + NEW met1 ( 1644270 48450 ) M1M2_PR + NEW met1 ( 1642430 96390 ) RECT ( 0 -70 355 70 ) ++ USE SIGNAL ; +- la_oen[57] ( PIN la_oen[57] ) ( mprj la_oen[57] ) + + ROUTED met2 ( 1662210 2380 0 ) ( 1662210 16660 ) + NEW met2 ( 1656690 16660 ) ( 1662210 16660 ) + NEW met1 ( 1355390 243610 ) ( 1362750 243610 ) + NEW met2 ( 1355390 243610 ) ( 1355390 260100 0 ) + NEW met2 ( 1362750 134810 ) ( 1362750 243610 ) + NEW met2 ( 1656690 16660 ) ( 1656690 134810 ) + NEW met1 ( 1362750 134810 ) ( 1656690 134810 ) + NEW met1 ( 1362750 134810 ) M1M2_PR + NEW met1 ( 1362750 243610 ) M1M2_PR + NEW met1 ( 1355390 243610 ) M1M2_PR + NEW met1 ( 1656690 134810 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[58] ( PIN la_oen[58] ) ( mprj la_oen[58] ) + + ROUTED met1 ( 1373330 243950 ) ( 1379310 243950 ) + NEW met2 ( 1373330 243950 ) ( 1373330 260100 0 ) + NEW met2 ( 1379310 120870 ) ( 1379310 243950 ) + NEW met2 ( 1679690 2380 0 ) ( 1679690 17340 ) + NEW met2 ( 1676930 17340 ) ( 1679690 17340 ) + NEW met1 ( 1379310 120870 ) ( 1676930 120870 ) + NEW met2 ( 1676930 17340 ) ( 1676930 120870 ) + NEW met1 ( 1379310 120870 ) M1M2_PR + NEW met1 ( 1379310 243950 ) M1M2_PR + NEW met1 ( 1373330 243950 ) M1M2_PR + NEW met1 ( 1676930 120870 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[59] ( PIN la_oen[59] ) ( mprj la_oen[59] ) + + ROUTED met2 ( 1391270 231370 ) ( 1391270 260100 0 ) + NEW met1 ( 1391270 231370 ) ( 1697630 231370 ) + NEW met2 ( 1697630 2380 0 ) ( 1697630 231370 ) + NEW met1 ( 1391270 231370 ) M1M2_PR + NEW met1 ( 1697630 231370 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[5] ( PIN la_oen[5] ) ( mprj la_oen[5] ) + + ROUTED met2 ( 734390 2380 0 ) ( 734390 17340 ) + NEW met3 ( 427570 17340 ) ( 734390 17340 ) + NEW met2 ( 426190 260100 0 ) ( 427570 260100 ) + NEW met2 ( 427570 17340 ) ( 427570 260100 ) + NEW met2 ( 427570 17340 ) via2_FR + NEW met2 ( 734390 17340 ) via2_FR ++ USE SIGNAL ; +- la_oen[60] ( PIN la_oen[60] ) ( mprj la_oen[60] ) + + ROUTED met2 ( 1715570 2380 0 ) ( 1715570 31110 ) + NEW met1 ( 1409210 243950 ) ( 1414270 243950 ) + NEW met2 ( 1409210 243950 ) ( 1409210 260100 0 ) + NEW met2 ( 1414270 31110 ) ( 1414270 243950 ) + NEW met1 ( 1414270 31110 ) ( 1715570 31110 ) + NEW met1 ( 1414270 31110 ) M1M2_PR + NEW met1 ( 1715570 31110 ) M1M2_PR + NEW met1 ( 1414270 243950 ) M1M2_PR + NEW met1 ( 1409210 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[61] ( PIN la_oen[61] ) ( mprj la_oen[61] ) + + ROUTED met2 ( 1733510 2380 0 ) ( 1733510 17340 ) + NEW met2 ( 1732130 17340 ) ( 1733510 17340 ) + NEW met2 ( 1732130 17340 ) ( 1732130 51850 ) + NEW met2 ( 1427150 260100 0 ) ( 1428070 260100 ) + NEW met2 ( 1428070 51850 ) ( 1428070 260100 ) + NEW met1 ( 1428070 51850 ) ( 1732130 51850 ) + NEW met1 ( 1732130 51850 ) M1M2_PR + NEW met1 ( 1428070 51850 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[62] ( PIN la_oen[62] ) ( mprj la_oen[62] ) + + ROUTED met1 ( 1738110 18870 ) ( 1738110 19210 ) + NEW met1 ( 1738110 19210 ) ( 1751450 19210 ) + NEW met2 ( 1751450 2380 0 ) ( 1751450 19210 ) + NEW met2 ( 1445090 260100 0 ) ( 1448770 260100 ) + NEW met2 ( 1448770 18870 ) ( 1448770 260100 ) + NEW met1 ( 1448770 18870 ) ( 1738110 18870 ) + NEW met1 ( 1448770 18870 ) M1M2_PR + NEW met1 ( 1751450 19210 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[63] ( PIN la_oen[63] ) ( mprj la_oen[63] ) + + ROUTED li1 ( 1737650 19210 ) ( 1737650 20570 ) + NEW met1 ( 1737650 20570 ) ( 1768930 20570 ) + NEW met2 ( 1768930 2380 0 ) ( 1768930 20570 ) + NEW met1 ( 1463030 243950 ) ( 1469470 243950 ) + NEW met2 ( 1463030 243950 ) ( 1463030 260100 0 ) + NEW met2 ( 1469470 19210 ) ( 1469470 243950 ) + NEW met1 ( 1469470 19210 ) ( 1737650 19210 ) + NEW met1 ( 1469470 19210 ) M1M2_PR + NEW li1 ( 1737650 19210 ) L1M1_PR_MR + NEW li1 ( 1737650 20570 ) L1M1_PR_MR + NEW met1 ( 1768930 20570 ) M1M2_PR + NEW met1 ( 1469470 243950 ) M1M2_PR + NEW met1 ( 1463030 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[64] ( PIN la_oen[64] ) ( mprj la_oen[64] ) + + ROUTED met2 ( 1480510 260100 0 ) ( 1483270 260100 ) + NEW met2 ( 1483270 18530 ) ( 1483270 260100 ) + NEW met2 ( 1786870 2380 0 ) ( 1786870 18530 ) + NEW met1 ( 1483270 18530 ) ( 1786870 18530 ) + NEW met1 ( 1483270 18530 ) M1M2_PR + NEW met1 ( 1786870 18530 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[65] ( PIN la_oen[65] ) ( mprj la_oen[65] ) + + ROUTED met2 ( 1804810 2380 0 ) ( 1804810 17170 ) + NEW met1 ( 1498450 243950 ) ( 1503970 243950 ) + NEW met2 ( 1498450 243950 ) ( 1498450 260100 0 ) + NEW met2 ( 1503970 17170 ) ( 1503970 243950 ) + NEW met1 ( 1503970 17170 ) ( 1804810 17170 ) + NEW met1 ( 1503970 17170 ) M1M2_PR + NEW met1 ( 1804810 17170 ) M1M2_PR + NEW met1 ( 1503970 243950 ) M1M2_PR + NEW met1 ( 1498450 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[66] ( PIN la_oen[66] ) ( mprj la_oen[66] ) + + ROUTED met2 ( 1822750 2380 0 ) ( 1822750 16660 ) + NEW met2 ( 1821830 16660 ) ( 1822750 16660 ) + NEW met2 ( 1821830 16660 ) ( 1821830 58650 ) + NEW met2 ( 1516390 260100 0 ) ( 1517770 260100 ) + NEW met2 ( 1517770 58650 ) ( 1517770 260100 ) + NEW met1 ( 1517770 58650 ) ( 1821830 58650 ) + NEW met1 ( 1821830 58650 ) M1M2_PR + NEW met1 ( 1517770 58650 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[67] ( PIN la_oen[67] ) ( mprj la_oen[67] ) + + ROUTED met2 ( 1840230 2380 0 ) ( 1840230 19550 ) + NEW met1 ( 1534330 243950 ) ( 1538470 243950 ) + NEW met2 ( 1534330 243950 ) ( 1534330 260100 0 ) + NEW met2 ( 1538470 19550 ) ( 1538470 243950 ) + NEW met1 ( 1538470 19550 ) ( 1840230 19550 ) + NEW met1 ( 1538470 19550 ) M1M2_PR + NEW met1 ( 1840230 19550 ) M1M2_PR + NEW met1 ( 1538470 243950 ) M1M2_PR + NEW met1 ( 1534330 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[68] ( PIN la_oen[68] ) ( mprj la_oen[68] ) + + ROUTED met2 ( 1552270 17850 ) ( 1552270 260100 0 ) + NEW li1 ( 1631390 17850 ) ( 1632310 17850 ) + NEW met1 ( 1552270 17850 ) ( 1631390 17850 ) + NEW met1 ( 1632310 17850 ) ( 1858170 17850 ) + NEW met2 ( 1858170 2380 0 ) ( 1858170 17850 ) + NEW met1 ( 1552270 17850 ) M1M2_PR + NEW li1 ( 1631390 17850 ) L1M1_PR_MR + NEW li1 ( 1632310 17850 ) L1M1_PR_MR + NEW met1 ( 1858170 17850 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[69] ( PIN la_oen[69] ) ( mprj la_oen[69] ) + + ROUTED met2 ( 1570210 260100 0 ) ( 1572970 260100 ) + NEW met2 ( 1572970 19890 ) ( 1572970 260100 ) + NEW met1 ( 1572970 19890 ) ( 1876110 19890 ) + NEW met2 ( 1876110 2380 0 ) ( 1876110 19890 ) + NEW met1 ( 1572970 19890 ) M1M2_PR + NEW met1 ( 1876110 19890 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[6] ( PIN la_oen[6] ) ( mprj la_oen[6] ) + + ROUTED met2 ( 752330 2380 0 ) ( 752330 17340 ) + NEW met2 ( 752330 17340 ) ( 753250 17340 ) + NEW met2 ( 443670 246670 ) ( 443670 260100 0 ) + NEW met1 ( 443670 246670 ) ( 753250 246670 ) + NEW met2 ( 753250 17340 ) ( 753250 246670 ) + NEW met1 ( 443670 246670 ) M1M2_PR + NEW met1 ( 753250 246670 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[70] ( PIN la_oen[70] ) ( mprj la_oen[70] ) + + ROUTED met1 ( 1588150 241570 ) ( 1593670 241570 ) + NEW met2 ( 1588150 241570 ) ( 1588150 260100 0 ) + NEW met2 ( 1593670 16490 ) ( 1593670 241570 ) + NEW met1 ( 1593670 16490 ) ( 1894050 16490 ) + NEW met2 ( 1894050 2380 0 ) ( 1894050 16490 ) + NEW met1 ( 1593670 16490 ) M1M2_PR + NEW met1 ( 1593670 241570 ) M1M2_PR + NEW met1 ( 1588150 241570 ) M1M2_PR + NEW met1 ( 1894050 16490 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[71] ( PIN la_oen[71] ) ( mprj la_oen[71] ) + + ROUTED met2 ( 1911530 17340 ) ( 1911530 18190 ) + NEW met2 ( 1911530 17340 ) ( 1911990 17340 ) + NEW met2 ( 1911990 2380 0 ) ( 1911990 17340 ) + NEW met2 ( 1605630 260100 0 ) ( 1607470 260100 ) + NEW met2 ( 1607470 17510 ) ( 1607470 260100 ) + NEW met1 ( 1631850 17510 ) ( 1631850 18190 ) + NEW met1 ( 1607470 17510 ) ( 1631850 17510 ) + NEW met1 ( 1631850 18190 ) ( 1911530 18190 ) + NEW met1 ( 1607470 17510 ) M1M2_PR + NEW met1 ( 1911530 18190 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[72] ( PIN la_oen[72] ) ( mprj la_oen[72] ) + + ROUTED met2 ( 1929470 2380 0 ) ( 1929470 16150 ) + NEW met1 ( 1623570 243950 ) ( 1628170 243950 ) + NEW met2 ( 1623570 243950 ) ( 1623570 260100 0 ) + NEW met2 ( 1628170 16150 ) ( 1628170 243950 ) + NEW met1 ( 1628170 16150 ) ( 1929470 16150 ) + NEW met1 ( 1929470 16150 ) M1M2_PR + NEW met1 ( 1628170 243950 ) M1M2_PR + NEW met1 ( 1623570 243950 ) M1M2_PR + NEW met1 ( 1628170 16150 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[73] ( PIN la_oen[73] ) ( mprj la_oen[73] ) + + ROUTED met2 ( 1641510 260100 0 ) ( 1641970 260100 ) + NEW met2 ( 1641970 17510 ) ( 1641970 260100 ) + NEW met1 ( 1641970 17510 ) ( 1947410 17510 ) + NEW met2 ( 1947410 2380 0 ) ( 1947410 17510 ) + NEW met1 ( 1641970 17510 ) M1M2_PR + NEW met1 ( 1947410 17510 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[74] ( PIN la_oen[74] ) ( mprj la_oen[74] ) + + ROUTED met2 ( 1659450 260100 0 ) ( 1662670 260100 ) + NEW met2 ( 1662670 15810 ) ( 1662670 260100 ) + NEW met1 ( 1662670 15810 ) ( 1965350 15810 ) + NEW met2 ( 1965350 2380 0 ) ( 1965350 15810 ) + NEW met1 ( 1662670 15810 ) M1M2_PR + NEW met1 ( 1965350 15810 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[75] ( PIN la_oen[75] ) ( mprj la_oen[75] ) + + ROUTED met1 ( 1677390 243950 ) ( 1683370 243950 ) + NEW met2 ( 1677390 243950 ) ( 1677390 260100 0 ) + NEW met2 ( 1683370 16830 ) ( 1683370 243950 ) + NEW met1 ( 1683370 16830 ) ( 1983290 16830 ) + NEW met2 ( 1983290 2380 0 ) ( 1983290 16830 ) + NEW met1 ( 1683370 16830 ) M1M2_PR + NEW met1 ( 1683370 243950 ) M1M2_PR + NEW met1 ( 1677390 243950 ) M1M2_PR + NEW met1 ( 1983290 16830 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[76] ( PIN la_oen[76] ) ( mprj la_oen[76] ) + + ROUTED met2 ( 2001230 2380 0 ) ( 2001230 16660 ) + NEW met2 ( 1695330 260100 0 ) ( 1697170 260100 ) + NEW met2 ( 1697170 16660 ) ( 1697170 260100 ) + NEW met3 ( 1697170 16660 ) ( 2001230 16660 ) + NEW met2 ( 1697170 16660 ) via2_FR + NEW met2 ( 2001230 16660 ) via2_FR ++ USE SIGNAL ; +- la_oen[77] ( PIN la_oen[77] ) ( mprj la_oen[77] ) + + ROUTED met2 ( 2018710 2380 0 ) ( 2018710 15470 ) + NEW met1 ( 1713270 243950 ) ( 1717870 243950 ) + NEW met2 ( 1713270 243950 ) ( 1713270 260100 0 ) + NEW met2 ( 1717870 15470 ) ( 1717870 243950 ) + NEW met1 ( 1717870 15470 ) ( 2018710 15470 ) + NEW met1 ( 2018710 15470 ) M1M2_PR + NEW met1 ( 1717870 15470 ) M1M2_PR + NEW met1 ( 1717870 243950 ) M1M2_PR + NEW met1 ( 1713270 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[78] ( PIN la_oen[78] ) ( mprj la_oen[78] ) + + ROUTED met2 ( 2036650 2380 0 ) ( 2036650 17340 ) + NEW met2 ( 2036190 17340 ) ( 2036650 17340 ) + NEW met2 ( 1730750 245310 ) ( 1730750 260100 0 ) + NEW met2 ( 2036190 17340 ) ( 2036190 245310 ) + NEW met1 ( 1730750 245310 ) ( 2036190 245310 ) + NEW met1 ( 1730750 245310 ) M1M2_PR + NEW met1 ( 2036190 245310 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[79] ( PIN la_oen[79] ) ( mprj la_oen[79] ) + + ROUTED met2 ( 1748690 260100 0 ) ( 1752370 260100 ) + NEW met2 ( 1752370 20230 ) ( 1752370 260100 ) + NEW met1 ( 1752370 20230 ) ( 2054590 20230 ) + NEW met2 ( 2054590 2380 0 ) ( 2054590 20230 ) + NEW met1 ( 1752370 20230 ) M1M2_PR + NEW met1 ( 2054590 20230 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[7] ( PIN la_oen[7] ) ( mprj la_oen[7] ) + + ROUTED met2 ( 769810 2380 0 ) ( 769810 16660 ) + NEW met3 ( 462070 16660 ) ( 769810 16660 ) + NEW met2 ( 461610 260100 0 ) ( 462070 260100 ) + NEW met2 ( 462070 16660 ) ( 462070 260100 ) + NEW met2 ( 769810 16660 ) via2_FR + NEW met2 ( 462070 16660 ) via2_FR ++ USE SIGNAL ; +- la_oen[80] ( PIN la_oen[80] ) ( mprj la_oen[80] ) + + ROUTED met1 ( 1766630 243950 ) ( 1773070 243950 ) + NEW met2 ( 1766630 243950 ) ( 1766630 260100 0 ) + NEW met2 ( 1773070 19210 ) ( 1773070 243950 ) + NEW met1 ( 1773070 19210 ) ( 2072530 19210 ) + NEW met2 ( 2072530 2380 0 ) ( 2072530 19210 ) + NEW met1 ( 1773070 19210 ) M1M2_PR + NEW met1 ( 1773070 243950 ) M1M2_PR + NEW met1 ( 1766630 243950 ) M1M2_PR + NEW met1 ( 2072530 19210 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[81] ( PIN la_oen[81] ) ( mprj la_oen[81] ) + + ROUTED met2 ( 1786870 19210 ) ( 1787330 19210 ) + NEW met2 ( 1787330 18530 ) ( 1787330 19210 ) + NEW met2 ( 1784570 260100 0 ) ( 1786870 260100 ) + NEW met2 ( 1786870 19210 ) ( 1786870 260100 ) + NEW met1 ( 1787330 18530 ) ( 2090010 18530 ) + NEW met2 ( 2090010 2380 0 ) ( 2090010 18530 ) + NEW met1 ( 1787330 18530 ) M1M2_PR + NEW met1 ( 2090010 18530 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[82] ( PIN la_oen[82] ) ( mprj la_oen[82] ) + + ROUTED met2 ( 2107950 2380 0 ) ( 2107950 20570 ) + NEW met1 ( 1802510 243950 ) ( 1807570 243950 ) + NEW met2 ( 1802510 243950 ) ( 1802510 260100 0 ) + NEW met2 ( 1807570 20570 ) ( 1807570 243950 ) + NEW met1 ( 1807570 20570 ) ( 2107950 20570 ) + NEW met1 ( 1807570 20570 ) M1M2_PR + NEW met1 ( 2107950 20570 ) M1M2_PR + NEW met1 ( 1807570 243950 ) M1M2_PR + NEW met1 ( 1802510 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[83] ( PIN la_oen[83] ) ( mprj la_oen[83] ) + + ROUTED met2 ( 2125890 2380 0 ) ( 2125890 17340 ) + NEW met2 ( 1820450 260100 0 ) ( 1821370 260100 ) + NEW met2 ( 1821370 17340 ) ( 1821370 260100 ) + NEW met3 ( 1821370 17340 ) ( 2125890 17340 ) + NEW met2 ( 2125890 17340 ) via2_FR + NEW met2 ( 1821370 17340 ) via2_FR ++ USE SIGNAL ; +- la_oen[84] ( PIN la_oen[84] ) ( mprj la_oen[84] ) + + ROUTED met2 ( 1838390 245990 ) ( 1838390 260100 0 ) + NEW met2 ( 2143830 2380 0 ) ( 2143830 13770 ) + NEW met1 ( 2143830 13770 ) ( 2143830 14110 ) + NEW met1 ( 2139690 14110 ) ( 2143830 14110 ) + NEW li1 ( 2139690 48450 ) ( 2139690 96390 ) + NEW met2 ( 2139690 14110 ) ( 2139690 48450 ) + NEW li1 ( 2139690 145010 ) ( 2139690 192950 ) + NEW met2 ( 2139690 96390 ) ( 2139690 145010 ) + NEW li1 ( 2139690 241570 ) ( 2139690 245990 ) + NEW met1 ( 1838390 245990 ) ( 2139690 245990 ) + NEW met2 ( 2139690 192950 ) ( 2139690 241570 ) + NEW met1 ( 1838390 245990 ) M1M2_PR + NEW met1 ( 2143830 13770 ) M1M2_PR + NEW met1 ( 2139690 14110 ) M1M2_PR + NEW li1 ( 2139690 48450 ) L1M1_PR_MR + NEW met1 ( 2139690 48450 ) M1M2_PR + NEW li1 ( 2139690 96390 ) L1M1_PR_MR + NEW met1 ( 2139690 96390 ) M1M2_PR + NEW li1 ( 2139690 145010 ) L1M1_PR_MR + NEW met1 ( 2139690 145010 ) M1M2_PR + NEW li1 ( 2139690 192950 ) L1M1_PR_MR + NEW met1 ( 2139690 192950 ) M1M2_PR + NEW li1 ( 2139690 245990 ) L1M1_PR_MR + NEW li1 ( 2139690 241570 ) L1M1_PR_MR + NEW met1 ( 2139690 241570 ) M1M2_PR + NEW met1 ( 2139690 48450 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2139690 96390 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2139690 145010 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2139690 192950 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2139690 241570 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- la_oen[85] ( PIN la_oen[85] ) ( mprj la_oen[85] ) + + ROUTED met2 ( 1855870 17170 ) ( 1855870 260100 0 ) + NEW met1 ( 1855870 17170 ) ( 2161770 17170 ) + NEW met2 ( 2161770 2380 0 ) ( 2161770 17170 ) + NEW met1 ( 1855870 17170 ) M1M2_PR + NEW met1 ( 2161770 17170 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[86] ( PIN la_oen[86] ) ( mprj la_oen[86] ) + + ROUTED met2 ( 1873810 246330 ) ( 1873810 260100 0 ) + NEW met2 ( 2179250 2380 0 ) ( 2179250 2890 ) + NEW li1 ( 2179250 2890 ) ( 2179250 48110 ) + NEW met1 ( 2174190 48110 ) ( 2179250 48110 ) + NEW li1 ( 2174190 48790 ) ( 2174190 96390 ) + NEW met2 ( 2174190 48110 ) ( 2174190 48790 ) + NEW li1 ( 2174190 145010 ) ( 2174190 192950 ) + NEW met2 ( 2174190 96390 ) ( 2174190 145010 ) + NEW li1 ( 2174190 241570 ) ( 2174190 246330 ) + NEW met1 ( 1873810 246330 ) ( 2174190 246330 ) + NEW met2 ( 2174190 192950 ) ( 2174190 241570 ) + NEW met1 ( 1873810 246330 ) M1M2_PR + NEW li1 ( 2179250 2890 ) L1M1_PR_MR + NEW met1 ( 2179250 2890 ) M1M2_PR + NEW li1 ( 2179250 48110 ) L1M1_PR_MR + NEW met1 ( 2174190 48110 ) M1M2_PR + NEW li1 ( 2174190 48790 ) L1M1_PR_MR + NEW met1 ( 2174190 48790 ) M1M2_PR + NEW li1 ( 2174190 96390 ) L1M1_PR_MR + NEW met1 ( 2174190 96390 ) M1M2_PR + NEW li1 ( 2174190 145010 ) L1M1_PR_MR + NEW met1 ( 2174190 145010 ) M1M2_PR + NEW li1 ( 2174190 192950 ) L1M1_PR_MR + NEW met1 ( 2174190 192950 ) M1M2_PR + NEW li1 ( 2174190 246330 ) L1M1_PR_MR + NEW li1 ( 2174190 241570 ) L1M1_PR_MR + NEW met1 ( 2174190 241570 ) M1M2_PR + NEW met1 ( 2179250 2890 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2174190 48790 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2174190 96390 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2174190 145010 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2174190 192950 ) RECT ( -355 -70 0 70 ) + NEW met1 ( 2174190 241570 ) RECT ( -355 -70 0 70 ) ++ USE SIGNAL ; +- la_oen[87] ( PIN la_oen[87] ) ( mprj la_oen[87] ) + + ROUTED met2 ( 2197190 2380 0 ) ( 2197190 18870 ) + NEW met1 ( 1891750 243950 ) ( 1897270 243950 ) + NEW met2 ( 1891750 243950 ) ( 1891750 260100 0 ) + NEW met2 ( 1897270 18870 ) ( 1897270 243950 ) + NEW met1 ( 1897270 18870 ) ( 2197190 18870 ) + NEW met1 ( 2197190 18870 ) M1M2_PR + NEW met1 ( 1897270 243950 ) M1M2_PR + NEW met1 ( 1891750 243950 ) M1M2_PR + NEW met1 ( 1897270 18870 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[88] ( PIN la_oen[88] ) ( mprj la_oen[88] ) + + ROUTED met2 ( 2215130 2380 0 ) ( 2215130 17340 ) + NEW met2 ( 2215130 17340 ) ( 2216050 17340 ) + NEW met2 ( 2216050 17340 ) ( 2216050 244970 ) + NEW met2 ( 1909690 244970 ) ( 1909690 260100 0 ) + NEW met1 ( 1909690 244970 ) ( 2216050 244970 ) + NEW met1 ( 2216050 244970 ) M1M2_PR + NEW met1 ( 1909690 244970 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[89] ( PIN la_oen[89] ) ( mprj la_oen[89] ) + + ROUTED met1 ( 2215590 18190 ) ( 2215590 18870 ) + NEW met1 ( 2215590 18870 ) ( 2233070 18870 ) + NEW met2 ( 2233070 2380 0 ) ( 2233070 18870 ) + NEW met1 ( 1927630 241910 ) ( 1931770 241910 ) + NEW met2 ( 1927630 241910 ) ( 1927630 260100 0 ) + NEW met2 ( 1931770 18190 ) ( 1931770 241910 ) + NEW met1 ( 1931770 18190 ) ( 2215590 18190 ) + NEW met1 ( 1931770 18190 ) M1M2_PR + NEW met1 ( 2233070 18870 ) M1M2_PR + NEW met1 ( 1931770 241910 ) M1M2_PR + NEW met1 ( 1927630 241910 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[8] ( PIN la_oen[8] ) ( mprj la_oen[8] ) + + ROUTED met2 ( 787750 2380 0 ) ( 787750 7820 ) + NEW met2 ( 787290 7820 ) ( 787750 7820 ) + NEW met2 ( 479550 244970 ) ( 479550 260100 0 ) + NEW met2 ( 787290 7820 ) ( 787290 244970 ) + NEW met1 ( 479550 244970 ) ( 787290 244970 ) + NEW met1 ( 479550 244970 ) M1M2_PR + NEW met1 ( 787290 244970 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[90] ( PIN la_oen[90] ) ( mprj la_oen[90] ) + + ROUTED met2 ( 2251010 2380 0 ) ( 2251010 16660 ) + NEW met2 ( 2250090 16660 ) ( 2251010 16660 ) + NEW met2 ( 1945570 245650 ) ( 1945570 260100 0 ) + NEW met2 ( 2250090 16660 ) ( 2250090 245650 ) + NEW met1 ( 1945570 245650 ) ( 2250090 245650 ) + NEW met1 ( 1945570 245650 ) M1M2_PR + NEW met1 ( 2250090 245650 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[91] ( PIN la_oen[91] ) ( mprj la_oen[91] ) + + ROUTED met2 ( 1963510 260100 0 ) ( 1966270 260100 ) + NEW met2 ( 2268490 2380 0 ) ( 2268490 19550 ) + NEW met2 ( 1966270 19550 ) ( 1966270 260100 ) + NEW met1 ( 1966270 19550 ) ( 2268490 19550 ) + NEW met1 ( 2268490 19550 ) M1M2_PR + NEW met1 ( 1966270 19550 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[92] ( PIN la_oen[92] ) ( mprj la_oen[92] ) + + ROUTED met2 ( 2286430 2380 0 ) ( 2286430 2890 ) + NEW met1 ( 2284590 2890 ) ( 2286430 2890 ) + NEW met2 ( 1980990 247010 ) ( 1980990 260100 0 ) + NEW met1 ( 1980990 247010 ) ( 2284590 247010 ) + NEW met2 ( 2284590 2890 ) ( 2284590 247010 ) + NEW met1 ( 2286430 2890 ) M1M2_PR + NEW met1 ( 2284590 2890 ) M1M2_PR + NEW met1 ( 1980990 247010 ) M1M2_PR + NEW met1 ( 2284590 247010 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[93] ( PIN la_oen[93] ) ( mprj la_oen[93] ) + + ROUTED met2 ( 2303910 19380 ) ( 2303910 19890 ) + NEW met2 ( 2303910 19380 ) ( 2304370 19380 ) + NEW met2 ( 2304370 2380 0 ) ( 2304370 19380 ) + NEW met2 ( 1998930 260100 0 ) ( 2000770 260100 ) + NEW met2 ( 2000770 19890 ) ( 2000770 260100 ) + NEW met1 ( 2000770 19890 ) ( 2303910 19890 ) + NEW met1 ( 2000770 19890 ) M1M2_PR + NEW met1 ( 2303910 19890 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[94] ( PIN la_oen[94] ) ( mprj la_oen[94] ) + + ROUTED met2 ( 2322310 2380 0 ) ( 2322310 16660 ) + NEW met2 ( 2319090 16660 ) ( 2322310 16660 ) + NEW met2 ( 2016870 246670 ) ( 2016870 260100 0 ) + NEW met2 ( 2319090 16660 ) ( 2319090 246670 ) + NEW met1 ( 2016870 246670 ) ( 2319090 246670 ) + NEW met1 ( 2016870 246670 ) M1M2_PR + NEW met1 ( 2319090 246670 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[95] ( PIN la_oen[95] ) ( mprj la_oen[95] ) + + ROUTED met2 ( 2339790 2380 0 ) ( 2339790 16660 ) + NEW met2 ( 2034810 260100 0 ) ( 2035270 260100 ) + NEW met2 ( 2035270 16660 ) ( 2035270 260100 ) + NEW met3 ( 2035270 16660 ) ( 2339790 16660 ) + NEW met2 ( 2035270 16660 ) via2_FR + NEW met2 ( 2339790 16660 ) via2_FR ++ USE SIGNAL ; +- la_oen[96] ( PIN la_oen[96] ) ( mprj la_oen[96] ) + + ROUTED met2 ( 2052750 260100 0 ) ( 2055970 260100 ) + NEW met2 ( 2357730 2380 0 ) ( 2357730 20230 ) + NEW met2 ( 2055970 20230 ) ( 2055970 260100 ) + NEW met1 ( 2055970 20230 ) ( 2357730 20230 ) + NEW met1 ( 2357730 20230 ) M1M2_PR + NEW met1 ( 2055970 20230 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[97] ( PIN la_oen[97] ) ( mprj la_oen[97] ) + + ROUTED met2 ( 2375670 2380 0 ) ( 2375670 19210 ) + NEW met1 ( 2070690 243950 ) ( 2076670 243950 ) + NEW met2 ( 2070690 243950 ) ( 2070690 260100 0 ) + NEW met2 ( 2076670 19210 ) ( 2076670 243950 ) + NEW met1 ( 2076670 19210 ) ( 2375670 19210 ) + NEW met1 ( 2375670 19210 ) M1M2_PR + NEW met1 ( 2076670 243950 ) M1M2_PR + NEW met1 ( 2070690 243950 ) M1M2_PR + NEW met1 ( 2076670 19210 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[98] ( PIN la_oen[98] ) ( mprj la_oen[98] ) + + ROUTED li1 ( 2214670 18530 ) ( 2216050 18530 ) + NEW met2 ( 2393610 2380 0 ) ( 2393610 18530 ) + NEW met1 ( 2216050 18530 ) ( 2393610 18530 ) + NEW met2 ( 2088630 260100 0 ) ( 2090470 260100 ) + NEW met2 ( 2090470 18530 ) ( 2090470 260100 ) + NEW met1 ( 2090470 18530 ) ( 2214670 18530 ) + NEW li1 ( 2214670 18530 ) L1M1_PR_MR + NEW li1 ( 2216050 18530 ) L1M1_PR_MR + NEW met1 ( 2393610 18530 ) M1M2_PR + NEW met1 ( 2090470 18530 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[99] ( PIN la_oen[99] ) ( mprj la_oen[99] ) + + ROUTED met2 ( 2411550 2380 0 ) ( 2411550 17850 ) + NEW met1 ( 2106110 243950 ) ( 2111170 243950 ) + NEW met2 ( 2106110 243950 ) ( 2106110 260100 0 ) + NEW met2 ( 2111170 17850 ) ( 2111170 243950 ) + NEW met1 ( 2111170 17850 ) ( 2411550 17850 ) + NEW met1 ( 2411550 17850 ) M1M2_PR + NEW met1 ( 2111170 17850 ) M1M2_PR + NEW met1 ( 2111170 243950 ) M1M2_PR + NEW met1 ( 2106110 243950 ) M1M2_PR ++ USE SIGNAL ; +- la_oen[9] ( PIN la_oen[9] ) ( mprj la_oen[9] ) + + ROUTED met2 ( 805690 2380 0 ) ( 805690 15810 ) + NEW met1 ( 497490 243950 ) ( 503470 243950 ) + NEW met2 ( 497490 243950 ) ( 497490 260100 0 ) + NEW met2 ( 503470 15810 ) ( 503470 243950 ) + NEW met1 ( 503470 15810 ) ( 805690 15810 ) + NEW met1 ( 503470 15810 ) M1M2_PR + NEW met1 ( 805690 15810 ) M1M2_PR + NEW met1 ( 503470 243950 ) M1M2_PR + NEW met1 ( 497490 243950 ) M1M2_PR +======= NEW met1 ( 1733050 1684190 ) ( 1737190 1684190 ) NEW met2 ( 1733050 1684190 ) ( 1733050 1700340 0 ) NEW met2 ( 1737190 1638630 ) ( 1737190 1684190 ) @@ -84624,10 +91262,235 @@ NEW met2 ( 807070 62220 ) ( 807070 1417970 ) NEW met1 ( 807070 1417970 ) M1M2_PR NEW met1 ( 1340210 1417970 ) M1M2_PR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; - user_clock2 ( PIN user_clock2 ) + USE SIGNAL ; - wb_clk_i ( PIN wb_clk_i ) ( mprj wb_clk_i ) +<<<<<<< HEAD + + ROUTED met2 ( 2990 2380 0 ) ( 2990 17170 ) + NEW met2 ( 310730 260100 ) ( 313030 260100 0 ) + NEW met2 ( 310730 17170 ) ( 310730 260100 ) + NEW met1 ( 2990 17170 ) ( 310730 17170 ) + NEW met1 ( 2990 17170 ) M1M2_PR + NEW met1 ( 310730 17170 ) M1M2_PR ++ USE SIGNAL ; +- wb_rst_i ( PIN wb_rst_i ) ( mprj wb_rst_i ) + + ROUTED met2 ( 8510 2380 0 ) ( 8510 17510 ) + NEW met2 ( 317630 260100 ) ( 318550 260100 0 ) + NEW met2 ( 317630 17510 ) ( 317630 260100 ) + NEW met1 ( 8510 17510 ) ( 317630 17510 ) + NEW met1 ( 8510 17510 ) M1M2_PR + NEW met1 ( 317630 17510 ) M1M2_PR ++ USE SIGNAL ; +- wbs_ack_o ( PIN wbs_ack_o ) ++ USE SIGNAL ; +- wbs_adr_i[0] ( PIN wbs_adr_i[0] ) ++ USE SIGNAL ; +- wbs_adr_i[10] ( PIN wbs_adr_i[10] ) ++ USE SIGNAL ; +- wbs_adr_i[11] ( PIN wbs_adr_i[11] ) ++ USE SIGNAL ; +- wbs_adr_i[12] ( PIN wbs_adr_i[12] ) ++ USE SIGNAL ; +- wbs_adr_i[13] ( PIN wbs_adr_i[13] ) ++ USE SIGNAL ; +- wbs_adr_i[14] ( PIN wbs_adr_i[14] ) ++ USE SIGNAL ; +- wbs_adr_i[15] ( PIN wbs_adr_i[15] ) ++ USE SIGNAL ; +- wbs_adr_i[16] ( PIN wbs_adr_i[16] ) ++ USE SIGNAL ; +- wbs_adr_i[17] ( PIN wbs_adr_i[17] ) ++ USE SIGNAL ; +- wbs_adr_i[18] ( PIN wbs_adr_i[18] ) ++ USE SIGNAL ; +- wbs_adr_i[19] ( PIN wbs_adr_i[19] ) ++ USE SIGNAL ; +- wbs_adr_i[1] ( PIN wbs_adr_i[1] ) ++ USE SIGNAL ; +- wbs_adr_i[20] ( PIN wbs_adr_i[20] ) ++ USE SIGNAL ; +- wbs_adr_i[21] ( PIN wbs_adr_i[21] ) ++ USE SIGNAL ; +- wbs_adr_i[22] ( PIN wbs_adr_i[22] ) ++ USE SIGNAL ; +- wbs_adr_i[23] ( PIN wbs_adr_i[23] ) ++ USE SIGNAL ; +- wbs_adr_i[24] ( PIN wbs_adr_i[24] ) ++ USE SIGNAL ; +- wbs_adr_i[25] ( PIN wbs_adr_i[25] ) ++ USE SIGNAL ; +- wbs_adr_i[26] ( PIN wbs_adr_i[26] ) ++ USE SIGNAL ; +- wbs_adr_i[27] ( PIN wbs_adr_i[27] ) ++ USE SIGNAL ; +- wbs_adr_i[28] ( PIN wbs_adr_i[28] ) ++ USE SIGNAL ; +- wbs_adr_i[29] ( PIN wbs_adr_i[29] ) ++ USE SIGNAL ; +- wbs_adr_i[2] ( PIN wbs_adr_i[2] ) ++ USE SIGNAL ; +- wbs_adr_i[30] ( PIN wbs_adr_i[30] ) ++ USE SIGNAL ; +- wbs_adr_i[31] ( PIN wbs_adr_i[31] ) ++ USE SIGNAL ; +- wbs_adr_i[3] ( PIN wbs_adr_i[3] ) ++ USE SIGNAL ; +- wbs_adr_i[4] ( PIN wbs_adr_i[4] ) ++ USE SIGNAL ; +- wbs_adr_i[5] ( PIN wbs_adr_i[5] ) ++ USE SIGNAL ; +- wbs_adr_i[6] ( PIN wbs_adr_i[6] ) ++ USE SIGNAL ; +- wbs_adr_i[7] ( PIN wbs_adr_i[7] ) ++ USE SIGNAL ; +- wbs_adr_i[8] ( PIN wbs_adr_i[8] ) ++ USE SIGNAL ; +- wbs_adr_i[9] ( PIN wbs_adr_i[9] ) ++ USE SIGNAL ; +- wbs_cyc_i ( PIN wbs_cyc_i ) ++ USE SIGNAL ; +- wbs_dat_i[0] ( PIN wbs_dat_i[0] ) ++ USE SIGNAL ; +- wbs_dat_i[10] ( PIN wbs_dat_i[10] ) ++ USE SIGNAL ; +- wbs_dat_i[11] ( PIN wbs_dat_i[11] ) ++ USE SIGNAL ; +- wbs_dat_i[12] ( PIN wbs_dat_i[12] ) ++ USE SIGNAL ; +- wbs_dat_i[13] ( PIN wbs_dat_i[13] ) ++ USE SIGNAL ; +- wbs_dat_i[14] ( PIN wbs_dat_i[14] ) ++ USE SIGNAL ; +- wbs_dat_i[15] ( PIN wbs_dat_i[15] ) ++ USE SIGNAL ; +- wbs_dat_i[16] ( PIN wbs_dat_i[16] ) ++ USE SIGNAL ; +- wbs_dat_i[17] ( PIN wbs_dat_i[17] ) ++ USE SIGNAL ; +- wbs_dat_i[18] ( PIN wbs_dat_i[18] ) ++ USE SIGNAL ; +- wbs_dat_i[19] ( PIN wbs_dat_i[19] ) ++ USE SIGNAL ; +- wbs_dat_i[1] ( PIN wbs_dat_i[1] ) ++ USE SIGNAL ; +- wbs_dat_i[20] ( PIN wbs_dat_i[20] ) ++ USE SIGNAL ; +- wbs_dat_i[21] ( PIN wbs_dat_i[21] ) ++ USE SIGNAL ; +- wbs_dat_i[22] ( PIN wbs_dat_i[22] ) ++ USE SIGNAL ; +- wbs_dat_i[23] ( PIN wbs_dat_i[23] ) ++ USE SIGNAL ; +- wbs_dat_i[24] ( PIN wbs_dat_i[24] ) ++ USE SIGNAL ; +- wbs_dat_i[25] ( PIN wbs_dat_i[25] ) ++ USE SIGNAL ; +- wbs_dat_i[26] ( PIN wbs_dat_i[26] ) ++ USE SIGNAL ; +- wbs_dat_i[27] ( PIN wbs_dat_i[27] ) ++ USE SIGNAL ; +- wbs_dat_i[28] ( PIN wbs_dat_i[28] ) ++ USE SIGNAL ; +- wbs_dat_i[29] ( PIN wbs_dat_i[29] ) ++ USE SIGNAL ; +- wbs_dat_i[2] ( PIN wbs_dat_i[2] ) ++ USE SIGNAL ; +- wbs_dat_i[30] ( PIN wbs_dat_i[30] ) ++ USE SIGNAL ; +- wbs_dat_i[31] ( PIN wbs_dat_i[31] ) ++ USE SIGNAL ; +- wbs_dat_i[3] ( PIN wbs_dat_i[3] ) ++ USE SIGNAL ; +- wbs_dat_i[4] ( PIN wbs_dat_i[4] ) ++ USE SIGNAL ; +- wbs_dat_i[5] ( PIN wbs_dat_i[5] ) ++ USE SIGNAL ; +- wbs_dat_i[6] ( PIN wbs_dat_i[6] ) ++ USE SIGNAL ; +- wbs_dat_i[7] ( PIN wbs_dat_i[7] ) ++ USE SIGNAL ; +- wbs_dat_i[8] ( PIN wbs_dat_i[8] ) ++ USE SIGNAL ; +- wbs_dat_i[9] ( PIN wbs_dat_i[9] ) ++ USE SIGNAL ; +- wbs_dat_o[0] ( PIN wbs_dat_o[0] ) ++ USE SIGNAL ; +- wbs_dat_o[10] ( PIN wbs_dat_o[10] ) ++ USE SIGNAL ; +- wbs_dat_o[11] ( PIN wbs_dat_o[11] ) ++ USE SIGNAL ; +- wbs_dat_o[12] ( PIN wbs_dat_o[12] ) ++ USE SIGNAL ; +- wbs_dat_o[13] ( PIN wbs_dat_o[13] ) ++ USE SIGNAL ; +- wbs_dat_o[14] ( PIN wbs_dat_o[14] ) ++ USE SIGNAL ; +- wbs_dat_o[15] ( PIN wbs_dat_o[15] ) ++ USE SIGNAL ; +- wbs_dat_o[16] ( PIN wbs_dat_o[16] ) ++ USE SIGNAL ; +- wbs_dat_o[17] ( PIN wbs_dat_o[17] ) ++ USE SIGNAL ; +- wbs_dat_o[18] ( PIN wbs_dat_o[18] ) ++ USE SIGNAL ; +- wbs_dat_o[19] ( PIN wbs_dat_o[19] ) ++ USE SIGNAL ; +- wbs_dat_o[1] ( PIN wbs_dat_o[1] ) ++ USE SIGNAL ; +- wbs_dat_o[20] ( PIN wbs_dat_o[20] ) ++ USE SIGNAL ; +- wbs_dat_o[21] ( PIN wbs_dat_o[21] ) ++ USE SIGNAL ; +- wbs_dat_o[22] ( PIN wbs_dat_o[22] ) ++ USE SIGNAL ; +- wbs_dat_o[23] ( PIN wbs_dat_o[23] ) ++ USE SIGNAL ; +- wbs_dat_o[24] ( PIN wbs_dat_o[24] ) ++ USE SIGNAL ; +- wbs_dat_o[25] ( PIN wbs_dat_o[25] ) ++ USE SIGNAL ; +- wbs_dat_o[26] ( PIN wbs_dat_o[26] ) ++ USE SIGNAL ; +- wbs_dat_o[27] ( PIN wbs_dat_o[27] ) ++ USE SIGNAL ; +- wbs_dat_o[28] ( PIN wbs_dat_o[28] ) ++ USE SIGNAL ; +- wbs_dat_o[29] ( PIN wbs_dat_o[29] ) ++ USE SIGNAL ; +- wbs_dat_o[2] ( PIN wbs_dat_o[2] ) ++ USE SIGNAL ; +- wbs_dat_o[30] ( PIN wbs_dat_o[30] ) ++ USE SIGNAL ; +- wbs_dat_o[31] ( PIN wbs_dat_o[31] ) ++ USE SIGNAL ; +- wbs_dat_o[3] ( PIN wbs_dat_o[3] ) ++ USE SIGNAL ; +- wbs_dat_o[4] ( PIN wbs_dat_o[4] ) ++ USE SIGNAL ; +- wbs_dat_o[5] ( PIN wbs_dat_o[5] ) ++ USE SIGNAL ; +- wbs_dat_o[6] ( PIN wbs_dat_o[6] ) ++ USE SIGNAL ; +- wbs_dat_o[7] ( PIN wbs_dat_o[7] ) ++ USE SIGNAL ; +- wbs_dat_o[8] ( PIN wbs_dat_o[8] ) ++ USE SIGNAL ; +- wbs_dat_o[9] ( PIN wbs_dat_o[9] ) ++ USE SIGNAL ; +- wbs_sel_i[0] ( PIN wbs_sel_i[0] ) ++ USE SIGNAL ; +- wbs_sel_i[1] ( PIN wbs_sel_i[1] ) ++ USE SIGNAL ; +- wbs_sel_i[2] ( PIN wbs_sel_i[2] ) ++ USE SIGNAL ; +- wbs_sel_i[3] ( PIN wbs_sel_i[3] ) ++ USE SIGNAL ; +- wbs_stb_i ( PIN wbs_stb_i ) ++ USE SIGNAL ; +- wbs_we_i ( PIN wbs_we_i ) +======= + ROUTED met2 ( 2990 2380 0 ) ( 2990 23970 ) NEW met2 ( 1173690 36210 ) ( 1174150 36210 ) NEW met2 ( 1174150 36210 ) ( 1174150 37740 ) @@ -88101,6 +94964,7 @@ NEW met3 ( 531300 20740 ) M3M4_PR_M NEW met2 ( 569710 20740 ) via2_FR NEW met2 ( 569710 17340 ) via2_FR +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d + USE SIGNAL ; END NETS END DESIGN
diff --git a/doc/Ghazi-SoC.png b/doc/Ghazi-SoC.png new file mode 100644 index 0000000..7576b87 --- /dev/null +++ b/doc/Ghazi-SoC.png Binary files differ
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diff --git a/gds/advSeal_6um_gen.gds.xz b/gds/advSeal_6um_gen.gds.xz new file mode 100644 index 0000000..d9e92d2 --- /dev/null +++ b/gds/advSeal_6um_gen.gds.xz Binary files differ
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diff --git a/gds/ghazi_top_dffram_csv.gds.xz b/gds/ghazi_top_dffram_csv.gds.xz new file mode 100644 index 0000000..7a44f80 --- /dev/null +++ b/gds/ghazi_top_dffram_csv.gds.xz Binary files differ
diff --git a/gds/gpio_control_block.gds.gz b/gds/gpio_control_block.gds.gz deleted file mode 100644 index b2f9b1f..0000000 --- a/gds/gpio_control_block.gds.gz +++ /dev/null Binary files differ
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diff --git a/gds/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds.xz b/gds/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds.xz new file mode 100644 index 0000000..d56741d --- /dev/null +++ b/gds/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.gds.xz Binary files differ
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diff --git a/gds/user_proj_example.gds.xz b/gds/user_proj_example.gds.xz new file mode 100644 index 0000000..e4abe08 --- /dev/null +++ b/gds/user_proj_example.gds.xz Binary files differ
diff --git a/gds/user_project_wrapper.gds.xz b/gds/user_project_wrapper.gds.xz new file mode 100644 index 0000000..cd154bf --- /dev/null +++ b/gds/user_project_wrapper.gds.xz Binary files differ
diff --git a/gds/user_project_wrapper_empty.gds.gz b/gds/user_project_wrapper_empty.gds.gz deleted file mode 100644 index c8fdfe7..0000000 --- a/gds/user_project_wrapper_empty.gds.gz +++ /dev/null Binary files differ
diff --git a/gds/user_project_wrapper_empty.gds.xz b/gds/user_project_wrapper_empty.gds.xz new file mode 100644 index 0000000..e42d903 --- /dev/null +++ b/gds/user_project_wrapper_empty.gds.xz Binary files differ
diff --git a/info.yaml b/info.yaml index 685ee5e..2de79f3 100644 --- a/info.yaml +++ b/info.yaml
@@ -1,18 +1,18 @@ --- project: - description: "A template SoC for Google sponsored Open MPW shuttles for SKY130." + description: "An SoC (System on a Chip) design for Google sponsored Open MPW shuttles for SKY130." foundry: "SkyWater" - git_url: "https://github.com/efabless/caravel.git" - organization: "Efabless" - organization_url: "http://efabless.com" - owner: "Tim Edwards" + git_url: "https://github.com/merledu/caravel_Ghazi_SoC.git" + organization: "Micro Electronics Research Laboratory" + organization_url: "http://merledupk.org" + owner: "Zain Rizwan Khan" process: "SKY130" - project_name: "Caravel" + project_name: "Ghazi SoC" tags: - "Open MPW" - - "Test Harness" - category: "Test Harness" + - "Ghazi SoC" + category: "Mega Project" top_level_netlist: "verilog/gl/caravel.v" user_level_netlist: "verilog/gl/user_project_wrapper.v" version: "1.00" - cover_image: "doc/ciic_harness.png" + cover_image: "doc/Ghazi_SoC.png"
diff --git a/lef/ghazi_top_dffram_csv.lef b/lef/ghazi_top_dffram_csv.lef new file mode 100644 index 0000000..cd54447 --- /dev/null +++ b/lef/ghazi_top_dffram_csv.lef
@@ -0,0 +1,4129 @@ +VERSION 5.7 ; + NOWIREEXTENSIONATPIN ON ; + DIVIDERCHAR "/" ; + BUSBITCHARS "[]" ; +MACRO ghazi_top_dffram_csv + CLASS BLOCK ; + FOREIGN ghazi_top_dffram_csv ; + ORIGIN 0.000 0.000 ; + SIZE 2300.000 BY 3000.000 ; + PIN io_in[0] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 33.360 2300.000 33.960 ; + END + END io_in[0] + PIN io_in[10] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 2033.240 2300.000 2033.840 ; + END + END io_in[10] + PIN io_in[11] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 2233.160 2300.000 2233.760 ; + END + END io_in[11] + PIN io_in[12] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 2433.080 2300.000 2433.680 ; + END + END io_in[12] + PIN io_in[13] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 2633.000 2300.000 2633.600 ; + END + END io_in[13] + PIN io_in[14] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 2832.920 2300.000 2833.520 ; + END + END io_in[14] + PIN io_in[15] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2256.850 2996.000 2257.130 3000.000 ; + END + END io_in[15] + PIN io_in[16] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2001.550 2996.000 2001.830 3000.000 ; + END + END io_in[16] + PIN io_in[17] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1745.790 2996.000 1746.070 3000.000 ; + END + END io_in[17] + PIN io_in[18] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1490.490 2996.000 1490.770 3000.000 ; + END + END io_in[18] + PIN io_in[19] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1234.730 2996.000 1235.010 3000.000 ; + END + END io_in[19] + PIN io_in[1] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 233.280 2300.000 233.880 ; + END + END io_in[1] + PIN io_in[20] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 979.430 2996.000 979.710 3000.000 ; + END + END io_in[20] + PIN io_in[21] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 723.670 2996.000 723.950 3000.000 ; + END + END io_in[21] + PIN io_in[22] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 467.910 2996.000 468.190 3000.000 ; + END + END io_in[22] + PIN io_in[23] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 212.610 2996.000 212.890 3000.000 ; + END + END io_in[23] + PIN io_in[24] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 2963.480 4.000 2964.080 ; + END + END io_in[24] + PIN io_in[25] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 2749.280 4.000 2749.880 ; + END + END io_in[25] + PIN io_in[26] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 2535.080 4.000 2535.680 ; + END + END io_in[26] + PIN io_in[27] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 2320.880 4.000 2321.480 ; + END + END io_in[27] + PIN io_in[28] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 2106.680 4.000 2107.280 ; + END + END io_in[28] + PIN io_in[29] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 1892.480 4.000 1893.080 ; + END + END io_in[29] + PIN io_in[2] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 433.200 2300.000 433.800 ; + END + END io_in[2] + PIN io_in[30] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 1678.280 4.000 1678.880 ; + END + END io_in[30] + PIN io_in[31] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 1463.400 4.000 1464.000 ; + END + END io_in[31] + PIN io_in[32] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 1249.200 4.000 1249.800 ; + END + END io_in[32] + PIN io_in[33] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 1035.000 4.000 1035.600 ; + END + END io_in[33] + PIN io_in[34] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 820.800 4.000 821.400 ; + END + END io_in[34] + PIN io_in[35] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 606.600 4.000 607.200 ; + END + END io_in[35] + PIN io_in[36] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 392.400 4.000 393.000 ; + END + END io_in[36] + PIN io_in[37] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 0.000 178.200 4.000 178.800 ; + END + END io_in[37] + PIN io_in[3] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 633.120 2300.000 633.720 ; + END + END io_in[3] + PIN io_in[4] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 833.040 2300.000 833.640 ; + END + END io_in[4] + PIN io_in[5] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 1032.960 2300.000 1033.560 ; + END + END io_in[5] + PIN io_in[6] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 1232.880 2300.000 1233.480 ; + END + END io_in[6] + PIN io_in[7] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 1432.800 2300.000 1433.400 ; + END + END io_in[7] + PIN io_in[8] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 1633.400 2300.000 1634.000 ; + END + END io_in[8] + PIN io_in[9] + DIRECTION INPUT ; + PORT + LAYER met3 ; + RECT 2296.000 1833.320 2300.000 1833.920 ; + END + END io_in[9] + PIN io_oeb[0] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 166.640 2300.000 167.240 ; + END + END io_oeb[0] + PIN io_oeb[10] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2166.520 2300.000 2167.120 ; + END + END io_oeb[10] + PIN io_oeb[11] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2366.440 2300.000 2367.040 ; + END + END io_oeb[11] + PIN io_oeb[12] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2566.360 2300.000 2566.960 ; + END + END io_oeb[12] + PIN io_oeb[13] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2766.280 2300.000 2766.880 ; + END + END io_oeb[13] + PIN io_oeb[14] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2966.200 2300.000 2966.800 ; + END + END io_oeb[14] + PIN io_oeb[15] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2086.650 2996.000 2086.930 3000.000 ; + END + END io_oeb[15] + PIN io_oeb[16] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1830.890 2996.000 1831.170 3000.000 ; + END + END io_oeb[16] + PIN io_oeb[17] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1575.590 2996.000 1575.870 3000.000 ; + END + END io_oeb[17] + PIN io_oeb[18] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1319.830 2996.000 1320.110 3000.000 ; + END + END io_oeb[18] + PIN io_oeb[19] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1064.530 2996.000 1064.810 3000.000 ; + END + END io_oeb[19] + PIN io_oeb[1] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 366.560 2300.000 367.160 ; + END + END io_oeb[1] + PIN io_oeb[20] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 808.770 2996.000 809.050 3000.000 ; + END + END io_oeb[20] + PIN io_oeb[21] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 553.470 2996.000 553.750 3000.000 ; + END + END io_oeb[21] + PIN io_oeb[22] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 297.710 2996.000 297.990 3000.000 ; + END + END io_oeb[22] + PIN io_oeb[23] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 42.410 2996.000 42.690 3000.000 ; + END + END io_oeb[23] + PIN io_oeb[24] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2820.680 4.000 2821.280 ; + END + END io_oeb[24] + PIN io_oeb[25] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2606.480 4.000 2607.080 ; + END + END io_oeb[25] + PIN io_oeb[26] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2392.280 4.000 2392.880 ; + END + END io_oeb[26] + PIN io_oeb[27] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2178.080 4.000 2178.680 ; + END + END io_oeb[27] + PIN io_oeb[28] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1963.880 4.000 1964.480 ; + END + END io_oeb[28] + PIN io_oeb[29] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1749.680 4.000 1750.280 ; + END + END io_oeb[29] + PIN io_oeb[2] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 566.480 2300.000 567.080 ; + END + END io_oeb[2] + PIN io_oeb[30] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1535.480 4.000 1536.080 ; + END + END io_oeb[30] + PIN io_oeb[31] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1320.600 4.000 1321.200 ; + END + END io_oeb[31] + PIN io_oeb[32] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1106.400 4.000 1107.000 ; + END + END io_oeb[32] + PIN io_oeb[33] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 892.200 4.000 892.800 ; + END + END io_oeb[33] + PIN io_oeb[34] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 678.000 4.000 678.600 ; + END + END io_oeb[34] + PIN io_oeb[35] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 463.800 4.000 464.400 ; + END + END io_oeb[35] + PIN io_oeb[36] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 249.600 4.000 250.200 ; + END + END io_oeb[36] + PIN io_oeb[37] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 35.400 4.000 36.000 ; + END + END io_oeb[37] + PIN io_oeb[3] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 766.400 2300.000 767.000 ; + END + END io_oeb[3] + PIN io_oeb[4] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 966.320 2300.000 966.920 ; + END + END io_oeb[4] + PIN io_oeb[5] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1166.240 2300.000 1166.840 ; + END + END io_oeb[5] + PIN io_oeb[6] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1366.160 2300.000 1366.760 ; + END + END io_oeb[6] + PIN io_oeb[7] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1566.760 2300.000 1567.360 ; + END + END io_oeb[7] + PIN io_oeb[8] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1766.680 2300.000 1767.280 ; + END + END io_oeb[8] + PIN io_oeb[9] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1966.600 2300.000 1967.200 ; + END + END io_oeb[9] + PIN io_out[0] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 100.000 2300.000 100.600 ; + END + END io_out[0] + PIN io_out[10] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2099.880 2300.000 2100.480 ; + END + END io_out[10] + PIN io_out[11] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2299.800 2300.000 2300.400 ; + END + END io_out[11] + PIN io_out[12] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2499.720 2300.000 2500.320 ; + END + END io_out[12] + PIN io_out[13] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2699.640 2300.000 2700.240 ; + END + END io_out[13] + PIN io_out[14] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 2899.560 2300.000 2900.160 ; + END + END io_out[14] + PIN io_out[15] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2171.750 2996.000 2172.030 3000.000 ; + END + END io_out[15] + PIN io_out[16] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1916.450 2996.000 1916.730 3000.000 ; + END + END io_out[16] + PIN io_out[17] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1660.690 2996.000 1660.970 3000.000 ; + END + END io_out[17] + PIN io_out[18] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1404.930 2996.000 1405.210 3000.000 ; + END + END io_out[18] + PIN io_out[19] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1149.630 2996.000 1149.910 3000.000 ; + END + END io_out[19] + PIN io_out[1] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 299.920 2300.000 300.520 ; + END + END io_out[1] + PIN io_out[20] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 893.870 2996.000 894.150 3000.000 ; + END + END io_out[20] + PIN io_out[21] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 638.570 2996.000 638.850 3000.000 ; + END + END io_out[21] + PIN io_out[22] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 382.810 2996.000 383.090 3000.000 ; + END + END io_out[22] + PIN io_out[23] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 127.510 2996.000 127.790 3000.000 ; + END + END io_out[23] + PIN io_out[24] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2892.080 4.000 2892.680 ; + END + END io_out[24] + PIN io_out[25] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2677.880 4.000 2678.480 ; + END + END io_out[25] + PIN io_out[26] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2463.680 4.000 2464.280 ; + END + END io_out[26] + PIN io_out[27] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2249.480 4.000 2250.080 ; + END + END io_out[27] + PIN io_out[28] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 2035.280 4.000 2035.880 ; + END + END io_out[28] + PIN io_out[29] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1821.080 4.000 1821.680 ; + END + END io_out[29] + PIN io_out[2] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 499.840 2300.000 500.440 ; + END + END io_out[2] + PIN io_out[30] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1606.880 4.000 1607.480 ; + END + END io_out[30] + PIN io_out[31] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1392.000 4.000 1392.600 ; + END + END io_out[31] + PIN io_out[32] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 1177.800 4.000 1178.400 ; + END + END io_out[32] + PIN io_out[33] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 963.600 4.000 964.200 ; + END + END io_out[33] + PIN io_out[34] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 749.400 4.000 750.000 ; + END + END io_out[34] + PIN io_out[35] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 535.200 4.000 535.800 ; + END + END io_out[35] + PIN io_out[36] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 321.000 4.000 321.600 ; + END + END io_out[36] + PIN io_out[37] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 0.000 106.800 4.000 107.400 ; + END + END io_out[37] + PIN io_out[3] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 699.760 2300.000 700.360 ; + END + END io_out[3] + PIN io_out[4] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 899.680 2300.000 900.280 ; + END + END io_out[4] + PIN io_out[5] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1099.600 2300.000 1100.200 ; + END + END io_out[5] + PIN io_out[6] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1299.520 2300.000 1300.120 ; + END + END io_out[6] + PIN io_out[7] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1499.440 2300.000 1500.040 ; + END + END io_out[7] + PIN io_out[8] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1700.040 2300.000 1700.640 ; + END + END io_out[8] + PIN io_out[9] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met3 ; + RECT 2296.000 1899.960 2300.000 1900.560 ; + END + END io_out[9] + PIN la_data_in[0] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 14.350 0.000 14.630 4.000 ; + END + END la_data_in[0] + PIN la_data_in[100] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1801.910 0.000 1802.190 4.000 ; + END + END la_data_in[100] + PIN la_data_in[101] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1819.850 0.000 1820.130 4.000 ; + END + END la_data_in[101] + PIN la_data_in[102] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1837.790 0.000 1838.070 4.000 ; + END + END la_data_in[102] + PIN la_data_in[103] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1855.730 0.000 1856.010 4.000 ; + END + END la_data_in[103] + PIN la_data_in[104] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1873.670 0.000 1873.950 4.000 ; + END + END la_data_in[104] + PIN la_data_in[105] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1891.610 0.000 1891.890 4.000 ; + END + END la_data_in[105] + PIN la_data_in[106] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1909.550 0.000 1909.830 4.000 ; + END + END la_data_in[106] + PIN la_data_in[107] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1927.030 0.000 1927.310 4.000 ; + END + END la_data_in[107] + PIN la_data_in[108] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1944.970 0.000 1945.250 4.000 ; + END + END la_data_in[108] + PIN la_data_in[109] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1962.910 0.000 1963.190 4.000 ; + END + END la_data_in[109] + PIN la_data_in[10] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 193.290 0.000 193.570 4.000 ; + END + END la_data_in[10] + PIN la_data_in[110] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1980.850 0.000 1981.130 4.000 ; + END + END la_data_in[110] + PIN la_data_in[111] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1998.790 0.000 1999.070 4.000 ; + END + END la_data_in[111] + PIN la_data_in[112] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2016.730 0.000 2017.010 4.000 ; + END + END la_data_in[112] + PIN la_data_in[113] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2034.670 0.000 2034.950 4.000 ; + END + END la_data_in[113] + PIN la_data_in[114] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2052.150 0.000 2052.430 4.000 ; + END + END la_data_in[114] + PIN la_data_in[115] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2070.090 0.000 2070.370 4.000 ; + END + END la_data_in[115] + PIN la_data_in[116] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2088.030 0.000 2088.310 4.000 ; + END + END la_data_in[116] + PIN la_data_in[117] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2105.970 0.000 2106.250 4.000 ; + END + END la_data_in[117] + PIN la_data_in[118] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2123.910 0.000 2124.190 4.000 ; + END + END la_data_in[118] + PIN la_data_in[119] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2141.850 0.000 2142.130 4.000 ; + END + END la_data_in[119] + PIN la_data_in[11] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 211.230 0.000 211.510 4.000 ; + END + END la_data_in[11] + PIN la_data_in[120] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2159.790 0.000 2160.070 4.000 ; + END + END la_data_in[120] + PIN la_data_in[121] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2177.270 0.000 2177.550 4.000 ; + END + END la_data_in[121] + PIN la_data_in[122] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2195.210 0.000 2195.490 4.000 ; + END + END la_data_in[122] + PIN la_data_in[123] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2213.150 0.000 2213.430 4.000 ; + END + END la_data_in[123] + PIN la_data_in[124] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2231.090 0.000 2231.370 4.000 ; + END + END la_data_in[124] + PIN la_data_in[125] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2249.030 0.000 2249.310 4.000 ; + END + END la_data_in[125] + PIN la_data_in[126] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2266.970 0.000 2267.250 4.000 ; + END + END la_data_in[126] + PIN la_data_in[127] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2284.910 0.000 2285.190 4.000 ; + END + END la_data_in[127] + PIN la_data_in[12] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 229.170 0.000 229.450 4.000 ; + END + END la_data_in[12] + PIN la_data_in[13] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 247.110 0.000 247.390 4.000 ; + END + END la_data_in[13] + PIN la_data_in[14] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 264.590 0.000 264.870 4.000 ; + END + END la_data_in[14] + PIN la_data_in[15] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 282.530 0.000 282.810 4.000 ; + END + END la_data_in[15] + PIN la_data_in[16] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 300.470 0.000 300.750 4.000 ; + END + END la_data_in[16] + PIN la_data_in[17] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 318.410 0.000 318.690 4.000 ; + END + END la_data_in[17] + PIN la_data_in[18] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 336.350 0.000 336.630 4.000 ; + END + END la_data_in[18] + PIN la_data_in[19] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 354.290 0.000 354.570 4.000 ; + END + END la_data_in[19] + PIN la_data_in[1] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 32.290 0.000 32.570 4.000 ; + END + END la_data_in[1] + PIN la_data_in[20] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 372.230 0.000 372.510 4.000 ; + END + END la_data_in[20] + PIN la_data_in[21] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 389.710 0.000 389.990 4.000 ; + END + END la_data_in[21] + PIN la_data_in[22] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 407.650 0.000 407.930 4.000 ; + END + END la_data_in[22] + PIN la_data_in[23] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 425.590 0.000 425.870 4.000 ; + END + END la_data_in[23] + PIN la_data_in[24] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 443.530 0.000 443.810 4.000 ; + END + END la_data_in[24] + PIN la_data_in[25] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 461.470 0.000 461.750 4.000 ; + END + END la_data_in[25] + PIN la_data_in[26] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 479.410 0.000 479.690 4.000 ; + END + END la_data_in[26] + PIN la_data_in[27] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 497.350 0.000 497.630 4.000 ; + END + END la_data_in[27] + PIN la_data_in[28] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 514.830 0.000 515.110 4.000 ; + END + END la_data_in[28] + PIN la_data_in[29] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 532.770 0.000 533.050 4.000 ; + END + END la_data_in[29] + PIN la_data_in[2] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 50.230 0.000 50.510 4.000 ; + END + END la_data_in[2] + PIN la_data_in[30] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 550.710 0.000 550.990 4.000 ; + END + END la_data_in[30] + PIN la_data_in[31] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 568.650 0.000 568.930 4.000 ; + END + END la_data_in[31] + PIN la_data_in[32] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 586.590 0.000 586.870 4.000 ; + END + END la_data_in[32] + PIN la_data_in[33] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 604.530 0.000 604.810 4.000 ; + END + END la_data_in[33] + PIN la_data_in[34] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 622.470 0.000 622.750 4.000 ; + END + END la_data_in[34] + PIN la_data_in[35] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 640.410 0.000 640.690 4.000 ; + END + END la_data_in[35] + PIN la_data_in[36] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 657.890 0.000 658.170 4.000 ; + END + END la_data_in[36] + PIN la_data_in[37] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 675.830 0.000 676.110 4.000 ; + END + END la_data_in[37] + PIN la_data_in[38] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 693.770 0.000 694.050 4.000 ; + END + END la_data_in[38] + PIN la_data_in[39] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 711.710 0.000 711.990 4.000 ; + END + END la_data_in[39] + PIN la_data_in[3] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 68.170 0.000 68.450 4.000 ; + END + END la_data_in[3] + PIN la_data_in[40] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 729.650 0.000 729.930 4.000 ; + END + END la_data_in[40] + PIN la_data_in[41] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 747.590 0.000 747.870 4.000 ; + END + END la_data_in[41] + PIN la_data_in[42] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 765.530 0.000 765.810 4.000 ; + END + END la_data_in[42] + PIN la_data_in[43] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 783.010 0.000 783.290 4.000 ; + END + END la_data_in[43] + PIN la_data_in[44] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 800.950 0.000 801.230 4.000 ; + END + END la_data_in[44] + PIN la_data_in[45] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 818.890 0.000 819.170 4.000 ; + END + END la_data_in[45] + PIN la_data_in[46] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 836.830 0.000 837.110 4.000 ; + END + END la_data_in[46] + PIN la_data_in[47] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 854.770 0.000 855.050 4.000 ; + END + END la_data_in[47] + PIN la_data_in[48] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 872.710 0.000 872.990 4.000 ; + END + END la_data_in[48] + PIN la_data_in[49] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 890.650 0.000 890.930 4.000 ; + END + END la_data_in[49] + PIN la_data_in[4] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 86.110 0.000 86.390 4.000 ; + END + END la_data_in[4] + PIN la_data_in[50] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 908.130 0.000 908.410 4.000 ; + END + END la_data_in[50] + PIN la_data_in[51] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 926.070 0.000 926.350 4.000 ; + END + END la_data_in[51] + PIN la_data_in[52] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 944.010 0.000 944.290 4.000 ; + END + END la_data_in[52] + PIN la_data_in[53] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 961.950 0.000 962.230 4.000 ; + END + END la_data_in[53] + PIN la_data_in[54] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 979.890 0.000 980.170 4.000 ; + END + END la_data_in[54] + PIN la_data_in[55] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 997.830 0.000 998.110 4.000 ; + END + END la_data_in[55] + PIN la_data_in[56] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1015.770 0.000 1016.050 4.000 ; + END + END la_data_in[56] + PIN la_data_in[57] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1033.250 0.000 1033.530 4.000 ; + END + END la_data_in[57] + PIN la_data_in[58] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1051.190 0.000 1051.470 4.000 ; + END + END la_data_in[58] + PIN la_data_in[59] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1069.130 0.000 1069.410 4.000 ; + END + END la_data_in[59] + PIN la_data_in[5] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 104.050 0.000 104.330 4.000 ; + END + END la_data_in[5] + PIN la_data_in[60] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1087.070 0.000 1087.350 4.000 ; + END + END la_data_in[60] + PIN la_data_in[61] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1105.010 0.000 1105.290 4.000 ; + END + END la_data_in[61] + PIN la_data_in[62] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1122.950 0.000 1123.230 4.000 ; + END + END la_data_in[62] + PIN la_data_in[63] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1140.890 0.000 1141.170 4.000 ; + END + END la_data_in[63] + PIN la_data_in[64] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1158.370 0.000 1158.650 4.000 ; + END + END la_data_in[64] + PIN la_data_in[65] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1176.310 0.000 1176.590 4.000 ; + END + END la_data_in[65] + PIN la_data_in[66] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1194.250 0.000 1194.530 4.000 ; + END + END la_data_in[66] + PIN la_data_in[67] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1212.190 0.000 1212.470 4.000 ; + END + END la_data_in[67] + PIN la_data_in[68] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1230.130 0.000 1230.410 4.000 ; + END + END la_data_in[68] + PIN la_data_in[69] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1248.070 0.000 1248.350 4.000 ; + END + END la_data_in[69] + PIN la_data_in[6] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 121.990 0.000 122.270 4.000 ; + END + END la_data_in[6] + PIN la_data_in[70] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1266.010 0.000 1266.290 4.000 ; + END + END la_data_in[70] + PIN la_data_in[71] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1283.490 0.000 1283.770 4.000 ; + END + END la_data_in[71] + PIN la_data_in[72] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1301.430 0.000 1301.710 4.000 ; + END + END la_data_in[72] + PIN la_data_in[73] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1319.370 0.000 1319.650 4.000 ; + END + END la_data_in[73] + PIN la_data_in[74] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1337.310 0.000 1337.590 4.000 ; + END + END la_data_in[74] + PIN la_data_in[75] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1355.250 0.000 1355.530 4.000 ; + END + END la_data_in[75] + PIN la_data_in[76] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1373.190 0.000 1373.470 4.000 ; + END + END la_data_in[76] + PIN la_data_in[77] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1391.130 0.000 1391.410 4.000 ; + END + END la_data_in[77] + PIN la_data_in[78] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1408.610 0.000 1408.890 4.000 ; + END + END la_data_in[78] + PIN la_data_in[79] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1426.550 0.000 1426.830 4.000 ; + END + END la_data_in[79] + PIN la_data_in[7] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 139.470 0.000 139.750 4.000 ; + END + END la_data_in[7] + PIN la_data_in[80] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1444.490 0.000 1444.770 4.000 ; + END + END la_data_in[80] + PIN la_data_in[81] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1462.430 0.000 1462.710 4.000 ; + END + END la_data_in[81] + PIN la_data_in[82] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1480.370 0.000 1480.650 4.000 ; + END + END la_data_in[82] + PIN la_data_in[83] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1498.310 0.000 1498.590 4.000 ; + END + END la_data_in[83] + PIN la_data_in[84] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1516.250 0.000 1516.530 4.000 ; + END + END la_data_in[84] + PIN la_data_in[85] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1534.190 0.000 1534.470 4.000 ; + END + END la_data_in[85] + PIN la_data_in[86] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1551.670 0.000 1551.950 4.000 ; + END + END la_data_in[86] + PIN la_data_in[87] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1569.610 0.000 1569.890 4.000 ; + END + END la_data_in[87] + PIN la_data_in[88] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1587.550 0.000 1587.830 4.000 ; + END + END la_data_in[88] + PIN la_data_in[89] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1605.490 0.000 1605.770 4.000 ; + END + END la_data_in[89] + PIN la_data_in[8] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 157.410 0.000 157.690 4.000 ; + END + END la_data_in[8] + PIN la_data_in[90] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1623.430 0.000 1623.710 4.000 ; + END + END la_data_in[90] + PIN la_data_in[91] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1641.370 0.000 1641.650 4.000 ; + END + END la_data_in[91] + PIN la_data_in[92] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1659.310 0.000 1659.590 4.000 ; + END + END la_data_in[92] + PIN la_data_in[93] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1676.790 0.000 1677.070 4.000 ; + END + END la_data_in[93] + PIN la_data_in[94] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1694.730 0.000 1695.010 4.000 ; + END + END la_data_in[94] + PIN la_data_in[95] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1712.670 0.000 1712.950 4.000 ; + END + END la_data_in[95] + PIN la_data_in[96] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1730.610 0.000 1730.890 4.000 ; + END + END la_data_in[96] + PIN la_data_in[97] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1748.550 0.000 1748.830 4.000 ; + END + END la_data_in[97] + PIN la_data_in[98] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1766.490 0.000 1766.770 4.000 ; + END + END la_data_in[98] + PIN la_data_in[99] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1784.430 0.000 1784.710 4.000 ; + END + END la_data_in[99] + PIN la_data_in[9] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 175.350 0.000 175.630 4.000 ; + END + END la_data_in[9] + PIN la_data_out[0] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 20.330 0.000 20.610 4.000 ; + END + END la_data_out[0] + PIN la_data_out[100] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1807.890 0.000 1808.170 4.000 ; + END + END la_data_out[100] + PIN la_data_out[101] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1825.830 0.000 1826.110 4.000 ; + END + END la_data_out[101] + PIN la_data_out[102] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1843.770 0.000 1844.050 4.000 ; + END + END la_data_out[102] + PIN la_data_out[103] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1861.710 0.000 1861.990 4.000 ; + END + END la_data_out[103] + PIN la_data_out[104] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1879.650 0.000 1879.930 4.000 ; + END + END la_data_out[104] + PIN la_data_out[105] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1897.590 0.000 1897.870 4.000 ; + END + END la_data_out[105] + PIN la_data_out[106] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1915.530 0.000 1915.810 4.000 ; + END + END la_data_out[106] + PIN la_data_out[107] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1933.010 0.000 1933.290 4.000 ; + END + END la_data_out[107] + PIN la_data_out[108] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1950.950 0.000 1951.230 4.000 ; + END + END la_data_out[108] + PIN la_data_out[109] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1968.890 0.000 1969.170 4.000 ; + END + END la_data_out[109] + PIN la_data_out[10] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 199.270 0.000 199.550 4.000 ; + END + END la_data_out[10] + PIN la_data_out[110] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1986.830 0.000 1987.110 4.000 ; + END + END la_data_out[110] + PIN la_data_out[111] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2004.770 0.000 2005.050 4.000 ; + END + END la_data_out[111] + PIN la_data_out[112] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2022.710 0.000 2022.990 4.000 ; + END + END la_data_out[112] + PIN la_data_out[113] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2040.650 0.000 2040.930 4.000 ; + END + END la_data_out[113] + PIN la_data_out[114] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2058.130 0.000 2058.410 4.000 ; + END + END la_data_out[114] + PIN la_data_out[115] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2076.070 0.000 2076.350 4.000 ; + END + END la_data_out[115] + PIN la_data_out[116] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2094.010 0.000 2094.290 4.000 ; + END + END la_data_out[116] + PIN la_data_out[117] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2111.950 0.000 2112.230 4.000 ; + END + END la_data_out[117] + PIN la_data_out[118] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2129.890 0.000 2130.170 4.000 ; + END + END la_data_out[118] + PIN la_data_out[119] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2147.830 0.000 2148.110 4.000 ; + END + END la_data_out[119] + PIN la_data_out[11] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 217.210 0.000 217.490 4.000 ; + END + END la_data_out[11] + PIN la_data_out[120] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2165.770 0.000 2166.050 4.000 ; + END + END la_data_out[120] + PIN la_data_out[121] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2183.250 0.000 2183.530 4.000 ; + END + END la_data_out[121] + PIN la_data_out[122] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2201.190 0.000 2201.470 4.000 ; + END + END la_data_out[122] + PIN la_data_out[123] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2219.130 0.000 2219.410 4.000 ; + END + END la_data_out[123] + PIN la_data_out[124] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2237.070 0.000 2237.350 4.000 ; + END + END la_data_out[124] + PIN la_data_out[125] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2255.010 0.000 2255.290 4.000 ; + END + END la_data_out[125] + PIN la_data_out[126] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2272.950 0.000 2273.230 4.000 ; + END + END la_data_out[126] + PIN la_data_out[127] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 2290.890 0.000 2291.170 4.000 ; + END + END la_data_out[127] + PIN la_data_out[12] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 235.150 0.000 235.430 4.000 ; + END + END la_data_out[12] + PIN la_data_out[13] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 253.090 0.000 253.370 4.000 ; + END + END la_data_out[13] + PIN la_data_out[14] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 270.570 0.000 270.850 4.000 ; + END + END la_data_out[14] + PIN la_data_out[15] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 288.510 0.000 288.790 4.000 ; + END + END la_data_out[15] + PIN la_data_out[16] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 306.450 0.000 306.730 4.000 ; + END + END la_data_out[16] + PIN la_data_out[17] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 324.390 0.000 324.670 4.000 ; + END + END la_data_out[17] + PIN la_data_out[18] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 342.330 0.000 342.610 4.000 ; + END + END la_data_out[18] + PIN la_data_out[19] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 360.270 0.000 360.550 4.000 ; + END + END la_data_out[19] + PIN la_data_out[1] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 38.270 0.000 38.550 4.000 ; + END + END la_data_out[1] + PIN la_data_out[20] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 378.210 0.000 378.490 4.000 ; + END + END la_data_out[20] + PIN la_data_out[21] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 395.690 0.000 395.970 4.000 ; + END + END la_data_out[21] + PIN la_data_out[22] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 413.630 0.000 413.910 4.000 ; + END + END la_data_out[22] + PIN la_data_out[23] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 431.570 0.000 431.850 4.000 ; + END + END la_data_out[23] + PIN la_data_out[24] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 449.510 0.000 449.790 4.000 ; + END + END la_data_out[24] + PIN la_data_out[25] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 467.450 0.000 467.730 4.000 ; + END + END la_data_out[25] + PIN la_data_out[26] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 485.390 0.000 485.670 4.000 ; + END + END la_data_out[26] + PIN la_data_out[27] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 503.330 0.000 503.610 4.000 ; + END + END la_data_out[27] + PIN la_data_out[28] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 520.810 0.000 521.090 4.000 ; + END + END la_data_out[28] + PIN la_data_out[29] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 538.750 0.000 539.030 4.000 ; + END + END la_data_out[29] + PIN la_data_out[2] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 56.210 0.000 56.490 4.000 ; + END + END la_data_out[2] + PIN la_data_out[30] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 556.690 0.000 556.970 4.000 ; + END + END la_data_out[30] + PIN la_data_out[31] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 574.630 0.000 574.910 4.000 ; + END + END la_data_out[31] + PIN la_data_out[32] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 592.570 0.000 592.850 4.000 ; + END + END la_data_out[32] + PIN la_data_out[33] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 610.510 0.000 610.790 4.000 ; + END + END la_data_out[33] + PIN la_data_out[34] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 628.450 0.000 628.730 4.000 ; + END + END la_data_out[34] + PIN la_data_out[35] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 645.930 0.000 646.210 4.000 ; + END + END la_data_out[35] + PIN la_data_out[36] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 663.870 0.000 664.150 4.000 ; + END + END la_data_out[36] + PIN la_data_out[37] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 681.810 0.000 682.090 4.000 ; + END + END la_data_out[37] + PIN la_data_out[38] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 699.750 0.000 700.030 4.000 ; + END + END la_data_out[38] + PIN la_data_out[39] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 717.690 0.000 717.970 4.000 ; + END + END la_data_out[39] + PIN la_data_out[3] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 74.150 0.000 74.430 4.000 ; + END + END la_data_out[3] + PIN la_data_out[40] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 735.630 0.000 735.910 4.000 ; + END + END la_data_out[40] + PIN la_data_out[41] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 753.570 0.000 753.850 4.000 ; + END + END la_data_out[41] + PIN la_data_out[42] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 771.050 0.000 771.330 4.000 ; + END + END la_data_out[42] + PIN la_data_out[43] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 788.990 0.000 789.270 4.000 ; + END + END la_data_out[43] + PIN la_data_out[44] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 806.930 0.000 807.210 4.000 ; + END + END la_data_out[44] + PIN la_data_out[45] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 824.870 0.000 825.150 4.000 ; + END + END la_data_out[45] + PIN la_data_out[46] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 842.810 0.000 843.090 4.000 ; + END + END la_data_out[46] + PIN la_data_out[47] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 860.750 0.000 861.030 4.000 ; + END + END la_data_out[47] + PIN la_data_out[48] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 878.690 0.000 878.970 4.000 ; + END + END la_data_out[48] + PIN la_data_out[49] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 896.630 0.000 896.910 4.000 ; + END + END la_data_out[49] + PIN la_data_out[4] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 92.090 0.000 92.370 4.000 ; + END + END la_data_out[4] + PIN la_data_out[50] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 914.110 0.000 914.390 4.000 ; + END + END la_data_out[50] + PIN la_data_out[51] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 932.050 0.000 932.330 4.000 ; + END + END la_data_out[51] + PIN la_data_out[52] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 949.990 0.000 950.270 4.000 ; + END + END la_data_out[52] + PIN la_data_out[53] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 967.930 0.000 968.210 4.000 ; + END + END la_data_out[53] + PIN la_data_out[54] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 985.870 0.000 986.150 4.000 ; + END + END la_data_out[54] + PIN la_data_out[55] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1003.810 0.000 1004.090 4.000 ; + END + END la_data_out[55] + PIN la_data_out[56] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1021.750 0.000 1022.030 4.000 ; + END + END la_data_out[56] + PIN la_data_out[57] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1039.230 0.000 1039.510 4.000 ; + END + END la_data_out[57] + PIN la_data_out[58] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1057.170 0.000 1057.450 4.000 ; + END + END la_data_out[58] + PIN la_data_out[59] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1075.110 0.000 1075.390 4.000 ; + END + END la_data_out[59] + PIN la_data_out[5] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 110.030 0.000 110.310 4.000 ; + END + END la_data_out[5] + PIN la_data_out[60] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1093.050 0.000 1093.330 4.000 ; + END + END la_data_out[60] + PIN la_data_out[61] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1110.990 0.000 1111.270 4.000 ; + END + END la_data_out[61] + PIN la_data_out[62] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1128.930 0.000 1129.210 4.000 ; + END + END la_data_out[62] + PIN la_data_out[63] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1146.870 0.000 1147.150 4.000 ; + END + END la_data_out[63] + PIN la_data_out[64] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1164.350 0.000 1164.630 4.000 ; + END + END la_data_out[64] + PIN la_data_out[65] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1182.290 0.000 1182.570 4.000 ; + END + END la_data_out[65] + PIN la_data_out[66] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1200.230 0.000 1200.510 4.000 ; + END + END la_data_out[66] + PIN la_data_out[67] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1218.170 0.000 1218.450 4.000 ; + END + END la_data_out[67] + PIN la_data_out[68] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1236.110 0.000 1236.390 4.000 ; + END + END la_data_out[68] + PIN la_data_out[69] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1254.050 0.000 1254.330 4.000 ; + END + END la_data_out[69] + PIN la_data_out[6] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 127.970 0.000 128.250 4.000 ; + END + END la_data_out[6] + PIN la_data_out[70] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1271.990 0.000 1272.270 4.000 ; + END + END la_data_out[70] + PIN la_data_out[71] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1289.470 0.000 1289.750 4.000 ; + END + END la_data_out[71] + PIN la_data_out[72] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1307.410 0.000 1307.690 4.000 ; + END + END la_data_out[72] + PIN la_data_out[73] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1325.350 0.000 1325.630 4.000 ; + END + END la_data_out[73] + PIN la_data_out[74] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1343.290 0.000 1343.570 4.000 ; + END + END la_data_out[74] + PIN la_data_out[75] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1361.230 0.000 1361.510 4.000 ; + END + END la_data_out[75] + PIN la_data_out[76] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1379.170 0.000 1379.450 4.000 ; + END + END la_data_out[76] + PIN la_data_out[77] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1397.110 0.000 1397.390 4.000 ; + END + END la_data_out[77] + PIN la_data_out[78] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1414.590 0.000 1414.870 4.000 ; + END + END la_data_out[78] + PIN la_data_out[79] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1432.530 0.000 1432.810 4.000 ; + END + END la_data_out[79] + PIN la_data_out[7] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 145.450 0.000 145.730 4.000 ; + END + END la_data_out[7] + PIN la_data_out[80] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1450.470 0.000 1450.750 4.000 ; + END + END la_data_out[80] + PIN la_data_out[81] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1468.410 0.000 1468.690 4.000 ; + END + END la_data_out[81] + PIN la_data_out[82] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1486.350 0.000 1486.630 4.000 ; + END + END la_data_out[82] + PIN la_data_out[83] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1504.290 0.000 1504.570 4.000 ; + END + END la_data_out[83] + PIN la_data_out[84] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1522.230 0.000 1522.510 4.000 ; + END + END la_data_out[84] + PIN la_data_out[85] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1539.710 0.000 1539.990 4.000 ; + END + END la_data_out[85] + PIN la_data_out[86] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1557.650 0.000 1557.930 4.000 ; + END + END la_data_out[86] + PIN la_data_out[87] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1575.590 0.000 1575.870 4.000 ; + END + END la_data_out[87] + PIN la_data_out[88] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1593.530 0.000 1593.810 4.000 ; + END + END la_data_out[88] + PIN la_data_out[89] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1611.470 0.000 1611.750 4.000 ; + END + END la_data_out[89] + PIN la_data_out[8] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 163.390 0.000 163.670 4.000 ; + END + END la_data_out[8] + PIN la_data_out[90] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1629.410 0.000 1629.690 4.000 ; + END + END la_data_out[90] + PIN la_data_out[91] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1647.350 0.000 1647.630 4.000 ; + END + END la_data_out[91] + PIN la_data_out[92] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1664.830 0.000 1665.110 4.000 ; + END + END la_data_out[92] + PIN la_data_out[93] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1682.770 0.000 1683.050 4.000 ; + END + END la_data_out[93] + PIN la_data_out[94] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1700.710 0.000 1700.990 4.000 ; + END + END la_data_out[94] + PIN la_data_out[95] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1718.650 0.000 1718.930 4.000 ; + END + END la_data_out[95] + PIN la_data_out[96] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1736.590 0.000 1736.870 4.000 ; + END + END la_data_out[96] + PIN la_data_out[97] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1754.530 0.000 1754.810 4.000 ; + END + END la_data_out[97] + PIN la_data_out[98] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1772.470 0.000 1772.750 4.000 ; + END + END la_data_out[98] + PIN la_data_out[99] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 1790.410 0.000 1790.690 4.000 ; + END + END la_data_out[99] + PIN la_data_out[9] + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER met2 ; + RECT 181.330 0.000 181.610 4.000 ; + END + END la_data_out[9] + PIN la_oen[0] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 26.310 0.000 26.590 4.000 ; + END + END la_oen[0] + PIN la_oen[100] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1813.870 0.000 1814.150 4.000 ; + END + END la_oen[100] + PIN la_oen[101] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1831.810 0.000 1832.090 4.000 ; + END + END la_oen[101] + PIN la_oen[102] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1849.750 0.000 1850.030 4.000 ; + END + END la_oen[102] + PIN la_oen[103] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1867.690 0.000 1867.970 4.000 ; + END + END la_oen[103] + PIN la_oen[104] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1885.630 0.000 1885.910 4.000 ; + END + END la_oen[104] + PIN la_oen[105] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1903.570 0.000 1903.850 4.000 ; + END + END la_oen[105] + PIN la_oen[106] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1921.050 0.000 1921.330 4.000 ; + END + END la_oen[106] + PIN la_oen[107] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1938.990 0.000 1939.270 4.000 ; + END + END la_oen[107] + PIN la_oen[108] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1956.930 0.000 1957.210 4.000 ; + END + END la_oen[108] + PIN la_oen[109] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1974.870 0.000 1975.150 4.000 ; + END + END la_oen[109] + PIN la_oen[10] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 205.250 0.000 205.530 4.000 ; + END + END la_oen[10] + PIN la_oen[110] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1992.810 0.000 1993.090 4.000 ; + END + END la_oen[110] + PIN la_oen[111] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2010.750 0.000 2011.030 4.000 ; + END + END la_oen[111] + PIN la_oen[112] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2028.690 0.000 2028.970 4.000 ; + END + END la_oen[112] + PIN la_oen[113] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2046.630 0.000 2046.910 4.000 ; + END + END la_oen[113] + PIN la_oen[114] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2064.110 0.000 2064.390 4.000 ; + END + END la_oen[114] + PIN la_oen[115] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2082.050 0.000 2082.330 4.000 ; + END + END la_oen[115] + PIN la_oen[116] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2099.990 0.000 2100.270 4.000 ; + END + END la_oen[116] + PIN la_oen[117] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2117.930 0.000 2118.210 4.000 ; + END + END la_oen[117] + PIN la_oen[118] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2135.870 0.000 2136.150 4.000 ; + END + END la_oen[118] + PIN la_oen[119] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2153.810 0.000 2154.090 4.000 ; + END + END la_oen[119] + PIN la_oen[11] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 223.190 0.000 223.470 4.000 ; + END + END la_oen[11] + PIN la_oen[120] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2171.750 0.000 2172.030 4.000 ; + END + END la_oen[120] + PIN la_oen[121] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2189.230 0.000 2189.510 4.000 ; + END + END la_oen[121] + PIN la_oen[122] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2207.170 0.000 2207.450 4.000 ; + END + END la_oen[122] + PIN la_oen[123] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2225.110 0.000 2225.390 4.000 ; + END + END la_oen[123] + PIN la_oen[124] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2243.050 0.000 2243.330 4.000 ; + END + END la_oen[124] + PIN la_oen[125] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2260.990 0.000 2261.270 4.000 ; + END + END la_oen[125] + PIN la_oen[126] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2278.930 0.000 2279.210 4.000 ; + END + END la_oen[126] + PIN la_oen[127] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2296.870 0.000 2297.150 4.000 ; + END + END la_oen[127] + PIN la_oen[12] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 241.130 0.000 241.410 4.000 ; + END + END la_oen[12] + PIN la_oen[13] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 258.610 0.000 258.890 4.000 ; + END + END la_oen[13] + PIN la_oen[14] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 276.550 0.000 276.830 4.000 ; + END + END la_oen[14] + PIN la_oen[15] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 294.490 0.000 294.770 4.000 ; + END + END la_oen[15] + PIN la_oen[16] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 312.430 0.000 312.710 4.000 ; + END + END la_oen[16] + PIN la_oen[17] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 330.370 0.000 330.650 4.000 ; + END + END la_oen[17] + PIN la_oen[18] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 348.310 0.000 348.590 4.000 ; + END + END la_oen[18] + PIN la_oen[19] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 366.250 0.000 366.530 4.000 ; + END + END la_oen[19] + PIN la_oen[1] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 44.250 0.000 44.530 4.000 ; + END + END la_oen[1] + PIN la_oen[20] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 384.190 0.000 384.470 4.000 ; + END + END la_oen[20] + PIN la_oen[21] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 401.670 0.000 401.950 4.000 ; + END + END la_oen[21] + PIN la_oen[22] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 419.610 0.000 419.890 4.000 ; + END + END la_oen[22] + PIN la_oen[23] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 437.550 0.000 437.830 4.000 ; + END + END la_oen[23] + PIN la_oen[24] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 455.490 0.000 455.770 4.000 ; + END + END la_oen[24] + PIN la_oen[25] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 473.430 0.000 473.710 4.000 ; + END + END la_oen[25] + PIN la_oen[26] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 491.370 0.000 491.650 4.000 ; + END + END la_oen[26] + PIN la_oen[27] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 509.310 0.000 509.590 4.000 ; + END + END la_oen[27] + PIN la_oen[28] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 526.790 0.000 527.070 4.000 ; + END + END la_oen[28] + PIN la_oen[29] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 544.730 0.000 545.010 4.000 ; + END + END la_oen[29] + PIN la_oen[2] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 62.190 0.000 62.470 4.000 ; + END + END la_oen[2] + PIN la_oen[30] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 562.670 0.000 562.950 4.000 ; + END + END la_oen[30] + PIN la_oen[31] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 580.610 0.000 580.890 4.000 ; + END + END la_oen[31] + PIN la_oen[32] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 598.550 0.000 598.830 4.000 ; + END + END la_oen[32] + PIN la_oen[33] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 616.490 0.000 616.770 4.000 ; + END + END la_oen[33] + PIN la_oen[34] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 634.430 0.000 634.710 4.000 ; + END + END la_oen[34] + PIN la_oen[35] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 651.910 0.000 652.190 4.000 ; + END + END la_oen[35] + PIN la_oen[36] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 669.850 0.000 670.130 4.000 ; + END + END la_oen[36] + PIN la_oen[37] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 687.790 0.000 688.070 4.000 ; + END + END la_oen[37] + PIN la_oen[38] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 705.730 0.000 706.010 4.000 ; + END + END la_oen[38] + PIN la_oen[39] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 723.670 0.000 723.950 4.000 ; + END + END la_oen[39] + PIN la_oen[3] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 80.130 0.000 80.410 4.000 ; + END + END la_oen[3] + PIN la_oen[40] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 741.610 0.000 741.890 4.000 ; + END + END la_oen[40] + PIN la_oen[41] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 759.550 0.000 759.830 4.000 ; + END + END la_oen[41] + PIN la_oen[42] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 777.030 0.000 777.310 4.000 ; + END + END la_oen[42] + PIN la_oen[43] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 794.970 0.000 795.250 4.000 ; + END + END la_oen[43] + PIN la_oen[44] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 812.910 0.000 813.190 4.000 ; + END + END la_oen[44] + PIN la_oen[45] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 830.850 0.000 831.130 4.000 ; + END + END la_oen[45] + PIN la_oen[46] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 848.790 0.000 849.070 4.000 ; + END + END la_oen[46] + PIN la_oen[47] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 866.730 0.000 867.010 4.000 ; + END + END la_oen[47] + PIN la_oen[48] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 884.670 0.000 884.950 4.000 ; + END + END la_oen[48] + PIN la_oen[49] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 902.150 0.000 902.430 4.000 ; + END + END la_oen[49] + PIN la_oen[4] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 98.070 0.000 98.350 4.000 ; + END + END la_oen[4] + PIN la_oen[50] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 920.090 0.000 920.370 4.000 ; + END + END la_oen[50] + PIN la_oen[51] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 938.030 0.000 938.310 4.000 ; + END + END la_oen[51] + PIN la_oen[52] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 955.970 0.000 956.250 4.000 ; + END + END la_oen[52] + PIN la_oen[53] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 973.910 0.000 974.190 4.000 ; + END + END la_oen[53] + PIN la_oen[54] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 991.850 0.000 992.130 4.000 ; + END + END la_oen[54] + PIN la_oen[55] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1009.790 0.000 1010.070 4.000 ; + END + END la_oen[55] + PIN la_oen[56] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1027.270 0.000 1027.550 4.000 ; + END + END la_oen[56] + PIN la_oen[57] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1045.210 0.000 1045.490 4.000 ; + END + END la_oen[57] + PIN la_oen[58] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1063.150 0.000 1063.430 4.000 ; + END + END la_oen[58] + PIN la_oen[59] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1081.090 0.000 1081.370 4.000 ; + END + END la_oen[59] + PIN la_oen[5] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 116.010 0.000 116.290 4.000 ; + END + END la_oen[5] + PIN la_oen[60] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1099.030 0.000 1099.310 4.000 ; + END + END la_oen[60] + PIN la_oen[61] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1116.970 0.000 1117.250 4.000 ; + END + END la_oen[61] + PIN la_oen[62] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1134.910 0.000 1135.190 4.000 ; + END + END la_oen[62] + PIN la_oen[63] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1152.850 0.000 1153.130 4.000 ; + END + END la_oen[63] + PIN la_oen[64] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1170.330 0.000 1170.610 4.000 ; + END + END la_oen[64] + PIN la_oen[65] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1188.270 0.000 1188.550 4.000 ; + END + END la_oen[65] + PIN la_oen[66] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1206.210 0.000 1206.490 4.000 ; + END + END la_oen[66] + PIN la_oen[67] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1224.150 0.000 1224.430 4.000 ; + END + END la_oen[67] + PIN la_oen[68] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1242.090 0.000 1242.370 4.000 ; + END + END la_oen[68] + PIN la_oen[69] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1260.030 0.000 1260.310 4.000 ; + END + END la_oen[69] + PIN la_oen[6] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 133.490 0.000 133.770 4.000 ; + END + END la_oen[6] + PIN la_oen[70] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1277.970 0.000 1278.250 4.000 ; + END + END la_oen[70] + PIN la_oen[71] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1295.450 0.000 1295.730 4.000 ; + END + END la_oen[71] + PIN la_oen[72] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1313.390 0.000 1313.670 4.000 ; + END + END la_oen[72] + PIN la_oen[73] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1331.330 0.000 1331.610 4.000 ; + END + END la_oen[73] + PIN la_oen[74] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1349.270 0.000 1349.550 4.000 ; + END + END la_oen[74] + PIN la_oen[75] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1367.210 0.000 1367.490 4.000 ; + END + END la_oen[75] + PIN la_oen[76] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1385.150 0.000 1385.430 4.000 ; + END + END la_oen[76] + PIN la_oen[77] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1403.090 0.000 1403.370 4.000 ; + END + END la_oen[77] + PIN la_oen[78] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1420.570 0.000 1420.850 4.000 ; + END + END la_oen[78] + PIN la_oen[79] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1438.510 0.000 1438.790 4.000 ; + END + END la_oen[79] + PIN la_oen[7] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 151.430 0.000 151.710 4.000 ; + END + END la_oen[7] + PIN la_oen[80] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1456.450 0.000 1456.730 4.000 ; + END + END la_oen[80] + PIN la_oen[81] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1474.390 0.000 1474.670 4.000 ; + END + END la_oen[81] + PIN la_oen[82] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1492.330 0.000 1492.610 4.000 ; + END + END la_oen[82] + PIN la_oen[83] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1510.270 0.000 1510.550 4.000 ; + END + END la_oen[83] + PIN la_oen[84] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1528.210 0.000 1528.490 4.000 ; + END + END la_oen[84] + PIN la_oen[85] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1545.690 0.000 1545.970 4.000 ; + END + END la_oen[85] + PIN la_oen[86] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1563.630 0.000 1563.910 4.000 ; + END + END la_oen[86] + PIN la_oen[87] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1581.570 0.000 1581.850 4.000 ; + END + END la_oen[87] + PIN la_oen[88] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1599.510 0.000 1599.790 4.000 ; + END + END la_oen[88] + PIN la_oen[89] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1617.450 0.000 1617.730 4.000 ; + END + END la_oen[89] + PIN la_oen[8] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 169.370 0.000 169.650 4.000 ; + END + END la_oen[8] + PIN la_oen[90] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1635.390 0.000 1635.670 4.000 ; + END + END la_oen[90] + PIN la_oen[91] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1653.330 0.000 1653.610 4.000 ; + END + END la_oen[91] + PIN la_oen[92] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1670.810 0.000 1671.090 4.000 ; + END + END la_oen[92] + PIN la_oen[93] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1688.750 0.000 1689.030 4.000 ; + END + END la_oen[93] + PIN la_oen[94] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1706.690 0.000 1706.970 4.000 ; + END + END la_oen[94] + PIN la_oen[95] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1724.630 0.000 1724.910 4.000 ; + END + END la_oen[95] + PIN la_oen[96] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1742.570 0.000 1742.850 4.000 ; + END + END la_oen[96] + PIN la_oen[97] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1760.510 0.000 1760.790 4.000 ; + END + END la_oen[97] + PIN la_oen[98] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1778.450 0.000 1778.730 4.000 ; + END + END la_oen[98] + PIN la_oen[99] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 1795.930 0.000 1796.210 4.000 ; + END + END la_oen[99] + PIN la_oen[9] + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 187.310 0.000 187.590 4.000 ; + END + END la_oen[9] + PIN wb_clk_i + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 2.850 0.000 3.130 4.000 ; + END + END wb_clk_i + PIN wb_rst_i + DIRECTION INPUT ; + PORT + LAYER met2 ; + RECT 8.370 0.000 8.650 4.000 ; + END + END wb_rst_i + PIN VPWR + DIRECTION INPUT ; + USE POWER ; + PORT + LAYER met4 ; + RECT 21.040 10.640 22.640 2986.800 ; + END + END VPWR + PIN VGND + DIRECTION INPUT ; + USE GROUND ; + PORT + LAYER met4 ; + RECT 97.840 10.640 99.440 2986.800 ; + END + END VGND + OBS + LAYER li1 ; + RECT 5.520 10.795 2294.480 2986.645 ; + LAYER met1 ; + RECT 5.520 8.540 2294.480 2986.800 ; + LAYER met2 ; + RECT 2.850 2995.720 42.130 2996.000 ; + RECT 42.970 2995.720 127.230 2996.000 ; + RECT 128.070 2995.720 212.330 2996.000 ; + RECT 213.170 2995.720 297.430 2996.000 ; + RECT 298.270 2995.720 382.530 2996.000 ; + RECT 383.370 2995.720 467.630 2996.000 ; + RECT 468.470 2995.720 553.190 2996.000 ; + RECT 554.030 2995.720 638.290 2996.000 ; + RECT 639.130 2995.720 723.390 2996.000 ; + RECT 724.230 2995.720 808.490 2996.000 ; + RECT 809.330 2995.720 893.590 2996.000 ; + RECT 894.430 2995.720 979.150 2996.000 ; + RECT 979.990 2995.720 1064.250 2996.000 ; + RECT 1065.090 2995.720 1149.350 2996.000 ; + RECT 1150.190 2995.720 1234.450 2996.000 ; + RECT 1235.290 2995.720 1319.550 2996.000 ; + RECT 1320.390 2995.720 1404.650 2996.000 ; + RECT 1405.490 2995.720 1490.210 2996.000 ; + RECT 1491.050 2995.720 1575.310 2996.000 ; + RECT 1576.150 2995.720 1660.410 2996.000 ; + RECT 1661.250 2995.720 1745.510 2996.000 ; + RECT 1746.350 2995.720 1830.610 2996.000 ; + RECT 1831.450 2995.720 1916.170 2996.000 ; + RECT 1917.010 2995.720 2001.270 2996.000 ; + RECT 2002.110 2995.720 2086.370 2996.000 ; + RECT 2087.210 2995.720 2171.470 2996.000 ; + RECT 2172.310 2995.720 2256.570 2996.000 ; + RECT 2257.410 2995.720 2292.540 2996.000 ; + RECT 2.850 4.280 2292.540 2995.720 ; + RECT 3.410 4.000 8.090 4.280 ; + RECT 8.930 4.000 14.070 4.280 ; + RECT 14.910 4.000 20.050 4.280 ; + RECT 20.890 4.000 26.030 4.280 ; + RECT 26.870 4.000 32.010 4.280 ; + RECT 32.850 4.000 37.990 4.280 ; + RECT 38.830 4.000 43.970 4.280 ; + RECT 44.810 4.000 49.950 4.280 ; + RECT 50.790 4.000 55.930 4.280 ; + RECT 56.770 4.000 61.910 4.280 ; + RECT 62.750 4.000 67.890 4.280 ; + RECT 68.730 4.000 73.870 4.280 ; + RECT 74.710 4.000 79.850 4.280 ; + RECT 80.690 4.000 85.830 4.280 ; + RECT 86.670 4.000 91.810 4.280 ; + RECT 92.650 4.000 97.790 4.280 ; + RECT 98.630 4.000 103.770 4.280 ; + RECT 104.610 4.000 109.750 4.280 ; + RECT 110.590 4.000 115.730 4.280 ; + RECT 116.570 4.000 121.710 4.280 ; + RECT 122.550 4.000 127.690 4.280 ; + RECT 128.530 4.000 133.210 4.280 ; + RECT 134.050 4.000 139.190 4.280 ; + RECT 140.030 4.000 145.170 4.280 ; + RECT 146.010 4.000 151.150 4.280 ; + RECT 151.990 4.000 157.130 4.280 ; + RECT 157.970 4.000 163.110 4.280 ; + RECT 163.950 4.000 169.090 4.280 ; + RECT 169.930 4.000 175.070 4.280 ; + RECT 175.910 4.000 181.050 4.280 ; + RECT 181.890 4.000 187.030 4.280 ; + RECT 187.870 4.000 193.010 4.280 ; + RECT 193.850 4.000 198.990 4.280 ; + RECT 199.830 4.000 204.970 4.280 ; + RECT 205.810 4.000 210.950 4.280 ; + RECT 211.790 4.000 216.930 4.280 ; + RECT 217.770 4.000 222.910 4.280 ; + RECT 223.750 4.000 228.890 4.280 ; + RECT 229.730 4.000 234.870 4.280 ; + RECT 235.710 4.000 240.850 4.280 ; + RECT 241.690 4.000 246.830 4.280 ; + RECT 247.670 4.000 252.810 4.280 ; + RECT 253.650 4.000 258.330 4.280 ; + RECT 259.170 4.000 264.310 4.280 ; + RECT 265.150 4.000 270.290 4.280 ; + RECT 271.130 4.000 276.270 4.280 ; + RECT 277.110 4.000 282.250 4.280 ; + RECT 283.090 4.000 288.230 4.280 ; + RECT 289.070 4.000 294.210 4.280 ; + RECT 295.050 4.000 300.190 4.280 ; + RECT 301.030 4.000 306.170 4.280 ; + RECT 307.010 4.000 312.150 4.280 ; + RECT 312.990 4.000 318.130 4.280 ; + RECT 318.970 4.000 324.110 4.280 ; + RECT 324.950 4.000 330.090 4.280 ; + RECT 330.930 4.000 336.070 4.280 ; + RECT 336.910 4.000 342.050 4.280 ; + RECT 342.890 4.000 348.030 4.280 ; + RECT 348.870 4.000 354.010 4.280 ; + RECT 354.850 4.000 359.990 4.280 ; + RECT 360.830 4.000 365.970 4.280 ; + RECT 366.810 4.000 371.950 4.280 ; + RECT 372.790 4.000 377.930 4.280 ; + RECT 378.770 4.000 383.910 4.280 ; + RECT 384.750 4.000 389.430 4.280 ; + RECT 390.270 4.000 395.410 4.280 ; + RECT 396.250 4.000 401.390 4.280 ; + RECT 402.230 4.000 407.370 4.280 ; + RECT 408.210 4.000 413.350 4.280 ; + RECT 414.190 4.000 419.330 4.280 ; + RECT 420.170 4.000 425.310 4.280 ; + RECT 426.150 4.000 431.290 4.280 ; + RECT 432.130 4.000 437.270 4.280 ; + RECT 438.110 4.000 443.250 4.280 ; + RECT 444.090 4.000 449.230 4.280 ; + RECT 450.070 4.000 455.210 4.280 ; + RECT 456.050 4.000 461.190 4.280 ; + RECT 462.030 4.000 467.170 4.280 ; + RECT 468.010 4.000 473.150 4.280 ; + RECT 473.990 4.000 479.130 4.280 ; + RECT 479.970 4.000 485.110 4.280 ; + RECT 485.950 4.000 491.090 4.280 ; + RECT 491.930 4.000 497.070 4.280 ; + RECT 497.910 4.000 503.050 4.280 ; + RECT 503.890 4.000 509.030 4.280 ; + RECT 509.870 4.000 514.550 4.280 ; + RECT 515.390 4.000 520.530 4.280 ; + RECT 521.370 4.000 526.510 4.280 ; + RECT 527.350 4.000 532.490 4.280 ; + RECT 533.330 4.000 538.470 4.280 ; + RECT 539.310 4.000 544.450 4.280 ; + RECT 545.290 4.000 550.430 4.280 ; + RECT 551.270 4.000 556.410 4.280 ; + RECT 557.250 4.000 562.390 4.280 ; + RECT 563.230 4.000 568.370 4.280 ; + RECT 569.210 4.000 574.350 4.280 ; + RECT 575.190 4.000 580.330 4.280 ; + RECT 581.170 4.000 586.310 4.280 ; + RECT 587.150 4.000 592.290 4.280 ; + RECT 593.130 4.000 598.270 4.280 ; + RECT 599.110 4.000 604.250 4.280 ; + RECT 605.090 4.000 610.230 4.280 ; + RECT 611.070 4.000 616.210 4.280 ; + RECT 617.050 4.000 622.190 4.280 ; + RECT 623.030 4.000 628.170 4.280 ; + RECT 629.010 4.000 634.150 4.280 ; + RECT 634.990 4.000 640.130 4.280 ; + RECT 640.970 4.000 645.650 4.280 ; + RECT 646.490 4.000 651.630 4.280 ; + RECT 652.470 4.000 657.610 4.280 ; + RECT 658.450 4.000 663.590 4.280 ; + RECT 664.430 4.000 669.570 4.280 ; + RECT 670.410 4.000 675.550 4.280 ; + RECT 676.390 4.000 681.530 4.280 ; + RECT 682.370 4.000 687.510 4.280 ; + RECT 688.350 4.000 693.490 4.280 ; + RECT 694.330 4.000 699.470 4.280 ; + RECT 700.310 4.000 705.450 4.280 ; + RECT 706.290 4.000 711.430 4.280 ; + RECT 712.270 4.000 717.410 4.280 ; + RECT 718.250 4.000 723.390 4.280 ; + RECT 724.230 4.000 729.370 4.280 ; + RECT 730.210 4.000 735.350 4.280 ; + RECT 736.190 4.000 741.330 4.280 ; + RECT 742.170 4.000 747.310 4.280 ; + RECT 748.150 4.000 753.290 4.280 ; + RECT 754.130 4.000 759.270 4.280 ; + RECT 760.110 4.000 765.250 4.280 ; + RECT 766.090 4.000 770.770 4.280 ; + RECT 771.610 4.000 776.750 4.280 ; + RECT 777.590 4.000 782.730 4.280 ; + RECT 783.570 4.000 788.710 4.280 ; + RECT 789.550 4.000 794.690 4.280 ; + RECT 795.530 4.000 800.670 4.280 ; + RECT 801.510 4.000 806.650 4.280 ; + RECT 807.490 4.000 812.630 4.280 ; + RECT 813.470 4.000 818.610 4.280 ; + RECT 819.450 4.000 824.590 4.280 ; + RECT 825.430 4.000 830.570 4.280 ; + RECT 831.410 4.000 836.550 4.280 ; + RECT 837.390 4.000 842.530 4.280 ; + RECT 843.370 4.000 848.510 4.280 ; + RECT 849.350 4.000 854.490 4.280 ; + RECT 855.330 4.000 860.470 4.280 ; + RECT 861.310 4.000 866.450 4.280 ; + RECT 867.290 4.000 872.430 4.280 ; + RECT 873.270 4.000 878.410 4.280 ; + RECT 879.250 4.000 884.390 4.280 ; + RECT 885.230 4.000 890.370 4.280 ; + RECT 891.210 4.000 896.350 4.280 ; + RECT 897.190 4.000 901.870 4.280 ; + RECT 902.710 4.000 907.850 4.280 ; + RECT 908.690 4.000 913.830 4.280 ; + RECT 914.670 4.000 919.810 4.280 ; + RECT 920.650 4.000 925.790 4.280 ; + RECT 926.630 4.000 931.770 4.280 ; + RECT 932.610 4.000 937.750 4.280 ; + RECT 938.590 4.000 943.730 4.280 ; + RECT 944.570 4.000 949.710 4.280 ; + RECT 950.550 4.000 955.690 4.280 ; + RECT 956.530 4.000 961.670 4.280 ; + RECT 962.510 4.000 967.650 4.280 ; + RECT 968.490 4.000 973.630 4.280 ; + RECT 974.470 4.000 979.610 4.280 ; + RECT 980.450 4.000 985.590 4.280 ; + RECT 986.430 4.000 991.570 4.280 ; + RECT 992.410 4.000 997.550 4.280 ; + RECT 998.390 4.000 1003.530 4.280 ; + RECT 1004.370 4.000 1009.510 4.280 ; + RECT 1010.350 4.000 1015.490 4.280 ; + RECT 1016.330 4.000 1021.470 4.280 ; + RECT 1022.310 4.000 1026.990 4.280 ; + RECT 1027.830 4.000 1032.970 4.280 ; + RECT 1033.810 4.000 1038.950 4.280 ; + RECT 1039.790 4.000 1044.930 4.280 ; + RECT 1045.770 4.000 1050.910 4.280 ; + RECT 1051.750 4.000 1056.890 4.280 ; + RECT 1057.730 4.000 1062.870 4.280 ; + RECT 1063.710 4.000 1068.850 4.280 ; + RECT 1069.690 4.000 1074.830 4.280 ; + RECT 1075.670 4.000 1080.810 4.280 ; + RECT 1081.650 4.000 1086.790 4.280 ; + RECT 1087.630 4.000 1092.770 4.280 ; + RECT 1093.610 4.000 1098.750 4.280 ; + RECT 1099.590 4.000 1104.730 4.280 ; + RECT 1105.570 4.000 1110.710 4.280 ; + RECT 1111.550 4.000 1116.690 4.280 ; + RECT 1117.530 4.000 1122.670 4.280 ; + RECT 1123.510 4.000 1128.650 4.280 ; + RECT 1129.490 4.000 1134.630 4.280 ; + RECT 1135.470 4.000 1140.610 4.280 ; + RECT 1141.450 4.000 1146.590 4.280 ; + RECT 1147.430 4.000 1152.570 4.280 ; + RECT 1153.410 4.000 1158.090 4.280 ; + RECT 1158.930 4.000 1164.070 4.280 ; + RECT 1164.910 4.000 1170.050 4.280 ; + RECT 1170.890 4.000 1176.030 4.280 ; + RECT 1176.870 4.000 1182.010 4.280 ; + RECT 1182.850 4.000 1187.990 4.280 ; + RECT 1188.830 4.000 1193.970 4.280 ; + RECT 1194.810 4.000 1199.950 4.280 ; + RECT 1200.790 4.000 1205.930 4.280 ; + RECT 1206.770 4.000 1211.910 4.280 ; + RECT 1212.750 4.000 1217.890 4.280 ; + RECT 1218.730 4.000 1223.870 4.280 ; + RECT 1224.710 4.000 1229.850 4.280 ; + RECT 1230.690 4.000 1235.830 4.280 ; + RECT 1236.670 4.000 1241.810 4.280 ; + RECT 1242.650 4.000 1247.790 4.280 ; + RECT 1248.630 4.000 1253.770 4.280 ; + RECT 1254.610 4.000 1259.750 4.280 ; + RECT 1260.590 4.000 1265.730 4.280 ; + RECT 1266.570 4.000 1271.710 4.280 ; + RECT 1272.550 4.000 1277.690 4.280 ; + RECT 1278.530 4.000 1283.210 4.280 ; + RECT 1284.050 4.000 1289.190 4.280 ; + RECT 1290.030 4.000 1295.170 4.280 ; + RECT 1296.010 4.000 1301.150 4.280 ; + RECT 1301.990 4.000 1307.130 4.280 ; + RECT 1307.970 4.000 1313.110 4.280 ; + RECT 1313.950 4.000 1319.090 4.280 ; + RECT 1319.930 4.000 1325.070 4.280 ; + RECT 1325.910 4.000 1331.050 4.280 ; + RECT 1331.890 4.000 1337.030 4.280 ; + RECT 1337.870 4.000 1343.010 4.280 ; + RECT 1343.850 4.000 1348.990 4.280 ; + RECT 1349.830 4.000 1354.970 4.280 ; + RECT 1355.810 4.000 1360.950 4.280 ; + RECT 1361.790 4.000 1366.930 4.280 ; + RECT 1367.770 4.000 1372.910 4.280 ; + RECT 1373.750 4.000 1378.890 4.280 ; + RECT 1379.730 4.000 1384.870 4.280 ; + RECT 1385.710 4.000 1390.850 4.280 ; + RECT 1391.690 4.000 1396.830 4.280 ; + RECT 1397.670 4.000 1402.810 4.280 ; + RECT 1403.650 4.000 1408.330 4.280 ; + RECT 1409.170 4.000 1414.310 4.280 ; + RECT 1415.150 4.000 1420.290 4.280 ; + RECT 1421.130 4.000 1426.270 4.280 ; + RECT 1427.110 4.000 1432.250 4.280 ; + RECT 1433.090 4.000 1438.230 4.280 ; + RECT 1439.070 4.000 1444.210 4.280 ; + RECT 1445.050 4.000 1450.190 4.280 ; + RECT 1451.030 4.000 1456.170 4.280 ; + RECT 1457.010 4.000 1462.150 4.280 ; + RECT 1462.990 4.000 1468.130 4.280 ; + RECT 1468.970 4.000 1474.110 4.280 ; + RECT 1474.950 4.000 1480.090 4.280 ; + RECT 1480.930 4.000 1486.070 4.280 ; + RECT 1486.910 4.000 1492.050 4.280 ; + RECT 1492.890 4.000 1498.030 4.280 ; + RECT 1498.870 4.000 1504.010 4.280 ; + RECT 1504.850 4.000 1509.990 4.280 ; + RECT 1510.830 4.000 1515.970 4.280 ; + RECT 1516.810 4.000 1521.950 4.280 ; + RECT 1522.790 4.000 1527.930 4.280 ; + RECT 1528.770 4.000 1533.910 4.280 ; + RECT 1534.750 4.000 1539.430 4.280 ; + RECT 1540.270 4.000 1545.410 4.280 ; + RECT 1546.250 4.000 1551.390 4.280 ; + RECT 1552.230 4.000 1557.370 4.280 ; + RECT 1558.210 4.000 1563.350 4.280 ; + RECT 1564.190 4.000 1569.330 4.280 ; + RECT 1570.170 4.000 1575.310 4.280 ; + RECT 1576.150 4.000 1581.290 4.280 ; + RECT 1582.130 4.000 1587.270 4.280 ; + RECT 1588.110 4.000 1593.250 4.280 ; + RECT 1594.090 4.000 1599.230 4.280 ; + RECT 1600.070 4.000 1605.210 4.280 ; + RECT 1606.050 4.000 1611.190 4.280 ; + RECT 1612.030 4.000 1617.170 4.280 ; + RECT 1618.010 4.000 1623.150 4.280 ; + RECT 1623.990 4.000 1629.130 4.280 ; + RECT 1629.970 4.000 1635.110 4.280 ; + RECT 1635.950 4.000 1641.090 4.280 ; + RECT 1641.930 4.000 1647.070 4.280 ; + RECT 1647.910 4.000 1653.050 4.280 ; + RECT 1653.890 4.000 1659.030 4.280 ; + RECT 1659.870 4.000 1664.550 4.280 ; + RECT 1665.390 4.000 1670.530 4.280 ; + RECT 1671.370 4.000 1676.510 4.280 ; + RECT 1677.350 4.000 1682.490 4.280 ; + RECT 1683.330 4.000 1688.470 4.280 ; + RECT 1689.310 4.000 1694.450 4.280 ; + RECT 1695.290 4.000 1700.430 4.280 ; + RECT 1701.270 4.000 1706.410 4.280 ; + RECT 1707.250 4.000 1712.390 4.280 ; + RECT 1713.230 4.000 1718.370 4.280 ; + RECT 1719.210 4.000 1724.350 4.280 ; + RECT 1725.190 4.000 1730.330 4.280 ; + RECT 1731.170 4.000 1736.310 4.280 ; + RECT 1737.150 4.000 1742.290 4.280 ; + RECT 1743.130 4.000 1748.270 4.280 ; + RECT 1749.110 4.000 1754.250 4.280 ; + RECT 1755.090 4.000 1760.230 4.280 ; + RECT 1761.070 4.000 1766.210 4.280 ; + RECT 1767.050 4.000 1772.190 4.280 ; + RECT 1773.030 4.000 1778.170 4.280 ; + RECT 1779.010 4.000 1784.150 4.280 ; + RECT 1784.990 4.000 1790.130 4.280 ; + RECT 1790.970 4.000 1795.650 4.280 ; + RECT 1796.490 4.000 1801.630 4.280 ; + RECT 1802.470 4.000 1807.610 4.280 ; + RECT 1808.450 4.000 1813.590 4.280 ; + RECT 1814.430 4.000 1819.570 4.280 ; + RECT 1820.410 4.000 1825.550 4.280 ; + RECT 1826.390 4.000 1831.530 4.280 ; + RECT 1832.370 4.000 1837.510 4.280 ; + RECT 1838.350 4.000 1843.490 4.280 ; + RECT 1844.330 4.000 1849.470 4.280 ; + RECT 1850.310 4.000 1855.450 4.280 ; + RECT 1856.290 4.000 1861.430 4.280 ; + RECT 1862.270 4.000 1867.410 4.280 ; + RECT 1868.250 4.000 1873.390 4.280 ; + RECT 1874.230 4.000 1879.370 4.280 ; + RECT 1880.210 4.000 1885.350 4.280 ; + RECT 1886.190 4.000 1891.330 4.280 ; + RECT 1892.170 4.000 1897.310 4.280 ; + RECT 1898.150 4.000 1903.290 4.280 ; + RECT 1904.130 4.000 1909.270 4.280 ; + RECT 1910.110 4.000 1915.250 4.280 ; + RECT 1916.090 4.000 1920.770 4.280 ; + RECT 1921.610 4.000 1926.750 4.280 ; + RECT 1927.590 4.000 1932.730 4.280 ; + RECT 1933.570 4.000 1938.710 4.280 ; + RECT 1939.550 4.000 1944.690 4.280 ; + RECT 1945.530 4.000 1950.670 4.280 ; + RECT 1951.510 4.000 1956.650 4.280 ; + RECT 1957.490 4.000 1962.630 4.280 ; + RECT 1963.470 4.000 1968.610 4.280 ; + RECT 1969.450 4.000 1974.590 4.280 ; + RECT 1975.430 4.000 1980.570 4.280 ; + RECT 1981.410 4.000 1986.550 4.280 ; + RECT 1987.390 4.000 1992.530 4.280 ; + RECT 1993.370 4.000 1998.510 4.280 ; + RECT 1999.350 4.000 2004.490 4.280 ; + RECT 2005.330 4.000 2010.470 4.280 ; + RECT 2011.310 4.000 2016.450 4.280 ; + RECT 2017.290 4.000 2022.430 4.280 ; + RECT 2023.270 4.000 2028.410 4.280 ; + RECT 2029.250 4.000 2034.390 4.280 ; + RECT 2035.230 4.000 2040.370 4.280 ; + RECT 2041.210 4.000 2046.350 4.280 ; + RECT 2047.190 4.000 2051.870 4.280 ; + RECT 2052.710 4.000 2057.850 4.280 ; + RECT 2058.690 4.000 2063.830 4.280 ; + RECT 2064.670 4.000 2069.810 4.280 ; + RECT 2070.650 4.000 2075.790 4.280 ; + RECT 2076.630 4.000 2081.770 4.280 ; + RECT 2082.610 4.000 2087.750 4.280 ; + RECT 2088.590 4.000 2093.730 4.280 ; + RECT 2094.570 4.000 2099.710 4.280 ; + RECT 2100.550 4.000 2105.690 4.280 ; + RECT 2106.530 4.000 2111.670 4.280 ; + RECT 2112.510 4.000 2117.650 4.280 ; + RECT 2118.490 4.000 2123.630 4.280 ; + RECT 2124.470 4.000 2129.610 4.280 ; + RECT 2130.450 4.000 2135.590 4.280 ; + RECT 2136.430 4.000 2141.570 4.280 ; + RECT 2142.410 4.000 2147.550 4.280 ; + RECT 2148.390 4.000 2153.530 4.280 ; + RECT 2154.370 4.000 2159.510 4.280 ; + RECT 2160.350 4.000 2165.490 4.280 ; + RECT 2166.330 4.000 2171.470 4.280 ; + RECT 2172.310 4.000 2176.990 4.280 ; + RECT 2177.830 4.000 2182.970 4.280 ; + RECT 2183.810 4.000 2188.950 4.280 ; + RECT 2189.790 4.000 2194.930 4.280 ; + RECT 2195.770 4.000 2200.910 4.280 ; + RECT 2201.750 4.000 2206.890 4.280 ; + RECT 2207.730 4.000 2212.870 4.280 ; + RECT 2213.710 4.000 2218.850 4.280 ; + RECT 2219.690 4.000 2224.830 4.280 ; + RECT 2225.670 4.000 2230.810 4.280 ; + RECT 2231.650 4.000 2236.790 4.280 ; + RECT 2237.630 4.000 2242.770 4.280 ; + RECT 2243.610 4.000 2248.750 4.280 ; + RECT 2249.590 4.000 2254.730 4.280 ; + RECT 2255.570 4.000 2260.710 4.280 ; + RECT 2261.550 4.000 2266.690 4.280 ; + RECT 2267.530 4.000 2272.670 4.280 ; + RECT 2273.510 4.000 2278.650 4.280 ; + RECT 2279.490 4.000 2284.630 4.280 ; + RECT 2285.470 4.000 2290.610 4.280 ; + RECT 2291.450 4.000 2292.540 4.280 ; + LAYER met3 ; + RECT 2.825 2967.200 2296.010 2986.725 ; + RECT 2.825 2965.800 2295.600 2967.200 ; + RECT 2.825 2964.480 2296.010 2965.800 ; + RECT 4.400 2963.080 2296.010 2964.480 ; + RECT 2.825 2900.560 2296.010 2963.080 ; + RECT 2.825 2899.160 2295.600 2900.560 ; + RECT 2.825 2893.080 2296.010 2899.160 ; + RECT 4.400 2891.680 2296.010 2893.080 ; + RECT 2.825 2833.920 2296.010 2891.680 ; + RECT 2.825 2832.520 2295.600 2833.920 ; + RECT 2.825 2821.680 2296.010 2832.520 ; + RECT 4.400 2820.280 2296.010 2821.680 ; + RECT 2.825 2767.280 2296.010 2820.280 ; + RECT 2.825 2765.880 2295.600 2767.280 ; + RECT 2.825 2750.280 2296.010 2765.880 ; + RECT 4.400 2748.880 2296.010 2750.280 ; + RECT 2.825 2700.640 2296.010 2748.880 ; + RECT 2.825 2699.240 2295.600 2700.640 ; + RECT 2.825 2678.880 2296.010 2699.240 ; + RECT 4.400 2677.480 2296.010 2678.880 ; + RECT 2.825 2634.000 2296.010 2677.480 ; + RECT 2.825 2632.600 2295.600 2634.000 ; + RECT 2.825 2607.480 2296.010 2632.600 ; + RECT 4.400 2606.080 2296.010 2607.480 ; + RECT 2.825 2567.360 2296.010 2606.080 ; + RECT 2.825 2565.960 2295.600 2567.360 ; + RECT 2.825 2536.080 2296.010 2565.960 ; + RECT 4.400 2534.680 2296.010 2536.080 ; + RECT 2.825 2500.720 2296.010 2534.680 ; + RECT 2.825 2499.320 2295.600 2500.720 ; + RECT 2.825 2464.680 2296.010 2499.320 ; + RECT 4.400 2463.280 2296.010 2464.680 ; + RECT 2.825 2434.080 2296.010 2463.280 ; + RECT 2.825 2432.680 2295.600 2434.080 ; + RECT 2.825 2393.280 2296.010 2432.680 ; + RECT 4.400 2391.880 2296.010 2393.280 ; + RECT 2.825 2367.440 2296.010 2391.880 ; + RECT 2.825 2366.040 2295.600 2367.440 ; + RECT 2.825 2321.880 2296.010 2366.040 ; + RECT 4.400 2320.480 2296.010 2321.880 ; + RECT 2.825 2300.800 2296.010 2320.480 ; + RECT 2.825 2299.400 2295.600 2300.800 ; + RECT 2.825 2250.480 2296.010 2299.400 ; + RECT 4.400 2249.080 2296.010 2250.480 ; + RECT 2.825 2234.160 2296.010 2249.080 ; + RECT 2.825 2232.760 2295.600 2234.160 ; + RECT 2.825 2179.080 2296.010 2232.760 ; + RECT 4.400 2177.680 2296.010 2179.080 ; + RECT 2.825 2167.520 2296.010 2177.680 ; + RECT 2.825 2166.120 2295.600 2167.520 ; + RECT 2.825 2107.680 2296.010 2166.120 ; + RECT 4.400 2106.280 2296.010 2107.680 ; + RECT 2.825 2100.880 2296.010 2106.280 ; + RECT 2.825 2099.480 2295.600 2100.880 ; + RECT 2.825 2036.280 2296.010 2099.480 ; + RECT 4.400 2034.880 2296.010 2036.280 ; + RECT 2.825 2034.240 2296.010 2034.880 ; + RECT 2.825 2032.840 2295.600 2034.240 ; + RECT 2.825 1967.600 2296.010 2032.840 ; + RECT 2.825 1966.200 2295.600 1967.600 ; + RECT 2.825 1964.880 2296.010 1966.200 ; + RECT 4.400 1963.480 2296.010 1964.880 ; + RECT 2.825 1900.960 2296.010 1963.480 ; + RECT 2.825 1899.560 2295.600 1900.960 ; + RECT 2.825 1893.480 2296.010 1899.560 ; + RECT 4.400 1892.080 2296.010 1893.480 ; + RECT 2.825 1834.320 2296.010 1892.080 ; + RECT 2.825 1832.920 2295.600 1834.320 ; + RECT 2.825 1822.080 2296.010 1832.920 ; + RECT 4.400 1820.680 2296.010 1822.080 ; + RECT 2.825 1767.680 2296.010 1820.680 ; + RECT 2.825 1766.280 2295.600 1767.680 ; + RECT 2.825 1750.680 2296.010 1766.280 ; + RECT 4.400 1749.280 2296.010 1750.680 ; + RECT 2.825 1701.040 2296.010 1749.280 ; + RECT 2.825 1699.640 2295.600 1701.040 ; + RECT 2.825 1679.280 2296.010 1699.640 ; + RECT 4.400 1677.880 2296.010 1679.280 ; + RECT 2.825 1634.400 2296.010 1677.880 ; + RECT 2.825 1633.000 2295.600 1634.400 ; + RECT 2.825 1607.880 2296.010 1633.000 ; + RECT 4.400 1606.480 2296.010 1607.880 ; + RECT 2.825 1567.760 2296.010 1606.480 ; + RECT 2.825 1566.360 2295.600 1567.760 ; + RECT 2.825 1536.480 2296.010 1566.360 ; + RECT 4.400 1535.080 2296.010 1536.480 ; + RECT 2.825 1500.440 2296.010 1535.080 ; + RECT 2.825 1499.040 2295.600 1500.440 ; + RECT 2.825 1464.400 2296.010 1499.040 ; + RECT 4.400 1463.000 2296.010 1464.400 ; + RECT 2.825 1433.800 2296.010 1463.000 ; + RECT 2.825 1432.400 2295.600 1433.800 ; + RECT 2.825 1393.000 2296.010 1432.400 ; + RECT 4.400 1391.600 2296.010 1393.000 ; + RECT 2.825 1367.160 2296.010 1391.600 ; + RECT 2.825 1365.760 2295.600 1367.160 ; + RECT 2.825 1321.600 2296.010 1365.760 ; + RECT 4.400 1320.200 2296.010 1321.600 ; + RECT 2.825 1300.520 2296.010 1320.200 ; + RECT 2.825 1299.120 2295.600 1300.520 ; + RECT 2.825 1250.200 2296.010 1299.120 ; + RECT 4.400 1248.800 2296.010 1250.200 ; + RECT 2.825 1233.880 2296.010 1248.800 ; + RECT 2.825 1232.480 2295.600 1233.880 ; + RECT 2.825 1178.800 2296.010 1232.480 ; + RECT 4.400 1177.400 2296.010 1178.800 ; + RECT 2.825 1167.240 2296.010 1177.400 ; + RECT 2.825 1165.840 2295.600 1167.240 ; + RECT 2.825 1107.400 2296.010 1165.840 ; + RECT 4.400 1106.000 2296.010 1107.400 ; + RECT 2.825 1100.600 2296.010 1106.000 ; + RECT 2.825 1099.200 2295.600 1100.600 ; + RECT 2.825 1036.000 2296.010 1099.200 ; + RECT 4.400 1034.600 2296.010 1036.000 ; + RECT 2.825 1033.960 2296.010 1034.600 ; + RECT 2.825 1032.560 2295.600 1033.960 ; + RECT 2.825 967.320 2296.010 1032.560 ; + RECT 2.825 965.920 2295.600 967.320 ; + RECT 2.825 964.600 2296.010 965.920 ; + RECT 4.400 963.200 2296.010 964.600 ; + RECT 2.825 900.680 2296.010 963.200 ; + RECT 2.825 899.280 2295.600 900.680 ; + RECT 2.825 893.200 2296.010 899.280 ; + RECT 4.400 891.800 2296.010 893.200 ; + RECT 2.825 834.040 2296.010 891.800 ; + RECT 2.825 832.640 2295.600 834.040 ; + RECT 2.825 821.800 2296.010 832.640 ; + RECT 4.400 820.400 2296.010 821.800 ; + RECT 2.825 767.400 2296.010 820.400 ; + RECT 2.825 766.000 2295.600 767.400 ; + RECT 2.825 750.400 2296.010 766.000 ; + RECT 4.400 749.000 2296.010 750.400 ; + RECT 2.825 700.760 2296.010 749.000 ; + RECT 2.825 699.360 2295.600 700.760 ; + RECT 2.825 679.000 2296.010 699.360 ; + RECT 4.400 677.600 2296.010 679.000 ; + RECT 2.825 634.120 2296.010 677.600 ; + RECT 2.825 632.720 2295.600 634.120 ; + RECT 2.825 607.600 2296.010 632.720 ; + RECT 4.400 606.200 2296.010 607.600 ; + RECT 2.825 567.480 2296.010 606.200 ; + RECT 2.825 566.080 2295.600 567.480 ; + RECT 2.825 536.200 2296.010 566.080 ; + RECT 4.400 534.800 2296.010 536.200 ; + RECT 2.825 500.840 2296.010 534.800 ; + RECT 2.825 499.440 2295.600 500.840 ; + RECT 2.825 464.800 2296.010 499.440 ; + RECT 4.400 463.400 2296.010 464.800 ; + RECT 2.825 434.200 2296.010 463.400 ; + RECT 2.825 432.800 2295.600 434.200 ; + RECT 2.825 393.400 2296.010 432.800 ; + RECT 4.400 392.000 2296.010 393.400 ; + RECT 2.825 367.560 2296.010 392.000 ; + RECT 2.825 366.160 2295.600 367.560 ; + RECT 2.825 322.000 2296.010 366.160 ; + RECT 4.400 320.600 2296.010 322.000 ; + RECT 2.825 300.920 2296.010 320.600 ; + RECT 2.825 299.520 2295.600 300.920 ; + RECT 2.825 250.600 2296.010 299.520 ; + RECT 4.400 249.200 2296.010 250.600 ; + RECT 2.825 234.280 2296.010 249.200 ; + RECT 2.825 232.880 2295.600 234.280 ; + RECT 2.825 179.200 2296.010 232.880 ; + RECT 4.400 177.800 2296.010 179.200 ; + RECT 2.825 167.640 2296.010 177.800 ; + RECT 2.825 166.240 2295.600 167.640 ; + RECT 2.825 107.800 2296.010 166.240 ; + RECT 4.400 106.400 2296.010 107.800 ; + RECT 2.825 101.000 2296.010 106.400 ; + RECT 2.825 99.600 2295.600 101.000 ; + RECT 2.825 36.400 2296.010 99.600 ; + RECT 4.400 35.000 2296.010 36.400 ; + RECT 2.825 34.360 2296.010 35.000 ; + RECT 2.825 32.960 2295.600 34.360 ; + RECT 2.825 10.715 2296.010 32.960 ; + LAYER met4 ; + RECT 16.855 10.640 20.640 2986.800 ; + RECT 23.040 10.640 97.440 2986.800 ; + RECT 99.840 10.640 2282.225 2986.800 ; + END +END ghazi_top_dffram_csv +END LIBRARY +
diff --git a/lef/user_project_wrapper.lef b/lef/user_project_wrapper.lef index 158d5da..dbfc26f 100644 --- a/lef/user_project_wrapper.lef +++ b/lef/user_project_wrapper.lef
@@ -259,2176 +259,10315 @@ DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2619.310 89.660 2619.630 89.720 ; + RECT 2898.990 89.660 2899.310 89.720 ; + RECT 2619.310 89.520 2899.310 89.660 ; + RECT 2619.310 89.460 2619.630 89.520 ; + RECT 2898.990 89.460 2899.310 89.520 ; + LAYER via ; + RECT 2619.340 89.460 2619.600 89.720 ; + RECT 2899.020 89.460 2899.280 89.720 ; + LAYER met2 ; + RECT 2619.330 293.235 2619.610 293.605 ; + RECT 2619.400 89.750 2619.540 293.235 ; + RECT 2619.340 89.430 2619.600 89.750 ; + RECT 2899.020 89.430 2899.280 89.750 ; + RECT 2899.080 88.245 2899.220 89.430 ; + RECT 2899.010 87.875 2899.290 88.245 ; + LAYER via2 ; + RECT 2619.330 293.280 2619.610 293.560 ; + RECT 2899.010 87.920 2899.290 88.200 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 293.570 2610.000 293.960 ; + RECT 2619.305 293.570 2619.635 293.585 ; + RECT 2606.000 293.360 2619.635 293.570 ; + RECT 2609.580 293.270 2619.635 293.360 ; + RECT 2619.305 293.255 2619.635 293.270 ; + RECT 2898.985 88.210 2899.315 88.225 ; + RECT 2917.600 88.210 2924.800 88.660 ; + RECT 2898.985 87.910 2924.800 88.210 ; + RECT 2898.985 87.895 2899.315 87.910 ; + RECT 2917.600 87.460 2924.800 87.910 ; +======= RECT 2919.700 87.460 2924.800 88.660 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[0] PIN io_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.610 2297.620 2621.930 2297.680 ; + RECT 2901.290 2297.620 2901.610 2297.680 ; + RECT 2621.610 2297.480 2901.610 2297.620 ; + RECT 2621.610 2297.420 2621.930 2297.480 ; + RECT 2901.290 2297.420 2901.610 2297.480 ; + LAYER via ; + RECT 2621.640 2297.420 2621.900 2297.680 ; + RECT 2901.320 2297.420 2901.580 2297.680 ; + LAYER met2 ; + RECT 2901.310 2433.875 2901.590 2434.245 ; + RECT 2901.380 2297.710 2901.520 2433.875 ; + RECT 2621.640 2297.390 2621.900 2297.710 ; + RECT 2901.320 2297.390 2901.580 2297.710 ; + RECT 2621.700 2293.485 2621.840 2297.390 ; + RECT 2621.630 2293.115 2621.910 2293.485 ; + LAYER via2 ; + RECT 2901.310 2433.920 2901.590 2434.200 ; + RECT 2621.630 2293.160 2621.910 2293.440 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2901.285 2434.210 2901.615 2434.225 ; + RECT 2917.600 2434.210 2924.800 2434.660 ; + RECT 2901.285 2433.910 2924.800 2434.210 ; + RECT 2901.285 2433.895 2901.615 2433.910 ; + RECT 2917.600 2433.460 2924.800 2433.910 ; + RECT 2606.000 2293.450 2610.000 2293.840 ; + RECT 2621.605 2293.450 2621.935 2293.465 ; + RECT 2606.000 2293.240 2621.935 2293.450 ; + RECT 2609.580 2293.150 2621.935 2293.240 ; + RECT 2621.605 2293.135 2621.935 2293.150 ; +======= RECT 2919.700 2433.460 2924.800 2434.660 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[10] PIN io_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2497.540 2618.710 2497.600 ; + RECT 2901.290 2497.540 2901.610 2497.600 ; + RECT 2618.390 2497.400 2901.610 2497.540 ; + RECT 2618.390 2497.340 2618.710 2497.400 ; + RECT 2901.290 2497.340 2901.610 2497.400 ; + LAYER via ; + RECT 2618.420 2497.340 2618.680 2497.600 ; + RECT 2901.320 2497.340 2901.580 2497.600 ; + LAYER met2 ; + RECT 2901.310 2669.155 2901.590 2669.525 ; + RECT 2901.380 2497.630 2901.520 2669.155 ; + RECT 2618.420 2497.310 2618.680 2497.630 ; + RECT 2901.320 2497.310 2901.580 2497.630 ; + RECT 2618.480 2493.405 2618.620 2497.310 ; + RECT 2618.410 2493.035 2618.690 2493.405 ; + LAYER via2 ; + RECT 2901.310 2669.200 2901.590 2669.480 ; + RECT 2618.410 2493.080 2618.690 2493.360 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2901.285 2669.490 2901.615 2669.505 ; + RECT 2917.600 2669.490 2924.800 2669.940 ; + RECT 2901.285 2669.190 2924.800 2669.490 ; + RECT 2901.285 2669.175 2901.615 2669.190 ; + RECT 2917.600 2668.740 2924.800 2669.190 ; + RECT 2606.000 2493.370 2610.000 2493.760 ; + RECT 2618.385 2493.370 2618.715 2493.385 ; + RECT 2606.000 2493.160 2618.715 2493.370 ; + RECT 2609.580 2493.070 2618.715 2493.160 ; + RECT 2618.385 2493.055 2618.715 2493.070 ; +======= RECT 2919.700 2668.740 2924.800 2669.940 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[11] PIN io_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2697.800 2618.710 2697.860 ; + RECT 2901.290 2697.800 2901.610 2697.860 ; + RECT 2618.390 2697.660 2901.610 2697.800 ; + RECT 2618.390 2697.600 2618.710 2697.660 ; + RECT 2901.290 2697.600 2901.610 2697.660 ; + LAYER via ; + RECT 2618.420 2697.600 2618.680 2697.860 ; + RECT 2901.320 2697.600 2901.580 2697.860 ; + LAYER met2 ; + RECT 2901.310 2903.755 2901.590 2904.125 ; + RECT 2901.380 2697.890 2901.520 2903.755 ; + RECT 2618.420 2697.570 2618.680 2697.890 ; + RECT 2901.320 2697.570 2901.580 2697.890 ; + RECT 2618.480 2693.325 2618.620 2697.570 ; + RECT 2618.410 2692.955 2618.690 2693.325 ; + LAYER via2 ; + RECT 2901.310 2903.800 2901.590 2904.080 ; + RECT 2618.410 2693.000 2618.690 2693.280 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2901.285 2904.090 2901.615 2904.105 ; + RECT 2917.600 2904.090 2924.800 2904.540 ; + RECT 2901.285 2903.790 2924.800 2904.090 ; + RECT 2901.285 2903.775 2901.615 2903.790 ; + RECT 2917.600 2903.340 2924.800 2903.790 ; + RECT 2606.000 2693.290 2610.000 2693.680 ; + RECT 2618.385 2693.290 2618.715 2693.305 ; + RECT 2606.000 2693.080 2618.715 2693.290 ; + RECT 2609.580 2692.990 2618.715 2693.080 ; + RECT 2618.385 2692.975 2618.715 2692.990 ; +======= RECT 2919.700 2903.340 2924.800 2904.540 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[12] PIN io_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.610 2898.060 2621.930 2898.120 ; + RECT 2901.750 2898.060 2902.070 2898.120 ; + RECT 2621.610 2897.920 2902.070 2898.060 ; + RECT 2621.610 2897.860 2621.930 2897.920 ; + RECT 2901.750 2897.860 2902.070 2897.920 ; + LAYER via ; + RECT 2621.640 2897.860 2621.900 2898.120 ; + RECT 2901.780 2897.860 2902.040 2898.120 ; + LAYER met2 ; + RECT 2901.770 3138.355 2902.050 3138.725 ; + RECT 2901.840 2898.150 2901.980 3138.355 ; + RECT 2621.640 2897.830 2621.900 2898.150 ; + RECT 2901.780 2897.830 2902.040 2898.150 ; + RECT 2621.700 2893.245 2621.840 2897.830 ; + RECT 2621.630 2892.875 2621.910 2893.245 ; + LAYER via2 ; + RECT 2901.770 3138.400 2902.050 3138.680 ; + RECT 2621.630 2892.920 2621.910 2893.200 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2901.745 3138.690 2902.075 3138.705 ; + RECT 2917.600 3138.690 2924.800 3139.140 ; + RECT 2901.745 3138.390 2924.800 3138.690 ; + RECT 2901.745 3138.375 2902.075 3138.390 ; + RECT 2917.600 3137.940 2924.800 3138.390 ; + RECT 2606.000 2893.210 2610.000 2893.600 ; + RECT 2621.605 2893.210 2621.935 2893.225 ; + RECT 2606.000 2893.000 2621.935 2893.210 ; + RECT 2609.580 2892.910 2621.935 2893.000 ; + RECT 2621.605 2892.895 2621.935 2892.910 ; +======= RECT 2919.700 3137.940 2924.800 3139.140 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[13] PIN io_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.610 3097.980 2621.930 3098.040 ; + RECT 2901.290 3097.980 2901.610 3098.040 ; + RECT 2621.610 3097.840 2901.610 3097.980 ; + RECT 2621.610 3097.780 2621.930 3097.840 ; + RECT 2901.290 3097.780 2901.610 3097.840 ; + LAYER via ; + RECT 2621.640 3097.780 2621.900 3098.040 ; + RECT 2901.320 3097.780 2901.580 3098.040 ; + LAYER met2 ; + RECT 2901.310 3372.955 2901.590 3373.325 ; + RECT 2901.380 3098.070 2901.520 3372.955 ; + RECT 2621.640 3097.750 2621.900 3098.070 ; + RECT 2901.320 3097.750 2901.580 3098.070 ; + RECT 2621.700 3093.165 2621.840 3097.750 ; + RECT 2621.630 3092.795 2621.910 3093.165 ; + LAYER via2 ; + RECT 2901.310 3373.000 2901.590 3373.280 ; + RECT 2621.630 3092.840 2621.910 3093.120 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2901.285 3373.290 2901.615 3373.305 ; + RECT 2917.600 3373.290 2924.800 3373.740 ; + RECT 2901.285 3372.990 2924.800 3373.290 ; + RECT 2901.285 3372.975 2901.615 3372.990 ; + RECT 2917.600 3372.540 2924.800 3372.990 ; + RECT 2606.000 3093.130 2610.000 3093.520 ; + RECT 2621.605 3093.130 2621.935 3093.145 ; + RECT 2606.000 3092.920 2621.935 3093.130 ; + RECT 2609.580 3092.830 2621.935 3092.920 ; + RECT 2621.605 3092.815 2621.935 3092.830 ; +======= RECT 2919.700 3372.540 2924.800 3373.740 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[14] PIN io_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2573.310 3502.240 2573.630 3502.300 ; + RECT 2798.250 3502.240 2798.570 3502.300 ; + RECT 2573.310 3502.100 2798.570 3502.240 ; + RECT 2573.310 3502.040 2573.630 3502.100 ; + RECT 2798.250 3502.040 2798.570 3502.100 ; + RECT 2566.870 3276.480 2567.190 3276.540 ; + RECT 2573.310 3276.480 2573.630 3276.540 ; + RECT 2566.870 3276.340 2573.630 3276.480 ; + RECT 2566.870 3276.280 2567.190 3276.340 ; + RECT 2573.310 3276.280 2573.630 3276.340 ; + LAYER via ; + RECT 2573.340 3502.040 2573.600 3502.300 ; + RECT 2798.280 3502.040 2798.540 3502.300 ; + RECT 2566.900 3276.280 2567.160 3276.540 ; + RECT 2573.340 3276.280 2573.600 3276.540 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2798.130 3517.600 2798.690 3524.800 ; + RECT 2798.340 3502.330 2798.480 3517.600 ; + RECT 2573.340 3502.010 2573.600 3502.330 ; + RECT 2798.280 3502.010 2798.540 3502.330 ; + RECT 2573.400 3276.570 2573.540 3502.010 ; + RECT 2566.900 3276.250 2567.160 3276.570 ; + RECT 2573.340 3276.250 2573.600 3276.570 ; + RECT 2566.960 3260.000 2567.100 3276.250 ; + RECT 2566.850 3256.000 2567.130 3260.000 ; +======= RECT 2798.130 3519.700 2798.690 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[15] PIN io_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2318.010 3502.240 2318.330 3502.300 ; + RECT 2473.950 3502.240 2474.270 3502.300 ; + RECT 2318.010 3502.100 2474.270 3502.240 ; + RECT 2318.010 3502.040 2318.330 3502.100 ; + RECT 2473.950 3502.040 2474.270 3502.100 ; + RECT 2311.570 3277.500 2311.890 3277.560 ; + RECT 2318.010 3277.500 2318.330 3277.560 ; + RECT 2311.570 3277.360 2318.330 3277.500 ; + RECT 2311.570 3277.300 2311.890 3277.360 ; + RECT 2318.010 3277.300 2318.330 3277.360 ; + LAYER via ; + RECT 2318.040 3502.040 2318.300 3502.300 ; + RECT 2473.980 3502.040 2474.240 3502.300 ; + RECT 2311.600 3277.300 2311.860 3277.560 ; + RECT 2318.040 3277.300 2318.300 3277.560 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2473.830 3517.600 2474.390 3524.800 ; + RECT 2474.040 3502.330 2474.180 3517.600 ; + RECT 2318.040 3502.010 2318.300 3502.330 ; + RECT 2473.980 3502.010 2474.240 3502.330 ; + RECT 2318.100 3277.590 2318.240 3502.010 ; + RECT 2311.600 3277.270 2311.860 3277.590 ; + RECT 2318.040 3277.270 2318.300 3277.590 ; + RECT 2311.660 3260.000 2311.800 3277.270 ; + RECT 2311.550 3256.000 2311.830 3260.000 ; +======= RECT 2473.830 3519.700 2474.390 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[16] PIN io_in[17] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2055.810 3502.240 2056.130 3502.300 ; + RECT 2149.190 3502.240 2149.510 3502.300 ; + RECT 2055.810 3502.100 2149.510 3502.240 ; + RECT 2055.810 3502.040 2056.130 3502.100 ; + RECT 2149.190 3502.040 2149.510 3502.100 ; + LAYER via ; + RECT 2055.840 3502.040 2056.100 3502.300 ; + RECT 2149.220 3502.040 2149.480 3502.300 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2149.070 3517.600 2149.630 3524.800 ; + RECT 2149.280 3502.330 2149.420 3517.600 ; + RECT 2055.840 3502.010 2056.100 3502.330 ; + RECT 2149.220 3502.010 2149.480 3502.330 ; + RECT 2055.900 3260.000 2056.040 3502.010 ; + RECT 2055.790 3256.000 2056.070 3260.000 ; +======= RECT 2149.070 3519.700 2149.630 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[17] PIN io_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1800.510 3498.500 1800.830 3498.560 ; + RECT 1824.890 3498.500 1825.210 3498.560 ; + RECT 1800.510 3498.360 1825.210 3498.500 ; + RECT 1800.510 3498.300 1800.830 3498.360 ; + RECT 1824.890 3498.300 1825.210 3498.360 ; + LAYER via ; + RECT 1800.540 3498.300 1800.800 3498.560 ; + RECT 1824.920 3498.300 1825.180 3498.560 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1824.770 3517.600 1825.330 3524.800 ; + RECT 1824.980 3498.590 1825.120 3517.600 ; + RECT 1800.540 3498.270 1800.800 3498.590 ; + RECT 1824.920 3498.270 1825.180 3498.590 ; + RECT 1800.600 3260.000 1800.740 3498.270 ; + RECT 1800.490 3256.000 1800.770 3260.000 ; +======= RECT 1824.770 3519.700 1825.330 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[18] PIN io_in[19] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1500.590 3498.500 1500.910 3498.560 ; + RECT 1503.810 3498.500 1504.130 3498.560 ; + RECT 1500.590 3498.360 1504.130 3498.500 ; + RECT 1500.590 3498.300 1500.910 3498.360 ; + RECT 1503.810 3498.300 1504.130 3498.360 ; + RECT 1503.810 3270.700 1504.130 3270.760 ; + RECT 1544.750 3270.700 1545.070 3270.760 ; + RECT 1503.810 3270.560 1545.070 3270.700 ; + RECT 1503.810 3270.500 1504.130 3270.560 ; + RECT 1544.750 3270.500 1545.070 3270.560 ; + LAYER via ; + RECT 1500.620 3498.300 1500.880 3498.560 ; + RECT 1503.840 3498.300 1504.100 3498.560 ; + RECT 1503.840 3270.500 1504.100 3270.760 ; + RECT 1544.780 3270.500 1545.040 3270.760 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1500.470 3517.600 1501.030 3524.800 ; + RECT 1500.680 3498.590 1500.820 3517.600 ; + RECT 1500.620 3498.270 1500.880 3498.590 ; + RECT 1503.840 3498.270 1504.100 3498.590 ; + RECT 1503.900 3270.790 1504.040 3498.270 ; + RECT 1503.840 3270.470 1504.100 3270.790 ; + RECT 1544.780 3270.470 1545.040 3270.790 ; + RECT 1544.840 3260.000 1544.980 3270.470 ; + RECT 1544.730 3256.000 1545.010 3260.000 ; +======= RECT 1500.470 3519.700 1501.030 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[19] PIN io_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2619.310 324.260 2619.630 324.320 ; + RECT 2898.990 324.260 2899.310 324.320 ; + RECT 2619.310 324.120 2899.310 324.260 ; + RECT 2619.310 324.060 2619.630 324.120 ; + RECT 2898.990 324.060 2899.310 324.120 ; + LAYER via ; + RECT 2619.340 324.060 2619.600 324.320 ; + RECT 2899.020 324.060 2899.280 324.320 ; + LAYER met2 ; + RECT 2619.330 493.155 2619.610 493.525 ; + RECT 2619.400 324.350 2619.540 493.155 ; + RECT 2619.340 324.030 2619.600 324.350 ; + RECT 2899.020 324.030 2899.280 324.350 ; + RECT 2899.080 322.845 2899.220 324.030 ; + RECT 2899.010 322.475 2899.290 322.845 ; + LAYER via2 ; + RECT 2619.330 493.200 2619.610 493.480 ; + RECT 2899.010 322.520 2899.290 322.800 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 493.490 2610.000 493.880 ; + RECT 2619.305 493.490 2619.635 493.505 ; + RECT 2606.000 493.280 2619.635 493.490 ; + RECT 2609.580 493.190 2619.635 493.280 ; + RECT 2619.305 493.175 2619.635 493.190 ; + RECT 2898.985 322.810 2899.315 322.825 ; + RECT 2917.600 322.810 2924.800 323.260 ; + RECT 2898.985 322.510 2924.800 322.810 ; + RECT 2898.985 322.495 2899.315 322.510 ; + RECT 2917.600 322.060 2924.800 322.510 ; +======= RECT 2919.700 322.060 2924.800 323.260 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[1] PIN io_in[20] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1175.830 3498.500 1176.150 3498.560 ; + RECT 1179.510 3498.500 1179.830 3498.560 ; + RECT 1175.830 3498.360 1179.830 3498.500 ; + RECT 1175.830 3498.300 1176.150 3498.360 ; + RECT 1179.510 3498.300 1179.830 3498.360 ; + RECT 1179.510 3274.100 1179.830 3274.160 ; + RECT 1289.450 3274.100 1289.770 3274.160 ; + RECT 1179.510 3273.960 1289.770 3274.100 ; + RECT 1179.510 3273.900 1179.830 3273.960 ; + RECT 1289.450 3273.900 1289.770 3273.960 ; + LAYER via ; + RECT 1175.860 3498.300 1176.120 3498.560 ; + RECT 1179.540 3498.300 1179.800 3498.560 ; + RECT 1179.540 3273.900 1179.800 3274.160 ; + RECT 1289.480 3273.900 1289.740 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1175.710 3517.600 1176.270 3524.800 ; + RECT 1175.920 3498.590 1176.060 3517.600 ; + RECT 1175.860 3498.270 1176.120 3498.590 ; + RECT 1179.540 3498.270 1179.800 3498.590 ; + RECT 1179.600 3274.190 1179.740 3498.270 ; + RECT 1179.540 3273.870 1179.800 3274.190 ; + RECT 1289.480 3273.870 1289.740 3274.190 ; + RECT 1289.540 3260.000 1289.680 3273.870 ; + RECT 1289.430 3256.000 1289.710 3260.000 ; +======= RECT 1175.710 3519.700 1176.270 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[20] PIN io_in[21] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 851.530 3501.220 851.850 3501.280 ; + RECT 855.210 3501.220 855.530 3501.280 ; + RECT 851.530 3501.080 855.530 3501.220 ; + RECT 851.530 3501.020 851.850 3501.080 ; + RECT 855.210 3501.020 855.530 3501.080 ; + RECT 855.210 3274.440 855.530 3274.500 ; + RECT 1033.690 3274.440 1034.010 3274.500 ; + RECT 855.210 3274.300 1034.010 3274.440 ; + RECT 855.210 3274.240 855.530 3274.300 ; + RECT 1033.690 3274.240 1034.010 3274.300 ; + LAYER via ; + RECT 851.560 3501.020 851.820 3501.280 ; + RECT 855.240 3501.020 855.500 3501.280 ; + RECT 855.240 3274.240 855.500 3274.500 ; + RECT 1033.720 3274.240 1033.980 3274.500 ; LAYER met2 ; +<<<<<<< HEAD + RECT 851.410 3517.600 851.970 3524.800 ; + RECT 851.620 3501.310 851.760 3517.600 ; + RECT 851.560 3500.990 851.820 3501.310 ; + RECT 855.240 3500.990 855.500 3501.310 ; + RECT 855.300 3274.530 855.440 3500.990 ; + RECT 855.240 3274.210 855.500 3274.530 ; + RECT 1033.720 3274.210 1033.980 3274.530 ; + RECT 1033.780 3260.000 1033.920 3274.210 ; + RECT 1033.670 3256.000 1033.950 3260.000 ; +======= RECT 851.410 3519.700 851.970 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[21] PIN io_in[22] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 527.230 3498.500 527.550 3498.560 ; + RECT 530.910 3498.500 531.230 3498.560 ; + RECT 527.230 3498.360 531.230 3498.500 ; + RECT 527.230 3498.300 527.550 3498.360 ; + RECT 530.910 3498.300 531.230 3498.360 ; + RECT 530.910 3274.440 531.230 3274.500 ; + RECT 777.930 3274.440 778.250 3274.500 ; + RECT 530.910 3274.300 778.250 3274.440 ; + RECT 530.910 3274.240 531.230 3274.300 ; + RECT 777.930 3274.240 778.250 3274.300 ; + LAYER via ; + RECT 527.260 3498.300 527.520 3498.560 ; + RECT 530.940 3498.300 531.200 3498.560 ; + RECT 530.940 3274.240 531.200 3274.500 ; + RECT 777.960 3274.240 778.220 3274.500 ; LAYER met2 ; +<<<<<<< HEAD + RECT 527.110 3517.600 527.670 3524.800 ; + RECT 527.320 3498.590 527.460 3517.600 ; + RECT 527.260 3498.270 527.520 3498.590 ; + RECT 530.940 3498.270 531.200 3498.590 ; + RECT 531.000 3274.530 531.140 3498.270 ; + RECT 530.940 3274.210 531.200 3274.530 ; + RECT 777.960 3274.210 778.220 3274.530 ; + RECT 778.020 3260.000 778.160 3274.210 ; + RECT 777.910 3256.000 778.190 3260.000 ; +======= RECT 527.110 3519.700 527.670 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[22] PIN io_in[23] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 202.470 3501.900 202.790 3501.960 ; + RECT 206.610 3501.900 206.930 3501.960 ; + RECT 202.470 3501.760 206.930 3501.900 ; + RECT 202.470 3501.700 202.790 3501.760 ; + RECT 206.610 3501.700 206.930 3501.760 ; + RECT 206.610 3274.440 206.930 3274.500 ; + RECT 522.630 3274.440 522.950 3274.500 ; + RECT 206.610 3274.300 522.950 3274.440 ; + RECT 206.610 3274.240 206.930 3274.300 ; + RECT 522.630 3274.240 522.950 3274.300 ; + LAYER via ; + RECT 202.500 3501.700 202.760 3501.960 ; + RECT 206.640 3501.700 206.900 3501.960 ; + RECT 206.640 3274.240 206.900 3274.500 ; + RECT 522.660 3274.240 522.920 3274.500 ; LAYER met2 ; +<<<<<<< HEAD + RECT 202.350 3517.600 202.910 3524.800 ; + RECT 202.560 3501.990 202.700 3517.600 ; + RECT 202.500 3501.670 202.760 3501.990 ; + RECT 206.640 3501.670 206.900 3501.990 ; + RECT 206.700 3274.530 206.840 3501.670 ; + RECT 206.640 3274.210 206.900 3274.530 ; + RECT 522.660 3274.210 522.920 3274.530 ; + RECT 522.720 3260.000 522.860 3274.210 ; + RECT 522.610 3256.000 522.890 3260.000 ; +======= RECT 202.350 3519.700 202.910 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[23] PIN io_in[24] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 3229.220 18.330 3229.280 ; + RECT 296.770 3229.220 297.090 3229.280 ; + RECT 18.010 3229.080 297.090 3229.220 ; + RECT 18.010 3229.020 18.330 3229.080 ; + RECT 296.770 3229.020 297.090 3229.080 ; + LAYER via ; + RECT 18.040 3229.020 18.300 3229.280 ; + RECT 296.800 3229.020 297.060 3229.280 ; + LAYER met2 ; + RECT 18.030 3411.035 18.310 3411.405 ; + RECT 18.100 3229.310 18.240 3411.035 ; + RECT 18.040 3228.990 18.300 3229.310 ; + RECT 296.800 3228.990 297.060 3229.310 ; + RECT 296.860 3223.725 297.000 3228.990 ; + RECT 296.790 3223.355 297.070 3223.725 ; + LAYER via2 ; + RECT 18.030 3411.080 18.310 3411.360 ; + RECT 296.790 3223.400 297.070 3223.680 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 3411.370 2.400 3411.820 ; + RECT 18.005 3411.370 18.335 3411.385 ; + RECT -4.800 3411.070 18.335 3411.370 ; + RECT -4.800 3410.620 2.400 3411.070 ; + RECT 18.005 3411.055 18.335 3411.070 ; + RECT 296.765 3223.690 297.095 3223.705 ; + RECT 310.000 3223.690 314.000 3224.080 ; + RECT 296.765 3223.480 314.000 3223.690 ; + RECT 296.765 3223.390 310.500 3223.480 ; + RECT 296.765 3223.375 297.095 3223.390 ; +======= RECT -4.800 3410.620 0.300 3411.820 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[24] PIN io_in[25] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 3015.360 18.330 3015.420 ; + RECT 296.770 3015.360 297.090 3015.420 ; + RECT 18.010 3015.220 297.090 3015.360 ; + RECT 18.010 3015.160 18.330 3015.220 ; + RECT 296.770 3015.160 297.090 3015.220 ; + LAYER via ; + RECT 18.040 3015.160 18.300 3015.420 ; + RECT 296.800 3015.160 297.060 3015.420 ; + LAYER met2 ; + RECT 18.030 3124.075 18.310 3124.445 ; + RECT 18.100 3015.450 18.240 3124.075 ; + RECT 18.040 3015.130 18.300 3015.450 ; + RECT 296.800 3015.130 297.060 3015.450 ; + RECT 296.860 3009.525 297.000 3015.130 ; + RECT 296.790 3009.155 297.070 3009.525 ; + LAYER via2 ; + RECT 18.030 3124.120 18.310 3124.400 ; + RECT 296.790 3009.200 297.070 3009.480 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 3124.410 2.400 3124.860 ; + RECT 18.005 3124.410 18.335 3124.425 ; + RECT -4.800 3124.110 18.335 3124.410 ; + RECT -4.800 3123.660 2.400 3124.110 ; + RECT 18.005 3124.095 18.335 3124.110 ; + RECT 296.765 3009.490 297.095 3009.505 ; + RECT 310.000 3009.490 314.000 3009.880 ; + RECT 296.765 3009.280 314.000 3009.490 ; + RECT 296.765 3009.190 310.500 3009.280 ; + RECT 296.765 3009.175 297.095 3009.190 ; +======= RECT -4.800 3123.660 0.300 3124.860 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[25] PIN io_in[26] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2801.160 17.410 2801.220 ; + RECT 296.770 2801.160 297.090 2801.220 ; + RECT 17.090 2801.020 297.090 2801.160 ; + RECT 17.090 2800.960 17.410 2801.020 ; + RECT 296.770 2800.960 297.090 2801.020 ; + LAYER via ; + RECT 17.120 2800.960 17.380 2801.220 ; + RECT 296.800 2800.960 297.060 2801.220 ; + LAYER met2 ; + RECT 17.110 2836.435 17.390 2836.805 ; + RECT 17.180 2801.250 17.320 2836.435 ; + RECT 17.120 2800.930 17.380 2801.250 ; + RECT 296.800 2800.930 297.060 2801.250 ; + RECT 296.860 2795.325 297.000 2800.930 ; + RECT 296.790 2794.955 297.070 2795.325 ; + LAYER via2 ; + RECT 17.110 2836.480 17.390 2836.760 ; + RECT 296.790 2795.000 297.070 2795.280 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 2836.770 2.400 2837.220 ; + RECT 17.085 2836.770 17.415 2836.785 ; + RECT -4.800 2836.470 17.415 2836.770 ; + RECT -4.800 2836.020 2.400 2836.470 ; + RECT 17.085 2836.455 17.415 2836.470 ; + RECT 296.765 2795.290 297.095 2795.305 ; + RECT 310.000 2795.290 314.000 2795.680 ; + RECT 296.765 2795.080 314.000 2795.290 ; + RECT 296.765 2794.990 310.500 2795.080 ; + RECT 296.765 2794.975 297.095 2794.990 ; +======= RECT -4.800 2836.020 0.300 2837.220 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[26] PIN io_in[27] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2580.840 17.410 2580.900 ; + RECT 296.770 2580.840 297.090 2580.900 ; + RECT 17.090 2580.700 297.090 2580.840 ; + RECT 17.090 2580.640 17.410 2580.700 ; + RECT 296.770 2580.640 297.090 2580.700 ; + LAYER via ; + RECT 17.120 2580.640 17.380 2580.900 ; + RECT 296.800 2580.640 297.060 2580.900 ; + LAYER met2 ; + RECT 17.120 2580.610 17.380 2580.930 ; + RECT 296.790 2580.755 297.070 2581.125 ; + RECT 296.800 2580.610 297.060 2580.755 ; + RECT 17.180 2549.845 17.320 2580.610 ; + RECT 17.110 2549.475 17.390 2549.845 ; + LAYER via2 ; + RECT 296.790 2580.800 297.070 2581.080 ; + RECT 17.110 2549.520 17.390 2549.800 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2581.090 297.095 2581.105 ; + RECT 310.000 2581.090 314.000 2581.480 ; + RECT 296.765 2580.880 314.000 2581.090 ; + RECT 296.765 2580.790 310.500 2580.880 ; + RECT 296.765 2580.775 297.095 2580.790 ; + RECT -4.800 2549.810 2.400 2550.260 ; + RECT 17.085 2549.810 17.415 2549.825 ; + RECT -4.800 2549.510 17.415 2549.810 ; + RECT -4.800 2549.060 2.400 2549.510 ; + RECT 17.085 2549.495 17.415 2549.510 ; +======= RECT -4.800 2549.060 0.300 2550.260 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[27] PIN io_in[28] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2366.980 17.410 2367.040 ; + RECT 296.770 2366.980 297.090 2367.040 ; + RECT 17.090 2366.840 297.090 2366.980 ; + RECT 17.090 2366.780 17.410 2366.840 ; + RECT 296.770 2366.780 297.090 2366.840 ; + LAYER via ; + RECT 17.120 2366.780 17.380 2367.040 ; + RECT 296.800 2366.780 297.060 2367.040 ; + LAYER met2 ; + RECT 17.120 2366.750 17.380 2367.070 ; + RECT 296.800 2366.925 297.060 2367.070 ; + RECT 17.180 2262.205 17.320 2366.750 ; + RECT 296.790 2366.555 297.070 2366.925 ; + RECT 17.110 2261.835 17.390 2262.205 ; + LAYER via2 ; + RECT 296.790 2366.600 297.070 2366.880 ; + RECT 17.110 2261.880 17.390 2262.160 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2366.890 297.095 2366.905 ; + RECT 310.000 2366.890 314.000 2367.280 ; + RECT 296.765 2366.680 314.000 2366.890 ; + RECT 296.765 2366.590 310.500 2366.680 ; + RECT 296.765 2366.575 297.095 2366.590 ; + RECT -4.800 2262.170 2.400 2262.620 ; + RECT 17.085 2262.170 17.415 2262.185 ; + RECT -4.800 2261.870 17.415 2262.170 ; + RECT -4.800 2261.420 2.400 2261.870 ; + RECT 17.085 2261.855 17.415 2261.870 ; +======= RECT -4.800 2261.420 0.300 2262.620 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[28] PIN io_in[29] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 2145.980 17.870 2146.040 ; + RECT 296.770 2145.980 297.090 2146.040 ; + RECT 17.550 2145.840 297.090 2145.980 ; + RECT 17.550 2145.780 17.870 2145.840 ; + RECT 296.770 2145.780 297.090 2145.840 ; + LAYER via ; + RECT 17.580 2145.780 17.840 2146.040 ; + RECT 296.800 2145.780 297.060 2146.040 ; + LAYER met2 ; + RECT 296.790 2152.355 297.070 2152.725 ; + RECT 296.860 2146.070 297.000 2152.355 ; + RECT 17.580 2145.750 17.840 2146.070 ; + RECT 296.800 2145.750 297.060 2146.070 ; + RECT 17.640 1975.245 17.780 2145.750 ; + RECT 17.570 1974.875 17.850 1975.245 ; + LAYER via2 ; + RECT 296.790 2152.400 297.070 2152.680 ; + RECT 17.570 1974.920 17.850 1975.200 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2152.690 297.095 2152.705 ; + RECT 310.000 2152.690 314.000 2153.080 ; + RECT 296.765 2152.480 314.000 2152.690 ; + RECT 296.765 2152.390 310.500 2152.480 ; + RECT 296.765 2152.375 297.095 2152.390 ; + RECT -4.800 1975.210 2.400 1975.660 ; + RECT 17.545 1975.210 17.875 1975.225 ; + RECT -4.800 1974.910 17.875 1975.210 ; + RECT -4.800 1974.460 2.400 1974.910 ; + RECT 17.545 1974.895 17.875 1974.910 ; +======= RECT -4.800 1974.460 0.300 1975.660 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[29] PIN io_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2619.310 558.860 2619.630 558.920 ; + RECT 2898.990 558.860 2899.310 558.920 ; + RECT 2619.310 558.720 2899.310 558.860 ; + RECT 2619.310 558.660 2619.630 558.720 ; + RECT 2898.990 558.660 2899.310 558.720 ; + LAYER via ; + RECT 2619.340 558.660 2619.600 558.920 ; + RECT 2899.020 558.660 2899.280 558.920 ; + LAYER met2 ; + RECT 2619.330 693.075 2619.610 693.445 ; + RECT 2619.400 558.950 2619.540 693.075 ; + RECT 2619.340 558.630 2619.600 558.950 ; + RECT 2899.020 558.630 2899.280 558.950 ; + RECT 2899.080 557.445 2899.220 558.630 ; + RECT 2899.010 557.075 2899.290 557.445 ; + LAYER via2 ; + RECT 2619.330 693.120 2619.610 693.400 ; + RECT 2899.010 557.120 2899.290 557.400 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 693.410 2610.000 693.800 ; + RECT 2619.305 693.410 2619.635 693.425 ; + RECT 2606.000 693.200 2619.635 693.410 ; + RECT 2609.580 693.110 2619.635 693.200 ; + RECT 2619.305 693.095 2619.635 693.110 ; + RECT 2898.985 557.410 2899.315 557.425 ; + RECT 2917.600 557.410 2924.800 557.860 ; + RECT 2898.985 557.110 2924.800 557.410 ; + RECT 2898.985 557.095 2899.315 557.110 ; + RECT 2917.600 556.660 2924.800 557.110 ; +======= RECT 2919.700 556.660 2924.800 557.860 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[2] PIN io_in[30] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 1690.380 18.330 1690.440 ; + RECT 299.990 1690.380 300.310 1690.440 ; + RECT 18.010 1690.240 300.310 1690.380 ; + RECT 18.010 1690.180 18.330 1690.240 ; + RECT 299.990 1690.180 300.310 1690.240 ; + LAYER via ; + RECT 18.040 1690.180 18.300 1690.440 ; + RECT 300.020 1690.180 300.280 1690.440 ; + LAYER met2 ; + RECT 300.010 1938.155 300.290 1938.525 ; + RECT 300.080 1690.470 300.220 1938.155 ; + RECT 18.040 1690.150 18.300 1690.470 ; + RECT 300.020 1690.150 300.280 1690.470 ; + RECT 18.100 1687.605 18.240 1690.150 ; + RECT 18.030 1687.235 18.310 1687.605 ; + LAYER via2 ; + RECT 300.010 1938.200 300.290 1938.480 ; + RECT 18.030 1687.280 18.310 1687.560 ; LAYER met3 ; +<<<<<<< HEAD + RECT 299.985 1938.490 300.315 1938.505 ; + RECT 310.000 1938.490 314.000 1938.880 ; + RECT 299.985 1938.280 314.000 1938.490 ; + RECT 299.985 1938.190 310.500 1938.280 ; + RECT 299.985 1938.175 300.315 1938.190 ; + RECT -4.800 1687.570 2.400 1688.020 ; + RECT 18.005 1687.570 18.335 1687.585 ; + RECT -4.800 1687.270 18.335 1687.570 ; + RECT -4.800 1686.820 2.400 1687.270 ; + RECT 18.005 1687.255 18.335 1687.270 ; +======= RECT -4.800 1686.820 0.300 1688.020 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[30] PIN io_in[31] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 15.250 1476.520 15.570 1476.580 ; + RECT 300.910 1476.520 301.230 1476.580 ; + RECT 15.250 1476.380 301.230 1476.520 ; + RECT 15.250 1476.320 15.570 1476.380 ; + RECT 300.910 1476.320 301.230 1476.380 ; + LAYER via ; + RECT 15.280 1476.320 15.540 1476.580 ; + RECT 300.940 1476.320 301.200 1476.580 ; + LAYER met2 ; + RECT 300.930 1723.275 301.210 1723.645 ; + RECT 301.000 1476.610 301.140 1723.275 ; + RECT 15.280 1476.290 15.540 1476.610 ; + RECT 300.940 1476.290 301.200 1476.610 ; + RECT 15.340 1472.045 15.480 1476.290 ; + RECT 15.270 1471.675 15.550 1472.045 ; + LAYER via2 ; + RECT 300.930 1723.320 301.210 1723.600 ; + RECT 15.270 1471.720 15.550 1472.000 ; LAYER met3 ; +<<<<<<< HEAD + RECT 300.905 1723.610 301.235 1723.625 ; + RECT 310.000 1723.610 314.000 1724.000 ; + RECT 300.905 1723.400 314.000 1723.610 ; + RECT 300.905 1723.310 310.500 1723.400 ; + RECT 300.905 1723.295 301.235 1723.310 ; + RECT -4.800 1472.010 2.400 1472.460 ; + RECT 15.245 1472.010 15.575 1472.025 ; + RECT -4.800 1471.710 15.575 1472.010 ; + RECT -4.800 1471.260 2.400 1471.710 ; + RECT 15.245 1471.695 15.575 1471.710 ; +======= RECT -4.800 1471.260 0.300 1472.460 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[31] PIN io_in[32] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 15.710 1262.660 16.030 1262.720 ; + RECT 300.450 1262.660 300.770 1262.720 ; + RECT 15.710 1262.520 300.770 1262.660 ; + RECT 15.710 1262.460 16.030 1262.520 ; + RECT 300.450 1262.460 300.770 1262.520 ; + LAYER via ; + RECT 15.740 1262.460 16.000 1262.720 ; + RECT 300.480 1262.460 300.740 1262.720 ; + LAYER met2 ; + RECT 300.470 1509.075 300.750 1509.445 ; + RECT 300.540 1262.750 300.680 1509.075 ; + RECT 15.740 1262.430 16.000 1262.750 ; + RECT 300.480 1262.430 300.740 1262.750 ; + RECT 15.800 1256.485 15.940 1262.430 ; + RECT 15.730 1256.115 16.010 1256.485 ; + LAYER via2 ; + RECT 300.470 1509.120 300.750 1509.400 ; + RECT 15.730 1256.160 16.010 1256.440 ; LAYER met3 ; +<<<<<<< HEAD + RECT 300.445 1509.410 300.775 1509.425 ; + RECT 310.000 1509.410 314.000 1509.800 ; + RECT 300.445 1509.200 314.000 1509.410 ; + RECT 300.445 1509.110 310.500 1509.200 ; + RECT 300.445 1509.095 300.775 1509.110 ; + RECT -4.800 1256.450 2.400 1256.900 ; + RECT 15.705 1256.450 16.035 1256.465 ; + RECT -4.800 1256.150 16.035 1256.450 ; + RECT -4.800 1255.700 2.400 1256.150 ; + RECT 15.705 1256.135 16.035 1256.150 ; +======= RECT -4.800 1255.700 0.300 1256.900 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[32] PIN io_in[33] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 15.710 1041.660 16.030 1041.720 ; + RECT 299.990 1041.660 300.310 1041.720 ; + RECT 15.710 1041.520 300.310 1041.660 ; + RECT 15.710 1041.460 16.030 1041.520 ; + RECT 299.990 1041.460 300.310 1041.520 ; + LAYER via ; + RECT 15.740 1041.460 16.000 1041.720 ; + RECT 300.020 1041.460 300.280 1041.720 ; + LAYER met2 ; + RECT 300.010 1294.875 300.290 1295.245 ; + RECT 300.080 1041.750 300.220 1294.875 ; + RECT 15.740 1041.430 16.000 1041.750 ; + RECT 300.020 1041.430 300.280 1041.750 ; + RECT 15.800 1040.925 15.940 1041.430 ; + RECT 15.730 1040.555 16.010 1040.925 ; + LAYER via2 ; + RECT 300.010 1294.920 300.290 1295.200 ; + RECT 15.730 1040.600 16.010 1040.880 ; LAYER met3 ; +<<<<<<< HEAD + RECT 299.985 1295.210 300.315 1295.225 ; + RECT 310.000 1295.210 314.000 1295.600 ; + RECT 299.985 1295.000 314.000 1295.210 ; + RECT 299.985 1294.910 310.500 1295.000 ; + RECT 299.985 1294.895 300.315 1294.910 ; + RECT -4.800 1040.890 2.400 1041.340 ; + RECT 15.705 1040.890 16.035 1040.905 ; + RECT -4.800 1040.590 16.035 1040.890 ; + RECT -4.800 1040.140 2.400 1040.590 ; + RECT 15.705 1040.575 16.035 1040.590 ; +======= RECT -4.800 1040.140 0.300 1041.340 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[33] PIN io_in[34] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 827.800 17.410 827.860 ; + RECT 300.450 827.800 300.770 827.860 ; + RECT 17.090 827.660 300.770 827.800 ; + RECT 17.090 827.600 17.410 827.660 ; + RECT 300.450 827.600 300.770 827.660 ; + LAYER via ; + RECT 17.120 827.600 17.380 827.860 ; + RECT 300.480 827.600 300.740 827.860 ; + LAYER met2 ; + RECT 300.470 1080.675 300.750 1081.045 ; + RECT 300.540 827.890 300.680 1080.675 ; + RECT 17.120 827.570 17.380 827.890 ; + RECT 300.480 827.570 300.740 827.890 ; + RECT 17.180 825.365 17.320 827.570 ; + RECT 17.110 824.995 17.390 825.365 ; + LAYER via2 ; + RECT 300.470 1080.720 300.750 1081.000 ; + RECT 17.110 825.040 17.390 825.320 ; LAYER met3 ; +<<<<<<< HEAD + RECT 300.445 1081.010 300.775 1081.025 ; + RECT 310.000 1081.010 314.000 1081.400 ; + RECT 300.445 1080.800 314.000 1081.010 ; + RECT 300.445 1080.710 310.500 1080.800 ; + RECT 300.445 1080.695 300.775 1080.710 ; + RECT -4.800 825.330 2.400 825.780 ; + RECT 17.085 825.330 17.415 825.345 ; + RECT -4.800 825.030 17.415 825.330 ; + RECT -4.800 824.580 2.400 825.030 ; + RECT 17.085 825.015 17.415 825.030 ; +======= RECT -4.800 824.580 0.300 825.780 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[34] PIN io_in[35] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 14.790 613.940 15.110 614.000 ; + RECT 299.990 613.940 300.310 614.000 ; + RECT 14.790 613.800 300.310 613.940 ; + RECT 14.790 613.740 15.110 613.800 ; + RECT 299.990 613.740 300.310 613.800 ; + LAYER via ; + RECT 14.820 613.740 15.080 614.000 ; + RECT 300.020 613.740 300.280 614.000 ; + LAYER met2 ; + RECT 300.010 866.475 300.290 866.845 ; + RECT 300.080 614.030 300.220 866.475 ; + RECT 14.820 613.710 15.080 614.030 ; + RECT 300.020 613.710 300.280 614.030 ; + RECT 14.880 610.485 15.020 613.710 ; + RECT 14.810 610.115 15.090 610.485 ; + LAYER via2 ; + RECT 300.010 866.520 300.290 866.800 ; + RECT 14.810 610.160 15.090 610.440 ; LAYER met3 ; +<<<<<<< HEAD + RECT 299.985 866.810 300.315 866.825 ; + RECT 310.000 866.810 314.000 867.200 ; + RECT 299.985 866.600 314.000 866.810 ; + RECT 299.985 866.510 310.500 866.600 ; + RECT 299.985 866.495 300.315 866.510 ; + RECT -4.800 610.450 2.400 610.900 ; + RECT 14.785 610.450 15.115 610.465 ; + RECT -4.800 610.150 15.115 610.450 ; + RECT -4.800 609.700 2.400 610.150 ; + RECT 14.785 610.135 15.115 610.150 ; +======= RECT -4.800 609.700 0.300 610.900 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[35] PIN io_in[36] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 15.250 400.080 15.570 400.140 ; + RECT 300.450 400.080 300.770 400.140 ; + RECT 15.250 399.940 300.770 400.080 ; + RECT 15.250 399.880 15.570 399.940 ; + RECT 300.450 399.880 300.770 399.940 ; + LAYER via ; + RECT 15.280 399.880 15.540 400.140 ; + RECT 300.480 399.880 300.740 400.140 ; + LAYER met2 ; + RECT 300.470 652.275 300.750 652.645 ; + RECT 300.540 400.170 300.680 652.275 ; + RECT 15.280 399.850 15.540 400.170 ; + RECT 300.480 399.850 300.740 400.170 ; + RECT 15.340 394.925 15.480 399.850 ; + RECT 15.270 394.555 15.550 394.925 ; + LAYER via2 ; + RECT 300.470 652.320 300.750 652.600 ; + RECT 15.270 394.600 15.550 394.880 ; LAYER met3 ; +<<<<<<< HEAD + RECT 300.445 652.610 300.775 652.625 ; + RECT 310.000 652.610 314.000 653.000 ; + RECT 300.445 652.400 314.000 652.610 ; + RECT 300.445 652.310 310.500 652.400 ; + RECT 300.445 652.295 300.775 652.310 ; + RECT -4.800 394.890 2.400 395.340 ; + RECT 15.245 394.890 15.575 394.905 ; + RECT -4.800 394.590 15.575 394.890 ; + RECT -4.800 394.140 2.400 394.590 ; + RECT 15.245 394.575 15.575 394.590 ; +======= RECT -4.800 394.140 0.300 395.340 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[36] PIN io_in[37] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 16.630 179.420 16.950 179.480 ; + RECT 299.990 179.420 300.310 179.480 ; + RECT 16.630 179.280 300.310 179.420 ; + RECT 16.630 179.220 16.950 179.280 ; + RECT 299.990 179.220 300.310 179.280 ; + LAYER via ; + RECT 16.660 179.220 16.920 179.480 ; + RECT 300.020 179.220 300.280 179.480 ; + LAYER met2 ; + RECT 300.010 438.075 300.290 438.445 ; + RECT 300.080 179.510 300.220 438.075 ; + RECT 16.660 179.365 16.920 179.510 ; + RECT 16.650 178.995 16.930 179.365 ; + RECT 300.020 179.190 300.280 179.510 ; + LAYER via2 ; + RECT 300.010 438.120 300.290 438.400 ; + RECT 16.650 179.040 16.930 179.320 ; LAYER met3 ; +<<<<<<< HEAD + RECT 299.985 438.410 300.315 438.425 ; + RECT 310.000 438.410 314.000 438.800 ; + RECT 299.985 438.200 314.000 438.410 ; + RECT 299.985 438.110 310.500 438.200 ; + RECT 299.985 438.095 300.315 438.110 ; + RECT -4.800 179.330 2.400 179.780 ; + RECT 16.625 179.330 16.955 179.345 ; + RECT -4.800 179.030 16.955 179.330 ; + RECT -4.800 178.580 2.400 179.030 ; + RECT 16.625 179.015 16.955 179.030 ; +======= RECT -4.800 178.580 0.300 179.780 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[37] PIN io_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2619.310 793.460 2619.630 793.520 ; + RECT 2898.990 793.460 2899.310 793.520 ; + RECT 2619.310 793.320 2899.310 793.460 ; + RECT 2619.310 793.260 2619.630 793.320 ; + RECT 2898.990 793.260 2899.310 793.320 ; + LAYER via ; + RECT 2619.340 793.260 2619.600 793.520 ; + RECT 2899.020 793.260 2899.280 793.520 ; + LAYER met2 ; + RECT 2619.330 892.995 2619.610 893.365 ; + RECT 2619.400 793.550 2619.540 892.995 ; + RECT 2619.340 793.230 2619.600 793.550 ; + RECT 2899.020 793.230 2899.280 793.550 ; + RECT 2899.080 792.045 2899.220 793.230 ; + RECT 2899.010 791.675 2899.290 792.045 ; + LAYER via2 ; + RECT 2619.330 893.040 2619.610 893.320 ; + RECT 2899.010 791.720 2899.290 792.000 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 893.330 2610.000 893.720 ; + RECT 2619.305 893.330 2619.635 893.345 ; + RECT 2606.000 893.120 2619.635 893.330 ; + RECT 2609.580 893.030 2619.635 893.120 ; + RECT 2619.305 893.015 2619.635 893.030 ; + RECT 2898.985 792.010 2899.315 792.025 ; + RECT 2917.600 792.010 2924.800 792.460 ; + RECT 2898.985 791.710 2924.800 792.010 ; + RECT 2898.985 791.695 2899.315 791.710 ; + RECT 2917.600 791.260 2924.800 791.710 ; +======= RECT 2919.700 791.260 2924.800 792.460 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[3] PIN io_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2619.310 1028.060 2619.630 1028.120 ; + RECT 2898.990 1028.060 2899.310 1028.120 ; + RECT 2619.310 1027.920 2899.310 1028.060 ; + RECT 2619.310 1027.860 2619.630 1027.920 ; + RECT 2898.990 1027.860 2899.310 1027.920 ; + LAYER via ; + RECT 2619.340 1027.860 2619.600 1028.120 ; + RECT 2899.020 1027.860 2899.280 1028.120 ; + LAYER met2 ; + RECT 2619.330 1092.915 2619.610 1093.285 ; + RECT 2619.400 1028.150 2619.540 1092.915 ; + RECT 2619.340 1027.830 2619.600 1028.150 ; + RECT 2899.020 1027.830 2899.280 1028.150 ; + RECT 2899.080 1026.645 2899.220 1027.830 ; + RECT 2899.010 1026.275 2899.290 1026.645 ; + LAYER via2 ; + RECT 2619.330 1092.960 2619.610 1093.240 ; + RECT 2899.010 1026.320 2899.290 1026.600 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1093.250 2610.000 1093.640 ; + RECT 2619.305 1093.250 2619.635 1093.265 ; + RECT 2606.000 1093.040 2619.635 1093.250 ; + RECT 2609.580 1092.950 2619.635 1093.040 ; + RECT 2619.305 1092.935 2619.635 1092.950 ; + RECT 2898.985 1026.610 2899.315 1026.625 ; + RECT 2917.600 1026.610 2924.800 1027.060 ; + RECT 2898.985 1026.310 2924.800 1026.610 ; + RECT 2898.985 1026.295 2899.315 1026.310 ; + RECT 2917.600 1025.860 2924.800 1026.310 ; +======= RECT 2919.700 1025.860 2924.800 1027.060 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[4] PIN io_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 1262.660 2618.710 1262.720 ; + RECT 2898.990 1262.660 2899.310 1262.720 ; + RECT 2618.390 1262.520 2899.310 1262.660 ; + RECT 2618.390 1262.460 2618.710 1262.520 ; + RECT 2898.990 1262.460 2899.310 1262.520 ; + LAYER via ; + RECT 2618.420 1262.460 2618.680 1262.720 ; + RECT 2899.020 1262.460 2899.280 1262.720 ; + LAYER met2 ; + RECT 2618.410 1292.835 2618.690 1293.205 ; + RECT 2618.480 1262.750 2618.620 1292.835 ; + RECT 2618.420 1262.430 2618.680 1262.750 ; + RECT 2899.020 1262.430 2899.280 1262.750 ; + RECT 2899.080 1261.245 2899.220 1262.430 ; + RECT 2899.010 1260.875 2899.290 1261.245 ; + LAYER via2 ; + RECT 2618.410 1292.880 2618.690 1293.160 ; + RECT 2899.010 1260.920 2899.290 1261.200 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1293.170 2610.000 1293.560 ; + RECT 2618.385 1293.170 2618.715 1293.185 ; + RECT 2606.000 1292.960 2618.715 1293.170 ; + RECT 2609.580 1292.870 2618.715 1292.960 ; + RECT 2618.385 1292.855 2618.715 1292.870 ; + RECT 2898.985 1261.210 2899.315 1261.225 ; + RECT 2917.600 1261.210 2924.800 1261.660 ; + RECT 2898.985 1260.910 2924.800 1261.210 ; + RECT 2898.985 1260.895 2899.315 1260.910 ; + RECT 2917.600 1260.460 2924.800 1260.910 ; +======= RECT 2919.700 1260.460 2924.800 1261.660 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[5] PIN io_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.610 1493.860 2621.930 1493.920 ; + RECT 2900.830 1493.860 2901.150 1493.920 ; + RECT 2621.610 1493.720 2901.150 1493.860 ; + RECT 2621.610 1493.660 2621.930 1493.720 ; + RECT 2900.830 1493.660 2901.150 1493.720 ; + LAYER via ; + RECT 2621.640 1493.660 2621.900 1493.920 ; + RECT 2900.860 1493.660 2901.120 1493.920 ; + LAYER met2 ; + RECT 2900.850 1495.475 2901.130 1495.845 ; + RECT 2900.920 1493.950 2901.060 1495.475 ; + RECT 2621.640 1493.630 2621.900 1493.950 ; + RECT 2900.860 1493.630 2901.120 1493.950 ; + RECT 2621.700 1493.125 2621.840 1493.630 ; + RECT 2621.630 1492.755 2621.910 1493.125 ; + LAYER via2 ; + RECT 2900.850 1495.520 2901.130 1495.800 ; + RECT 2621.630 1492.800 2621.910 1493.080 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 1495.810 2901.155 1495.825 ; + RECT 2917.600 1495.810 2924.800 1496.260 ; + RECT 2900.825 1495.510 2924.800 1495.810 ; + RECT 2900.825 1495.495 2901.155 1495.510 ; + RECT 2917.600 1495.060 2924.800 1495.510 ; + RECT 2606.000 1493.090 2610.000 1493.480 ; + RECT 2621.605 1493.090 2621.935 1493.105 ; + RECT 2606.000 1492.880 2621.935 1493.090 ; + RECT 2609.580 1492.790 2621.935 1492.880 ; + RECT 2621.605 1492.775 2621.935 1492.790 ; +======= RECT 2919.700 1495.060 2924.800 1496.260 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[6] PIN io_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 1725.400 2619.170 1725.460 ; + RECT 2900.830 1725.400 2901.150 1725.460 ; + RECT 2618.850 1725.260 2901.150 1725.400 ; + RECT 2618.850 1725.200 2619.170 1725.260 ; + RECT 2900.830 1725.200 2901.150 1725.260 ; + LAYER via ; + RECT 2618.880 1725.200 2619.140 1725.460 ; + RECT 2900.860 1725.200 2901.120 1725.460 ; + LAYER met2 ; + RECT 2900.850 1730.075 2901.130 1730.445 ; + RECT 2900.920 1725.490 2901.060 1730.075 ; + RECT 2618.880 1725.170 2619.140 1725.490 ; + RECT 2900.860 1725.170 2901.120 1725.490 ; + RECT 2618.940 1693.045 2619.080 1725.170 ; + RECT 2618.870 1692.675 2619.150 1693.045 ; + LAYER via2 ; + RECT 2900.850 1730.120 2901.130 1730.400 ; + RECT 2618.870 1692.720 2619.150 1693.000 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 1730.410 2901.155 1730.425 ; + RECT 2917.600 1730.410 2924.800 1730.860 ; + RECT 2900.825 1730.110 2924.800 1730.410 ; + RECT 2900.825 1730.095 2901.155 1730.110 ; + RECT 2917.600 1729.660 2924.800 1730.110 ; + RECT 2606.000 1693.010 2610.000 1693.400 ; + RECT 2618.845 1693.010 2619.175 1693.025 ; + RECT 2606.000 1692.800 2619.175 1693.010 ; + RECT 2609.580 1692.710 2619.175 1692.800 ; + RECT 2618.845 1692.695 2619.175 1692.710 ; +======= RECT 2919.700 1729.660 2924.800 1730.860 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[7] PIN io_in[8] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 1960.000 2618.710 1960.060 ; + RECT 2900.830 1960.000 2901.150 1960.060 ; + RECT 2618.390 1959.860 2901.150 1960.000 ; + RECT 2618.390 1959.800 2618.710 1959.860 ; + RECT 2900.830 1959.800 2901.150 1959.860 ; + LAYER via ; + RECT 2618.420 1959.800 2618.680 1960.060 ; + RECT 2900.860 1959.800 2901.120 1960.060 ; + LAYER met2 ; + RECT 2900.850 1964.675 2901.130 1965.045 ; + RECT 2900.920 1960.090 2901.060 1964.675 ; + RECT 2618.420 1959.770 2618.680 1960.090 ; + RECT 2900.860 1959.770 2901.120 1960.090 ; + RECT 2618.480 1893.645 2618.620 1959.770 ; + RECT 2618.410 1893.275 2618.690 1893.645 ; + LAYER via2 ; + RECT 2900.850 1964.720 2901.130 1965.000 ; + RECT 2618.410 1893.320 2618.690 1893.600 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 1965.010 2901.155 1965.025 ; + RECT 2917.600 1965.010 2924.800 1965.460 ; + RECT 2900.825 1964.710 2924.800 1965.010 ; + RECT 2900.825 1964.695 2901.155 1964.710 ; + RECT 2917.600 1964.260 2924.800 1964.710 ; + RECT 2606.000 1893.610 2610.000 1894.000 ; + RECT 2618.385 1893.610 2618.715 1893.625 ; + RECT 2606.000 1893.400 2618.715 1893.610 ; + RECT 2609.580 1893.310 2618.715 1893.400 ; + RECT 2618.385 1893.295 2618.715 1893.310 ; +======= RECT 2919.700 1964.260 2924.800 1965.460 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[8] PIN io_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2194.600 2618.710 2194.660 ; + RECT 2900.830 2194.600 2901.150 2194.660 ; + RECT 2618.390 2194.460 2901.150 2194.600 ; + RECT 2618.390 2194.400 2618.710 2194.460 ; + RECT 2900.830 2194.400 2901.150 2194.460 ; + LAYER via ; + RECT 2618.420 2194.400 2618.680 2194.660 ; + RECT 2900.860 2194.400 2901.120 2194.660 ; + LAYER met2 ; + RECT 2900.850 2199.275 2901.130 2199.645 ; + RECT 2900.920 2194.690 2901.060 2199.275 ; + RECT 2618.420 2194.370 2618.680 2194.690 ; + RECT 2900.860 2194.370 2901.120 2194.690 ; + RECT 2618.480 2093.565 2618.620 2194.370 ; + RECT 2618.410 2093.195 2618.690 2093.565 ; + LAYER via2 ; + RECT 2900.850 2199.320 2901.130 2199.600 ; + RECT 2618.410 2093.240 2618.690 2093.520 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2199.610 2901.155 2199.625 ; + RECT 2917.600 2199.610 2924.800 2200.060 ; + RECT 2900.825 2199.310 2924.800 2199.610 ; + RECT 2900.825 2199.295 2901.155 2199.310 ; + RECT 2917.600 2198.860 2924.800 2199.310 ; + RECT 2606.000 2093.530 2610.000 2093.920 ; + RECT 2618.385 2093.530 2618.715 2093.545 ; + RECT 2606.000 2093.320 2618.715 2093.530 ; + RECT 2609.580 2093.230 2618.715 2093.320 ; + RECT 2618.385 2093.215 2618.715 2093.230 ; +======= RECT 2919.700 2198.860 2924.800 2200.060 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_in[9] PIN io_oeb[0] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 206.960 2618.710 207.020 ; + RECT 2900.830 206.960 2901.150 207.020 ; + RECT 2618.390 206.820 2901.150 206.960 ; + RECT 2618.390 206.760 2618.710 206.820 ; + RECT 2900.830 206.760 2901.150 206.820 ; + LAYER via ; + RECT 2618.420 206.760 2618.680 207.020 ; + RECT 2900.860 206.760 2901.120 207.020 ; + LAYER met2 ; + RECT 2618.410 426.515 2618.690 426.885 ; + RECT 2618.480 207.050 2618.620 426.515 ; + RECT 2618.420 206.730 2618.680 207.050 ; + RECT 2900.860 206.730 2901.120 207.050 ; + RECT 2900.920 205.205 2901.060 206.730 ; + RECT 2900.850 204.835 2901.130 205.205 ; + LAYER via2 ; + RECT 2618.410 426.560 2618.690 426.840 ; + RECT 2900.850 204.880 2901.130 205.160 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 426.850 2610.000 427.240 ; + RECT 2618.385 426.850 2618.715 426.865 ; + RECT 2606.000 426.640 2618.715 426.850 ; + RECT 2609.580 426.550 2618.715 426.640 ; + RECT 2618.385 426.535 2618.715 426.550 ; + RECT 2900.825 205.170 2901.155 205.185 ; + RECT 2917.600 205.170 2924.800 205.620 ; + RECT 2900.825 204.870 2924.800 205.170 ; + RECT 2900.825 204.855 2901.155 204.870 ; + RECT 2917.600 204.420 2924.800 204.870 ; +======= RECT 2919.700 204.420 2924.800 205.620 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[0] PIN io_oeb[10] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 2546.500 2619.170 2546.560 ; + RECT 2900.830 2546.500 2901.150 2546.560 ; + RECT 2618.850 2546.360 2901.150 2546.500 ; + RECT 2618.850 2546.300 2619.170 2546.360 ; + RECT 2900.830 2546.300 2901.150 2546.360 ; + LAYER via ; + RECT 2618.880 2546.300 2619.140 2546.560 ; + RECT 2900.860 2546.300 2901.120 2546.560 ; + LAYER met2 ; + RECT 2900.850 2551.515 2901.130 2551.885 ; + RECT 2900.920 2546.590 2901.060 2551.515 ; + RECT 2618.880 2546.270 2619.140 2546.590 ; + RECT 2900.860 2546.270 2901.120 2546.590 ; + RECT 2618.940 2426.765 2619.080 2546.270 ; + RECT 2618.870 2426.395 2619.150 2426.765 ; + LAYER via2 ; + RECT 2900.850 2551.560 2901.130 2551.840 ; + RECT 2618.870 2426.440 2619.150 2426.720 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2551.850 2901.155 2551.865 ; + RECT 2917.600 2551.850 2924.800 2552.300 ; + RECT 2900.825 2551.550 2924.800 2551.850 ; + RECT 2900.825 2551.535 2901.155 2551.550 ; + RECT 2917.600 2551.100 2924.800 2551.550 ; + RECT 2606.000 2426.730 2610.000 2427.120 ; + RECT 2618.845 2426.730 2619.175 2426.745 ; + RECT 2606.000 2426.520 2619.175 2426.730 ; + RECT 2609.580 2426.430 2619.175 2426.520 ; + RECT 2618.845 2426.415 2619.175 2426.430 ; +======= RECT 2919.700 2551.100 2924.800 2552.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[10] PIN io_oeb[11] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 2781.100 2619.170 2781.160 ; + RECT 2900.830 2781.100 2901.150 2781.160 ; + RECT 2618.850 2780.960 2901.150 2781.100 ; + RECT 2618.850 2780.900 2619.170 2780.960 ; + RECT 2900.830 2780.900 2901.150 2780.960 ; + LAYER via ; + RECT 2618.880 2780.900 2619.140 2781.160 ; + RECT 2900.860 2780.900 2901.120 2781.160 ; + LAYER met2 ; + RECT 2900.850 2786.115 2901.130 2786.485 ; + RECT 2900.920 2781.190 2901.060 2786.115 ; + RECT 2618.880 2780.870 2619.140 2781.190 ; + RECT 2900.860 2780.870 2901.120 2781.190 ; + RECT 2618.940 2626.685 2619.080 2780.870 ; + RECT 2618.870 2626.315 2619.150 2626.685 ; + LAYER via2 ; + RECT 2900.850 2786.160 2901.130 2786.440 ; + RECT 2618.870 2626.360 2619.150 2626.640 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2786.450 2901.155 2786.465 ; + RECT 2917.600 2786.450 2924.800 2786.900 ; + RECT 2900.825 2786.150 2924.800 2786.450 ; + RECT 2900.825 2786.135 2901.155 2786.150 ; + RECT 2917.600 2785.700 2924.800 2786.150 ; + RECT 2606.000 2626.650 2610.000 2627.040 ; + RECT 2618.845 2626.650 2619.175 2626.665 ; + RECT 2606.000 2626.440 2619.175 2626.650 ; + RECT 2609.580 2626.350 2619.175 2626.440 ; + RECT 2618.845 2626.335 2619.175 2626.350 ; +======= RECT 2919.700 2785.700 2924.800 2786.900 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[11] PIN io_oeb[12] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2615.630 2829.040 2615.950 2829.100 ; + RECT 2902.210 2829.040 2902.530 2829.100 ; + RECT 2615.630 2828.900 2902.530 2829.040 ; + RECT 2615.630 2828.840 2615.950 2828.900 ; + RECT 2902.210 2828.840 2902.530 2828.900 ; + LAYER via ; + RECT 2615.660 2828.840 2615.920 2829.100 ; + RECT 2902.240 2828.840 2902.500 2829.100 ; + LAYER met2 ; + RECT 2902.230 3020.715 2902.510 3021.085 ; + RECT 2902.300 2829.130 2902.440 3020.715 ; + RECT 2615.660 2828.810 2615.920 2829.130 ; + RECT 2902.240 2828.810 2902.500 2829.130 ; + RECT 2615.720 2826.605 2615.860 2828.810 ; + RECT 2615.650 2826.235 2615.930 2826.605 ; + LAYER via2 ; + RECT 2902.230 3020.760 2902.510 3021.040 ; + RECT 2615.650 2826.280 2615.930 2826.560 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2902.205 3021.050 2902.535 3021.065 ; + RECT 2917.600 3021.050 2924.800 3021.500 ; + RECT 2902.205 3020.750 2924.800 3021.050 ; + RECT 2902.205 3020.735 2902.535 3020.750 ; + RECT 2917.600 3020.300 2924.800 3020.750 ; + RECT 2606.000 2826.570 2610.000 2826.960 ; + RECT 2615.625 2826.570 2615.955 2826.585 ; + RECT 2606.000 2826.360 2615.955 2826.570 ; + RECT 2609.580 2826.270 2615.955 2826.360 ; + RECT 2615.625 2826.255 2615.955 2826.270 ; +======= RECT 2919.700 3020.300 2924.800 3021.500 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[12] PIN io_oeb[13] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2615.630 3028.960 2615.950 3029.020 ; + RECT 2902.210 3028.960 2902.530 3029.020 ; + RECT 2615.630 3028.820 2902.530 3028.960 ; + RECT 2615.630 3028.760 2615.950 3028.820 ; + RECT 2902.210 3028.760 2902.530 3028.820 ; + LAYER via ; + RECT 2615.660 3028.760 2615.920 3029.020 ; + RECT 2902.240 3028.760 2902.500 3029.020 ; + LAYER met2 ; + RECT 2902.230 3255.315 2902.510 3255.685 ; + RECT 2902.300 3029.050 2902.440 3255.315 ; + RECT 2615.660 3028.730 2615.920 3029.050 ; + RECT 2902.240 3028.730 2902.500 3029.050 ; + RECT 2615.720 3026.525 2615.860 3028.730 ; + RECT 2615.650 3026.155 2615.930 3026.525 ; + LAYER via2 ; + RECT 2902.230 3255.360 2902.510 3255.640 ; + RECT 2615.650 3026.200 2615.930 3026.480 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2902.205 3255.650 2902.535 3255.665 ; + RECT 2917.600 3255.650 2924.800 3256.100 ; + RECT 2902.205 3255.350 2924.800 3255.650 ; + RECT 2902.205 3255.335 2902.535 3255.350 ; + RECT 2917.600 3254.900 2924.800 3255.350 ; + RECT 2606.000 3026.490 2610.000 3026.880 ; + RECT 2615.625 3026.490 2615.955 3026.505 ; + RECT 2606.000 3026.280 2615.955 3026.490 ; + RECT 2609.580 3026.190 2615.955 3026.280 ; + RECT 2615.625 3026.175 2615.955 3026.190 ; +======= RECT 2919.700 3254.900 2924.800 3256.100 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[13] PIN io_oeb[14] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 3484.900 2619.170 3484.960 ; + RECT 2900.830 3484.900 2901.150 3484.960 ; + RECT 2618.850 3484.760 2901.150 3484.900 ; + RECT 2618.850 3484.700 2619.170 3484.760 ; + RECT 2900.830 3484.700 2901.150 3484.760 ; + LAYER via ; + RECT 2618.880 3484.700 2619.140 3484.960 ; + RECT 2900.860 3484.700 2901.120 3484.960 ; + LAYER met2 ; + RECT 2900.850 3489.915 2901.130 3490.285 ; + RECT 2900.920 3484.990 2901.060 3489.915 ; + RECT 2618.880 3484.670 2619.140 3484.990 ; + RECT 2900.860 3484.670 2901.120 3484.990 ; + RECT 2618.940 3226.445 2619.080 3484.670 ; + RECT 2618.870 3226.075 2619.150 3226.445 ; + LAYER via2 ; + RECT 2900.850 3489.960 2901.130 3490.240 ; + RECT 2618.870 3226.120 2619.150 3226.400 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 3490.250 2901.155 3490.265 ; + RECT 2917.600 3490.250 2924.800 3490.700 ; + RECT 2900.825 3489.950 2924.800 3490.250 ; + RECT 2900.825 3489.935 2901.155 3489.950 ; + RECT 2917.600 3489.500 2924.800 3489.950 ; + RECT 2606.000 3226.410 2610.000 3226.800 ; + RECT 2618.845 3226.410 2619.175 3226.425 ; + RECT 2606.000 3226.200 2619.175 3226.410 ; + RECT 2609.580 3226.110 2619.175 3226.200 ; + RECT 2618.845 3226.095 2619.175 3226.110 ; +======= RECT 2919.700 3489.500 2924.800 3490.700 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[14] PIN io_oeb[15] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2400.810 3501.560 2401.130 3501.620 ; + RECT 2635.870 3501.560 2636.190 3501.620 ; + RECT 2400.810 3501.420 2636.190 3501.560 ; + RECT 2400.810 3501.360 2401.130 3501.420 ; + RECT 2635.870 3501.360 2636.190 3501.420 ; + RECT 2396.670 3277.500 2396.990 3277.560 ; + RECT 2400.810 3277.500 2401.130 3277.560 ; + RECT 2396.670 3277.360 2401.130 3277.500 ; + RECT 2396.670 3277.300 2396.990 3277.360 ; + RECT 2400.810 3277.300 2401.130 3277.360 ; + LAYER via ; + RECT 2400.840 3501.360 2401.100 3501.620 ; + RECT 2635.900 3501.360 2636.160 3501.620 ; + RECT 2396.700 3277.300 2396.960 3277.560 ; + RECT 2400.840 3277.300 2401.100 3277.560 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2635.750 3517.600 2636.310 3524.800 ; + RECT 2635.960 3501.650 2636.100 3517.600 ; + RECT 2400.840 3501.330 2401.100 3501.650 ; + RECT 2635.900 3501.330 2636.160 3501.650 ; + RECT 2400.900 3277.590 2401.040 3501.330 ; + RECT 2396.700 3277.270 2396.960 3277.590 ; + RECT 2400.840 3277.270 2401.100 3277.590 ; + RECT 2396.760 3260.000 2396.900 3277.270 ; + RECT 2396.650 3256.000 2396.930 3260.000 ; +======= RECT 2635.750 3519.700 2636.310 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[15] PIN io_oeb[16] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2145.510 3501.560 2145.830 3501.620 ; + RECT 2311.570 3501.560 2311.890 3501.620 ; + RECT 2145.510 3501.420 2311.890 3501.560 ; + RECT 2145.510 3501.360 2145.830 3501.420 ; + RECT 2311.570 3501.360 2311.890 3501.420 ; + RECT 2140.910 3277.500 2141.230 3277.560 ; + RECT 2145.510 3277.500 2145.830 3277.560 ; + RECT 2140.910 3277.360 2145.830 3277.500 ; + RECT 2140.910 3277.300 2141.230 3277.360 ; + RECT 2145.510 3277.300 2145.830 3277.360 ; + LAYER via ; + RECT 2145.540 3501.360 2145.800 3501.620 ; + RECT 2311.600 3501.360 2311.860 3501.620 ; + RECT 2140.940 3277.300 2141.200 3277.560 ; + RECT 2145.540 3277.300 2145.800 3277.560 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2311.450 3517.600 2312.010 3524.800 ; + RECT 2311.660 3501.650 2311.800 3517.600 ; + RECT 2145.540 3501.330 2145.800 3501.650 ; + RECT 2311.600 3501.330 2311.860 3501.650 ; + RECT 2145.600 3277.590 2145.740 3501.330 ; + RECT 2140.940 3277.270 2141.200 3277.590 ; + RECT 2145.540 3277.270 2145.800 3277.590 ; + RECT 2141.000 3260.000 2141.140 3277.270 ; + RECT 2140.890 3256.000 2141.170 3260.000 ; +======= RECT 2311.450 3519.700 2312.010 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[16] PIN io_oeb[17] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1890.210 3501.560 1890.530 3501.620 ; + RECT 1987.270 3501.560 1987.590 3501.620 ; + RECT 1890.210 3501.420 1987.590 3501.560 ; + RECT 1890.210 3501.360 1890.530 3501.420 ; + RECT 1987.270 3501.360 1987.590 3501.420 ; + RECT 1885.610 3277.500 1885.930 3277.560 ; + RECT 1890.210 3277.500 1890.530 3277.560 ; + RECT 1885.610 3277.360 1890.530 3277.500 ; + RECT 1885.610 3277.300 1885.930 3277.360 ; + RECT 1890.210 3277.300 1890.530 3277.360 ; + LAYER via ; + RECT 1890.240 3501.360 1890.500 3501.620 ; + RECT 1987.300 3501.360 1987.560 3501.620 ; + RECT 1885.640 3277.300 1885.900 3277.560 ; + RECT 1890.240 3277.300 1890.500 3277.560 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1987.150 3517.600 1987.710 3524.800 ; + RECT 1987.360 3501.650 1987.500 3517.600 ; + RECT 1890.240 3501.330 1890.500 3501.650 ; + RECT 1987.300 3501.330 1987.560 3501.650 ; + RECT 1890.300 3277.590 1890.440 3501.330 ; + RECT 1885.640 3277.270 1885.900 3277.590 ; + RECT 1890.240 3277.270 1890.500 3277.590 ; + RECT 1885.700 3260.000 1885.840 3277.270 ; + RECT 1885.590 3256.000 1885.870 3260.000 ; +======= RECT 1987.150 3519.700 1987.710 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[17] PIN io_oeb[18] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1634.910 3498.500 1635.230 3498.560 ; + RECT 1662.510 3498.500 1662.830 3498.560 ; + RECT 1634.910 3498.360 1662.830 3498.500 ; + RECT 1634.910 3498.300 1635.230 3498.360 ; + RECT 1662.510 3498.300 1662.830 3498.360 ; + RECT 1629.850 3275.800 1630.170 3275.860 ; + RECT 1634.910 3275.800 1635.230 3275.860 ; + RECT 1629.850 3275.660 1635.230 3275.800 ; + RECT 1629.850 3275.600 1630.170 3275.660 ; + RECT 1634.910 3275.600 1635.230 3275.660 ; + LAYER via ; + RECT 1634.940 3498.300 1635.200 3498.560 ; + RECT 1662.540 3498.300 1662.800 3498.560 ; + RECT 1629.880 3275.600 1630.140 3275.860 ; + RECT 1634.940 3275.600 1635.200 3275.860 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1662.390 3517.600 1662.950 3524.800 ; + RECT 1662.600 3498.590 1662.740 3517.600 ; + RECT 1634.940 3498.270 1635.200 3498.590 ; + RECT 1662.540 3498.270 1662.800 3498.590 ; + RECT 1635.000 3275.890 1635.140 3498.270 ; + RECT 1629.880 3275.570 1630.140 3275.890 ; + RECT 1634.940 3275.570 1635.200 3275.890 ; + RECT 1629.940 3260.000 1630.080 3275.570 ; + RECT 1629.830 3256.000 1630.110 3260.000 ; +======= RECT 1662.390 3519.700 1662.950 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[18] PIN io_oeb[19] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1338.210 3274.100 1338.530 3274.160 ; + RECT 1374.550 3274.100 1374.870 3274.160 ; + RECT 1338.210 3273.960 1374.870 3274.100 ; + RECT 1338.210 3273.900 1338.530 3273.960 ; + RECT 1374.550 3273.900 1374.870 3273.960 ; + LAYER via ; + RECT 1338.240 3273.900 1338.500 3274.160 ; + RECT 1374.580 3273.900 1374.840 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1338.090 3517.600 1338.650 3524.800 ; + RECT 1338.300 3274.190 1338.440 3517.600 ; + RECT 1338.240 3273.870 1338.500 3274.190 ; + RECT 1374.580 3273.870 1374.840 3274.190 ; + RECT 1374.640 3260.000 1374.780 3273.870 ; + RECT 1374.530 3256.000 1374.810 3260.000 ; +======= RECT 1338.090 3519.700 1338.650 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[19] PIN io_oeb[1] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 441.560 2618.710 441.620 ; + RECT 2900.830 441.560 2901.150 441.620 ; + RECT 2618.390 441.420 2901.150 441.560 ; + RECT 2618.390 441.360 2618.710 441.420 ; + RECT 2900.830 441.360 2901.150 441.420 ; + LAYER via ; + RECT 2618.420 441.360 2618.680 441.620 ; + RECT 2900.860 441.360 2901.120 441.620 ; + LAYER met2 ; + RECT 2618.410 626.435 2618.690 626.805 ; + RECT 2618.480 441.650 2618.620 626.435 ; + RECT 2618.420 441.330 2618.680 441.650 ; + RECT 2900.860 441.330 2901.120 441.650 ; + RECT 2900.920 439.805 2901.060 441.330 ; + RECT 2900.850 439.435 2901.130 439.805 ; + LAYER via2 ; + RECT 2618.410 626.480 2618.690 626.760 ; + RECT 2900.850 439.480 2901.130 439.760 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 626.770 2610.000 627.160 ; + RECT 2618.385 626.770 2618.715 626.785 ; + RECT 2606.000 626.560 2618.715 626.770 ; + RECT 2609.580 626.470 2618.715 626.560 ; + RECT 2618.385 626.455 2618.715 626.470 ; + RECT 2900.825 439.770 2901.155 439.785 ; + RECT 2917.600 439.770 2924.800 440.220 ; + RECT 2900.825 439.470 2924.800 439.770 ; + RECT 2900.825 439.455 2901.155 439.470 ; + RECT 2917.600 439.020 2924.800 439.470 ; +======= RECT 2919.700 439.020 2924.800 440.220 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[1] PIN io_oeb[20] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1013.910 3274.100 1014.230 3274.160 ; + RECT 1118.790 3274.100 1119.110 3274.160 ; + RECT 1013.910 3273.960 1119.110 3274.100 ; + RECT 1013.910 3273.900 1014.230 3273.960 ; + RECT 1118.790 3273.900 1119.110 3273.960 ; + LAYER via ; + RECT 1013.940 3273.900 1014.200 3274.160 ; + RECT 1118.820 3273.900 1119.080 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1013.790 3517.600 1014.350 3524.800 ; + RECT 1014.000 3274.190 1014.140 3517.600 ; + RECT 1013.940 3273.870 1014.200 3274.190 ; + RECT 1118.820 3273.870 1119.080 3274.190 ; + RECT 1118.880 3260.000 1119.020 3273.870 ; + RECT 1118.770 3256.000 1119.050 3260.000 ; +======= RECT 1013.790 3519.700 1014.350 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[20] PIN io_oeb[21] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER li1 ; + RECT 689.225 3429.325 689.395 3477.435 ; + LAYER mcon ; + RECT 689.225 3477.265 689.395 3477.435 ; + LAYER met1 ; + RECT 688.690 3491.360 689.010 3491.420 ; + RECT 689.610 3491.360 689.930 3491.420 ; + RECT 688.690 3491.220 689.930 3491.360 ; + RECT 688.690 3491.160 689.010 3491.220 ; + RECT 689.610 3491.160 689.930 3491.220 ; + RECT 689.165 3477.420 689.455 3477.465 ; + RECT 689.610 3477.420 689.930 3477.480 ; + RECT 689.165 3477.280 689.930 3477.420 ; + RECT 689.165 3477.235 689.455 3477.280 ; + RECT 689.610 3477.220 689.930 3477.280 ; + RECT 689.150 3429.480 689.470 3429.540 ; + RECT 688.955 3429.340 689.470 3429.480 ; + RECT 689.150 3429.280 689.470 3429.340 ; + RECT 689.150 3395.140 689.470 3395.200 ; + RECT 688.780 3395.000 689.470 3395.140 ; + RECT 688.780 3394.860 688.920 3395.000 ; + RECT 689.150 3394.940 689.470 3395.000 ; + RECT 688.690 3394.600 689.010 3394.860 ; + RECT 688.690 3367.600 689.010 3367.660 ; + RECT 689.610 3367.600 689.930 3367.660 ; + RECT 688.690 3367.460 689.930 3367.600 ; + RECT 688.690 3367.400 689.010 3367.460 ; + RECT 689.610 3367.400 689.930 3367.460 ; + RECT 688.690 3274.780 689.010 3274.840 ; + RECT 863.490 3274.780 863.810 3274.840 ; + RECT 688.690 3274.640 863.810 3274.780 ; + RECT 688.690 3274.580 689.010 3274.640 ; + RECT 863.490 3274.580 863.810 3274.640 ; + LAYER via ; + RECT 688.720 3491.160 688.980 3491.420 ; + RECT 689.640 3491.160 689.900 3491.420 ; + RECT 689.640 3477.220 689.900 3477.480 ; + RECT 689.180 3429.280 689.440 3429.540 ; + RECT 689.180 3394.940 689.440 3395.200 ; + RECT 688.720 3394.600 688.980 3394.860 ; + RECT 688.720 3367.400 688.980 3367.660 ; + RECT 689.640 3367.400 689.900 3367.660 ; + RECT 688.720 3274.580 688.980 3274.840 ; + RECT 863.520 3274.580 863.780 3274.840 ; LAYER met2 ; +<<<<<<< HEAD + RECT 689.030 3517.600 689.590 3524.800 ; + RECT 689.240 3517.370 689.380 3517.600 ; + RECT 688.780 3517.230 689.380 3517.370 ; + RECT 688.780 3491.450 688.920 3517.230 ; + RECT 688.720 3491.130 688.980 3491.450 ; + RECT 689.640 3491.130 689.900 3491.450 ; + RECT 689.700 3477.510 689.840 3491.130 ; + RECT 689.640 3477.190 689.900 3477.510 ; + RECT 689.180 3429.250 689.440 3429.570 ; + RECT 689.240 3395.230 689.380 3429.250 ; + RECT 689.180 3394.910 689.440 3395.230 ; + RECT 688.720 3394.570 688.980 3394.890 ; + RECT 688.780 3367.690 688.920 3394.570 ; + RECT 688.720 3367.370 688.980 3367.690 ; + RECT 689.640 3367.370 689.900 3367.690 ; + RECT 689.700 3318.810 689.840 3367.370 ; + RECT 688.780 3318.670 689.840 3318.810 ; + RECT 688.780 3274.870 688.920 3318.670 ; + RECT 688.720 3274.550 688.980 3274.870 ; + RECT 863.520 3274.550 863.780 3274.870 ; + RECT 863.580 3260.000 863.720 3274.550 ; + RECT 863.470 3256.000 863.750 3260.000 ; +======= RECT 689.030 3519.700 689.590 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[21] PIN io_oeb[22] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER li1 ; + RECT 362.625 3416.065 362.795 3463.835 ; + RECT 363.545 3394.305 363.715 3415.555 ; + RECT 364.005 3284.485 364.175 3332.595 ; + LAYER mcon ; + RECT 362.625 3463.665 362.795 3463.835 ; + RECT 363.545 3415.385 363.715 3415.555 ; + RECT 364.005 3332.425 364.175 3332.595 ; + LAYER met1 ; + RECT 362.565 3463.820 362.855 3463.865 ; + RECT 363.470 3463.820 363.790 3463.880 ; + RECT 362.565 3463.680 363.790 3463.820 ; + RECT 362.565 3463.635 362.855 3463.680 ; + RECT 363.470 3463.620 363.790 3463.680 ; + RECT 362.550 3416.220 362.870 3416.280 ; + RECT 362.355 3416.080 362.870 3416.220 ; + RECT 362.550 3416.020 362.870 3416.080 ; + RECT 362.550 3415.540 362.870 3415.600 ; + RECT 363.485 3415.540 363.775 3415.585 ; + RECT 362.550 3415.400 363.775 3415.540 ; + RECT 362.550 3415.340 362.870 3415.400 ; + RECT 363.485 3415.355 363.775 3415.400 ; + RECT 363.470 3394.460 363.790 3394.520 ; + RECT 363.275 3394.320 363.790 3394.460 ; + RECT 363.470 3394.260 363.790 3394.320 ; + RECT 363.470 3346.520 363.790 3346.580 ; + RECT 364.390 3346.520 364.710 3346.580 ; + RECT 363.470 3346.380 364.710 3346.520 ; + RECT 363.470 3346.320 363.790 3346.380 ; + RECT 364.390 3346.320 364.710 3346.380 ; + RECT 363.945 3332.580 364.235 3332.625 ; + RECT 364.390 3332.580 364.710 3332.640 ; + RECT 363.945 3332.440 364.710 3332.580 ; + RECT 363.945 3332.395 364.235 3332.440 ; + RECT 364.390 3332.380 364.710 3332.440 ; + RECT 363.930 3284.640 364.250 3284.700 ; + RECT 363.735 3284.500 364.250 3284.640 ; + RECT 363.930 3284.440 364.250 3284.500 ; + RECT 363.930 3274.780 364.250 3274.840 ; + RECT 607.730 3274.780 608.050 3274.840 ; + RECT 363.930 3274.640 608.050 3274.780 ; + RECT 363.930 3274.580 364.250 3274.640 ; + RECT 607.730 3274.580 608.050 3274.640 ; + LAYER via ; + RECT 363.500 3463.620 363.760 3463.880 ; + RECT 362.580 3416.020 362.840 3416.280 ; + RECT 362.580 3415.340 362.840 3415.600 ; + RECT 363.500 3394.260 363.760 3394.520 ; + RECT 363.500 3346.320 363.760 3346.580 ; + RECT 364.420 3346.320 364.680 3346.580 ; + RECT 364.420 3332.380 364.680 3332.640 ; + RECT 363.960 3284.440 364.220 3284.700 ; + RECT 363.960 3274.580 364.220 3274.840 ; + RECT 607.760 3274.580 608.020 3274.840 ; LAYER met2 ; +<<<<<<< HEAD + RECT 364.730 3517.600 365.290 3524.800 ; + RECT 364.940 3517.370 365.080 3517.600 ; + RECT 364.020 3517.230 365.080 3517.370 ; + RECT 364.020 3491.530 364.160 3517.230 ; + RECT 363.560 3491.390 364.160 3491.530 ; + RECT 363.560 3463.910 363.700 3491.390 ; + RECT 363.500 3463.590 363.760 3463.910 ; + RECT 362.580 3415.990 362.840 3416.310 ; + RECT 362.640 3415.630 362.780 3415.990 ; + RECT 362.580 3415.310 362.840 3415.630 ; + RECT 363.500 3394.230 363.760 3394.550 ; + RECT 363.560 3346.610 363.700 3394.230 ; + RECT 363.500 3346.290 363.760 3346.610 ; + RECT 364.420 3346.290 364.680 3346.610 ; + RECT 364.480 3332.670 364.620 3346.290 ; + RECT 364.420 3332.350 364.680 3332.670 ; + RECT 363.960 3284.410 364.220 3284.730 ; + RECT 364.020 3274.870 364.160 3284.410 ; + RECT 363.960 3274.550 364.220 3274.870 ; + RECT 607.760 3274.550 608.020 3274.870 ; + RECT 607.820 3260.000 607.960 3274.550 ; + RECT 607.710 3256.000 607.990 3260.000 ; +======= RECT 364.730 3519.700 365.290 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[22] PIN io_oeb[23] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER li1 ; + RECT 40.625 3429.325 40.795 3477.435 ; + LAYER mcon ; + RECT 40.625 3477.265 40.795 3477.435 ; + LAYER met1 ; + RECT 40.090 3491.360 40.410 3491.420 ; + RECT 41.010 3491.360 41.330 3491.420 ; + RECT 40.090 3491.220 41.330 3491.360 ; + RECT 40.090 3491.160 40.410 3491.220 ; + RECT 41.010 3491.160 41.330 3491.220 ; + RECT 40.565 3477.420 40.855 3477.465 ; + RECT 41.010 3477.420 41.330 3477.480 ; + RECT 40.565 3477.280 41.330 3477.420 ; + RECT 40.565 3477.235 40.855 3477.280 ; + RECT 41.010 3477.220 41.330 3477.280 ; + RECT 40.550 3429.480 40.870 3429.540 ; + RECT 40.355 3429.340 40.870 3429.480 ; + RECT 40.550 3429.280 40.870 3429.340 ; + RECT 40.550 3395.140 40.870 3395.200 ; + RECT 40.180 3395.000 40.870 3395.140 ; + RECT 40.180 3394.860 40.320 3395.000 ; + RECT 40.550 3394.940 40.870 3395.000 ; + RECT 40.090 3394.600 40.410 3394.860 ; + RECT 40.090 3367.600 40.410 3367.660 ; + RECT 41.010 3367.600 41.330 3367.660 ; + RECT 40.090 3367.460 41.330 3367.600 ; + RECT 40.090 3367.400 40.410 3367.460 ; + RECT 41.010 3367.400 41.330 3367.460 ; + RECT 40.090 3274.780 40.410 3274.840 ; + RECT 352.430 3274.780 352.750 3274.840 ; + RECT 40.090 3274.640 352.750 3274.780 ; + RECT 40.090 3274.580 40.410 3274.640 ; + RECT 352.430 3274.580 352.750 3274.640 ; + LAYER via ; + RECT 40.120 3491.160 40.380 3491.420 ; + RECT 41.040 3491.160 41.300 3491.420 ; + RECT 41.040 3477.220 41.300 3477.480 ; + RECT 40.580 3429.280 40.840 3429.540 ; + RECT 40.580 3394.940 40.840 3395.200 ; + RECT 40.120 3394.600 40.380 3394.860 ; + RECT 40.120 3367.400 40.380 3367.660 ; + RECT 41.040 3367.400 41.300 3367.660 ; + RECT 40.120 3274.580 40.380 3274.840 ; + RECT 352.460 3274.580 352.720 3274.840 ; LAYER met2 ; +<<<<<<< HEAD + RECT 40.430 3517.600 40.990 3524.800 ; + RECT 40.640 3517.370 40.780 3517.600 ; + RECT 40.180 3517.230 40.780 3517.370 ; + RECT 40.180 3491.450 40.320 3517.230 ; + RECT 40.120 3491.130 40.380 3491.450 ; + RECT 41.040 3491.130 41.300 3491.450 ; + RECT 41.100 3477.510 41.240 3491.130 ; + RECT 41.040 3477.190 41.300 3477.510 ; + RECT 40.580 3429.250 40.840 3429.570 ; + RECT 40.640 3395.230 40.780 3429.250 ; + RECT 40.580 3394.910 40.840 3395.230 ; + RECT 40.120 3394.570 40.380 3394.890 ; + RECT 40.180 3367.690 40.320 3394.570 ; + RECT 40.120 3367.370 40.380 3367.690 ; + RECT 41.040 3367.370 41.300 3367.690 ; + RECT 41.100 3318.810 41.240 3367.370 ; + RECT 40.180 3318.670 41.240 3318.810 ; + RECT 40.180 3274.870 40.320 3318.670 ; + RECT 40.120 3274.550 40.380 3274.870 ; + RECT 352.460 3274.550 352.720 3274.870 ; + RECT 352.520 3260.000 352.660 3274.550 ; + RECT 352.410 3256.000 352.690 3260.000 ; +======= RECT 40.430 3519.700 40.990 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[23] PIN io_oeb[24] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 3084.040 17.870 3084.100 ; + RECT 296.770 3084.040 297.090 3084.100 ; + RECT 17.550 3083.900 297.090 3084.040 ; + RECT 17.550 3083.840 17.870 3083.900 ; + RECT 296.770 3083.840 297.090 3083.900 ; + LAYER via ; + RECT 17.580 3083.840 17.840 3084.100 ; + RECT 296.800 3083.840 297.060 3084.100 ; + LAYER met2 ; + RECT 17.570 3267.555 17.850 3267.925 ; + RECT 17.640 3084.130 17.780 3267.555 ; + RECT 17.580 3083.810 17.840 3084.130 ; + RECT 296.800 3083.810 297.060 3084.130 ; + RECT 296.860 3080.925 297.000 3083.810 ; + RECT 296.790 3080.555 297.070 3080.925 ; + LAYER via2 ; + RECT 17.570 3267.600 17.850 3267.880 ; + RECT 296.790 3080.600 297.070 3080.880 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 3267.890 2.400 3268.340 ; + RECT 17.545 3267.890 17.875 3267.905 ; + RECT -4.800 3267.590 17.875 3267.890 ; + RECT -4.800 3267.140 2.400 3267.590 ; + RECT 17.545 3267.575 17.875 3267.590 ; + RECT 296.765 3080.890 297.095 3080.905 ; + RECT 310.000 3080.890 314.000 3081.280 ; + RECT 296.765 3080.680 314.000 3080.890 ; + RECT 296.765 3080.590 310.500 3080.680 ; + RECT 296.765 3080.575 297.095 3080.590 ; +======= RECT -4.800 3267.140 0.300 3268.340 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[24] PIN io_oeb[25] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 2870.180 17.870 2870.240 ; + RECT 296.770 2870.180 297.090 2870.240 ; + RECT 17.550 2870.040 297.090 2870.180 ; + RECT 17.550 2869.980 17.870 2870.040 ; + RECT 296.770 2869.980 297.090 2870.040 ; + LAYER via ; + RECT 17.580 2869.980 17.840 2870.240 ; + RECT 296.800 2869.980 297.060 2870.240 ; + LAYER met2 ; + RECT 17.570 2979.915 17.850 2980.285 ; + RECT 17.640 2870.270 17.780 2979.915 ; + RECT 17.580 2869.950 17.840 2870.270 ; + RECT 296.800 2869.950 297.060 2870.270 ; + RECT 296.860 2866.725 297.000 2869.950 ; + RECT 296.790 2866.355 297.070 2866.725 ; + LAYER via2 ; + RECT 17.570 2979.960 17.850 2980.240 ; + RECT 296.790 2866.400 297.070 2866.680 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 2980.250 2.400 2980.700 ; + RECT 17.545 2980.250 17.875 2980.265 ; + RECT -4.800 2979.950 17.875 2980.250 ; + RECT -4.800 2979.500 2.400 2979.950 ; + RECT 17.545 2979.935 17.875 2979.950 ; + RECT 296.765 2866.690 297.095 2866.705 ; + RECT 310.000 2866.690 314.000 2867.080 ; + RECT 296.765 2866.480 314.000 2866.690 ; + RECT 296.765 2866.390 310.500 2866.480 ; + RECT 296.765 2866.375 297.095 2866.390 ; +======= RECT -4.800 2979.500 0.300 2980.700 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[25] PIN io_oeb[26] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2656.320 17.410 2656.380 ; + RECT 296.770 2656.320 297.090 2656.380 ; + RECT 17.090 2656.180 297.090 2656.320 ; + RECT 17.090 2656.120 17.410 2656.180 ; + RECT 296.770 2656.120 297.090 2656.180 ; + LAYER via ; + RECT 17.120 2656.120 17.380 2656.380 ; + RECT 296.800 2656.120 297.060 2656.380 ; + LAYER met2 ; + RECT 17.110 2692.955 17.390 2693.325 ; + RECT 17.180 2656.410 17.320 2692.955 ; + RECT 17.120 2656.090 17.380 2656.410 ; + RECT 296.800 2656.090 297.060 2656.410 ; + RECT 296.860 2652.525 297.000 2656.090 ; + RECT 296.790 2652.155 297.070 2652.525 ; + LAYER via2 ; + RECT 17.110 2693.000 17.390 2693.280 ; + RECT 296.790 2652.200 297.070 2652.480 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 2693.290 2.400 2693.740 ; + RECT 17.085 2693.290 17.415 2693.305 ; + RECT -4.800 2692.990 17.415 2693.290 ; + RECT -4.800 2692.540 2.400 2692.990 ; + RECT 17.085 2692.975 17.415 2692.990 ; + RECT 296.765 2652.490 297.095 2652.505 ; + RECT 310.000 2652.490 314.000 2652.880 ; + RECT 296.765 2652.280 314.000 2652.490 ; + RECT 296.765 2652.190 310.500 2652.280 ; + RECT 296.765 2652.175 297.095 2652.190 ; +======= RECT -4.800 2692.540 0.300 2693.740 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[26] PIN io_oeb[27] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2436.000 17.410 2436.060 ; + RECT 296.770 2436.000 297.090 2436.060 ; + RECT 17.090 2435.860 297.090 2436.000 ; + RECT 17.090 2435.800 17.410 2435.860 ; + RECT 296.770 2435.800 297.090 2435.860 ; + LAYER via ; + RECT 17.120 2435.800 17.380 2436.060 ; + RECT 296.800 2435.800 297.060 2436.060 ; + LAYER met2 ; + RECT 296.790 2437.955 297.070 2438.325 ; + RECT 296.860 2436.090 297.000 2437.955 ; + RECT 17.120 2435.770 17.380 2436.090 ; + RECT 296.800 2435.770 297.060 2436.090 ; + RECT 17.180 2405.685 17.320 2435.770 ; + RECT 17.110 2405.315 17.390 2405.685 ; + LAYER via2 ; + RECT 296.790 2438.000 297.070 2438.280 ; + RECT 17.110 2405.360 17.390 2405.640 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2438.290 297.095 2438.305 ; + RECT 310.000 2438.290 314.000 2438.680 ; + RECT 296.765 2438.080 314.000 2438.290 ; + RECT 296.765 2437.990 310.500 2438.080 ; + RECT 296.765 2437.975 297.095 2437.990 ; + RECT -4.800 2405.650 2.400 2406.100 ; + RECT 17.085 2405.650 17.415 2405.665 ; + RECT -4.800 2405.350 17.415 2405.650 ; + RECT -4.800 2404.900 2.400 2405.350 ; + RECT 17.085 2405.335 17.415 2405.350 ; +======= RECT -4.800 2404.900 0.300 2406.100 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[27] PIN io_oeb[28] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2222.140 17.410 2222.200 ; + RECT 296.770 2222.140 297.090 2222.200 ; + RECT 17.090 2222.000 297.090 2222.140 ; + RECT 17.090 2221.940 17.410 2222.000 ; + RECT 296.770 2221.940 297.090 2222.000 ; + LAYER via ; + RECT 17.120 2221.940 17.380 2222.200 ; + RECT 296.800 2221.940 297.060 2222.200 ; + LAYER met2 ; + RECT 296.790 2223.755 297.070 2224.125 ; + RECT 296.860 2222.230 297.000 2223.755 ; + RECT 17.120 2221.910 17.380 2222.230 ; + RECT 296.800 2221.910 297.060 2222.230 ; + RECT 17.180 2118.725 17.320 2221.910 ; + RECT 17.110 2118.355 17.390 2118.725 ; + LAYER via2 ; + RECT 296.790 2223.800 297.070 2224.080 ; + RECT 17.110 2118.400 17.390 2118.680 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2224.090 297.095 2224.105 ; + RECT 310.000 2224.090 314.000 2224.480 ; + RECT 296.765 2223.880 314.000 2224.090 ; + RECT 296.765 2223.790 310.500 2223.880 ; + RECT 296.765 2223.775 297.095 2223.790 ; + RECT -4.800 2118.690 2.400 2119.140 ; + RECT 17.085 2118.690 17.415 2118.705 ; + RECT -4.800 2118.390 17.415 2118.690 ; + RECT -4.800 2117.940 2.400 2118.390 ; + RECT 17.085 2118.375 17.415 2118.390 ; +======= RECT -4.800 2117.940 0.300 2119.140 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[28] PIN io_oeb[29] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 2008.280 18.330 2008.340 ; + RECT 296.770 2008.280 297.090 2008.340 ; + RECT 18.010 2008.140 297.090 2008.280 ; + RECT 18.010 2008.080 18.330 2008.140 ; + RECT 296.770 2008.080 297.090 2008.140 ; + LAYER via ; + RECT 18.040 2008.080 18.300 2008.340 ; + RECT 296.800 2008.080 297.060 2008.340 ; + LAYER met2 ; + RECT 296.790 2009.555 297.070 2009.925 ; + RECT 296.860 2008.370 297.000 2009.555 ; + RECT 18.040 2008.050 18.300 2008.370 ; + RECT 296.800 2008.050 297.060 2008.370 ; + RECT 18.100 1831.085 18.240 2008.050 ; + RECT 18.030 1830.715 18.310 1831.085 ; + LAYER via2 ; + RECT 296.790 2009.600 297.070 2009.880 ; + RECT 18.030 1830.760 18.310 1831.040 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2009.890 297.095 2009.905 ; + RECT 310.000 2009.890 314.000 2010.280 ; + RECT 296.765 2009.680 314.000 2009.890 ; + RECT 296.765 2009.590 310.500 2009.680 ; + RECT 296.765 2009.575 297.095 2009.590 ; + RECT -4.800 1831.050 2.400 1831.500 ; + RECT 18.005 1831.050 18.335 1831.065 ; + RECT -4.800 1830.750 18.335 1831.050 ; + RECT -4.800 1830.300 2.400 1830.750 ; + RECT 18.005 1830.735 18.335 1830.750 ; +======= RECT -4.800 1830.300 0.300 1831.500 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[29] PIN io_oeb[2] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 676.160 2618.710 676.220 ; + RECT 2900.830 676.160 2901.150 676.220 ; + RECT 2618.390 676.020 2901.150 676.160 ; + RECT 2618.390 675.960 2618.710 676.020 ; + RECT 2900.830 675.960 2901.150 676.020 ; + LAYER via ; + RECT 2618.420 675.960 2618.680 676.220 ; + RECT 2900.860 675.960 2901.120 676.220 ; + LAYER met2 ; + RECT 2618.410 826.355 2618.690 826.725 ; + RECT 2618.480 676.250 2618.620 826.355 ; + RECT 2618.420 675.930 2618.680 676.250 ; + RECT 2900.860 675.930 2901.120 676.250 ; + RECT 2900.920 674.405 2901.060 675.930 ; + RECT 2900.850 674.035 2901.130 674.405 ; + LAYER via2 ; + RECT 2618.410 826.400 2618.690 826.680 ; + RECT 2900.850 674.080 2901.130 674.360 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 826.690 2610.000 827.080 ; + RECT 2618.385 826.690 2618.715 826.705 ; + RECT 2606.000 826.480 2618.715 826.690 ; + RECT 2609.580 826.390 2618.715 826.480 ; + RECT 2618.385 826.375 2618.715 826.390 ; + RECT 2900.825 674.370 2901.155 674.385 ; + RECT 2917.600 674.370 2924.800 674.820 ; + RECT 2900.825 674.070 2924.800 674.370 ; + RECT 2900.825 674.055 2901.155 674.070 ; + RECT 2917.600 673.620 2924.800 674.070 ; +======= RECT 2919.700 673.620 2924.800 674.820 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[2] PIN io_oeb[30] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 1794.080 17.410 1794.140 ; + RECT 296.770 1794.080 297.090 1794.140 ; + RECT 17.090 1793.940 297.090 1794.080 ; + RECT 17.090 1793.880 17.410 1793.940 ; + RECT 296.770 1793.880 297.090 1793.940 ; + LAYER via ; + RECT 17.120 1793.880 17.380 1794.140 ; + RECT 296.800 1793.880 297.060 1794.140 ; + LAYER met2 ; + RECT 296.790 1795.355 297.070 1795.725 ; + RECT 296.860 1794.170 297.000 1795.355 ; + RECT 17.120 1793.850 17.380 1794.170 ; + RECT 296.800 1793.850 297.060 1794.170 ; + RECT 17.180 1544.125 17.320 1793.850 ; + RECT 17.110 1543.755 17.390 1544.125 ; + LAYER via2 ; + RECT 296.790 1795.400 297.070 1795.680 ; + RECT 17.110 1543.800 17.390 1544.080 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1795.690 297.095 1795.705 ; + RECT 310.000 1795.690 314.000 1796.080 ; + RECT 296.765 1795.480 314.000 1795.690 ; + RECT 296.765 1795.390 310.500 1795.480 ; + RECT 296.765 1795.375 297.095 1795.390 ; + RECT -4.800 1544.090 2.400 1544.540 ; + RECT 17.085 1544.090 17.415 1544.105 ; + RECT -4.800 1543.790 17.415 1544.090 ; + RECT -4.800 1543.340 2.400 1543.790 ; + RECT 17.085 1543.775 17.415 1543.790 ; +======= RECT -4.800 1543.340 0.300 1544.540 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[30] PIN io_oeb[31] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.470 1580.220 18.790 1580.280 ; + RECT 296.770 1580.220 297.090 1580.280 ; + RECT 18.470 1580.080 297.090 1580.220 ; + RECT 18.470 1580.020 18.790 1580.080 ; + RECT 296.770 1580.020 297.090 1580.080 ; + LAYER via ; + RECT 18.500 1580.020 18.760 1580.280 ; + RECT 296.800 1580.020 297.060 1580.280 ; + LAYER met2 ; + RECT 296.790 1580.475 297.070 1580.845 ; + RECT 296.860 1580.310 297.000 1580.475 ; + RECT 18.500 1579.990 18.760 1580.310 ; + RECT 296.800 1579.990 297.060 1580.310 ; + RECT 18.560 1328.565 18.700 1579.990 ; + RECT 18.490 1328.195 18.770 1328.565 ; + LAYER via2 ; + RECT 296.790 1580.520 297.070 1580.800 ; + RECT 18.490 1328.240 18.770 1328.520 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1580.810 297.095 1580.825 ; + RECT 310.000 1580.810 314.000 1581.200 ; + RECT 296.765 1580.600 314.000 1580.810 ; + RECT 296.765 1580.510 310.500 1580.600 ; + RECT 296.765 1580.495 297.095 1580.510 ; + RECT -4.800 1328.530 2.400 1328.980 ; + RECT 18.465 1328.530 18.795 1328.545 ; + RECT -4.800 1328.230 18.795 1328.530 ; + RECT -4.800 1327.780 2.400 1328.230 ; + RECT 18.465 1328.215 18.795 1328.230 ; +======= RECT -4.800 1327.780 0.300 1328.980 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[31] PIN io_oeb[32] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 1366.360 18.330 1366.420 ; + RECT 296.770 1366.360 297.090 1366.420 ; + RECT 18.010 1366.220 297.090 1366.360 ; + RECT 18.010 1366.160 18.330 1366.220 ; + RECT 296.770 1366.160 297.090 1366.220 ; + LAYER via ; + RECT 18.040 1366.160 18.300 1366.420 ; + RECT 296.800 1366.160 297.060 1366.420 ; + LAYER met2 ; + RECT 18.040 1366.130 18.300 1366.450 ; + RECT 296.790 1366.275 297.070 1366.645 ; + RECT 296.800 1366.130 297.060 1366.275 ; + RECT 18.100 1113.005 18.240 1366.130 ; + RECT 18.030 1112.635 18.310 1113.005 ; + LAYER via2 ; + RECT 296.790 1366.320 297.070 1366.600 ; + RECT 18.030 1112.680 18.310 1112.960 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1366.610 297.095 1366.625 ; + RECT 310.000 1366.610 314.000 1367.000 ; + RECT 296.765 1366.400 314.000 1366.610 ; + RECT 296.765 1366.310 310.500 1366.400 ; + RECT 296.765 1366.295 297.095 1366.310 ; + RECT -4.800 1112.970 2.400 1113.420 ; + RECT 18.005 1112.970 18.335 1112.985 ; + RECT -4.800 1112.670 18.335 1112.970 ; + RECT -4.800 1112.220 2.400 1112.670 ; + RECT 18.005 1112.655 18.335 1112.670 ; +======= RECT -4.800 1112.220 0.300 1113.420 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[32] PIN io_oeb[33] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.470 1145.700 18.790 1145.760 ; + RECT 296.770 1145.700 297.090 1145.760 ; + RECT 18.470 1145.560 297.090 1145.700 ; + RECT 18.470 1145.500 18.790 1145.560 ; + RECT 296.770 1145.500 297.090 1145.560 ; + LAYER via ; + RECT 18.500 1145.500 18.760 1145.760 ; + RECT 296.800 1145.500 297.060 1145.760 ; + LAYER met2 ; + RECT 296.790 1152.075 297.070 1152.445 ; + RECT 296.860 1145.790 297.000 1152.075 ; + RECT 18.500 1145.470 18.760 1145.790 ; + RECT 296.800 1145.470 297.060 1145.790 ; + RECT 18.560 897.445 18.700 1145.470 ; + RECT 18.490 897.075 18.770 897.445 ; + LAYER via2 ; + RECT 296.790 1152.120 297.070 1152.400 ; + RECT 18.490 897.120 18.770 897.400 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1152.410 297.095 1152.425 ; + RECT 310.000 1152.410 314.000 1152.800 ; + RECT 296.765 1152.200 314.000 1152.410 ; + RECT 296.765 1152.110 310.500 1152.200 ; + RECT 296.765 1152.095 297.095 1152.110 ; + RECT -4.800 897.410 2.400 897.860 ; + RECT 18.465 897.410 18.795 897.425 ; + RECT -4.800 897.110 18.795 897.410 ; + RECT -4.800 896.660 2.400 897.110 ; + RECT 18.465 897.095 18.795 897.110 ; +======= RECT -4.800 896.660 0.300 897.860 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[33] PIN io_oeb[34] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 931.840 18.330 931.900 ; + RECT 296.770 931.840 297.090 931.900 ; + RECT 18.010 931.700 297.090 931.840 ; + RECT 18.010 931.640 18.330 931.700 ; + RECT 296.770 931.640 297.090 931.700 ; + LAYER via ; + RECT 18.040 931.640 18.300 931.900 ; + RECT 296.800 931.640 297.060 931.900 ; + LAYER met2 ; + RECT 296.790 937.875 297.070 938.245 ; + RECT 296.860 931.930 297.000 937.875 ; + RECT 18.040 931.610 18.300 931.930 ; + RECT 296.800 931.610 297.060 931.930 ; + RECT 18.100 681.885 18.240 931.610 ; + RECT 18.030 681.515 18.310 681.885 ; + LAYER via2 ; + RECT 296.790 937.920 297.070 938.200 ; + RECT 18.030 681.560 18.310 681.840 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 938.210 297.095 938.225 ; + RECT 310.000 938.210 314.000 938.600 ; + RECT 296.765 938.000 314.000 938.210 ; + RECT 296.765 937.910 310.500 938.000 ; + RECT 296.765 937.895 297.095 937.910 ; + RECT -4.800 681.850 2.400 682.300 ; + RECT 18.005 681.850 18.335 681.865 ; + RECT -4.800 681.550 18.335 681.850 ; + RECT -4.800 681.100 2.400 681.550 ; + RECT 18.005 681.535 18.335 681.550 ; +======= RECT -4.800 681.100 0.300 682.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[34] PIN io_oeb[35] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.470 717.980 18.790 718.040 ; + RECT 296.770 717.980 297.090 718.040 ; + RECT 18.470 717.840 297.090 717.980 ; + RECT 18.470 717.780 18.790 717.840 ; + RECT 296.770 717.780 297.090 717.840 ; + LAYER via ; + RECT 18.500 717.780 18.760 718.040 ; + RECT 296.800 717.780 297.060 718.040 ; + LAYER met2 ; + RECT 296.790 723.675 297.070 724.045 ; + RECT 296.860 718.070 297.000 723.675 ; + RECT 18.500 717.750 18.760 718.070 ; + RECT 296.800 717.750 297.060 718.070 ; + RECT 18.560 466.325 18.700 717.750 ; + RECT 18.490 465.955 18.770 466.325 ; + LAYER via2 ; + RECT 296.790 723.720 297.070 724.000 ; + RECT 18.490 466.000 18.770 466.280 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 724.010 297.095 724.025 ; + RECT 310.000 724.010 314.000 724.400 ; + RECT 296.765 723.800 314.000 724.010 ; + RECT 296.765 723.710 310.500 723.800 ; + RECT 296.765 723.695 297.095 723.710 ; + RECT -4.800 466.290 2.400 466.740 ; + RECT 18.465 466.290 18.795 466.305 ; + RECT -4.800 465.990 18.795 466.290 ; + RECT -4.800 465.540 2.400 465.990 ; + RECT 18.465 465.975 18.795 465.990 ; +======= RECT -4.800 465.540 0.300 466.740 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[35] PIN io_oeb[36] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 503.780 18.330 503.840 ; + RECT 296.770 503.780 297.090 503.840 ; + RECT 18.010 503.640 297.090 503.780 ; + RECT 18.010 503.580 18.330 503.640 ; + RECT 296.770 503.580 297.090 503.640 ; + LAYER via ; + RECT 18.040 503.580 18.300 503.840 ; + RECT 296.800 503.580 297.060 503.840 ; + LAYER met2 ; + RECT 296.790 509.475 297.070 509.845 ; + RECT 296.860 503.870 297.000 509.475 ; + RECT 18.040 503.550 18.300 503.870 ; + RECT 296.800 503.550 297.060 503.870 ; + RECT 18.100 250.765 18.240 503.550 ; + RECT 18.030 250.395 18.310 250.765 ; + LAYER via2 ; + RECT 296.790 509.520 297.070 509.800 ; + RECT 18.030 250.440 18.310 250.720 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 509.810 297.095 509.825 ; + RECT 310.000 509.810 314.000 510.200 ; + RECT 296.765 509.600 314.000 509.810 ; + RECT 296.765 509.510 310.500 509.600 ; + RECT 296.765 509.495 297.095 509.510 ; + RECT -4.800 250.730 2.400 251.180 ; + RECT 18.005 250.730 18.335 250.745 ; + RECT -4.800 250.430 18.335 250.730 ; + RECT -4.800 249.980 2.400 250.430 ; + RECT 18.005 250.415 18.335 250.430 ; +======= RECT -4.800 249.980 0.300 251.180 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[36] PIN io_oeb[37] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 289.920 17.870 289.980 ; + RECT 296.770 289.920 297.090 289.980 ; + RECT 17.550 289.780 297.090 289.920 ; + RECT 17.550 289.720 17.870 289.780 ; + RECT 296.770 289.720 297.090 289.780 ; + LAYER via ; + RECT 17.580 289.720 17.840 289.980 ; + RECT 296.800 289.720 297.060 289.980 ; + LAYER met2 ; + RECT 296.790 295.275 297.070 295.645 ; + RECT 296.860 290.010 297.000 295.275 ; + RECT 17.580 289.690 17.840 290.010 ; + RECT 296.800 289.690 297.060 290.010 ; + RECT 17.640 35.885 17.780 289.690 ; + RECT 17.570 35.515 17.850 35.885 ; + LAYER via2 ; + RECT 296.790 295.320 297.070 295.600 ; + RECT 17.570 35.560 17.850 35.840 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 295.610 297.095 295.625 ; + RECT 310.000 295.610 314.000 296.000 ; + RECT 296.765 295.400 314.000 295.610 ; + RECT 296.765 295.310 310.500 295.400 ; + RECT 296.765 295.295 297.095 295.310 ; + RECT -4.800 35.850 2.400 36.300 ; + RECT 17.545 35.850 17.875 35.865 ; + RECT -4.800 35.550 17.875 35.850 ; + RECT -4.800 35.100 2.400 35.550 ; + RECT 17.545 35.535 17.875 35.550 ; +======= RECT -4.800 35.100 0.300 36.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[37] PIN io_oeb[3] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 910.760 2618.710 910.820 ; + RECT 2900.830 910.760 2901.150 910.820 ; + RECT 2618.390 910.620 2901.150 910.760 ; + RECT 2618.390 910.560 2618.710 910.620 ; + RECT 2900.830 910.560 2901.150 910.620 ; + LAYER via ; + RECT 2618.420 910.560 2618.680 910.820 ; + RECT 2900.860 910.560 2901.120 910.820 ; + LAYER met2 ; + RECT 2618.410 1026.275 2618.690 1026.645 ; + RECT 2618.480 910.850 2618.620 1026.275 ; + RECT 2618.420 910.530 2618.680 910.850 ; + RECT 2900.860 910.530 2901.120 910.850 ; + RECT 2900.920 909.685 2901.060 910.530 ; + RECT 2900.850 909.315 2901.130 909.685 ; + LAYER via2 ; + RECT 2618.410 1026.320 2618.690 1026.600 ; + RECT 2900.850 909.360 2901.130 909.640 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1026.610 2610.000 1027.000 ; + RECT 2618.385 1026.610 2618.715 1026.625 ; + RECT 2606.000 1026.400 2618.715 1026.610 ; + RECT 2609.580 1026.310 2618.715 1026.400 ; + RECT 2618.385 1026.295 2618.715 1026.310 ; + RECT 2900.825 909.650 2901.155 909.665 ; + RECT 2917.600 909.650 2924.800 910.100 ; + RECT 2900.825 909.350 2924.800 909.650 ; + RECT 2900.825 909.335 2901.155 909.350 ; + RECT 2917.600 908.900 2924.800 909.350 ; +======= RECT 2919.700 908.900 2924.800 910.100 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[3] PIN io_oeb[4] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 1145.360 2618.710 1145.420 ; + RECT 2900.830 1145.360 2901.150 1145.420 ; + RECT 2618.390 1145.220 2901.150 1145.360 ; + RECT 2618.390 1145.160 2618.710 1145.220 ; + RECT 2900.830 1145.160 2901.150 1145.220 ; + LAYER via ; + RECT 2618.420 1145.160 2618.680 1145.420 ; + RECT 2900.860 1145.160 2901.120 1145.420 ; + LAYER met2 ; + RECT 2618.410 1226.195 2618.690 1226.565 ; + RECT 2618.480 1145.450 2618.620 1226.195 ; + RECT 2618.420 1145.130 2618.680 1145.450 ; + RECT 2900.860 1145.130 2901.120 1145.450 ; + RECT 2900.920 1144.285 2901.060 1145.130 ; + RECT 2900.850 1143.915 2901.130 1144.285 ; + LAYER via2 ; + RECT 2618.410 1226.240 2618.690 1226.520 ; + RECT 2900.850 1143.960 2901.130 1144.240 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1226.530 2610.000 1226.920 ; + RECT 2618.385 1226.530 2618.715 1226.545 ; + RECT 2606.000 1226.320 2618.715 1226.530 ; + RECT 2609.580 1226.230 2618.715 1226.320 ; + RECT 2618.385 1226.215 2618.715 1226.230 ; + RECT 2900.825 1144.250 2901.155 1144.265 ; + RECT 2917.600 1144.250 2924.800 1144.700 ; + RECT 2900.825 1143.950 2924.800 1144.250 ; + RECT 2900.825 1143.935 2901.155 1143.950 ; + RECT 2917.600 1143.500 2924.800 1143.950 ; +======= RECT 2919.700 1143.500 2924.800 1144.700 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[4] PIN io_oeb[5] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 1379.960 2618.710 1380.020 ; + RECT 2900.830 1379.960 2901.150 1380.020 ; + RECT 2618.390 1379.820 2901.150 1379.960 ; + RECT 2618.390 1379.760 2618.710 1379.820 ; + RECT 2900.830 1379.760 2901.150 1379.820 ; + LAYER via ; + RECT 2618.420 1379.760 2618.680 1380.020 ; + RECT 2900.860 1379.760 2901.120 1380.020 ; + LAYER met2 ; + RECT 2618.410 1426.115 2618.690 1426.485 ; + RECT 2618.480 1380.050 2618.620 1426.115 ; + RECT 2618.420 1379.730 2618.680 1380.050 ; + RECT 2900.860 1379.730 2901.120 1380.050 ; + RECT 2900.920 1378.885 2901.060 1379.730 ; + RECT 2900.850 1378.515 2901.130 1378.885 ; + LAYER via2 ; + RECT 2618.410 1426.160 2618.690 1426.440 ; + RECT 2900.850 1378.560 2901.130 1378.840 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1426.450 2610.000 1426.840 ; + RECT 2618.385 1426.450 2618.715 1426.465 ; + RECT 2606.000 1426.240 2618.715 1426.450 ; + RECT 2609.580 1426.150 2618.715 1426.240 ; + RECT 2618.385 1426.135 2618.715 1426.150 ; + RECT 2900.825 1378.850 2901.155 1378.865 ; + RECT 2917.600 1378.850 2924.800 1379.300 ; + RECT 2900.825 1378.550 2924.800 1378.850 ; + RECT 2900.825 1378.535 2901.155 1378.550 ; + RECT 2917.600 1378.100 2924.800 1378.550 ; +======= RECT 2919.700 1378.100 2924.800 1379.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[5] PIN io_oeb[6] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.610 1614.560 2621.930 1614.620 ; + RECT 2900.830 1614.560 2901.150 1614.620 ; + RECT 2621.610 1614.420 2901.150 1614.560 ; + RECT 2621.610 1614.360 2621.930 1614.420 ; + RECT 2900.830 1614.360 2901.150 1614.420 ; + LAYER via ; + RECT 2621.640 1614.360 2621.900 1614.620 ; + RECT 2900.860 1614.360 2901.120 1614.620 ; + LAYER met2 ; + RECT 2621.630 1626.035 2621.910 1626.405 ; + RECT 2621.700 1614.650 2621.840 1626.035 ; + RECT 2621.640 1614.330 2621.900 1614.650 ; + RECT 2900.860 1614.330 2901.120 1614.650 ; + RECT 2900.920 1613.485 2901.060 1614.330 ; + RECT 2900.850 1613.115 2901.130 1613.485 ; + LAYER via2 ; + RECT 2621.630 1626.080 2621.910 1626.360 ; + RECT 2900.850 1613.160 2901.130 1613.440 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1626.370 2610.000 1626.760 ; + RECT 2621.605 1626.370 2621.935 1626.385 ; + RECT 2606.000 1626.160 2621.935 1626.370 ; + RECT 2609.580 1626.070 2621.935 1626.160 ; + RECT 2621.605 1626.055 2621.935 1626.070 ; + RECT 2900.825 1613.450 2901.155 1613.465 ; + RECT 2917.600 1613.450 2924.800 1613.900 ; + RECT 2900.825 1613.150 2924.800 1613.450 ; + RECT 2900.825 1613.135 2901.155 1613.150 ; + RECT 2917.600 1612.700 2924.800 1613.150 ; +======= RECT 2919.700 1612.700 2924.800 1613.900 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[6] PIN io_oeb[7] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.150 1842.700 2621.470 1842.760 ; + RECT 2900.830 1842.700 2901.150 1842.760 ; + RECT 2621.150 1842.560 2901.150 1842.700 ; + RECT 2621.150 1842.500 2621.470 1842.560 ; + RECT 2900.830 1842.500 2901.150 1842.560 ; + LAYER via ; + RECT 2621.180 1842.500 2621.440 1842.760 ; + RECT 2900.860 1842.500 2901.120 1842.760 ; + LAYER met2 ; + RECT 2900.850 1847.715 2901.130 1848.085 ; + RECT 2900.920 1842.790 2901.060 1847.715 ; + RECT 2621.180 1842.470 2621.440 1842.790 ; + RECT 2900.860 1842.470 2901.120 1842.790 ; + RECT 2621.240 1827.005 2621.380 1842.470 ; + RECT 2621.170 1826.635 2621.450 1827.005 ; + LAYER via2 ; + RECT 2900.850 1847.760 2901.130 1848.040 ; + RECT 2621.170 1826.680 2621.450 1826.960 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 1848.050 2901.155 1848.065 ; + RECT 2917.600 1848.050 2924.800 1848.500 ; + RECT 2900.825 1847.750 2924.800 1848.050 ; + RECT 2900.825 1847.735 2901.155 1847.750 ; + RECT 2917.600 1847.300 2924.800 1847.750 ; + RECT 2606.000 1826.970 2610.000 1827.360 ; + RECT 2621.145 1826.970 2621.475 1826.985 ; + RECT 2606.000 1826.760 2621.475 1826.970 ; + RECT 2609.580 1826.670 2621.475 1826.760 ; + RECT 2621.145 1826.655 2621.475 1826.670 ; +======= RECT 2919.700 1847.300 2924.800 1848.500 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[7] PIN io_oeb[8] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2077.300 2618.710 2077.360 ; + RECT 2900.830 2077.300 2901.150 2077.360 ; + RECT 2618.390 2077.160 2901.150 2077.300 ; + RECT 2618.390 2077.100 2618.710 2077.160 ; + RECT 2900.830 2077.100 2901.150 2077.160 ; + LAYER via ; + RECT 2618.420 2077.100 2618.680 2077.360 ; + RECT 2900.860 2077.100 2901.120 2077.360 ; + LAYER met2 ; + RECT 2900.850 2082.315 2901.130 2082.685 ; + RECT 2900.920 2077.390 2901.060 2082.315 ; + RECT 2618.420 2077.070 2618.680 2077.390 ; + RECT 2900.860 2077.070 2901.120 2077.390 ; + RECT 2618.480 2026.925 2618.620 2077.070 ; + RECT 2618.410 2026.555 2618.690 2026.925 ; + LAYER via2 ; + RECT 2900.850 2082.360 2901.130 2082.640 ; + RECT 2618.410 2026.600 2618.690 2026.880 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2082.650 2901.155 2082.665 ; + RECT 2917.600 2082.650 2924.800 2083.100 ; + RECT 2900.825 2082.350 2924.800 2082.650 ; + RECT 2900.825 2082.335 2901.155 2082.350 ; + RECT 2917.600 2081.900 2924.800 2082.350 ; + RECT 2606.000 2026.890 2610.000 2027.280 ; + RECT 2618.385 2026.890 2618.715 2026.905 ; + RECT 2606.000 2026.680 2618.715 2026.890 ; + RECT 2609.580 2026.590 2618.715 2026.680 ; + RECT 2618.385 2026.575 2618.715 2026.590 ; +======= RECT 2919.700 2081.900 2924.800 2083.100 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[8] PIN io_oeb[9] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2311.900 2618.710 2311.960 ; + RECT 2900.830 2311.900 2901.150 2311.960 ; + RECT 2618.390 2311.760 2901.150 2311.900 ; + RECT 2618.390 2311.700 2618.710 2311.760 ; + RECT 2900.830 2311.700 2901.150 2311.760 ; + LAYER via ; + RECT 2618.420 2311.700 2618.680 2311.960 ; + RECT 2900.860 2311.700 2901.120 2311.960 ; + LAYER met2 ; + RECT 2900.850 2316.915 2901.130 2317.285 ; + RECT 2900.920 2311.990 2901.060 2316.915 ; + RECT 2618.420 2311.670 2618.680 2311.990 ; + RECT 2900.860 2311.670 2901.120 2311.990 ; + RECT 2618.480 2226.845 2618.620 2311.670 ; + RECT 2618.410 2226.475 2618.690 2226.845 ; + LAYER via2 ; + RECT 2900.850 2316.960 2901.130 2317.240 ; + RECT 2618.410 2226.520 2618.690 2226.800 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2317.250 2901.155 2317.265 ; + RECT 2917.600 2317.250 2924.800 2317.700 ; + RECT 2900.825 2316.950 2924.800 2317.250 ; + RECT 2900.825 2316.935 2901.155 2316.950 ; + RECT 2917.600 2316.500 2924.800 2316.950 ; + RECT 2606.000 2226.810 2610.000 2227.200 ; + RECT 2618.385 2226.810 2618.715 2226.825 ; + RECT 2606.000 2226.600 2618.715 2226.810 ; + RECT 2609.580 2226.510 2618.715 2226.600 ; + RECT 2618.385 2226.495 2618.715 2226.510 ; +======= RECT 2919.700 2316.500 2924.800 2317.700 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_oeb[9] PIN io_out[0] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 151.540 2619.170 151.600 ; + RECT 2900.830 151.540 2901.150 151.600 ; + RECT 2618.850 151.400 2901.150 151.540 ; + RECT 2618.850 151.340 2619.170 151.400 ; + RECT 2900.830 151.340 2901.150 151.400 ; + LAYER via ; + RECT 2618.880 151.340 2619.140 151.600 ; + RECT 2900.860 151.340 2901.120 151.600 ; + LAYER met2 ; + RECT 2618.870 359.875 2619.150 360.245 ; + RECT 2618.940 151.630 2619.080 359.875 ; + RECT 2618.880 151.310 2619.140 151.630 ; + RECT 2900.860 151.310 2901.120 151.630 ; + RECT 2900.920 146.725 2901.060 151.310 ; + RECT 2900.850 146.355 2901.130 146.725 ; + LAYER via2 ; + RECT 2618.870 359.920 2619.150 360.200 ; + RECT 2900.850 146.400 2901.130 146.680 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 360.210 2610.000 360.600 ; + RECT 2618.845 360.210 2619.175 360.225 ; + RECT 2606.000 360.000 2619.175 360.210 ; + RECT 2609.580 359.910 2619.175 360.000 ; + RECT 2618.845 359.895 2619.175 359.910 ; + RECT 2900.825 146.690 2901.155 146.705 ; + RECT 2917.600 146.690 2924.800 147.140 ; + RECT 2900.825 146.390 2924.800 146.690 ; + RECT 2900.825 146.375 2901.155 146.390 ; + RECT 2917.600 145.940 2924.800 146.390 ; +======= RECT 2919.700 145.940 2924.800 147.140 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[0] PIN io_out[10] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2491.080 2618.710 2491.140 ; + RECT 2900.830 2491.080 2901.150 2491.140 ; + RECT 2618.390 2490.940 2901.150 2491.080 ; + RECT 2618.390 2490.880 2618.710 2490.940 ; + RECT 2900.830 2490.880 2901.150 2490.940 ; + LAYER via ; + RECT 2618.420 2490.880 2618.680 2491.140 ; + RECT 2900.860 2490.880 2901.120 2491.140 ; + LAYER met2 ; + RECT 2900.850 2493.035 2901.130 2493.405 ; + RECT 2900.920 2491.170 2901.060 2493.035 ; + RECT 2618.420 2490.850 2618.680 2491.170 ; + RECT 2900.860 2490.850 2901.120 2491.170 ; + RECT 2618.480 2360.125 2618.620 2490.850 ; + RECT 2618.410 2359.755 2618.690 2360.125 ; + LAYER via2 ; + RECT 2900.850 2493.080 2901.130 2493.360 ; + RECT 2618.410 2359.800 2618.690 2360.080 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2493.370 2901.155 2493.385 ; + RECT 2917.600 2493.370 2924.800 2493.820 ; + RECT 2900.825 2493.070 2924.800 2493.370 ; + RECT 2900.825 2493.055 2901.155 2493.070 ; + RECT 2917.600 2492.620 2924.800 2493.070 ; + RECT 2606.000 2360.090 2610.000 2360.480 ; + RECT 2618.385 2360.090 2618.715 2360.105 ; + RECT 2606.000 2359.880 2618.715 2360.090 ; + RECT 2609.580 2359.790 2618.715 2359.880 ; + RECT 2618.385 2359.775 2618.715 2359.790 ; +======= RECT 2919.700 2492.620 2924.800 2493.820 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[10] PIN io_out[11] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2617.470 2725.680 2617.790 2725.740 ; + RECT 2900.830 2725.680 2901.150 2725.740 ; + RECT 2617.470 2725.540 2901.150 2725.680 ; + RECT 2617.470 2725.480 2617.790 2725.540 ; + RECT 2900.830 2725.480 2901.150 2725.540 ; + LAYER via ; + RECT 2617.500 2725.480 2617.760 2725.740 ; + RECT 2900.860 2725.480 2901.120 2725.740 ; + LAYER met2 ; + RECT 2900.850 2727.635 2901.130 2728.005 ; + RECT 2900.920 2725.770 2901.060 2727.635 ; + RECT 2617.500 2725.450 2617.760 2725.770 ; + RECT 2900.860 2725.450 2901.120 2725.770 ; + RECT 2617.560 2691.170 2617.700 2725.450 ; + RECT 2617.560 2691.030 2618.620 2691.170 ; + RECT 2618.480 2560.045 2618.620 2691.030 ; + RECT 2618.410 2559.675 2618.690 2560.045 ; + LAYER via2 ; + RECT 2900.850 2727.680 2901.130 2727.960 ; + RECT 2618.410 2559.720 2618.690 2560.000 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2727.970 2901.155 2727.985 ; + RECT 2917.600 2727.970 2924.800 2728.420 ; + RECT 2900.825 2727.670 2924.800 2727.970 ; + RECT 2900.825 2727.655 2901.155 2727.670 ; + RECT 2917.600 2727.220 2924.800 2727.670 ; + RECT 2606.000 2560.010 2610.000 2560.400 ; + RECT 2618.385 2560.010 2618.715 2560.025 ; + RECT 2606.000 2559.800 2618.715 2560.010 ; + RECT 2609.580 2559.710 2618.715 2559.800 ; + RECT 2618.385 2559.695 2618.715 2559.710 ; +======= RECT 2919.700 2727.220 2924.800 2728.420 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[11] PIN io_out[12] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 2960.280 2618.710 2960.340 ; + RECT 2898.990 2960.280 2899.310 2960.340 ; + RECT 2618.390 2960.140 2899.310 2960.280 ; + RECT 2618.390 2960.080 2618.710 2960.140 ; + RECT 2898.990 2960.080 2899.310 2960.140 ; + LAYER via ; + RECT 2618.420 2960.080 2618.680 2960.340 ; + RECT 2899.020 2960.080 2899.280 2960.340 ; + LAYER met2 ; + RECT 2899.010 2962.235 2899.290 2962.605 ; + RECT 2899.080 2960.370 2899.220 2962.235 ; + RECT 2618.420 2960.050 2618.680 2960.370 ; + RECT 2899.020 2960.050 2899.280 2960.370 ; + RECT 2618.480 2759.965 2618.620 2960.050 ; + RECT 2618.410 2759.595 2618.690 2759.965 ; + LAYER via2 ; + RECT 2899.010 2962.280 2899.290 2962.560 ; + RECT 2618.410 2759.640 2618.690 2759.920 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2898.985 2962.570 2899.315 2962.585 ; + RECT 2917.600 2962.570 2924.800 2963.020 ; + RECT 2898.985 2962.270 2924.800 2962.570 ; + RECT 2898.985 2962.255 2899.315 2962.270 ; + RECT 2917.600 2961.820 2924.800 2962.270 ; + RECT 2606.000 2759.930 2610.000 2760.320 ; + RECT 2618.385 2759.930 2618.715 2759.945 ; + RECT 2606.000 2759.720 2618.715 2759.930 ; + RECT 2609.580 2759.630 2618.715 2759.720 ; + RECT 2618.385 2759.615 2618.715 2759.630 ; +======= RECT 2919.700 2961.820 2924.800 2963.020 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[12] PIN io_out[13] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 3194.880 2619.170 3194.940 ; + RECT 2900.830 3194.880 2901.150 3194.940 ; + RECT 2618.850 3194.740 2901.150 3194.880 ; + RECT 2618.850 3194.680 2619.170 3194.740 ; + RECT 2900.830 3194.680 2901.150 3194.740 ; + LAYER via ; + RECT 2618.880 3194.680 2619.140 3194.940 ; + RECT 2900.860 3194.680 2901.120 3194.940 ; + LAYER met2 ; + RECT 2900.850 3196.835 2901.130 3197.205 ; + RECT 2900.920 3194.970 2901.060 3196.835 ; + RECT 2618.880 3194.650 2619.140 3194.970 ; + RECT 2900.860 3194.650 2901.120 3194.970 ; + RECT 2618.940 2959.885 2619.080 3194.650 ; + RECT 2618.870 2959.515 2619.150 2959.885 ; + LAYER via2 ; + RECT 2900.850 3196.880 2901.130 3197.160 ; + RECT 2618.870 2959.560 2619.150 2959.840 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 3197.170 2901.155 3197.185 ; + RECT 2917.600 3197.170 2924.800 3197.620 ; + RECT 2900.825 3196.870 2924.800 3197.170 ; + RECT 2900.825 3196.855 2901.155 3196.870 ; + RECT 2917.600 3196.420 2924.800 3196.870 ; + RECT 2606.000 2959.850 2610.000 2960.240 ; + RECT 2618.845 2959.850 2619.175 2959.865 ; + RECT 2606.000 2959.640 2619.175 2959.850 ; + RECT 2609.580 2959.550 2619.175 2959.640 ; + RECT 2618.845 2959.535 2619.175 2959.550 ; +======= RECT 2919.700 3196.420 2924.800 3197.620 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[13] PIN io_out[14] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 3429.480 2618.710 3429.540 ; + RECT 2900.830 3429.480 2901.150 3429.540 ; + RECT 2618.390 3429.340 2901.150 3429.480 ; + RECT 2618.390 3429.280 2618.710 3429.340 ; + RECT 2900.830 3429.280 2901.150 3429.340 ; + LAYER via ; + RECT 2618.420 3429.280 2618.680 3429.540 ; + RECT 2900.860 3429.280 2901.120 3429.540 ; + LAYER met2 ; + RECT 2900.850 3431.435 2901.130 3431.805 ; + RECT 2900.920 3429.570 2901.060 3431.435 ; + RECT 2618.420 3429.250 2618.680 3429.570 ; + RECT 2900.860 3429.250 2901.120 3429.570 ; + RECT 2618.480 3159.805 2618.620 3429.250 ; + RECT 2618.410 3159.435 2618.690 3159.805 ; + LAYER via2 ; + RECT 2900.850 3431.480 2901.130 3431.760 ; + RECT 2618.410 3159.480 2618.690 3159.760 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 3431.770 2901.155 3431.785 ; + RECT 2917.600 3431.770 2924.800 3432.220 ; + RECT 2900.825 3431.470 2924.800 3431.770 ; + RECT 2900.825 3431.455 2901.155 3431.470 ; + RECT 2917.600 3431.020 2924.800 3431.470 ; + RECT 2606.000 3159.770 2610.000 3160.160 ; + RECT 2618.385 3159.770 2618.715 3159.785 ; + RECT 2606.000 3159.560 2618.715 3159.770 ; + RECT 2609.580 3159.470 2618.715 3159.560 ; + RECT 2618.385 3159.455 2618.715 3159.470 ; +======= RECT 2919.700 3431.020 2924.800 3432.220 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[14] PIN io_out[15] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2483.610 3501.900 2483.930 3501.960 ; + RECT 2717.290 3501.900 2717.610 3501.960 ; + RECT 2483.610 3501.760 2717.610 3501.900 ; + RECT 2483.610 3501.700 2483.930 3501.760 ; + RECT 2717.290 3501.700 2717.610 3501.760 ; + LAYER via ; + RECT 2483.640 3501.700 2483.900 3501.960 ; + RECT 2717.320 3501.700 2717.580 3501.960 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2717.170 3517.600 2717.730 3524.800 ; + RECT 2717.380 3501.990 2717.520 3517.600 ; + RECT 2483.640 3501.670 2483.900 3501.990 ; + RECT 2717.320 3501.670 2717.580 3501.990 ; + RECT 2481.750 3259.650 2482.030 3260.000 ; + RECT 2483.700 3259.650 2483.840 3501.670 ; + RECT 2481.750 3259.510 2483.840 3259.650 ; + RECT 2481.750 3256.000 2482.030 3259.510 ; +======= RECT 2717.170 3519.700 2717.730 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[15] PIN io_out[16] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2228.310 3501.900 2228.630 3501.960 ; + RECT 2392.530 3501.900 2392.850 3501.960 ; + RECT 2228.310 3501.760 2392.850 3501.900 ; + RECT 2228.310 3501.700 2228.630 3501.760 ; + RECT 2392.530 3501.700 2392.850 3501.760 ; + LAYER via ; + RECT 2228.340 3501.700 2228.600 3501.960 ; + RECT 2392.560 3501.700 2392.820 3501.960 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2392.410 3517.600 2392.970 3524.800 ; + RECT 2392.620 3501.990 2392.760 3517.600 ; + RECT 2228.340 3501.670 2228.600 3501.990 ; + RECT 2392.560 3501.670 2392.820 3501.990 ; + RECT 2226.450 3259.650 2226.730 3260.000 ; + RECT 2228.400 3259.650 2228.540 3501.670 ; + RECT 2226.450 3259.510 2228.540 3259.650 ; + RECT 2226.450 3256.000 2226.730 3259.510 ; +======= RECT 2392.410 3519.700 2392.970 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[16] PIN io_out[17] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1973.010 3501.900 1973.330 3501.960 ; + RECT 2068.230 3501.900 2068.550 3501.960 ; + RECT 1973.010 3501.760 2068.550 3501.900 ; + RECT 1973.010 3501.700 1973.330 3501.760 ; + RECT 2068.230 3501.700 2068.550 3501.760 ; + LAYER via ; + RECT 1973.040 3501.700 1973.300 3501.960 ; + RECT 2068.260 3501.700 2068.520 3501.960 ; LAYER met2 ; +<<<<<<< HEAD + RECT 2068.110 3517.600 2068.670 3524.800 ; + RECT 2068.320 3501.990 2068.460 3517.600 ; + RECT 1973.040 3501.670 1973.300 3501.990 ; + RECT 2068.260 3501.670 2068.520 3501.990 ; + RECT 1970.690 3258.970 1970.970 3260.000 ; + RECT 1973.100 3258.970 1973.240 3501.670 ; + RECT 1970.690 3258.830 1973.240 3258.970 ; + RECT 1970.690 3256.000 1970.970 3258.830 ; +======= RECT 2068.110 3519.700 2068.670 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[17] PIN io_out[18] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 1717.710 3501.560 1718.030 3501.620 ; + RECT 1743.930 3501.560 1744.250 3501.620 ; + RECT 1717.710 3501.420 1744.250 3501.560 ; + RECT 1717.710 3501.360 1718.030 3501.420 ; + RECT 1743.930 3501.360 1744.250 3501.420 ; + LAYER via ; + RECT 1717.740 3501.360 1718.000 3501.620 ; + RECT 1743.960 3501.360 1744.220 3501.620 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1743.810 3517.600 1744.370 3524.800 ; + RECT 1744.020 3501.650 1744.160 3517.600 ; + RECT 1717.740 3501.330 1718.000 3501.650 ; + RECT 1743.960 3501.330 1744.220 3501.650 ; + RECT 1714.930 3258.970 1715.210 3260.000 ; + RECT 1717.800 3258.970 1717.940 3501.330 ; + RECT 1714.930 3258.830 1717.940 3258.970 ; + RECT 1714.930 3256.000 1715.210 3258.830 ; +======= RECT 1743.810 3519.700 1744.370 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[18] PIN io_out[19] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER li1 ; + RECT 1420.165 3381.045 1420.335 3429.155 ; + LAYER mcon ; + RECT 1420.165 3428.985 1420.335 3429.155 ; + LAYER met1 ; + RECT 1419.170 3477.760 1419.490 3477.820 ; + RECT 1419.630 3477.760 1419.950 3477.820 ; + RECT 1419.170 3477.620 1419.950 3477.760 ; + RECT 1419.170 3477.560 1419.490 3477.620 ; + RECT 1419.630 3477.560 1419.950 3477.620 ; + RECT 1419.630 3443.080 1419.950 3443.140 ; + RECT 1420.550 3443.080 1420.870 3443.140 ; + RECT 1419.630 3442.940 1420.870 3443.080 ; + RECT 1419.630 3442.880 1419.950 3442.940 ; + RECT 1420.550 3442.880 1420.870 3442.940 ; + RECT 1420.105 3429.140 1420.395 3429.185 ; + RECT 1420.550 3429.140 1420.870 3429.200 ; + RECT 1420.105 3429.000 1420.870 3429.140 ; + RECT 1420.105 3428.955 1420.395 3429.000 ; + RECT 1420.550 3428.940 1420.870 3429.000 ; + RECT 1420.090 3381.200 1420.410 3381.260 ; + RECT 1419.895 3381.060 1420.410 3381.200 ; + RECT 1420.090 3381.000 1420.410 3381.060 ; + RECT 1420.090 3367.600 1420.410 3367.660 ; + RECT 1421.010 3367.600 1421.330 3367.660 ; + RECT 1420.090 3367.460 1421.330 3367.600 ; + RECT 1420.090 3367.400 1420.410 3367.460 ; + RECT 1421.010 3367.400 1421.330 3367.460 ; + RECT 1420.090 3274.100 1420.410 3274.160 ; + RECT 1459.650 3274.100 1459.970 3274.160 ; + RECT 1420.090 3273.960 1459.970 3274.100 ; + RECT 1420.090 3273.900 1420.410 3273.960 ; + RECT 1459.650 3273.900 1459.970 3273.960 ; + LAYER via ; + RECT 1419.200 3477.560 1419.460 3477.820 ; + RECT 1419.660 3477.560 1419.920 3477.820 ; + RECT 1419.660 3442.880 1419.920 3443.140 ; + RECT 1420.580 3442.880 1420.840 3443.140 ; + RECT 1420.580 3428.940 1420.840 3429.200 ; + RECT 1420.120 3381.000 1420.380 3381.260 ; + RECT 1420.120 3367.400 1420.380 3367.660 ; + RECT 1421.040 3367.400 1421.300 3367.660 ; + RECT 1420.120 3273.900 1420.380 3274.160 ; + RECT 1459.680 3273.900 1459.940 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1419.050 3517.600 1419.610 3524.800 ; + RECT 1419.260 3477.850 1419.400 3517.600 ; + RECT 1419.200 3477.530 1419.460 3477.850 ; + RECT 1419.660 3477.530 1419.920 3477.850 ; + RECT 1419.720 3443.170 1419.860 3477.530 ; + RECT 1419.660 3442.850 1419.920 3443.170 ; + RECT 1420.580 3442.850 1420.840 3443.170 ; + RECT 1420.640 3429.230 1420.780 3442.850 ; + RECT 1420.580 3428.910 1420.840 3429.230 ; + RECT 1420.120 3380.970 1420.380 3381.290 ; + RECT 1420.180 3367.690 1420.320 3380.970 ; + RECT 1420.120 3367.370 1420.380 3367.690 ; + RECT 1421.040 3367.370 1421.300 3367.690 ; + RECT 1421.100 3318.810 1421.240 3367.370 ; + RECT 1420.180 3318.670 1421.240 3318.810 ; + RECT 1420.180 3274.190 1420.320 3318.670 ; + RECT 1420.120 3273.870 1420.380 3274.190 ; + RECT 1459.680 3273.870 1459.940 3274.190 ; + RECT 1459.740 3260.000 1459.880 3273.870 ; + RECT 1459.630 3256.000 1459.910 3260.000 ; +======= RECT 1419.050 3519.700 1419.610 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[19] PIN io_out[1] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 386.140 2619.170 386.200 ; + RECT 2900.830 386.140 2901.150 386.200 ; + RECT 2618.850 386.000 2901.150 386.140 ; + RECT 2618.850 385.940 2619.170 386.000 ; + RECT 2900.830 385.940 2901.150 386.000 ; + LAYER via ; + RECT 2618.880 385.940 2619.140 386.200 ; + RECT 2900.860 385.940 2901.120 386.200 ; + LAYER met2 ; + RECT 2618.870 559.795 2619.150 560.165 ; + RECT 2618.940 386.230 2619.080 559.795 ; + RECT 2618.880 385.910 2619.140 386.230 ; + RECT 2900.860 385.910 2901.120 386.230 ; + RECT 2900.920 381.325 2901.060 385.910 ; + RECT 2900.850 380.955 2901.130 381.325 ; + LAYER via2 ; + RECT 2618.870 559.840 2619.150 560.120 ; + RECT 2900.850 381.000 2901.130 381.280 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 560.130 2610.000 560.520 ; + RECT 2618.845 560.130 2619.175 560.145 ; + RECT 2606.000 559.920 2619.175 560.130 ; + RECT 2609.580 559.830 2619.175 559.920 ; + RECT 2618.845 559.815 2619.175 559.830 ; + RECT 2900.825 381.290 2901.155 381.305 ; + RECT 2917.600 381.290 2924.800 381.740 ; + RECT 2900.825 380.990 2924.800 381.290 ; + RECT 2900.825 380.975 2901.155 380.990 ; + RECT 2917.600 380.540 2924.800 380.990 ; +======= RECT 2919.700 380.540 2924.800 381.740 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[1] PIN io_out[20] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER li1 ; + RECT 1095.405 3429.325 1095.575 3477.435 ; + RECT 1095.405 3284.485 1095.575 3332.595 ; + LAYER mcon ; + RECT 1095.405 3477.265 1095.575 3477.435 ; + RECT 1095.405 3332.425 1095.575 3332.595 ; + LAYER met1 ; + RECT 1095.345 3477.420 1095.635 3477.465 ; + RECT 1095.790 3477.420 1096.110 3477.480 ; + RECT 1095.345 3477.280 1096.110 3477.420 ; + RECT 1095.345 3477.235 1095.635 3477.280 ; + RECT 1095.790 3477.220 1096.110 3477.280 ; + RECT 1095.330 3429.480 1095.650 3429.540 ; + RECT 1095.135 3429.340 1095.650 3429.480 ; + RECT 1095.330 3429.280 1095.650 3429.340 ; + RECT 1095.330 3395.140 1095.650 3395.200 ; + RECT 1094.960 3395.000 1095.650 3395.140 ; + RECT 1094.960 3394.860 1095.100 3395.000 ; + RECT 1095.330 3394.940 1095.650 3395.000 ; + RECT 1094.870 3394.600 1095.190 3394.860 ; + RECT 1094.870 3346.520 1095.190 3346.580 ; + RECT 1095.790 3346.520 1096.110 3346.580 ; + RECT 1094.870 3346.380 1096.110 3346.520 ; + RECT 1094.870 3346.320 1095.190 3346.380 ; + RECT 1095.790 3346.320 1096.110 3346.380 ; + RECT 1095.345 3332.580 1095.635 3332.625 ; + RECT 1095.790 3332.580 1096.110 3332.640 ; + RECT 1095.345 3332.440 1096.110 3332.580 ; + RECT 1095.345 3332.395 1095.635 3332.440 ; + RECT 1095.790 3332.380 1096.110 3332.440 ; + RECT 1095.330 3284.640 1095.650 3284.700 ; + RECT 1095.135 3284.500 1095.650 3284.640 ; + RECT 1095.330 3284.440 1095.650 3284.500 ; + RECT 1095.330 3274.440 1095.650 3274.500 ; + RECT 1203.890 3274.440 1204.210 3274.500 ; + RECT 1095.330 3274.300 1204.210 3274.440 ; + RECT 1095.330 3274.240 1095.650 3274.300 ; + RECT 1203.890 3274.240 1204.210 3274.300 ; + LAYER via ; + RECT 1095.820 3477.220 1096.080 3477.480 ; + RECT 1095.360 3429.280 1095.620 3429.540 ; + RECT 1095.360 3394.940 1095.620 3395.200 ; + RECT 1094.900 3394.600 1095.160 3394.860 ; + RECT 1094.900 3346.320 1095.160 3346.580 ; + RECT 1095.820 3346.320 1096.080 3346.580 ; + RECT 1095.820 3332.380 1096.080 3332.640 ; + RECT 1095.360 3284.440 1095.620 3284.700 ; + RECT 1095.360 3274.240 1095.620 3274.500 ; + RECT 1203.920 3274.240 1204.180 3274.500 ; LAYER met2 ; +<<<<<<< HEAD + RECT 1094.750 3517.600 1095.310 3524.800 ; + RECT 1094.960 3517.370 1095.100 3517.600 ; + RECT 1094.500 3517.230 1095.100 3517.370 ; + RECT 1094.500 3478.725 1094.640 3517.230 ; + RECT 1094.430 3478.355 1094.710 3478.725 ; + RECT 1096.270 3477.930 1096.550 3478.045 ; + RECT 1095.880 3477.790 1096.550 3477.930 ; + RECT 1095.880 3477.510 1096.020 3477.790 ; + RECT 1096.270 3477.675 1096.550 3477.790 ; + RECT 1095.820 3477.190 1096.080 3477.510 ; + RECT 1095.360 3429.250 1095.620 3429.570 ; + RECT 1095.420 3395.230 1095.560 3429.250 ; + RECT 1095.360 3394.910 1095.620 3395.230 ; + RECT 1094.900 3394.570 1095.160 3394.890 ; + RECT 1094.960 3346.610 1095.100 3394.570 ; + RECT 1094.900 3346.290 1095.160 3346.610 ; + RECT 1095.820 3346.290 1096.080 3346.610 ; + RECT 1095.880 3332.670 1096.020 3346.290 ; + RECT 1095.820 3332.350 1096.080 3332.670 ; + RECT 1095.360 3284.410 1095.620 3284.730 ; + RECT 1095.420 3274.530 1095.560 3284.410 ; + RECT 1095.360 3274.210 1095.620 3274.530 ; + RECT 1203.920 3274.210 1204.180 3274.530 ; + RECT 1203.980 3260.000 1204.120 3274.210 ; + RECT 1203.870 3256.000 1204.150 3260.000 ; + LAYER via2 ; + RECT 1094.430 3478.400 1094.710 3478.680 ; + RECT 1096.270 3477.720 1096.550 3478.000 ; + LAYER met3 ; + RECT 1094.405 3478.690 1094.735 3478.705 ; + RECT 1094.405 3478.390 1097.250 3478.690 ; + RECT 1094.405 3478.375 1094.735 3478.390 ; + RECT 1096.245 3478.010 1096.575 3478.025 ; + RECT 1096.950 3478.010 1097.250 3478.390 ; + RECT 1096.245 3477.710 1097.250 3478.010 ; + RECT 1096.245 3477.695 1096.575 3477.710 ; +======= RECT 1094.750 3519.700 1095.310 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[20] PIN io_out[21] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER li1 ; + RECT 771.565 3381.045 771.735 3429.155 ; + LAYER mcon ; + RECT 771.565 3428.985 771.735 3429.155 ; + LAYER met1 ; + RECT 770.570 3477.760 770.890 3477.820 ; + RECT 771.030 3477.760 771.350 3477.820 ; + RECT 770.570 3477.620 771.350 3477.760 ; + RECT 770.570 3477.560 770.890 3477.620 ; + RECT 771.030 3477.560 771.350 3477.620 ; + RECT 771.030 3443.080 771.350 3443.140 ; + RECT 771.950 3443.080 772.270 3443.140 ; + RECT 771.030 3442.940 772.270 3443.080 ; + RECT 771.030 3442.880 771.350 3442.940 ; + RECT 771.950 3442.880 772.270 3442.940 ; + RECT 771.505 3429.140 771.795 3429.185 ; + RECT 771.950 3429.140 772.270 3429.200 ; + RECT 771.505 3429.000 772.270 3429.140 ; + RECT 771.505 3428.955 771.795 3429.000 ; + RECT 771.950 3428.940 772.270 3429.000 ; + RECT 771.490 3381.200 771.810 3381.260 ; + RECT 771.295 3381.060 771.810 3381.200 ; + RECT 771.490 3381.000 771.810 3381.060 ; + RECT 771.490 3367.600 771.810 3367.660 ; + RECT 772.410 3367.600 772.730 3367.660 ; + RECT 771.490 3367.460 772.730 3367.600 ; + RECT 771.490 3367.400 771.810 3367.460 ; + RECT 772.410 3367.400 772.730 3367.460 ; + RECT 771.490 3274.100 771.810 3274.160 ; + RECT 948.590 3274.100 948.910 3274.160 ; + RECT 771.490 3273.960 948.910 3274.100 ; + RECT 771.490 3273.900 771.810 3273.960 ; + RECT 948.590 3273.900 948.910 3273.960 ; + LAYER via ; + RECT 770.600 3477.560 770.860 3477.820 ; + RECT 771.060 3477.560 771.320 3477.820 ; + RECT 771.060 3442.880 771.320 3443.140 ; + RECT 771.980 3442.880 772.240 3443.140 ; + RECT 771.980 3428.940 772.240 3429.200 ; + RECT 771.520 3381.000 771.780 3381.260 ; + RECT 771.520 3367.400 771.780 3367.660 ; + RECT 772.440 3367.400 772.700 3367.660 ; + RECT 771.520 3273.900 771.780 3274.160 ; + RECT 948.620 3273.900 948.880 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 770.450 3517.600 771.010 3524.800 ; + RECT 770.660 3477.850 770.800 3517.600 ; + RECT 770.600 3477.530 770.860 3477.850 ; + RECT 771.060 3477.530 771.320 3477.850 ; + RECT 771.120 3443.170 771.260 3477.530 ; + RECT 771.060 3442.850 771.320 3443.170 ; + RECT 771.980 3442.850 772.240 3443.170 ; + RECT 772.040 3429.230 772.180 3442.850 ; + RECT 771.980 3428.910 772.240 3429.230 ; + RECT 771.520 3380.970 771.780 3381.290 ; + RECT 771.580 3367.690 771.720 3380.970 ; + RECT 771.520 3367.370 771.780 3367.690 ; + RECT 772.440 3367.370 772.700 3367.690 ; + RECT 772.500 3318.810 772.640 3367.370 ; + RECT 771.580 3318.670 772.640 3318.810 ; + RECT 771.580 3274.190 771.720 3318.670 ; + RECT 771.520 3273.870 771.780 3274.190 ; + RECT 948.620 3273.870 948.880 3274.190 ; + RECT 948.680 3260.000 948.820 3273.870 ; + RECT 948.570 3256.000 948.850 3260.000 ; +======= RECT 770.450 3519.700 771.010 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[21] PIN io_out[22] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 445.810 3498.500 446.130 3498.560 ; + RECT 448.110 3498.500 448.430 3498.560 ; + RECT 445.810 3498.360 448.430 3498.500 ; + RECT 445.810 3498.300 446.130 3498.360 ; + RECT 448.110 3498.300 448.430 3498.360 ; + RECT 448.110 3274.100 448.430 3274.160 ; + RECT 692.830 3274.100 693.150 3274.160 ; + RECT 448.110 3273.960 693.150 3274.100 ; + RECT 448.110 3273.900 448.430 3273.960 ; + RECT 692.830 3273.900 693.150 3273.960 ; + LAYER via ; + RECT 445.840 3498.300 446.100 3498.560 ; + RECT 448.140 3498.300 448.400 3498.560 ; + RECT 448.140 3273.900 448.400 3274.160 ; + RECT 692.860 3273.900 693.120 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 445.690 3517.600 446.250 3524.800 ; + RECT 445.900 3498.590 446.040 3517.600 ; + RECT 445.840 3498.270 446.100 3498.590 ; + RECT 448.140 3498.270 448.400 3498.590 ; + RECT 448.200 3274.190 448.340 3498.270 ; + RECT 448.140 3273.870 448.400 3274.190 ; + RECT 692.860 3273.870 693.120 3274.190 ; + RECT 692.920 3260.000 693.060 3273.870 ; + RECT 692.810 3256.000 693.090 3260.000 ; +======= RECT 445.690 3519.700 446.250 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[22] PIN io_out[23] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 121.510 3498.500 121.830 3498.560 ; + RECT 123.810 3498.500 124.130 3498.560 ; + RECT 121.510 3498.360 124.130 3498.500 ; + RECT 121.510 3498.300 121.830 3498.360 ; + RECT 123.810 3498.300 124.130 3498.360 ; + RECT 123.810 3274.100 124.130 3274.160 ; + RECT 437.530 3274.100 437.850 3274.160 ; + RECT 123.810 3273.960 437.850 3274.100 ; + RECT 123.810 3273.900 124.130 3273.960 ; + RECT 437.530 3273.900 437.850 3273.960 ; + LAYER via ; + RECT 121.540 3498.300 121.800 3498.560 ; + RECT 123.840 3498.300 124.100 3498.560 ; + RECT 123.840 3273.900 124.100 3274.160 ; + RECT 437.560 3273.900 437.820 3274.160 ; LAYER met2 ; +<<<<<<< HEAD + RECT 121.390 3517.600 121.950 3524.800 ; + RECT 121.600 3498.590 121.740 3517.600 ; + RECT 121.540 3498.270 121.800 3498.590 ; + RECT 123.840 3498.270 124.100 3498.590 ; + RECT 123.900 3274.190 124.040 3498.270 ; + RECT 123.840 3273.870 124.100 3274.190 ; + RECT 437.560 3273.870 437.820 3274.190 ; + RECT 437.620 3260.000 437.760 3273.870 ; + RECT 437.510 3256.000 437.790 3260.000 ; +======= RECT 121.390 3519.700 121.950 3524.800 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[23] PIN io_out[24] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 3153.060 17.410 3153.120 ; + RECT 296.770 3153.060 297.090 3153.120 ; + RECT 17.090 3152.920 297.090 3153.060 ; + RECT 17.090 3152.860 17.410 3152.920 ; + RECT 296.770 3152.860 297.090 3152.920 ; + LAYER via ; + RECT 17.120 3152.860 17.380 3153.120 ; + RECT 296.800 3152.860 297.060 3153.120 ; + LAYER met2 ; + RECT 17.110 3339.635 17.390 3340.005 ; + RECT 17.180 3153.150 17.320 3339.635 ; + RECT 17.120 3152.830 17.380 3153.150 ; + RECT 296.800 3152.830 297.060 3153.150 ; + RECT 296.860 3152.325 297.000 3152.830 ; + RECT 296.790 3151.955 297.070 3152.325 ; + LAYER via2 ; + RECT 17.110 3339.680 17.390 3339.960 ; + RECT 296.790 3152.000 297.070 3152.280 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 3339.970 2.400 3340.420 ; + RECT 17.085 3339.970 17.415 3339.985 ; + RECT -4.800 3339.670 17.415 3339.970 ; + RECT -4.800 3339.220 2.400 3339.670 ; + RECT 17.085 3339.655 17.415 3339.670 ; + RECT 296.765 3152.290 297.095 3152.305 ; + RECT 310.000 3152.290 314.000 3152.680 ; + RECT 296.765 3152.080 314.000 3152.290 ; + RECT 296.765 3151.990 310.500 3152.080 ; + RECT 296.765 3151.975 297.095 3151.990 ; +======= RECT -4.800 3339.220 0.300 3340.420 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[24] PIN io_out[25] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2939.200 17.410 2939.260 ; + RECT 296.770 2939.200 297.090 2939.260 ; + RECT 17.090 2939.060 297.090 2939.200 ; + RECT 17.090 2939.000 17.410 2939.060 ; + RECT 296.770 2939.000 297.090 2939.060 ; + LAYER via ; + RECT 17.120 2939.000 17.380 2939.260 ; + RECT 296.800 2939.000 297.060 2939.260 ; + LAYER met2 ; + RECT 17.110 3051.995 17.390 3052.365 ; + RECT 17.180 2939.290 17.320 3051.995 ; + RECT 17.120 2938.970 17.380 2939.290 ; + RECT 296.800 2938.970 297.060 2939.290 ; + RECT 296.860 2938.125 297.000 2938.970 ; + RECT 296.790 2937.755 297.070 2938.125 ; + LAYER via2 ; + RECT 17.110 3052.040 17.390 3052.320 ; + RECT 296.790 2937.800 297.070 2938.080 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 3052.330 2.400 3052.780 ; + RECT 17.085 3052.330 17.415 3052.345 ; + RECT -4.800 3052.030 17.415 3052.330 ; + RECT -4.800 3051.580 2.400 3052.030 ; + RECT 17.085 3052.015 17.415 3052.030 ; + RECT 296.765 2938.090 297.095 2938.105 ; + RECT 310.000 2938.090 314.000 2938.480 ; + RECT 296.765 2937.880 314.000 2938.090 ; + RECT 296.765 2937.790 310.500 2937.880 ; + RECT 296.765 2937.775 297.095 2937.790 ; +======= RECT -4.800 3051.580 0.300 3052.780 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[25] PIN io_out[26] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2725.340 17.410 2725.400 ; + RECT 296.770 2725.340 297.090 2725.400 ; + RECT 17.090 2725.200 297.090 2725.340 ; + RECT 17.090 2725.140 17.410 2725.200 ; + RECT 296.770 2725.140 297.090 2725.200 ; + LAYER via ; + RECT 17.120 2725.140 17.380 2725.400 ; + RECT 296.800 2725.140 297.060 2725.400 ; + LAYER met2 ; + RECT 17.110 2765.035 17.390 2765.405 ; + RECT 17.180 2725.430 17.320 2765.035 ; + RECT 17.120 2725.110 17.380 2725.430 ; + RECT 296.800 2725.110 297.060 2725.430 ; + RECT 296.860 2723.925 297.000 2725.110 ; + RECT 296.790 2723.555 297.070 2723.925 ; + LAYER via2 ; + RECT 17.110 2765.080 17.390 2765.360 ; + RECT 296.790 2723.600 297.070 2723.880 ; LAYER met3 ; +<<<<<<< HEAD + RECT -4.800 2765.370 2.400 2765.820 ; + RECT 17.085 2765.370 17.415 2765.385 ; + RECT -4.800 2765.070 17.415 2765.370 ; + RECT -4.800 2764.620 2.400 2765.070 ; + RECT 17.085 2765.055 17.415 2765.070 ; + RECT 296.765 2723.890 297.095 2723.905 ; + RECT 310.000 2723.890 314.000 2724.280 ; + RECT 296.765 2723.680 314.000 2723.890 ; + RECT 296.765 2723.590 310.500 2723.680 ; + RECT 296.765 2723.575 297.095 2723.590 ; +======= RECT -4.800 2764.620 0.300 2765.820 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[26] PIN io_out[27] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 16.630 2505.020 16.950 2505.080 ; + RECT 296.770 2505.020 297.090 2505.080 ; + RECT 16.630 2504.880 297.090 2505.020 ; + RECT 16.630 2504.820 16.950 2504.880 ; + RECT 296.770 2504.820 297.090 2504.880 ; + LAYER via ; + RECT 16.660 2504.820 16.920 2505.080 ; + RECT 296.800 2504.820 297.060 2505.080 ; + LAYER met2 ; + RECT 296.790 2509.355 297.070 2509.725 ; + RECT 296.860 2505.110 297.000 2509.355 ; + RECT 16.660 2504.790 16.920 2505.110 ; + RECT 296.800 2504.790 297.060 2505.110 ; + RECT 16.720 2477.765 16.860 2504.790 ; + RECT 16.650 2477.395 16.930 2477.765 ; + LAYER via2 ; + RECT 296.790 2509.400 297.070 2509.680 ; + RECT 16.650 2477.440 16.930 2477.720 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2509.690 297.095 2509.705 ; + RECT 310.000 2509.690 314.000 2510.080 ; + RECT 296.765 2509.480 314.000 2509.690 ; + RECT 296.765 2509.390 310.500 2509.480 ; + RECT 296.765 2509.375 297.095 2509.390 ; + RECT -4.800 2477.730 2.400 2478.180 ; + RECT 16.625 2477.730 16.955 2477.745 ; + RECT -4.800 2477.430 16.955 2477.730 ; + RECT -4.800 2476.980 2.400 2477.430 ; + RECT 16.625 2477.415 16.955 2477.430 ; +======= RECT -4.800 2476.980 0.300 2478.180 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[27] PIN io_out[28] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 2291.160 17.870 2291.220 ; + RECT 296.770 2291.160 297.090 2291.220 ; + RECT 17.550 2291.020 297.090 2291.160 ; + RECT 17.550 2290.960 17.870 2291.020 ; + RECT 296.770 2290.960 297.090 2291.020 ; + LAYER via ; + RECT 17.580 2290.960 17.840 2291.220 ; + RECT 296.800 2290.960 297.060 2291.220 ; + LAYER met2 ; + RECT 296.790 2295.155 297.070 2295.525 ; + RECT 296.860 2291.250 297.000 2295.155 ; + RECT 17.580 2290.930 17.840 2291.250 ; + RECT 296.800 2290.930 297.060 2291.250 ; + RECT 17.640 2190.125 17.780 2290.930 ; + RECT 17.570 2189.755 17.850 2190.125 ; + LAYER via2 ; + RECT 296.790 2295.200 297.070 2295.480 ; + RECT 17.570 2189.800 17.850 2190.080 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2295.490 297.095 2295.505 ; + RECT 310.000 2295.490 314.000 2295.880 ; + RECT 296.765 2295.280 314.000 2295.490 ; + RECT 296.765 2295.190 310.500 2295.280 ; + RECT 296.765 2295.175 297.095 2295.190 ; + RECT -4.800 2190.090 2.400 2190.540 ; + RECT 17.545 2190.090 17.875 2190.105 ; + RECT -4.800 2189.790 17.875 2190.090 ; + RECT -4.800 2189.340 2.400 2189.790 ; + RECT 17.545 2189.775 17.875 2189.790 ; +======= RECT -4.800 2189.340 0.300 2190.540 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[28] PIN io_out[29] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 2077.300 17.410 2077.360 ; + RECT 296.770 2077.300 297.090 2077.360 ; + RECT 17.090 2077.160 297.090 2077.300 ; + RECT 17.090 2077.100 17.410 2077.160 ; + RECT 296.770 2077.100 297.090 2077.160 ; + LAYER via ; + RECT 17.120 2077.100 17.380 2077.360 ; + RECT 296.800 2077.100 297.060 2077.360 ; + LAYER met2 ; + RECT 296.790 2080.955 297.070 2081.325 ; + RECT 296.860 2077.390 297.000 2080.955 ; + RECT 17.120 2077.070 17.380 2077.390 ; + RECT 296.800 2077.070 297.060 2077.390 ; + RECT 17.180 1903.165 17.320 2077.070 ; + RECT 17.110 1902.795 17.390 1903.165 ; + LAYER via2 ; + RECT 296.790 2081.000 297.070 2081.280 ; + RECT 17.110 1902.840 17.390 1903.120 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 2081.290 297.095 2081.305 ; + RECT 310.000 2081.290 314.000 2081.680 ; + RECT 296.765 2081.080 314.000 2081.290 ; + RECT 296.765 2080.990 310.500 2081.080 ; + RECT 296.765 2080.975 297.095 2080.990 ; + RECT -4.800 1903.130 2.400 1903.580 ; + RECT 17.085 1903.130 17.415 1903.145 ; + RECT -4.800 1902.830 17.415 1903.130 ; + RECT -4.800 1902.380 2.400 1902.830 ; + RECT 17.085 1902.815 17.415 1902.830 ; +======= RECT -4.800 1902.380 0.300 1903.580 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[29] PIN io_out[2] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 620.740 2619.170 620.800 ; + RECT 2900.830 620.740 2901.150 620.800 ; + RECT 2618.850 620.600 2901.150 620.740 ; + RECT 2618.850 620.540 2619.170 620.600 ; + RECT 2900.830 620.540 2901.150 620.600 ; + LAYER via ; + RECT 2618.880 620.540 2619.140 620.800 ; + RECT 2900.860 620.540 2901.120 620.800 ; + LAYER met2 ; + RECT 2618.870 759.715 2619.150 760.085 ; + RECT 2618.940 620.830 2619.080 759.715 ; + RECT 2618.880 620.510 2619.140 620.830 ; + RECT 2900.860 620.510 2901.120 620.830 ; + RECT 2900.920 615.925 2901.060 620.510 ; + RECT 2900.850 615.555 2901.130 615.925 ; + LAYER via2 ; + RECT 2618.870 759.760 2619.150 760.040 ; + RECT 2900.850 615.600 2901.130 615.880 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 760.050 2610.000 760.440 ; + RECT 2618.845 760.050 2619.175 760.065 ; + RECT 2606.000 759.840 2619.175 760.050 ; + RECT 2609.580 759.750 2619.175 759.840 ; + RECT 2618.845 759.735 2619.175 759.750 ; + RECT 2900.825 615.890 2901.155 615.905 ; + RECT 2917.600 615.890 2924.800 616.340 ; + RECT 2900.825 615.590 2924.800 615.890 ; + RECT 2900.825 615.575 2901.155 615.590 ; + RECT 2917.600 615.140 2924.800 615.590 ; +======= RECT 2919.700 615.140 2924.800 616.340 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[2] PIN io_out[30] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 1863.100 17.870 1863.160 ; + RECT 296.770 1863.100 297.090 1863.160 ; + RECT 17.550 1862.960 297.090 1863.100 ; + RECT 17.550 1862.900 17.870 1862.960 ; + RECT 296.770 1862.900 297.090 1862.960 ; + LAYER via ; + RECT 17.580 1862.900 17.840 1863.160 ; + RECT 296.800 1862.900 297.060 1863.160 ; + LAYER met2 ; + RECT 296.790 1866.755 297.070 1867.125 ; + RECT 296.860 1863.190 297.000 1866.755 ; + RECT 17.580 1862.870 17.840 1863.190 ; + RECT 296.800 1862.870 297.060 1863.190 ; + RECT 17.640 1615.525 17.780 1862.870 ; + RECT 17.570 1615.155 17.850 1615.525 ; + LAYER via2 ; + RECT 296.790 1866.800 297.070 1867.080 ; + RECT 17.570 1615.200 17.850 1615.480 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1867.090 297.095 1867.105 ; + RECT 310.000 1867.090 314.000 1867.480 ; + RECT 296.765 1866.880 314.000 1867.090 ; + RECT 296.765 1866.790 310.500 1866.880 ; + RECT 296.765 1866.775 297.095 1866.790 ; + RECT -4.800 1615.490 2.400 1615.940 ; + RECT 17.545 1615.490 17.875 1615.505 ; + RECT -4.800 1615.190 17.875 1615.490 ; + RECT -4.800 1614.740 2.400 1615.190 ; + RECT 17.545 1615.175 17.875 1615.190 ; +======= RECT -4.800 1614.740 0.300 1615.940 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[30] PIN io_out[31] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 18.010 1649.240 18.330 1649.300 ; + RECT 296.770 1649.240 297.090 1649.300 ; + RECT 18.010 1649.100 297.090 1649.240 ; + RECT 18.010 1649.040 18.330 1649.100 ; + RECT 296.770 1649.040 297.090 1649.100 ; + LAYER via ; + RECT 18.040 1649.040 18.300 1649.300 ; + RECT 296.800 1649.040 297.060 1649.300 ; + LAYER met2 ; + RECT 296.790 1651.875 297.070 1652.245 ; + RECT 296.860 1649.330 297.000 1651.875 ; + RECT 18.040 1649.010 18.300 1649.330 ; + RECT 296.800 1649.010 297.060 1649.330 ; + RECT 18.100 1400.645 18.240 1649.010 ; + RECT 18.030 1400.275 18.310 1400.645 ; + LAYER via2 ; + RECT 296.790 1651.920 297.070 1652.200 ; + RECT 18.030 1400.320 18.310 1400.600 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1652.210 297.095 1652.225 ; + RECT 310.000 1652.210 314.000 1652.600 ; + RECT 296.765 1652.000 314.000 1652.210 ; + RECT 296.765 1651.910 310.500 1652.000 ; + RECT 296.765 1651.895 297.095 1651.910 ; + RECT -4.800 1400.610 2.400 1401.060 ; + RECT 18.005 1400.610 18.335 1400.625 ; + RECT -4.800 1400.310 18.335 1400.610 ; + RECT -4.800 1399.860 2.400 1400.310 ; + RECT 18.005 1400.295 18.335 1400.310 ; +======= RECT -4.800 1399.860 0.300 1401.060 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[31] PIN io_out[32] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 1435.380 17.870 1435.440 ; + RECT 296.770 1435.380 297.090 1435.440 ; + RECT 17.550 1435.240 297.090 1435.380 ; + RECT 17.550 1435.180 17.870 1435.240 ; + RECT 296.770 1435.180 297.090 1435.240 ; + LAYER via ; + RECT 17.580 1435.180 17.840 1435.440 ; + RECT 296.800 1435.180 297.060 1435.440 ; + LAYER met2 ; + RECT 296.790 1437.675 297.070 1438.045 ; + RECT 296.860 1435.470 297.000 1437.675 ; + RECT 17.580 1435.150 17.840 1435.470 ; + RECT 296.800 1435.150 297.060 1435.470 ; + RECT 17.640 1185.085 17.780 1435.150 ; + RECT 17.570 1184.715 17.850 1185.085 ; + LAYER via2 ; + RECT 296.790 1437.720 297.070 1438.000 ; + RECT 17.570 1184.760 17.850 1185.040 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1438.010 297.095 1438.025 ; + RECT 310.000 1438.010 314.000 1438.400 ; + RECT 296.765 1437.800 314.000 1438.010 ; + RECT 296.765 1437.710 310.500 1437.800 ; + RECT 296.765 1437.695 297.095 1437.710 ; + RECT -4.800 1185.050 2.400 1185.500 ; + RECT 17.545 1185.050 17.875 1185.065 ; + RECT -4.800 1184.750 17.875 1185.050 ; + RECT -4.800 1184.300 2.400 1184.750 ; + RECT 17.545 1184.735 17.875 1184.750 ; +======= RECT -4.800 1184.300 0.300 1185.500 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[32] PIN io_out[33] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 1221.520 17.410 1221.580 ; + RECT 296.770 1221.520 297.090 1221.580 ; + RECT 17.090 1221.380 297.090 1221.520 ; + RECT 17.090 1221.320 17.410 1221.380 ; + RECT 296.770 1221.320 297.090 1221.380 ; + LAYER via ; + RECT 17.120 1221.320 17.380 1221.580 ; + RECT 296.800 1221.320 297.060 1221.580 ; + LAYER met2 ; + RECT 296.790 1223.475 297.070 1223.845 ; + RECT 296.860 1221.610 297.000 1223.475 ; + RECT 17.120 1221.290 17.380 1221.610 ; + RECT 296.800 1221.290 297.060 1221.610 ; + RECT 17.180 969.525 17.320 1221.290 ; + RECT 17.110 969.155 17.390 969.525 ; + LAYER via2 ; + RECT 296.790 1223.520 297.070 1223.800 ; + RECT 17.110 969.200 17.390 969.480 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1223.810 297.095 1223.825 ; + RECT 310.000 1223.810 314.000 1224.200 ; + RECT 296.765 1223.600 314.000 1223.810 ; + RECT 296.765 1223.510 310.500 1223.600 ; + RECT 296.765 1223.495 297.095 1223.510 ; + RECT -4.800 969.490 2.400 969.940 ; + RECT 17.085 969.490 17.415 969.505 ; + RECT -4.800 969.190 17.415 969.490 ; + RECT -4.800 968.740 2.400 969.190 ; + RECT 17.085 969.175 17.415 969.190 ; +======= RECT -4.800 968.740 0.300 969.940 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[33] PIN io_out[34] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 1007.660 17.870 1007.720 ; + RECT 296.770 1007.660 297.090 1007.720 ; + RECT 17.550 1007.520 297.090 1007.660 ; + RECT 17.550 1007.460 17.870 1007.520 ; + RECT 296.770 1007.460 297.090 1007.520 ; + LAYER via ; + RECT 17.580 1007.460 17.840 1007.720 ; + RECT 296.800 1007.460 297.060 1007.720 ; + LAYER met2 ; + RECT 296.790 1009.275 297.070 1009.645 ; + RECT 296.860 1007.750 297.000 1009.275 ; + RECT 17.580 1007.430 17.840 1007.750 ; + RECT 296.800 1007.430 297.060 1007.750 ; + RECT 17.640 753.965 17.780 1007.430 ; + RECT 17.570 753.595 17.850 753.965 ; + LAYER via2 ; + RECT 296.790 1009.320 297.070 1009.600 ; + RECT 17.570 753.640 17.850 753.920 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 1009.610 297.095 1009.625 ; + RECT 310.000 1009.610 314.000 1010.000 ; + RECT 296.765 1009.400 314.000 1009.610 ; + RECT 296.765 1009.310 310.500 1009.400 ; + RECT 296.765 1009.295 297.095 1009.310 ; + RECT -4.800 753.930 2.400 754.380 ; + RECT 17.545 753.930 17.875 753.945 ; + RECT -4.800 753.630 17.875 753.930 ; + RECT -4.800 753.180 2.400 753.630 ; + RECT 17.545 753.615 17.875 753.630 ; +======= RECT -4.800 753.180 0.300 754.380 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[34] PIN io_out[35] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 793.800 17.410 793.860 ; + RECT 296.770 793.800 297.090 793.860 ; + RECT 17.090 793.660 297.090 793.800 ; + RECT 17.090 793.600 17.410 793.660 ; + RECT 296.770 793.600 297.090 793.660 ; + LAYER via ; + RECT 17.120 793.600 17.380 793.860 ; + RECT 296.800 793.600 297.060 793.860 ; + LAYER met2 ; + RECT 296.790 795.075 297.070 795.445 ; + RECT 296.860 793.890 297.000 795.075 ; + RECT 17.120 793.570 17.380 793.890 ; + RECT 296.800 793.570 297.060 793.890 ; + RECT 17.180 538.405 17.320 793.570 ; + RECT 17.110 538.035 17.390 538.405 ; + LAYER via2 ; + RECT 296.790 795.120 297.070 795.400 ; + RECT 17.110 538.080 17.390 538.360 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 795.410 297.095 795.425 ; + RECT 310.000 795.410 314.000 795.800 ; + RECT 296.765 795.200 314.000 795.410 ; + RECT 296.765 795.110 310.500 795.200 ; + RECT 296.765 795.095 297.095 795.110 ; + RECT -4.800 538.370 2.400 538.820 ; + RECT 17.085 538.370 17.415 538.385 ; + RECT -4.800 538.070 17.415 538.370 ; + RECT -4.800 537.620 2.400 538.070 ; + RECT 17.085 538.055 17.415 538.070 ; +======= RECT -4.800 537.620 0.300 538.820 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[35] PIN io_out[36] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.550 579.940 17.870 580.000 ; + RECT 296.770 579.940 297.090 580.000 ; + RECT 17.550 579.800 297.090 579.940 ; + RECT 17.550 579.740 17.870 579.800 ; + RECT 296.770 579.740 297.090 579.800 ; + LAYER via ; + RECT 17.580 579.740 17.840 580.000 ; + RECT 296.800 579.740 297.060 580.000 ; + LAYER met2 ; + RECT 296.790 580.875 297.070 581.245 ; + RECT 296.860 580.030 297.000 580.875 ; + RECT 17.580 579.710 17.840 580.030 ; + RECT 296.800 579.710 297.060 580.030 ; + RECT 17.640 322.845 17.780 579.710 ; + RECT 17.570 322.475 17.850 322.845 ; + LAYER via2 ; + RECT 296.790 580.920 297.070 581.200 ; + RECT 17.570 322.520 17.850 322.800 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 581.210 297.095 581.225 ; + RECT 310.000 581.210 314.000 581.600 ; + RECT 296.765 581.000 314.000 581.210 ; + RECT 296.765 580.910 310.500 581.000 ; + RECT 296.765 580.895 297.095 580.910 ; + RECT -4.800 322.810 2.400 323.260 ; + RECT 17.545 322.810 17.875 322.825 ; + RECT -4.800 322.510 17.875 322.810 ; + RECT -4.800 322.060 2.400 322.510 ; + RECT 17.545 322.495 17.875 322.510 ; +======= RECT -4.800 322.060 0.300 323.260 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[36] PIN io_out[37] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 17.090 366.080 17.410 366.140 ; + RECT 296.770 366.080 297.090 366.140 ; + RECT 17.090 365.940 297.090 366.080 ; + RECT 17.090 365.880 17.410 365.940 ; + RECT 296.770 365.880 297.090 365.940 ; + LAYER via ; + RECT 17.120 365.880 17.380 366.140 ; + RECT 296.800 365.880 297.060 366.140 ; + LAYER met2 ; + RECT 296.790 366.675 297.070 367.045 ; + RECT 296.860 366.170 297.000 366.675 ; + RECT 17.120 365.850 17.380 366.170 ; + RECT 296.800 365.850 297.060 366.170 ; + RECT 17.180 107.285 17.320 365.850 ; + RECT 17.110 106.915 17.390 107.285 ; + LAYER via2 ; + RECT 296.790 366.720 297.070 367.000 ; + RECT 17.110 106.960 17.390 107.240 ; LAYER met3 ; +<<<<<<< HEAD + RECT 296.765 367.010 297.095 367.025 ; + RECT 310.000 367.010 314.000 367.400 ; + RECT 296.765 366.800 314.000 367.010 ; + RECT 296.765 366.710 310.500 366.800 ; + RECT 296.765 366.695 297.095 366.710 ; + RECT -4.800 107.250 2.400 107.700 ; + RECT 17.085 107.250 17.415 107.265 ; + RECT -4.800 106.950 17.415 107.250 ; + RECT -4.800 106.500 2.400 106.950 ; + RECT 17.085 106.935 17.415 106.950 ; +======= RECT -4.800 106.500 0.300 107.700 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[37] PIN io_out[3] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 855.340 2619.170 855.400 ; + RECT 2900.830 855.340 2901.150 855.400 ; + RECT 2618.850 855.200 2901.150 855.340 ; + RECT 2618.850 855.140 2619.170 855.200 ; + RECT 2900.830 855.140 2901.150 855.200 ; + LAYER via ; + RECT 2618.880 855.140 2619.140 855.400 ; + RECT 2900.860 855.140 2901.120 855.400 ; + LAYER met2 ; + RECT 2618.870 959.635 2619.150 960.005 ; + RECT 2618.940 855.430 2619.080 959.635 ; + RECT 2618.880 855.110 2619.140 855.430 ; + RECT 2900.860 855.110 2901.120 855.430 ; + RECT 2900.920 850.525 2901.060 855.110 ; + RECT 2900.850 850.155 2901.130 850.525 ; + LAYER via2 ; + RECT 2618.870 959.680 2619.150 959.960 ; + RECT 2900.850 850.200 2901.130 850.480 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 959.970 2610.000 960.360 ; + RECT 2618.845 959.970 2619.175 959.985 ; + RECT 2606.000 959.760 2619.175 959.970 ; + RECT 2609.580 959.670 2619.175 959.760 ; + RECT 2618.845 959.655 2619.175 959.670 ; + RECT 2900.825 850.490 2901.155 850.505 ; + RECT 2917.600 850.490 2924.800 850.940 ; + RECT 2900.825 850.190 2924.800 850.490 ; + RECT 2900.825 850.175 2901.155 850.190 ; + RECT 2917.600 849.740 2924.800 850.190 ; +======= RECT 2919.700 849.740 2924.800 850.940 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[3] PIN io_out[4] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 1089.940 2619.170 1090.000 ; + RECT 2900.830 1089.940 2901.150 1090.000 ; + RECT 2618.850 1089.800 2901.150 1089.940 ; + RECT 2618.850 1089.740 2619.170 1089.800 ; + RECT 2900.830 1089.740 2901.150 1089.800 ; + LAYER via ; + RECT 2618.880 1089.740 2619.140 1090.000 ; + RECT 2900.860 1089.740 2901.120 1090.000 ; + LAYER met2 ; + RECT 2618.870 1159.555 2619.150 1159.925 ; + RECT 2618.940 1090.030 2619.080 1159.555 ; + RECT 2618.880 1089.710 2619.140 1090.030 ; + RECT 2900.860 1089.710 2901.120 1090.030 ; + RECT 2900.920 1085.125 2901.060 1089.710 ; + RECT 2900.850 1084.755 2901.130 1085.125 ; + LAYER via2 ; + RECT 2618.870 1159.600 2619.150 1159.880 ; + RECT 2900.850 1084.800 2901.130 1085.080 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1159.890 2610.000 1160.280 ; + RECT 2618.845 1159.890 2619.175 1159.905 ; + RECT 2606.000 1159.680 2619.175 1159.890 ; + RECT 2609.580 1159.590 2619.175 1159.680 ; + RECT 2618.845 1159.575 2619.175 1159.590 ; + RECT 2900.825 1085.090 2901.155 1085.105 ; + RECT 2917.600 1085.090 2924.800 1085.540 ; + RECT 2900.825 1084.790 2924.800 1085.090 ; + RECT 2900.825 1084.775 2901.155 1084.790 ; + RECT 2917.600 1084.340 2924.800 1084.790 ; +======= RECT 2919.700 1084.340 2924.800 1085.540 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[4] PIN io_out[5] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 1324.540 2618.710 1324.600 ; + RECT 2900.830 1324.540 2901.150 1324.600 ; + RECT 2618.390 1324.400 2901.150 1324.540 ; + RECT 2618.390 1324.340 2618.710 1324.400 ; + RECT 2900.830 1324.340 2901.150 1324.400 ; + LAYER via ; + RECT 2618.420 1324.340 2618.680 1324.600 ; + RECT 2900.860 1324.340 2901.120 1324.600 ; + LAYER met2 ; + RECT 2618.410 1359.475 2618.690 1359.845 ; + RECT 2618.480 1324.630 2618.620 1359.475 ; + RECT 2618.420 1324.310 2618.680 1324.630 ; + RECT 2900.860 1324.310 2901.120 1324.630 ; + RECT 2900.920 1319.725 2901.060 1324.310 ; + RECT 2900.850 1319.355 2901.130 1319.725 ; + LAYER via2 ; + RECT 2618.410 1359.520 2618.690 1359.800 ; + RECT 2900.850 1319.400 2901.130 1319.680 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1359.810 2610.000 1360.200 ; + RECT 2618.385 1359.810 2618.715 1359.825 ; + RECT 2606.000 1359.600 2618.715 1359.810 ; + RECT 2609.580 1359.510 2618.715 1359.600 ; + RECT 2618.385 1359.495 2618.715 1359.510 ; + RECT 2900.825 1319.690 2901.155 1319.705 ; + RECT 2917.600 1319.690 2924.800 1320.140 ; + RECT 2900.825 1319.390 2924.800 1319.690 ; + RECT 2900.825 1319.375 2901.155 1319.390 ; + RECT 2917.600 1318.940 2924.800 1319.390 ; +======= RECT 2919.700 1318.940 2924.800 1320.140 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[5] PIN io_out[6] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2621.610 1559.140 2621.930 1559.200 ; + RECT 2900.830 1559.140 2901.150 1559.200 ; + RECT 2621.610 1559.000 2901.150 1559.140 ; + RECT 2621.610 1558.940 2621.930 1559.000 ; + RECT 2900.830 1558.940 2901.150 1559.000 ; + LAYER via ; + RECT 2621.640 1558.940 2621.900 1559.200 ; + RECT 2900.860 1558.940 2901.120 1559.200 ; + LAYER met2 ; + RECT 2621.630 1559.395 2621.910 1559.765 ; + RECT 2621.700 1559.230 2621.840 1559.395 ; + RECT 2621.640 1558.910 2621.900 1559.230 ; + RECT 2900.860 1558.910 2901.120 1559.230 ; + RECT 2900.920 1554.325 2901.060 1558.910 ; + RECT 2900.850 1553.955 2901.130 1554.325 ; + LAYER via2 ; + RECT 2621.630 1559.440 2621.910 1559.720 ; + RECT 2900.850 1554.000 2901.130 1554.280 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2606.000 1559.730 2610.000 1560.120 ; + RECT 2621.605 1559.730 2621.935 1559.745 ; + RECT 2606.000 1559.520 2621.935 1559.730 ; + RECT 2609.580 1559.430 2621.935 1559.520 ; + RECT 2621.605 1559.415 2621.935 1559.430 ; + RECT 2900.825 1554.290 2901.155 1554.305 ; + RECT 2917.600 1554.290 2924.800 1554.740 ; + RECT 2900.825 1553.990 2924.800 1554.290 ; + RECT 2900.825 1553.975 2901.155 1553.990 ; + RECT 2917.600 1553.540 2924.800 1553.990 ; +======= RECT 2919.700 1553.540 2924.800 1554.740 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[6] PIN io_out[7] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.390 1787.280 2618.710 1787.340 ; + RECT 2900.830 1787.280 2901.150 1787.340 ; + RECT 2618.390 1787.140 2901.150 1787.280 ; + RECT 2618.390 1787.080 2618.710 1787.140 ; + RECT 2900.830 1787.080 2901.150 1787.140 ; + LAYER via ; + RECT 2618.420 1787.080 2618.680 1787.340 ; + RECT 2900.860 1787.080 2901.120 1787.340 ; + LAYER met2 ; + RECT 2900.850 1789.235 2901.130 1789.605 ; + RECT 2900.920 1787.370 2901.060 1789.235 ; + RECT 2618.420 1787.050 2618.680 1787.370 ; + RECT 2900.860 1787.050 2901.120 1787.370 ; + RECT 2618.480 1759.685 2618.620 1787.050 ; + RECT 2618.410 1759.315 2618.690 1759.685 ; + LAYER via2 ; + RECT 2900.850 1789.280 2901.130 1789.560 ; + RECT 2618.410 1759.360 2618.690 1759.640 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 1789.570 2901.155 1789.585 ; + RECT 2917.600 1789.570 2924.800 1790.020 ; + RECT 2900.825 1789.270 2924.800 1789.570 ; + RECT 2900.825 1789.255 2901.155 1789.270 ; + RECT 2917.600 1788.820 2924.800 1789.270 ; + RECT 2606.000 1759.650 2610.000 1760.040 ; + RECT 2618.385 1759.650 2618.715 1759.665 ; + RECT 2606.000 1759.440 2618.715 1759.650 ; + RECT 2609.580 1759.350 2618.715 1759.440 ; + RECT 2618.385 1759.335 2618.715 1759.350 ; +======= RECT 2919.700 1788.820 2924.800 1790.020 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[7] PIN io_out[8] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 2021.880 2619.170 2021.940 ; + RECT 2900.830 2021.880 2901.150 2021.940 ; + RECT 2618.850 2021.740 2901.150 2021.880 ; + RECT 2618.850 2021.680 2619.170 2021.740 ; + RECT 2900.830 2021.680 2901.150 2021.740 ; + LAYER via ; + RECT 2618.880 2021.680 2619.140 2021.940 ; + RECT 2900.860 2021.680 2901.120 2021.940 ; + LAYER met2 ; + RECT 2900.850 2023.835 2901.130 2024.205 ; + RECT 2900.920 2021.970 2901.060 2023.835 ; + RECT 2618.880 2021.650 2619.140 2021.970 ; + RECT 2900.860 2021.650 2901.120 2021.970 ; + RECT 2618.940 1960.285 2619.080 2021.650 ; + RECT 2618.870 1959.915 2619.150 1960.285 ; + LAYER via2 ; + RECT 2900.850 2023.880 2901.130 2024.160 ; + RECT 2618.870 1959.960 2619.150 1960.240 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2024.170 2901.155 2024.185 ; + RECT 2917.600 2024.170 2924.800 2024.620 ; + RECT 2900.825 2023.870 2924.800 2024.170 ; + RECT 2900.825 2023.855 2901.155 2023.870 ; + RECT 2917.600 2023.420 2924.800 2023.870 ; + RECT 2606.000 1960.250 2610.000 1960.640 ; + RECT 2618.845 1960.250 2619.175 1960.265 ; + RECT 2606.000 1960.040 2619.175 1960.250 ; + RECT 2609.580 1959.950 2619.175 1960.040 ; + RECT 2618.845 1959.935 2619.175 1959.950 ; +======= RECT 2919.700 2023.420 2924.800 2024.620 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[8] PIN io_out[9] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT + LAYER met1 ; + RECT 2618.850 2256.480 2619.170 2256.540 ; + RECT 2900.830 2256.480 2901.150 2256.540 ; + RECT 2618.850 2256.340 2901.150 2256.480 ; + RECT 2618.850 2256.280 2619.170 2256.340 ; + RECT 2900.830 2256.280 2901.150 2256.340 ; + LAYER via ; + RECT 2618.880 2256.280 2619.140 2256.540 ; + RECT 2900.860 2256.280 2901.120 2256.540 ; + LAYER met2 ; + RECT 2900.850 2258.435 2901.130 2258.805 ; + RECT 2900.920 2256.570 2901.060 2258.435 ; + RECT 2618.880 2256.250 2619.140 2256.570 ; + RECT 2900.860 2256.250 2901.120 2256.570 ; + RECT 2618.940 2160.205 2619.080 2256.250 ; + RECT 2618.870 2159.835 2619.150 2160.205 ; + LAYER via2 ; + RECT 2900.850 2258.480 2901.130 2258.760 ; + RECT 2618.870 2159.880 2619.150 2160.160 ; LAYER met3 ; +<<<<<<< HEAD + RECT 2900.825 2258.770 2901.155 2258.785 ; + RECT 2917.600 2258.770 2924.800 2259.220 ; + RECT 2900.825 2258.470 2924.800 2258.770 ; + RECT 2900.825 2258.455 2901.155 2258.470 ; + RECT 2917.600 2258.020 2924.800 2258.470 ; + RECT 2606.000 2160.170 2610.000 2160.560 ; + RECT 2618.845 2160.170 2619.175 2160.185 ; + RECT 2606.000 2159.960 2619.175 2160.170 ; + RECT 2609.580 2159.870 2619.175 2159.960 ; + RECT 2618.845 2159.855 2619.175 2159.870 ; +======= RECT 2919.700 2258.020 2924.800 2259.220 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END io_out[9] PIN la_data_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 324.370 243.680 324.690 243.740 ; + RECT 330.810 243.680 331.130 243.740 ; + RECT 324.370 243.540 331.130 243.680 ; + RECT 324.370 243.480 324.690 243.540 ; + RECT 330.810 243.480 331.130 243.540 ; + RECT 330.810 24.380 331.130 24.440 ; + RECT 633.030 24.380 633.350 24.440 ; + RECT 330.810 24.240 633.350 24.380 ; + RECT 330.810 24.180 331.130 24.240 ; + RECT 633.030 24.180 633.350 24.240 ; + LAYER via ; + RECT 324.400 243.480 324.660 243.740 ; + RECT 330.840 243.480 331.100 243.740 ; + RECT 330.840 24.180 331.100 24.440 ; + RECT 633.060 24.180 633.320 24.440 ; + LAYER met2 ; + RECT 324.350 260.000 324.630 264.000 ; + RECT 324.460 243.770 324.600 260.000 ; + RECT 324.400 243.450 324.660 243.770 ; + RECT 330.840 243.450 331.100 243.770 ; + RECT 330.900 24.470 331.040 243.450 ; + RECT 330.840 24.150 331.100 24.470 ; + RECT 633.060 24.150 633.320 24.470 ; + RECT 633.120 2.400 633.260 24.150 ; + RECT 632.910 -4.800 633.470 2.400 ; +======= LAYER met2 ; RECT 632.910 -4.800 633.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[0] PIN la_data_in[100] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2111.930 241.640 2112.250 241.700 ; + RECT 2117.910 241.640 2118.230 241.700 ; + RECT 2111.930 241.500 2118.230 241.640 ; + RECT 2111.930 241.440 2112.250 241.500 ; + RECT 2117.910 241.440 2118.230 241.500 ; + RECT 2117.910 37.980 2118.230 38.040 ; + RECT 2417.370 37.980 2417.690 38.040 ; + RECT 2117.910 37.840 2417.690 37.980 ; + RECT 2117.910 37.780 2118.230 37.840 ; + RECT 2417.370 37.780 2417.690 37.840 ; + LAYER via ; + RECT 2111.960 241.440 2112.220 241.700 ; + RECT 2117.940 241.440 2118.200 241.700 ; + RECT 2117.940 37.780 2118.200 38.040 ; + RECT 2417.400 37.780 2417.660 38.040 ; + LAYER met2 ; + RECT 2111.910 260.000 2112.190 264.000 ; + RECT 2112.020 241.730 2112.160 260.000 ; + RECT 2111.960 241.410 2112.220 241.730 ; + RECT 2117.940 241.410 2118.200 241.730 ; + RECT 2118.000 38.070 2118.140 241.410 ; + RECT 2117.940 37.750 2118.200 38.070 ; + RECT 2417.400 37.750 2417.660 38.070 ; + RECT 2417.460 2.400 2417.600 37.750 ; + RECT 2417.250 -4.800 2417.810 2.400 ; +======= LAYER met2 ; RECT 2417.250 -4.800 2417.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[100] PIN la_data_in[101] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2131.710 30.840 2132.030 30.900 ; + RECT 2434.850 30.840 2435.170 30.900 ; + RECT 2131.710 30.700 2435.170 30.840 ; + RECT 2131.710 30.640 2132.030 30.700 ; + RECT 2434.850 30.640 2435.170 30.700 ; + LAYER via ; + RECT 2131.740 30.640 2132.000 30.900 ; + RECT 2434.880 30.640 2435.140 30.900 ; + LAYER met2 ; + RECT 2129.850 260.170 2130.130 264.000 ; + RECT 2129.850 260.030 2131.940 260.170 ; + RECT 2129.850 260.000 2130.130 260.030 ; + RECT 2131.800 30.930 2131.940 260.030 ; + RECT 2131.740 30.610 2132.000 30.930 ; + RECT 2434.880 30.610 2435.140 30.930 ; + RECT 2434.940 2.400 2435.080 30.610 ; + RECT 2434.730 -4.800 2435.290 2.400 ; +======= LAYER met2 ; RECT 2434.730 -4.800 2435.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[101] PIN la_data_in[102] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2147.810 244.020 2148.130 244.080 ; + RECT 2152.410 244.020 2152.730 244.080 ; + RECT 2147.810 243.880 2152.730 244.020 ; + RECT 2147.810 243.820 2148.130 243.880 ; + RECT 2152.410 243.820 2152.730 243.880 ; + RECT 2152.410 44.780 2152.730 44.840 ; + RECT 2452.790 44.780 2453.110 44.840 ; + RECT 2152.410 44.640 2453.110 44.780 ; + RECT 2152.410 44.580 2152.730 44.640 ; + RECT 2452.790 44.580 2453.110 44.640 ; + LAYER via ; + RECT 2147.840 243.820 2148.100 244.080 ; + RECT 2152.440 243.820 2152.700 244.080 ; + RECT 2152.440 44.580 2152.700 44.840 ; + RECT 2452.820 44.580 2453.080 44.840 ; + LAYER met2 ; + RECT 2147.790 260.000 2148.070 264.000 ; + RECT 2147.900 244.110 2148.040 260.000 ; + RECT 2147.840 243.790 2148.100 244.110 ; + RECT 2152.440 243.790 2152.700 244.110 ; + RECT 2152.500 44.870 2152.640 243.790 ; + RECT 2152.440 44.550 2152.700 44.870 ; + RECT 2452.820 44.550 2453.080 44.870 ; + RECT 2452.880 2.400 2453.020 44.550 ; + RECT 2452.670 -4.800 2453.230 2.400 ; +======= LAYER met2 ; RECT 2452.670 -4.800 2453.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[102] PIN la_data_in[103] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2166.210 237.900 2166.530 237.960 ; + RECT 2470.270 237.900 2470.590 237.960 ; + RECT 2166.210 237.760 2470.590 237.900 ; + RECT 2166.210 237.700 2166.530 237.760 ; + RECT 2470.270 237.700 2470.590 237.760 ; + LAYER via ; + RECT 2166.240 237.700 2166.500 237.960 ; + RECT 2470.300 237.700 2470.560 237.960 ; + LAYER met2 ; + RECT 2165.730 260.170 2166.010 264.000 ; + RECT 2165.730 260.030 2166.440 260.170 ; + RECT 2165.730 260.000 2166.010 260.030 ; + RECT 2166.300 237.990 2166.440 260.030 ; + RECT 2166.240 237.670 2166.500 237.990 ; + RECT 2470.300 237.670 2470.560 237.990 ; + RECT 2470.360 17.410 2470.500 237.670 ; + RECT 2470.360 17.270 2470.960 17.410 ; + RECT 2470.820 2.400 2470.960 17.270 ; + RECT 2470.610 -4.800 2471.170 2.400 ; +======= LAYER met2 ; RECT 2470.610 -4.800 2471.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[103] PIN la_data_in[104] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2183.690 231.100 2184.010 231.160 ; + RECT 2484.070 231.100 2484.390 231.160 ; + RECT 2183.690 230.960 2484.390 231.100 ; + RECT 2183.690 230.900 2184.010 230.960 ; + RECT 2484.070 230.900 2484.390 230.960 ; + LAYER via ; + RECT 2183.720 230.900 2183.980 231.160 ; + RECT 2484.100 230.900 2484.360 231.160 ; + LAYER met2 ; + RECT 2183.670 260.000 2183.950 264.000 ; + RECT 2183.780 231.190 2183.920 260.000 ; + RECT 2183.720 230.870 2183.980 231.190 ; + RECT 2484.100 230.870 2484.360 231.190 ; + RECT 2484.160 17.410 2484.300 230.870 ; + RECT 2484.160 17.270 2488.900 17.410 ; + RECT 2488.760 2.400 2488.900 17.270 ; + RECT 2488.550 -4.800 2489.110 2.400 ; +======= LAYER met2 ; RECT 2488.550 -4.800 2489.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[104] PIN la_data_in[105] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2201.630 244.020 2201.950 244.080 ; + RECT 2207.610 244.020 2207.930 244.080 ; + RECT 2201.630 243.880 2207.930 244.020 ; + RECT 2201.630 243.820 2201.950 243.880 ; + RECT 2207.610 243.820 2207.930 243.880 ; + RECT 2207.610 51.920 2207.930 51.980 ; + RECT 2504.770 51.920 2505.090 51.980 ; + RECT 2207.610 51.780 2505.090 51.920 ; + RECT 2207.610 51.720 2207.930 51.780 ; + RECT 2504.770 51.720 2505.090 51.780 ; + LAYER via ; + RECT 2201.660 243.820 2201.920 244.080 ; + RECT 2207.640 243.820 2207.900 244.080 ; + RECT 2207.640 51.720 2207.900 51.980 ; + RECT 2504.800 51.720 2505.060 51.980 ; + LAYER met2 ; + RECT 2201.610 260.000 2201.890 264.000 ; + RECT 2201.720 244.110 2201.860 260.000 ; + RECT 2201.660 243.790 2201.920 244.110 ; + RECT 2207.640 243.790 2207.900 244.110 ; + RECT 2207.700 52.010 2207.840 243.790 ; + RECT 2207.640 51.690 2207.900 52.010 ; + RECT 2504.800 51.690 2505.060 52.010 ; + RECT 2504.860 4.490 2505.000 51.690 ; + RECT 2504.860 4.350 2506.380 4.490 ; + RECT 2506.240 2.400 2506.380 4.350 ; + RECT 2506.030 -4.800 2506.590 2.400 ; +======= LAYER met2 ; RECT 2506.030 -4.800 2506.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[105] PIN la_data_in[106] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2221.410 58.720 2221.730 58.780 ; + RECT 2518.570 58.720 2518.890 58.780 ; + RECT 2221.410 58.580 2518.890 58.720 ; + RECT 2221.410 58.520 2221.730 58.580 ; + RECT 2518.570 58.520 2518.890 58.580 ; + LAYER via ; + RECT 2221.440 58.520 2221.700 58.780 ; + RECT 2518.600 58.520 2518.860 58.780 ; + LAYER met2 ; + RECT 2219.550 260.170 2219.830 264.000 ; + RECT 2219.550 260.030 2221.640 260.170 ; + RECT 2219.550 260.000 2219.830 260.030 ; + RECT 2221.500 58.810 2221.640 260.030 ; + RECT 2221.440 58.490 2221.700 58.810 ; + RECT 2518.600 58.490 2518.860 58.810 ; + RECT 2518.660 16.730 2518.800 58.490 ; + RECT 2518.660 16.590 2524.320 16.730 ; + RECT 2524.180 2.400 2524.320 16.590 ; + RECT 2523.970 -4.800 2524.530 2.400 ; +======= LAYER met2 ; RECT 2523.970 -4.800 2524.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[106] PIN la_data_in[107] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2237.050 244.020 2237.370 244.080 ; + RECT 2242.110 244.020 2242.430 244.080 ; + RECT 2237.050 243.880 2242.430 244.020 ; + RECT 2237.050 243.820 2237.370 243.880 ; + RECT 2242.110 243.820 2242.430 243.880 ; + RECT 2242.110 65.520 2242.430 65.580 ; + RECT 2539.270 65.520 2539.590 65.580 ; + RECT 2242.110 65.380 2539.590 65.520 ; + RECT 2242.110 65.320 2242.430 65.380 ; + RECT 2539.270 65.320 2539.590 65.380 ; + LAYER via ; + RECT 2237.080 243.820 2237.340 244.080 ; + RECT 2242.140 243.820 2242.400 244.080 ; + RECT 2242.140 65.320 2242.400 65.580 ; + RECT 2539.300 65.320 2539.560 65.580 ; + LAYER met2 ; + RECT 2237.030 260.000 2237.310 264.000 ; + RECT 2237.140 244.110 2237.280 260.000 ; + RECT 2237.080 243.790 2237.340 244.110 ; + RECT 2242.140 243.790 2242.400 244.110 ; + RECT 2242.200 65.610 2242.340 243.790 ; + RECT 2242.140 65.290 2242.400 65.610 ; + RECT 2539.300 65.290 2539.560 65.610 ; + RECT 2539.360 16.730 2539.500 65.290 ; + RECT 2539.360 16.590 2542.260 16.730 ; + RECT 2542.120 2.400 2542.260 16.590 ; + RECT 2541.910 -4.800 2542.470 2.400 ; +======= LAYER met2 ; RECT 2541.910 -4.800 2542.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[107] PIN la_data_in[108] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2255.910 224.300 2256.230 224.360 ; + RECT 2559.970 224.300 2560.290 224.360 ; + RECT 2255.910 224.160 2560.290 224.300 ; + RECT 2255.910 224.100 2256.230 224.160 ; + RECT 2559.970 224.100 2560.290 224.160 ; + LAYER via ; + RECT 2255.940 224.100 2256.200 224.360 ; + RECT 2560.000 224.100 2560.260 224.360 ; + LAYER met2 ; + RECT 2254.970 260.170 2255.250 264.000 ; + RECT 2254.970 260.030 2256.140 260.170 ; + RECT 2254.970 260.000 2255.250 260.030 ; + RECT 2256.000 224.390 2256.140 260.030 ; + RECT 2255.940 224.070 2256.200 224.390 ; + RECT 2560.000 224.070 2560.260 224.390 ; + RECT 2560.060 2.400 2560.200 224.070 ; + RECT 2559.850 -4.800 2560.410 2.400 ; +======= LAYER met2 ; RECT 2559.850 -4.800 2560.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[108] PIN la_data_in[109] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2276.610 25.400 2276.930 25.460 ; + RECT 2577.910 25.400 2578.230 25.460 ; + RECT 2276.610 25.260 2578.230 25.400 ; + RECT 2276.610 25.200 2276.930 25.260 ; + RECT 2577.910 25.200 2578.230 25.260 ; + LAYER via ; + RECT 2276.640 25.200 2276.900 25.460 ; + RECT 2577.940 25.200 2578.200 25.460 ; + LAYER met2 ; + RECT 2272.910 260.170 2273.190 264.000 ; + RECT 2272.910 260.030 2276.840 260.170 ; + RECT 2272.910 260.000 2273.190 260.030 ; + RECT 2276.700 25.490 2276.840 260.030 ; + RECT 2276.640 25.170 2276.900 25.490 ; + RECT 2577.940 25.170 2578.200 25.490 ; + RECT 2578.000 2.400 2578.140 25.170 ; + RECT 2577.790 -4.800 2578.350 2.400 ; +======= LAYER met2 ; RECT 2577.790 -4.800 2578.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[109] PIN la_data_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 502.850 30.840 503.170 30.900 ; + RECT 811.510 30.840 811.830 30.900 ; + RECT 502.850 30.700 811.830 30.840 ; + RECT 502.850 30.640 503.170 30.700 ; + RECT 811.510 30.640 811.830 30.700 ; + LAYER via ; + RECT 502.880 30.640 503.140 30.900 ; + RECT 811.540 30.640 811.800 30.900 ; + LAYER met2 ; + RECT 503.290 260.170 503.570 264.000 ; + RECT 502.940 260.030 503.570 260.170 ; + RECT 502.940 30.930 503.080 260.030 ; + RECT 503.290 260.000 503.570 260.030 ; + RECT 502.880 30.610 503.140 30.930 ; + RECT 811.540 30.610 811.800 30.930 ; + RECT 811.600 2.400 811.740 30.610 ; + RECT 811.390 -4.800 811.950 2.400 ; +======= LAYER met2 ; RECT 811.390 -4.800 811.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[10] PIN la_data_in[110] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2290.870 244.020 2291.190 244.080 ; + RECT 2297.310 244.020 2297.630 244.080 ; + RECT 2290.870 243.880 2297.630 244.020 ; + RECT 2290.870 243.820 2291.190 243.880 ; + RECT 2297.310 243.820 2297.630 243.880 ; + RECT 2297.310 24.380 2297.630 24.440 ; + RECT 2595.390 24.380 2595.710 24.440 ; + RECT 2297.310 24.240 2595.710 24.380 ; + RECT 2297.310 24.180 2297.630 24.240 ; + RECT 2595.390 24.180 2595.710 24.240 ; + LAYER via ; + RECT 2290.900 243.820 2291.160 244.080 ; + RECT 2297.340 243.820 2297.600 244.080 ; + RECT 2297.340 24.180 2297.600 24.440 ; + RECT 2595.420 24.180 2595.680 24.440 ; + LAYER met2 ; + RECT 2290.850 260.000 2291.130 264.000 ; + RECT 2290.960 244.110 2291.100 260.000 ; + RECT 2290.900 243.790 2291.160 244.110 ; + RECT 2297.340 243.790 2297.600 244.110 ; + RECT 2297.400 24.470 2297.540 243.790 ; + RECT 2297.340 24.150 2297.600 24.470 ; + RECT 2595.420 24.150 2595.680 24.470 ; + RECT 2595.480 2.400 2595.620 24.150 ; + RECT 2595.270 -4.800 2595.830 2.400 ; +======= LAYER met2 ; RECT 2595.270 -4.800 2595.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[110] PIN la_data_in[111] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2311.110 24.720 2311.430 24.780 ; + RECT 2613.330 24.720 2613.650 24.780 ; + RECT 2311.110 24.580 2613.650 24.720 ; + RECT 2311.110 24.520 2311.430 24.580 ; + RECT 2613.330 24.520 2613.650 24.580 ; + LAYER via ; + RECT 2311.140 24.520 2311.400 24.780 ; + RECT 2613.360 24.520 2613.620 24.780 ; + LAYER met2 ; + RECT 2308.790 260.170 2309.070 264.000 ; + RECT 2308.790 260.030 2311.340 260.170 ; + RECT 2308.790 260.000 2309.070 260.030 ; + RECT 2311.200 24.810 2311.340 260.030 ; + RECT 2311.140 24.490 2311.400 24.810 ; + RECT 2613.360 24.490 2613.620 24.810 ; + RECT 2613.420 2.400 2613.560 24.490 ; + RECT 2613.210 -4.800 2613.770 2.400 ; +======= LAYER met2 ; RECT 2613.210 -4.800 2613.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[111] PIN la_data_in[112] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2326.750 244.020 2327.070 244.080 ; + RECT 2331.810 244.020 2332.130 244.080 ; + RECT 2326.750 243.880 2332.130 244.020 ; + RECT 2326.750 243.820 2327.070 243.880 ; + RECT 2331.810 243.820 2332.130 243.880 ; + RECT 2331.810 25.060 2332.130 25.120 ; + RECT 2631.270 25.060 2631.590 25.120 ; + RECT 2331.810 24.920 2631.590 25.060 ; + RECT 2331.810 24.860 2332.130 24.920 ; + RECT 2631.270 24.860 2631.590 24.920 ; + LAYER via ; + RECT 2326.780 243.820 2327.040 244.080 ; + RECT 2331.840 243.820 2332.100 244.080 ; + RECT 2331.840 24.860 2332.100 25.120 ; + RECT 2631.300 24.860 2631.560 25.120 ; + LAYER met2 ; + RECT 2326.730 260.000 2327.010 264.000 ; + RECT 2326.840 244.110 2326.980 260.000 ; + RECT 2326.780 243.790 2327.040 244.110 ; + RECT 2331.840 243.790 2332.100 244.110 ; + RECT 2331.900 25.150 2332.040 243.790 ; + RECT 2331.840 24.830 2332.100 25.150 ; + RECT 2631.300 24.830 2631.560 25.150 ; + RECT 2631.360 2.400 2631.500 24.830 ; + RECT 2631.150 -4.800 2631.710 2.400 ; +======= LAYER met2 ; RECT 2631.150 -4.800 2631.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[112] PIN la_data_in[113] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2345.610 72.320 2345.930 72.380 ; + RECT 2643.230 72.320 2643.550 72.380 ; + RECT 2345.610 72.180 2643.550 72.320 ; + RECT 2345.610 72.120 2345.930 72.180 ; + RECT 2643.230 72.120 2643.550 72.180 ; + RECT 2643.230 18.940 2643.550 19.000 ; + RECT 2649.210 18.940 2649.530 19.000 ; + RECT 2643.230 18.800 2649.530 18.940 ; + RECT 2643.230 18.740 2643.550 18.800 ; + RECT 2649.210 18.740 2649.530 18.800 ; + LAYER via ; + RECT 2345.640 72.120 2345.900 72.380 ; + RECT 2643.260 72.120 2643.520 72.380 ; + RECT 2643.260 18.740 2643.520 19.000 ; + RECT 2649.240 18.740 2649.500 19.000 ; + LAYER met2 ; + RECT 2344.670 260.170 2344.950 264.000 ; + RECT 2344.670 260.030 2345.840 260.170 ; + RECT 2344.670 260.000 2344.950 260.030 ; + RECT 2345.700 72.410 2345.840 260.030 ; + RECT 2345.640 72.090 2345.900 72.410 ; + RECT 2643.260 72.090 2643.520 72.410 ; + RECT 2643.320 19.030 2643.460 72.090 ; + RECT 2643.260 18.710 2643.520 19.030 ; + RECT 2649.240 18.710 2649.500 19.030 ; + RECT 2649.300 2.400 2649.440 18.710 ; + RECT 2649.090 -4.800 2649.650 2.400 ; +======= LAYER met2 ; RECT 2649.090 -4.800 2649.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[113] PIN la_data_in[114] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2362.170 243.680 2362.490 243.740 ; + RECT 2369.990 243.680 2370.310 243.740 ; + RECT 2362.170 243.540 2370.310 243.680 ; + RECT 2362.170 243.480 2362.490 243.540 ; + RECT 2369.990 243.480 2370.310 243.540 ; + RECT 2369.990 217.160 2370.310 217.220 ; + RECT 2663.470 217.160 2663.790 217.220 ; + RECT 2369.990 217.020 2663.790 217.160 ; + RECT 2369.990 216.960 2370.310 217.020 ; + RECT 2663.470 216.960 2663.790 217.020 ; + LAYER via ; + RECT 2362.200 243.480 2362.460 243.740 ; + RECT 2370.020 243.480 2370.280 243.740 ; + RECT 2370.020 216.960 2370.280 217.220 ; + RECT 2663.500 216.960 2663.760 217.220 ; + LAYER met2 ; + RECT 2362.150 260.000 2362.430 264.000 ; + RECT 2362.260 243.770 2362.400 260.000 ; + RECT 2362.200 243.450 2362.460 243.770 ; + RECT 2370.020 243.450 2370.280 243.770 ; + RECT 2370.080 217.250 2370.220 243.450 ; + RECT 2370.020 216.930 2370.280 217.250 ; + RECT 2663.500 216.930 2663.760 217.250 ; + RECT 2663.560 17.410 2663.700 216.930 ; + RECT 2663.560 17.270 2667.380 17.410 ; + RECT 2667.240 2.400 2667.380 17.270 ; + RECT 2667.030 -4.800 2667.590 2.400 ; +======= LAYER met2 ; RECT 2667.030 -4.800 2667.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[114] PIN la_data_in[115] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2380.110 24.040 2380.430 24.100 ; + RECT 2684.630 24.040 2684.950 24.100 ; + RECT 2380.110 23.900 2684.950 24.040 ; + RECT 2380.110 23.840 2380.430 23.900 ; + RECT 2684.630 23.840 2684.950 23.900 ; + LAYER via ; + RECT 2380.140 23.840 2380.400 24.100 ; + RECT 2684.660 23.840 2684.920 24.100 ; + LAYER met2 ; + RECT 2380.090 260.000 2380.370 264.000 ; + RECT 2380.200 24.130 2380.340 260.000 ; + RECT 2380.140 23.810 2380.400 24.130 ; + RECT 2684.660 23.810 2684.920 24.130 ; + RECT 2684.720 2.400 2684.860 23.810 ; + RECT 2684.510 -4.800 2685.070 2.400 ; +======= LAYER met2 ; RECT 2684.510 -4.800 2685.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[115] PIN la_data_in[116] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2400.810 26.760 2401.130 26.820 ; + RECT 2702.570 26.760 2702.890 26.820 ; + RECT 2400.810 26.620 2702.890 26.760 ; + RECT 2400.810 26.560 2401.130 26.620 ; + RECT 2702.570 26.560 2702.890 26.620 ; + LAYER via ; + RECT 2400.840 26.560 2401.100 26.820 ; + RECT 2702.600 26.560 2702.860 26.820 ; + LAYER met2 ; + RECT 2398.030 260.170 2398.310 264.000 ; + RECT 2398.030 260.030 2401.040 260.170 ; + RECT 2398.030 260.000 2398.310 260.030 ; + RECT 2400.900 26.850 2401.040 260.030 ; + RECT 2400.840 26.530 2401.100 26.850 ; + RECT 2702.600 26.530 2702.860 26.850 ; + RECT 2702.660 2.400 2702.800 26.530 ; + RECT 2702.450 -4.800 2703.010 2.400 ; +======= LAYER met2 ; RECT 2702.450 -4.800 2703.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[116] PIN la_data_in[117] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2415.990 244.020 2416.310 244.080 ; + RECT 2421.510 244.020 2421.830 244.080 ; + RECT 2415.990 243.880 2421.830 244.020 ; + RECT 2415.990 243.820 2416.310 243.880 ; + RECT 2421.510 243.820 2421.830 243.880 ; + RECT 2421.510 26.420 2421.830 26.480 ; + RECT 2720.510 26.420 2720.830 26.480 ; + RECT 2421.510 26.280 2720.830 26.420 ; + RECT 2421.510 26.220 2421.830 26.280 ; + RECT 2720.510 26.220 2720.830 26.280 ; + LAYER via ; + RECT 2416.020 243.820 2416.280 244.080 ; + RECT 2421.540 243.820 2421.800 244.080 ; + RECT 2421.540 26.220 2421.800 26.480 ; + RECT 2720.540 26.220 2720.800 26.480 ; + LAYER met2 ; + RECT 2415.970 260.000 2416.250 264.000 ; + RECT 2416.080 244.110 2416.220 260.000 ; + RECT 2416.020 243.790 2416.280 244.110 ; + RECT 2421.540 243.790 2421.800 244.110 ; + RECT 2421.600 26.510 2421.740 243.790 ; + RECT 2421.540 26.190 2421.800 26.510 ; + RECT 2720.540 26.190 2720.800 26.510 ; + RECT 2720.600 2.400 2720.740 26.190 ; + RECT 2720.390 -4.800 2720.950 2.400 ; +======= LAYER met2 ; RECT 2720.390 -4.800 2720.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[117] PIN la_data_in[118] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2435.310 26.080 2435.630 26.140 ; + RECT 2738.450 26.080 2738.770 26.140 ; + RECT 2435.310 25.940 2738.770 26.080 ; + RECT 2435.310 25.880 2435.630 25.940 ; + RECT 2738.450 25.880 2738.770 25.940 ; + LAYER via ; + RECT 2435.340 25.880 2435.600 26.140 ; + RECT 2738.480 25.880 2738.740 26.140 ; + LAYER met2 ; + RECT 2433.910 260.170 2434.190 264.000 ; + RECT 2433.910 260.030 2435.540 260.170 ; + RECT 2433.910 260.000 2434.190 260.030 ; + RECT 2435.400 26.170 2435.540 260.030 ; + RECT 2435.340 25.850 2435.600 26.170 ; + RECT 2738.480 25.850 2738.740 26.170 ; + RECT 2738.540 2.400 2738.680 25.850 ; + RECT 2738.330 -4.800 2738.890 2.400 ; +======= LAYER met2 ; RECT 2738.330 -4.800 2738.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[118] PIN la_data_in[119] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2451.870 238.240 2452.190 238.300 ; + RECT 2753.170 238.240 2753.490 238.300 ; + RECT 2451.870 238.100 2753.490 238.240 ; + RECT 2451.870 238.040 2452.190 238.100 ; + RECT 2753.170 238.040 2753.490 238.100 ; + LAYER via ; + RECT 2451.900 238.040 2452.160 238.300 ; + RECT 2753.200 238.040 2753.460 238.300 ; + LAYER met2 ; + RECT 2451.850 260.000 2452.130 264.000 ; + RECT 2451.960 238.330 2452.100 260.000 ; + RECT 2451.900 238.010 2452.160 238.330 ; + RECT 2753.200 238.010 2753.460 238.330 ; + RECT 2753.260 17.410 2753.400 238.010 ; + RECT 2753.260 17.270 2756.160 17.410 ; + RECT 2756.020 2.400 2756.160 17.270 ; + RECT 2755.810 -4.800 2756.370 2.400 ; +======= LAYER met2 ; RECT 2755.810 -4.800 2756.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[119] PIN la_data_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 524.010 38.320 524.330 38.380 ; + RECT 829.450 38.320 829.770 38.380 ; + RECT 524.010 38.180 829.770 38.320 ; + RECT 524.010 38.120 524.330 38.180 ; + RECT 829.450 38.120 829.770 38.180 ; + LAYER via ; + RECT 524.040 38.120 524.300 38.380 ; + RECT 829.480 38.120 829.740 38.380 ; + LAYER met2 ; + RECT 521.230 260.170 521.510 264.000 ; + RECT 521.230 260.030 524.240 260.170 ; + RECT 521.230 260.000 521.510 260.030 ; + RECT 524.100 38.410 524.240 260.030 ; + RECT 524.040 38.090 524.300 38.410 ; + RECT 829.480 38.090 829.740 38.410 ; + RECT 829.540 2.400 829.680 38.090 ; + RECT 829.330 -4.800 829.890 2.400 ; +======= LAYER met2 ; RECT 829.330 -4.800 829.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[11] PIN la_data_in[120] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2469.350 210.360 2469.670 210.420 ; + RECT 2773.870 210.360 2774.190 210.420 ; + RECT 2469.350 210.220 2774.190 210.360 ; + RECT 2469.350 210.160 2469.670 210.220 ; + RECT 2773.870 210.160 2774.190 210.220 ; + LAYER via ; + RECT 2469.380 210.160 2469.640 210.420 ; + RECT 2773.900 210.160 2774.160 210.420 ; + LAYER met2 ; + RECT 2469.790 260.170 2470.070 264.000 ; + RECT 2469.440 260.030 2470.070 260.170 ; + RECT 2469.440 210.450 2469.580 260.030 ; + RECT 2469.790 260.000 2470.070 260.030 ; + RECT 2469.380 210.130 2469.640 210.450 ; + RECT 2773.900 210.130 2774.160 210.450 ; + RECT 2773.960 2.400 2774.100 210.130 ; + RECT 2773.750 -4.800 2774.310 2.400 ; +======= LAYER met2 ; RECT 2773.750 -4.800 2774.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[120] PIN la_data_in[121] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2487.290 231.100 2487.610 231.160 ; + RECT 2787.670 231.100 2787.990 231.160 ; + RECT 2487.290 230.960 2787.990 231.100 ; + RECT 2487.290 230.900 2487.610 230.960 ; + RECT 2787.670 230.900 2787.990 230.960 ; + RECT 2787.670 2.960 2787.990 3.020 ; + RECT 2791.810 2.960 2792.130 3.020 ; + RECT 2787.670 2.820 2792.130 2.960 ; + RECT 2787.670 2.760 2787.990 2.820 ; + RECT 2791.810 2.760 2792.130 2.820 ; + LAYER via ; + RECT 2487.320 230.900 2487.580 231.160 ; + RECT 2787.700 230.900 2787.960 231.160 ; + RECT 2787.700 2.760 2787.960 3.020 ; + RECT 2791.840 2.760 2792.100 3.020 ; + LAYER met2 ; + RECT 2487.270 260.000 2487.550 264.000 ; + RECT 2487.380 231.190 2487.520 260.000 ; + RECT 2487.320 230.870 2487.580 231.190 ; + RECT 2787.700 230.870 2787.960 231.190 ; + RECT 2787.760 3.050 2787.900 230.870 ; + RECT 2787.700 2.730 2787.960 3.050 ; + RECT 2791.840 2.730 2792.100 3.050 ; + RECT 2791.900 2.400 2792.040 2.730 ; + RECT 2791.690 -4.800 2792.250 2.400 ; +======= LAYER met2 ; RECT 2791.690 -4.800 2792.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[121] PIN la_data_in[122] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2505.230 244.020 2505.550 244.080 ; + RECT 2511.210 244.020 2511.530 244.080 ; + RECT 2505.230 243.880 2511.530 244.020 ; + RECT 2505.230 243.820 2505.550 243.880 ; + RECT 2511.210 243.820 2511.530 243.880 ; + RECT 2511.210 30.840 2511.530 30.900 ; + RECT 2809.750 30.840 2810.070 30.900 ; + RECT 2511.210 30.700 2810.070 30.840 ; + RECT 2511.210 30.640 2511.530 30.700 ; + RECT 2809.750 30.640 2810.070 30.700 ; + LAYER via ; + RECT 2505.260 243.820 2505.520 244.080 ; + RECT 2511.240 243.820 2511.500 244.080 ; + RECT 2511.240 30.640 2511.500 30.900 ; + RECT 2809.780 30.640 2810.040 30.900 ; + LAYER met2 ; + RECT 2505.210 260.000 2505.490 264.000 ; + RECT 2505.320 244.110 2505.460 260.000 ; + RECT 2505.260 243.790 2505.520 244.110 ; + RECT 2511.240 243.790 2511.500 244.110 ; + RECT 2511.300 30.930 2511.440 243.790 ; + RECT 2511.240 30.610 2511.500 30.930 ; + RECT 2809.780 30.610 2810.040 30.930 ; + RECT 2809.840 2.400 2809.980 30.610 ; + RECT 2809.630 -4.800 2810.190 2.400 ; +======= LAYER met2 ; RECT 2809.630 -4.800 2810.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[122] PIN la_data_in[123] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2525.010 79.460 2525.330 79.520 ; + RECT 2822.170 79.460 2822.490 79.520 ; + RECT 2525.010 79.320 2822.490 79.460 ; + RECT 2525.010 79.260 2525.330 79.320 ; + RECT 2822.170 79.260 2822.490 79.320 ; + RECT 2822.170 2.960 2822.490 3.020 ; + RECT 2827.690 2.960 2828.010 3.020 ; + RECT 2822.170 2.820 2828.010 2.960 ; + RECT 2822.170 2.760 2822.490 2.820 ; + RECT 2827.690 2.760 2828.010 2.820 ; + LAYER via ; + RECT 2525.040 79.260 2525.300 79.520 ; + RECT 2822.200 79.260 2822.460 79.520 ; + RECT 2822.200 2.760 2822.460 3.020 ; + RECT 2827.720 2.760 2827.980 3.020 ; + LAYER met2 ; + RECT 2523.150 260.170 2523.430 264.000 ; + RECT 2523.150 260.030 2525.240 260.170 ; + RECT 2523.150 260.000 2523.430 260.030 ; + RECT 2525.100 79.550 2525.240 260.030 ; + RECT 2525.040 79.230 2525.300 79.550 ; + RECT 2822.200 79.230 2822.460 79.550 ; + RECT 2822.260 3.050 2822.400 79.230 ; + RECT 2822.200 2.730 2822.460 3.050 ; + RECT 2827.720 2.730 2827.980 3.050 ; + RECT 2827.780 2.400 2827.920 2.730 ; + RECT 2827.570 -4.800 2828.130 2.400 ; +======= LAYER met2 ; RECT 2827.570 -4.800 2828.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[123] PIN la_data_in[124] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2541.110 244.020 2541.430 244.080 ; + RECT 2545.710 244.020 2546.030 244.080 ; + RECT 2541.110 243.880 2546.030 244.020 ; + RECT 2541.110 243.820 2541.430 243.880 ; + RECT 2545.710 243.820 2546.030 243.880 ; + RECT 2545.710 224.640 2546.030 224.700 ; + RECT 2842.870 224.640 2843.190 224.700 ; + RECT 2545.710 224.500 2843.190 224.640 ; + RECT 2545.710 224.440 2546.030 224.500 ; + RECT 2842.870 224.440 2843.190 224.500 ; + LAYER via ; + RECT 2541.140 243.820 2541.400 244.080 ; + RECT 2545.740 243.820 2546.000 244.080 ; + RECT 2545.740 224.440 2546.000 224.700 ; + RECT 2842.900 224.440 2843.160 224.700 ; + LAYER met2 ; + RECT 2541.090 260.000 2541.370 264.000 ; + RECT 2541.200 244.110 2541.340 260.000 ; + RECT 2541.140 243.790 2541.400 244.110 ; + RECT 2545.740 243.790 2546.000 244.110 ; + RECT 2545.800 224.730 2545.940 243.790 ; + RECT 2545.740 224.410 2546.000 224.730 ; + RECT 2842.900 224.410 2843.160 224.730 ; + RECT 2842.960 6.530 2843.100 224.410 ; + RECT 2842.960 6.390 2845.400 6.530 ; + RECT 2845.260 2.400 2845.400 6.390 ; + RECT 2845.050 -4.800 2845.610 2.400 ; +======= LAYER met2 ; RECT 2845.050 -4.800 2845.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[124] PIN la_data_in[125] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2559.050 196.760 2559.370 196.820 ; + RECT 2857.130 196.760 2857.450 196.820 ; + RECT 2559.050 196.620 2857.450 196.760 ; + RECT 2559.050 196.560 2559.370 196.620 ; + RECT 2857.130 196.560 2857.450 196.620 ; + RECT 2857.130 17.580 2857.450 17.640 ; + RECT 2863.110 17.580 2863.430 17.640 ; + RECT 2857.130 17.440 2863.430 17.580 ; + RECT 2857.130 17.380 2857.450 17.440 ; + RECT 2863.110 17.380 2863.430 17.440 ; + LAYER via ; + RECT 2559.080 196.560 2559.340 196.820 ; + RECT 2857.160 196.560 2857.420 196.820 ; + RECT 2857.160 17.380 2857.420 17.640 ; + RECT 2863.140 17.380 2863.400 17.640 ; + LAYER met2 ; + RECT 2559.030 260.000 2559.310 264.000 ; + RECT 2559.140 196.850 2559.280 260.000 ; + RECT 2559.080 196.530 2559.340 196.850 ; + RECT 2857.160 196.530 2857.420 196.850 ; + RECT 2857.220 17.670 2857.360 196.530 ; + RECT 2857.160 17.350 2857.420 17.670 ; + RECT 2863.140 17.350 2863.400 17.670 ; + RECT 2863.200 2.400 2863.340 17.350 ; + RECT 2862.990 -4.800 2863.550 2.400 ; +======= LAYER met2 ; RECT 2862.990 -4.800 2863.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[125] PIN la_data_in[126] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2580.210 51.580 2580.530 51.640 ; + RECT 2877.370 51.580 2877.690 51.640 ; + RECT 2580.210 51.440 2877.690 51.580 ; + RECT 2580.210 51.380 2580.530 51.440 ; + RECT 2877.370 51.380 2877.690 51.440 ; + LAYER via ; + RECT 2580.240 51.380 2580.500 51.640 ; + RECT 2877.400 51.380 2877.660 51.640 ; + LAYER met2 ; + RECT 2576.970 260.170 2577.250 264.000 ; + RECT 2576.970 260.030 2580.440 260.170 ; + RECT 2576.970 260.000 2577.250 260.030 ; + RECT 2580.300 51.670 2580.440 260.030 ; + RECT 2580.240 51.350 2580.500 51.670 ; + RECT 2877.400 51.350 2877.660 51.670 ; + RECT 2877.460 17.410 2877.600 51.350 ; + RECT 2877.460 17.270 2881.280 17.410 ; + RECT 2881.140 2.400 2881.280 17.270 ; + RECT 2880.930 -4.800 2881.490 2.400 ; +======= LAYER met2 ; RECT 2880.930 -4.800 2881.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[126] PIN la_data_in[127] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2594.930 244.020 2595.250 244.080 ; + RECT 2600.450 244.020 2600.770 244.080 ; + RECT 2594.930 243.880 2600.770 244.020 ; + RECT 2594.930 243.820 2595.250 243.880 ; + RECT 2600.450 243.820 2600.770 243.880 ; + RECT 2600.450 189.620 2600.770 189.680 ; + RECT 2894.390 189.620 2894.710 189.680 ; + RECT 2600.450 189.480 2894.710 189.620 ; + RECT 2600.450 189.420 2600.770 189.480 ; + RECT 2894.390 189.420 2894.710 189.480 ; + RECT 2894.390 17.580 2894.710 17.640 ; + RECT 2898.990 17.580 2899.310 17.640 ; + RECT 2894.390 17.440 2899.310 17.580 ; + RECT 2894.390 17.380 2894.710 17.440 ; + RECT 2898.990 17.380 2899.310 17.440 ; + LAYER via ; + RECT 2594.960 243.820 2595.220 244.080 ; + RECT 2600.480 243.820 2600.740 244.080 ; + RECT 2600.480 189.420 2600.740 189.680 ; + RECT 2894.420 189.420 2894.680 189.680 ; + RECT 2894.420 17.380 2894.680 17.640 ; + RECT 2899.020 17.380 2899.280 17.640 ; + LAYER met2 ; + RECT 2594.910 260.000 2595.190 264.000 ; + RECT 2595.020 244.110 2595.160 260.000 ; + RECT 2594.960 243.790 2595.220 244.110 ; + RECT 2600.480 243.790 2600.740 244.110 ; + RECT 2600.540 189.710 2600.680 243.790 ; + RECT 2600.480 189.390 2600.740 189.710 ; + RECT 2894.420 189.390 2894.680 189.710 ; + RECT 2894.480 17.670 2894.620 189.390 ; + RECT 2894.420 17.350 2894.680 17.670 ; + RECT 2899.020 17.350 2899.280 17.670 ; + RECT 2899.080 2.400 2899.220 17.350 ; + RECT 2898.870 -4.800 2899.430 2.400 ; +======= LAYER met2 ; RECT 2898.870 -4.800 2899.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[127] PIN la_data_in[12] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 539.190 244.020 539.510 244.080 ; + RECT 544.710 244.020 545.030 244.080 ; + RECT 539.190 243.880 545.030 244.020 ; + RECT 539.190 243.820 539.510 243.880 ; + RECT 544.710 243.820 545.030 243.880 ; + RECT 544.710 44.780 545.030 44.840 ; + RECT 846.930 44.780 847.250 44.840 ; + RECT 544.710 44.640 847.250 44.780 ; + RECT 544.710 44.580 545.030 44.640 ; + RECT 846.930 44.580 847.250 44.640 ; + LAYER via ; + RECT 539.220 243.820 539.480 244.080 ; + RECT 544.740 243.820 545.000 244.080 ; + RECT 544.740 44.580 545.000 44.840 ; + RECT 846.960 44.580 847.220 44.840 ; + LAYER met2 ; + RECT 539.170 260.000 539.450 264.000 ; + RECT 539.280 244.110 539.420 260.000 ; + RECT 539.220 243.790 539.480 244.110 ; + RECT 544.740 243.790 545.000 244.110 ; + RECT 544.800 44.870 544.940 243.790 ; + RECT 544.740 44.550 545.000 44.870 ; + RECT 846.960 44.550 847.220 44.870 ; + RECT 847.020 2.400 847.160 44.550 ; + RECT 846.810 -4.800 847.370 2.400 ; +======= LAYER met2 ; RECT 846.810 -4.800 847.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[12] PIN la_data_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 558.510 51.580 558.830 51.640 ; + RECT 862.570 51.580 862.890 51.640 ; + RECT 558.510 51.440 862.890 51.580 ; + RECT 558.510 51.380 558.830 51.440 ; + RECT 862.570 51.380 862.890 51.440 ; + LAYER via ; + RECT 558.540 51.380 558.800 51.640 ; + RECT 862.600 51.380 862.860 51.640 ; + LAYER met2 ; + RECT 557.110 260.170 557.390 264.000 ; + RECT 557.110 260.030 558.740 260.170 ; + RECT 557.110 260.000 557.390 260.030 ; + RECT 558.600 51.670 558.740 260.030 ; + RECT 558.540 51.350 558.800 51.670 ; + RECT 862.600 51.350 862.860 51.670 ; + RECT 862.660 16.730 862.800 51.350 ; + RECT 862.660 16.590 865.100 16.730 ; + RECT 864.960 2.400 865.100 16.590 ; + RECT 864.750 -4.800 865.310 2.400 ; +======= LAYER met2 ; RECT 864.750 -4.800 865.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[13] PIN la_data_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 574.610 244.020 574.930 244.080 ; + RECT 579.210 244.020 579.530 244.080 ; + RECT 574.610 243.880 579.530 244.020 ; + RECT 574.610 243.820 574.930 243.880 ; + RECT 579.210 243.820 579.530 243.880 ; + RECT 579.210 58.720 579.530 58.780 ; + RECT 876.830 58.720 877.150 58.780 ; + RECT 579.210 58.580 877.150 58.720 ; + RECT 579.210 58.520 579.530 58.580 ; + RECT 876.830 58.520 877.150 58.580 ; + RECT 876.830 16.560 877.150 16.620 ; + RECT 882.810 16.560 883.130 16.620 ; + RECT 876.830 16.420 883.130 16.560 ; + RECT 876.830 16.360 877.150 16.420 ; + RECT 882.810 16.360 883.130 16.420 ; + LAYER via ; + RECT 574.640 243.820 574.900 244.080 ; + RECT 579.240 243.820 579.500 244.080 ; + RECT 579.240 58.520 579.500 58.780 ; + RECT 876.860 58.520 877.120 58.780 ; + RECT 876.860 16.360 877.120 16.620 ; + RECT 882.840 16.360 883.100 16.620 ; + LAYER met2 ; + RECT 574.590 260.000 574.870 264.000 ; + RECT 574.700 244.110 574.840 260.000 ; + RECT 574.640 243.790 574.900 244.110 ; + RECT 579.240 243.790 579.500 244.110 ; + RECT 579.300 58.810 579.440 243.790 ; + RECT 579.240 58.490 579.500 58.810 ; + RECT 876.860 58.490 877.120 58.810 ; + RECT 876.920 16.650 877.060 58.490 ; + RECT 876.860 16.330 877.120 16.650 ; + RECT 882.840 16.330 883.100 16.650 ; + RECT 882.900 2.400 883.040 16.330 ; + RECT 882.690 -4.800 883.250 2.400 ; +======= LAYER met2 ; RECT 882.690 -4.800 883.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[14] PIN la_data_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 592.550 65.520 592.870 65.580 ; + RECT 897.070 65.520 897.390 65.580 ; + RECT 592.550 65.380 897.390 65.520 ; + RECT 592.550 65.320 592.870 65.380 ; + RECT 897.070 65.320 897.390 65.380 ; + LAYER via ; + RECT 592.580 65.320 592.840 65.580 ; + RECT 897.100 65.320 897.360 65.580 ; + LAYER met2 ; + RECT 592.530 260.000 592.810 264.000 ; + RECT 592.640 65.610 592.780 260.000 ; + RECT 592.580 65.290 592.840 65.610 ; + RECT 897.100 65.290 897.360 65.610 ; + RECT 897.160 16.730 897.300 65.290 ; + RECT 897.160 16.590 900.980 16.730 ; + RECT 900.840 2.400 900.980 16.590 ; + RECT 900.630 -4.800 901.190 2.400 ; +======= LAYER met2 ; RECT 900.630 -4.800 901.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[15] PIN la_data_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 613.710 72.320 614.030 72.380 ; + RECT 918.230 72.320 918.550 72.380 ; + RECT 613.710 72.180 918.550 72.320 ; + RECT 613.710 72.120 614.030 72.180 ; + RECT 918.230 72.120 918.550 72.180 ; + LAYER via ; + RECT 613.740 72.120 614.000 72.380 ; + RECT 918.260 72.120 918.520 72.380 ; + LAYER met2 ; + RECT 610.470 260.170 610.750 264.000 ; + RECT 610.470 260.030 613.940 260.170 ; + RECT 610.470 260.000 610.750 260.030 ; + RECT 613.800 72.410 613.940 260.030 ; + RECT 613.740 72.090 614.000 72.410 ; + RECT 918.260 72.090 918.520 72.410 ; + RECT 918.320 17.410 918.460 72.090 ; + RECT 918.320 17.270 918.920 17.410 ; + RECT 918.780 2.400 918.920 17.270 ; + RECT 918.570 -4.800 919.130 2.400 ; +======= LAYER met2 ; RECT 918.570 -4.800 919.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[16] PIN la_data_in[17] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 628.430 243.340 628.750 243.400 ; + RECT 634.410 243.340 634.730 243.400 ; + RECT 628.430 243.200 634.730 243.340 ; + RECT 628.430 243.140 628.750 243.200 ; + RECT 634.410 243.140 634.730 243.200 ; + RECT 634.410 79.800 634.730 79.860 ; + RECT 931.570 79.800 931.890 79.860 ; + RECT 634.410 79.660 931.890 79.800 ; + RECT 634.410 79.600 634.730 79.660 ; + RECT 931.570 79.600 931.890 79.660 ; + LAYER via ; + RECT 628.460 243.140 628.720 243.400 ; + RECT 634.440 243.140 634.700 243.400 ; + RECT 634.440 79.600 634.700 79.860 ; + RECT 931.600 79.600 931.860 79.860 ; + LAYER met2 ; + RECT 628.410 260.000 628.690 264.000 ; + RECT 628.520 243.430 628.660 260.000 ; + RECT 628.460 243.110 628.720 243.430 ; + RECT 634.440 243.110 634.700 243.430 ; + RECT 634.500 79.890 634.640 243.110 ; + RECT 634.440 79.570 634.700 79.890 ; + RECT 931.600 79.570 931.860 79.890 ; + RECT 931.660 16.730 931.800 79.570 ; + RECT 931.660 16.590 936.400 16.730 ; + RECT 936.260 2.400 936.400 16.590 ; + RECT 936.050 -4.800 936.610 2.400 ; +======= LAYER met2 ; RECT 936.050 -4.800 936.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[17] PIN la_data_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 648.210 86.260 648.530 86.320 ; + RECT 952.270 86.260 952.590 86.320 ; + RECT 648.210 86.120 952.590 86.260 ; + RECT 648.210 86.060 648.530 86.120 ; + RECT 952.270 86.060 952.590 86.120 ; + LAYER via ; + RECT 648.240 86.060 648.500 86.320 ; + RECT 952.300 86.060 952.560 86.320 ; + LAYER met2 ; + RECT 646.350 260.170 646.630 264.000 ; + RECT 646.350 260.030 648.440 260.170 ; + RECT 646.350 260.000 646.630 260.030 ; + RECT 648.300 86.350 648.440 260.030 ; + RECT 648.240 86.030 648.500 86.350 ; + RECT 952.300 86.030 952.560 86.350 ; + RECT 952.360 16.730 952.500 86.030 ; + RECT 952.360 16.590 954.340 16.730 ; + RECT 954.200 2.400 954.340 16.590 ; + RECT 953.990 -4.800 954.550 2.400 ; +======= LAYER met2 ; RECT 953.990 -4.800 954.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[18] PIN la_data_in[19] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 664.310 244.020 664.630 244.080 ; + RECT 668.910 244.020 669.230 244.080 ; + RECT 664.310 243.880 669.230 244.020 ; + RECT 664.310 243.820 664.630 243.880 ; + RECT 668.910 243.820 669.230 243.880 ; + RECT 668.910 24.720 669.230 24.780 ; + RECT 972.050 24.720 972.370 24.780 ; + RECT 668.910 24.580 972.370 24.720 ; + RECT 668.910 24.520 669.230 24.580 ; + RECT 972.050 24.520 972.370 24.580 ; + LAYER via ; + RECT 664.340 243.820 664.600 244.080 ; + RECT 668.940 243.820 669.200 244.080 ; + RECT 668.940 24.520 669.200 24.780 ; + RECT 972.080 24.520 972.340 24.780 ; + LAYER met2 ; + RECT 664.290 260.000 664.570 264.000 ; + RECT 664.400 244.110 664.540 260.000 ; + RECT 664.340 243.790 664.600 244.110 ; + RECT 668.940 243.790 669.200 244.110 ; + RECT 669.000 24.810 669.140 243.790 ; + RECT 668.940 24.490 669.200 24.810 ; + RECT 972.080 24.490 972.340 24.810 ; + RECT 972.140 2.400 972.280 24.490 ; + RECT 971.930 -4.800 972.490 2.400 ; +======= LAYER met2 ; RECT 971.930 -4.800 972.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[19] PIN la_data_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 344.610 24.040 344.930 24.100 ; + RECT 650.970 24.040 651.290 24.100 ; + RECT 344.610 23.900 651.290 24.040 ; + RECT 344.610 23.840 344.930 23.900 ; + RECT 650.970 23.840 651.290 23.900 ; + LAYER via ; + RECT 344.640 23.840 344.900 24.100 ; + RECT 651.000 23.840 651.260 24.100 ; + LAYER met2 ; + RECT 342.290 260.170 342.570 264.000 ; + RECT 342.290 260.030 344.840 260.170 ; + RECT 342.290 260.000 342.570 260.030 ; + RECT 344.700 24.130 344.840 260.030 ; + RECT 344.640 23.810 344.900 24.130 ; + RECT 651.000 23.810 651.260 24.130 ; + RECT 651.060 2.400 651.200 23.810 ; + RECT 650.850 -4.800 651.410 2.400 ; +======= LAYER met2 ; RECT 650.850 -4.800 651.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[1] PIN la_data_in[20] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 682.710 237.900 683.030 237.960 ; + RECT 986.770 237.900 987.090 237.960 ; + RECT 682.710 237.760 987.090 237.900 ; + RECT 682.710 237.700 683.030 237.760 ; + RECT 986.770 237.700 987.090 237.760 ; + LAYER via ; + RECT 682.740 237.700 683.000 237.960 ; + RECT 986.800 237.700 987.060 237.960 ; + LAYER met2 ; + RECT 682.230 260.170 682.510 264.000 ; + RECT 682.230 260.030 682.940 260.170 ; + RECT 682.230 260.000 682.510 260.030 ; + RECT 682.800 237.990 682.940 260.030 ; + RECT 682.740 237.670 683.000 237.990 ; + RECT 986.800 237.670 987.060 237.990 ; + RECT 986.860 16.730 987.000 237.670 ; + RECT 986.860 16.590 990.220 16.730 ; + RECT 990.080 2.400 990.220 16.590 ; + RECT 989.870 -4.800 990.430 2.400 ; +======= LAYER met2 ; RECT 989.870 -4.800 990.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[20] PIN la_data_in[21] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 703.410 93.060 703.730 93.120 ; + RECT 1007.930 93.060 1008.250 93.120 ; + RECT 703.410 92.920 1008.250 93.060 ; + RECT 703.410 92.860 703.730 92.920 ; + RECT 1007.930 92.860 1008.250 92.920 ; + LAYER via ; + RECT 703.440 92.860 703.700 93.120 ; + RECT 1007.960 92.860 1008.220 93.120 ; + LAYER met2 ; + RECT 699.710 260.170 699.990 264.000 ; + RECT 699.710 260.030 703.640 260.170 ; + RECT 699.710 260.000 699.990 260.030 ; + RECT 703.500 93.150 703.640 260.030 ; + RECT 703.440 92.830 703.700 93.150 ; + RECT 1007.960 92.830 1008.220 93.150 ; + RECT 1008.020 17.410 1008.160 92.830 ; + RECT 1007.560 17.270 1008.160 17.410 ; + RECT 1007.560 2.400 1007.700 17.270 ; + RECT 1007.350 -4.800 1007.910 2.400 ; +======= LAYER met2 ; RECT 1007.350 -4.800 1007.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[21] PIN la_data_in[22] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 717.670 242.660 717.990 242.720 ; + RECT 724.110 242.660 724.430 242.720 ; + RECT 717.670 242.520 724.430 242.660 ; + RECT 717.670 242.460 717.990 242.520 ; + RECT 724.110 242.460 724.430 242.520 ; + RECT 724.110 99.860 724.430 99.920 ; + RECT 1021.270 99.860 1021.590 99.920 ; + RECT 724.110 99.720 1021.590 99.860 ; + RECT 724.110 99.660 724.430 99.720 ; + RECT 1021.270 99.660 1021.590 99.720 ; + LAYER via ; + RECT 717.700 242.460 717.960 242.720 ; + RECT 724.140 242.460 724.400 242.720 ; + RECT 724.140 99.660 724.400 99.920 ; + RECT 1021.300 99.660 1021.560 99.920 ; + LAYER met2 ; + RECT 717.650 260.000 717.930 264.000 ; + RECT 717.760 242.750 717.900 260.000 ; + RECT 717.700 242.430 717.960 242.750 ; + RECT 724.140 242.430 724.400 242.750 ; + RECT 724.200 99.950 724.340 242.430 ; + RECT 724.140 99.630 724.400 99.950 ; + RECT 1021.300 99.630 1021.560 99.950 ; + RECT 1021.360 16.730 1021.500 99.630 ; + RECT 1021.360 16.590 1025.640 16.730 ; + RECT 1025.500 2.400 1025.640 16.590 ; + RECT 1025.290 -4.800 1025.850 2.400 ; +======= LAYER met2 ; RECT 1025.290 -4.800 1025.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[22] PIN la_data_in[23] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 737.910 107.000 738.230 107.060 ; + RECT 1041.970 107.000 1042.290 107.060 ; + RECT 737.910 106.860 1042.290 107.000 ; + RECT 737.910 106.800 738.230 106.860 ; + RECT 1041.970 106.800 1042.290 106.860 ; + LAYER via ; + RECT 737.940 106.800 738.200 107.060 ; + RECT 1042.000 106.800 1042.260 107.060 ; + LAYER met2 ; + RECT 735.590 260.170 735.870 264.000 ; + RECT 735.590 260.030 738.140 260.170 ; + RECT 735.590 260.000 735.870 260.030 ; + RECT 738.000 107.090 738.140 260.030 ; + RECT 737.940 106.770 738.200 107.090 ; + RECT 1042.000 106.770 1042.260 107.090 ; + RECT 1042.060 16.730 1042.200 106.770 ; + RECT 1042.060 16.590 1043.580 16.730 ; + RECT 1043.440 2.400 1043.580 16.590 ; + RECT 1043.230 -4.800 1043.790 2.400 ; +======= LAYER met2 ; RECT 1043.230 -4.800 1043.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[23] PIN la_data_in[24] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 753.550 244.020 753.870 244.080 ; + RECT 758.610 244.020 758.930 244.080 ; + RECT 753.550 243.880 758.930 244.020 ; + RECT 753.550 243.820 753.870 243.880 ; + RECT 758.610 243.820 758.930 243.880 ; + RECT 758.610 113.800 758.930 113.860 ; + RECT 1055.770 113.800 1056.090 113.860 ; + RECT 758.610 113.660 1056.090 113.800 ; + RECT 758.610 113.600 758.930 113.660 ; + RECT 1055.770 113.600 1056.090 113.660 ; + LAYER via ; + RECT 753.580 243.820 753.840 244.080 ; + RECT 758.640 243.820 758.900 244.080 ; + RECT 758.640 113.600 758.900 113.860 ; + RECT 1055.800 113.600 1056.060 113.860 ; + LAYER met2 ; + RECT 753.530 260.000 753.810 264.000 ; + RECT 753.640 244.110 753.780 260.000 ; + RECT 753.580 243.790 753.840 244.110 ; + RECT 758.640 243.790 758.900 244.110 ; + RECT 758.700 113.890 758.840 243.790 ; + RECT 758.640 113.570 758.900 113.890 ; + RECT 1055.800 113.570 1056.060 113.890 ; + RECT 1055.860 16.730 1056.000 113.570 ; + RECT 1055.860 16.590 1061.520 16.730 ; + RECT 1061.380 2.400 1061.520 16.590 ; + RECT 1061.170 -4.800 1061.730 2.400 ; +======= LAYER met2 ; RECT 1061.170 -4.800 1061.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[24] PIN la_data_in[25] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 772.410 120.600 772.730 120.660 ; + RECT 1076.470 120.600 1076.790 120.660 ; + RECT 772.410 120.460 1076.790 120.600 ; + RECT 772.410 120.400 772.730 120.460 ; + RECT 1076.470 120.400 1076.790 120.460 ; + LAYER via ; + RECT 772.440 120.400 772.700 120.660 ; + RECT 1076.500 120.400 1076.760 120.660 ; + LAYER met2 ; + RECT 771.470 260.170 771.750 264.000 ; + RECT 771.470 260.030 772.640 260.170 ; + RECT 771.470 260.000 771.750 260.030 ; + RECT 772.500 120.690 772.640 260.030 ; + RECT 772.440 120.370 772.700 120.690 ; + RECT 1076.500 120.370 1076.760 120.690 ; + RECT 1076.560 16.730 1076.700 120.370 ; + RECT 1076.560 16.590 1079.460 16.730 ; + RECT 1079.320 2.400 1079.460 16.590 ; + RECT 1079.110 -4.800 1079.670 2.400 ; +======= LAYER met2 ; RECT 1079.110 -4.800 1079.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[25] PIN la_data_in[26] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 789.430 244.020 789.750 244.080 ; + RECT 793.110 244.020 793.430 244.080 ; + RECT 789.430 243.880 793.430 244.020 ; + RECT 789.430 243.820 789.750 243.880 ; + RECT 793.110 243.820 793.430 243.880 ; + RECT 793.110 127.740 793.430 127.800 ; + RECT 1090.730 127.740 1091.050 127.800 ; + RECT 793.110 127.600 1091.050 127.740 ; + RECT 793.110 127.540 793.430 127.600 ; + RECT 1090.730 127.540 1091.050 127.600 ; + RECT 1090.730 17.920 1091.050 17.980 ; + RECT 1096.710 17.920 1097.030 17.980 ; + RECT 1090.730 17.780 1097.030 17.920 ; + RECT 1090.730 17.720 1091.050 17.780 ; + RECT 1096.710 17.720 1097.030 17.780 ; + LAYER via ; + RECT 789.460 243.820 789.720 244.080 ; + RECT 793.140 243.820 793.400 244.080 ; + RECT 793.140 127.540 793.400 127.800 ; + RECT 1090.760 127.540 1091.020 127.800 ; + RECT 1090.760 17.720 1091.020 17.980 ; + RECT 1096.740 17.720 1097.000 17.980 ; + LAYER met2 ; + RECT 789.410 260.000 789.690 264.000 ; + RECT 789.520 244.110 789.660 260.000 ; + RECT 789.460 243.790 789.720 244.110 ; + RECT 793.140 243.790 793.400 244.110 ; + RECT 793.200 127.830 793.340 243.790 ; + RECT 793.140 127.510 793.400 127.830 ; + RECT 1090.760 127.510 1091.020 127.830 ; + RECT 1090.820 18.010 1090.960 127.510 ; + RECT 1090.760 17.690 1091.020 18.010 ; + RECT 1096.740 17.690 1097.000 18.010 ; + RECT 1096.800 2.400 1096.940 17.690 ; + RECT 1096.590 -4.800 1097.150 2.400 ; +======= LAYER met2 ; RECT 1096.590 -4.800 1097.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[26] PIN la_data_in[27] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 807.370 244.020 807.690 244.080 ; + RECT 813.810 244.020 814.130 244.080 ; + RECT 807.370 243.880 814.130 244.020 ; + RECT 807.370 243.820 807.690 243.880 ; + RECT 813.810 243.820 814.130 243.880 ; + RECT 813.810 31.520 814.130 31.580 ; + RECT 1114.650 31.520 1114.970 31.580 ; + RECT 813.810 31.380 1114.970 31.520 ; + RECT 813.810 31.320 814.130 31.380 ; + RECT 1114.650 31.320 1114.970 31.380 ; + LAYER via ; + RECT 807.400 243.820 807.660 244.080 ; + RECT 813.840 243.820 814.100 244.080 ; + RECT 813.840 31.320 814.100 31.580 ; + RECT 1114.680 31.320 1114.940 31.580 ; + LAYER met2 ; + RECT 807.350 260.000 807.630 264.000 ; + RECT 807.460 244.110 807.600 260.000 ; + RECT 807.400 243.790 807.660 244.110 ; + RECT 813.840 243.790 814.100 244.110 ; + RECT 813.900 31.610 814.040 243.790 ; + RECT 813.840 31.290 814.100 31.610 ; + RECT 1114.680 31.290 1114.940 31.610 ; + RECT 1114.740 2.400 1114.880 31.290 ; + RECT 1114.530 -4.800 1115.090 2.400 ; +======= LAYER met2 ; RECT 1114.530 -4.800 1115.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[27] PIN la_data_in[28] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 827.610 134.540 827.930 134.600 ; + RECT 1131.670 134.540 1131.990 134.600 ; + RECT 827.610 134.400 1131.990 134.540 ; + RECT 827.610 134.340 827.930 134.400 ; + RECT 1131.670 134.340 1131.990 134.400 ; + LAYER via ; + RECT 827.640 134.340 827.900 134.600 ; + RECT 1131.700 134.340 1131.960 134.600 ; + LAYER met2 ; + RECT 824.830 260.170 825.110 264.000 ; + RECT 824.830 260.030 827.840 260.170 ; + RECT 824.830 260.000 825.110 260.030 ; + RECT 827.700 134.630 827.840 260.030 ; + RECT 827.640 134.310 827.900 134.630 ; + RECT 1131.700 134.310 1131.960 134.630 ; + RECT 1131.760 16.730 1131.900 134.310 ; + RECT 1131.760 16.590 1132.820 16.730 ; + RECT 1132.680 2.400 1132.820 16.590 ; + RECT 1132.470 -4.800 1133.030 2.400 ; +======= LAYER met2 ; RECT 1132.470 -4.800 1133.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[28] PIN la_data_in[29] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 842.790 244.020 843.110 244.080 ; + RECT 848.310 244.020 848.630 244.080 ; + RECT 842.790 243.880 848.630 244.020 ; + RECT 842.790 243.820 843.110 243.880 ; + RECT 848.310 243.820 848.630 243.880 ; + RECT 848.310 38.320 848.630 38.380 ; + RECT 1150.530 38.320 1150.850 38.380 ; + RECT 848.310 38.180 1150.850 38.320 ; + RECT 848.310 38.120 848.630 38.180 ; + RECT 1150.530 38.120 1150.850 38.180 ; + LAYER via ; + RECT 842.820 243.820 843.080 244.080 ; + RECT 848.340 243.820 848.600 244.080 ; + RECT 848.340 38.120 848.600 38.380 ; + RECT 1150.560 38.120 1150.820 38.380 ; + LAYER met2 ; + RECT 842.770 260.000 843.050 264.000 ; + RECT 842.880 244.110 843.020 260.000 ; + RECT 842.820 243.790 843.080 244.110 ; + RECT 848.340 243.790 848.600 244.110 ; + RECT 848.400 38.410 848.540 243.790 ; + RECT 848.340 38.090 848.600 38.410 ; + RECT 1150.560 38.090 1150.820 38.410 ; + RECT 1150.620 2.400 1150.760 38.090 ; + RECT 1150.410 -4.800 1150.970 2.400 ; +======= LAYER met2 ; RECT 1150.410 -4.800 1150.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[29] PIN la_data_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 360.250 244.020 360.570 244.080 ; + RECT 365.310 244.020 365.630 244.080 ; + RECT 360.250 243.880 365.630 244.020 ; + RECT 360.250 243.820 360.570 243.880 ; + RECT 365.310 243.820 365.630 243.880 ; + RECT 365.310 93.060 365.630 93.120 ; + RECT 662.930 93.060 663.250 93.120 ; + RECT 365.310 92.920 663.250 93.060 ; + RECT 365.310 92.860 365.630 92.920 ; + RECT 662.930 92.860 663.250 92.920 ; + RECT 662.930 20.300 663.250 20.360 ; + RECT 668.910 20.300 669.230 20.360 ; + RECT 662.930 20.160 669.230 20.300 ; + RECT 662.930 20.100 663.250 20.160 ; + RECT 668.910 20.100 669.230 20.160 ; + LAYER via ; + RECT 360.280 243.820 360.540 244.080 ; + RECT 365.340 243.820 365.600 244.080 ; + RECT 365.340 92.860 365.600 93.120 ; + RECT 662.960 92.860 663.220 93.120 ; + RECT 662.960 20.100 663.220 20.360 ; + RECT 668.940 20.100 669.200 20.360 ; + LAYER met2 ; + RECT 360.230 260.000 360.510 264.000 ; + RECT 360.340 244.110 360.480 260.000 ; + RECT 360.280 243.790 360.540 244.110 ; + RECT 365.340 243.790 365.600 244.110 ; + RECT 365.400 93.150 365.540 243.790 ; + RECT 365.340 92.830 365.600 93.150 ; + RECT 662.960 92.830 663.220 93.150 ; + RECT 663.020 20.390 663.160 92.830 ; + RECT 662.960 20.070 663.220 20.390 ; + RECT 668.940 20.070 669.200 20.390 ; + RECT 669.000 2.400 669.140 20.070 ; + RECT 668.790 -4.800 669.350 2.400 ; +======= LAYER met2 ; RECT 668.790 -4.800 669.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[2] PIN la_data_in[30] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 862.110 44.780 862.430 44.840 ; + RECT 1168.470 44.780 1168.790 44.840 ; + RECT 862.110 44.640 1168.790 44.780 ; + RECT 862.110 44.580 862.430 44.640 ; + RECT 1168.470 44.580 1168.790 44.640 ; + LAYER via ; + RECT 862.140 44.580 862.400 44.840 ; + RECT 1168.500 44.580 1168.760 44.840 ; + LAYER met2 ; + RECT 860.710 260.170 860.990 264.000 ; + RECT 860.710 260.030 862.340 260.170 ; + RECT 860.710 260.000 860.990 260.030 ; + RECT 862.200 44.870 862.340 260.030 ; + RECT 862.140 44.550 862.400 44.870 ; + RECT 1168.500 44.550 1168.760 44.870 ; + RECT 1168.560 2.400 1168.700 44.550 ; + RECT 1168.350 -4.800 1168.910 2.400 ; +======= LAYER met2 ; RECT 1168.350 -4.800 1168.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[30] PIN la_data_in[31] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 878.670 244.020 878.990 244.080 ; + RECT 882.810 244.020 883.130 244.080 ; + RECT 878.670 243.880 883.130 244.020 ; + RECT 878.670 243.820 878.990 243.880 ; + RECT 882.810 243.820 883.130 243.880 ; + RECT 882.810 51.920 883.130 51.980 ; + RECT 1180.430 51.920 1180.750 51.980 ; + RECT 882.810 51.780 1180.750 51.920 ; + RECT 882.810 51.720 883.130 51.780 ; + RECT 1180.430 51.720 1180.750 51.780 ; + RECT 1180.430 17.920 1180.750 17.980 ; + RECT 1185.950 17.920 1186.270 17.980 ; + RECT 1180.430 17.780 1186.270 17.920 ; + RECT 1180.430 17.720 1180.750 17.780 ; + RECT 1185.950 17.720 1186.270 17.780 ; + LAYER via ; + RECT 878.700 243.820 878.960 244.080 ; + RECT 882.840 243.820 883.100 244.080 ; + RECT 882.840 51.720 883.100 51.980 ; + RECT 1180.460 51.720 1180.720 51.980 ; + RECT 1180.460 17.720 1180.720 17.980 ; + RECT 1185.980 17.720 1186.240 17.980 ; + LAYER met2 ; + RECT 878.650 260.000 878.930 264.000 ; + RECT 878.760 244.110 878.900 260.000 ; + RECT 878.700 243.790 878.960 244.110 ; + RECT 882.840 243.790 883.100 244.110 ; + RECT 882.900 52.010 883.040 243.790 ; + RECT 882.840 51.690 883.100 52.010 ; + RECT 1180.460 51.690 1180.720 52.010 ; + RECT 1180.520 18.010 1180.660 51.690 ; + RECT 1180.460 17.690 1180.720 18.010 ; + RECT 1185.980 17.690 1186.240 18.010 ; + RECT 1186.040 2.400 1186.180 17.690 ; + RECT 1185.830 -4.800 1186.390 2.400 ; +======= LAYER met2 ; RECT 1185.830 -4.800 1186.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[31] PIN la_data_in[32] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 896.150 58.720 896.470 58.780 ; + RECT 1200.670 58.720 1200.990 58.780 ; + RECT 896.150 58.580 1200.990 58.720 ; + RECT 896.150 58.520 896.470 58.580 ; + RECT 1200.670 58.520 1200.990 58.580 ; + LAYER via ; + RECT 896.180 58.520 896.440 58.780 ; + RECT 1200.700 58.520 1200.960 58.780 ; + LAYER met2 ; + RECT 896.590 260.170 896.870 264.000 ; + RECT 896.240 260.030 896.870 260.170 ; + RECT 896.240 58.810 896.380 260.030 ; + RECT 896.590 260.000 896.870 260.030 ; + RECT 896.180 58.490 896.440 58.810 ; + RECT 1200.700 58.490 1200.960 58.810 ; + RECT 1200.760 16.730 1200.900 58.490 ; + RECT 1200.760 16.590 1204.120 16.730 ; + RECT 1203.980 2.400 1204.120 16.590 ; + RECT 1203.770 -4.800 1204.330 2.400 ; +======= LAYER met2 ; RECT 1203.770 -4.800 1204.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[32] PIN la_data_in[33] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 917.310 65.520 917.630 65.580 ; + RECT 1221.830 65.520 1222.150 65.580 ; + RECT 917.310 65.380 1222.150 65.520 ; + RECT 917.310 65.320 917.630 65.380 ; + RECT 1221.830 65.320 1222.150 65.380 ; + LAYER via ; + RECT 917.340 65.320 917.600 65.580 ; + RECT 1221.860 65.320 1222.120 65.580 ; + LAYER met2 ; + RECT 914.530 260.170 914.810 264.000 ; + RECT 914.530 260.030 917.540 260.170 ; + RECT 914.530 260.000 914.810 260.030 ; + RECT 917.400 65.610 917.540 260.030 ; + RECT 917.340 65.290 917.600 65.610 ; + RECT 1221.860 65.290 1222.120 65.610 ; + RECT 1221.920 2.400 1222.060 65.290 ; + RECT 1221.710 -4.800 1222.270 2.400 ; +======= LAYER met2 ; RECT 1221.710 -4.800 1222.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[33] PIN la_data_in[34] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 932.490 244.020 932.810 244.080 ; + RECT 938.010 244.020 938.330 244.080 ; + RECT 932.490 243.880 938.330 244.020 ; + RECT 932.490 243.820 932.810 243.880 ; + RECT 938.010 243.820 938.330 243.880 ; + RECT 938.010 72.320 938.330 72.380 ; + RECT 1235.170 72.320 1235.490 72.380 ; + RECT 938.010 72.180 1235.490 72.320 ; + RECT 938.010 72.120 938.330 72.180 ; + RECT 1235.170 72.120 1235.490 72.180 ; + LAYER via ; + RECT 932.520 243.820 932.780 244.080 ; + RECT 938.040 243.820 938.300 244.080 ; + RECT 938.040 72.120 938.300 72.380 ; + RECT 1235.200 72.120 1235.460 72.380 ; + LAYER met2 ; + RECT 932.470 260.000 932.750 264.000 ; + RECT 932.580 244.110 932.720 260.000 ; + RECT 932.520 243.790 932.780 244.110 ; + RECT 938.040 243.790 938.300 244.110 ; + RECT 938.100 72.410 938.240 243.790 ; + RECT 938.040 72.090 938.300 72.410 ; + RECT 1235.200 72.090 1235.460 72.410 ; + RECT 1235.260 16.730 1235.400 72.090 ; + RECT 1235.260 16.590 1240.000 16.730 ; + RECT 1239.860 2.400 1240.000 16.590 ; + RECT 1239.650 -4.800 1240.210 2.400 ; +======= LAYER met2 ; RECT 1239.650 -4.800 1240.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[34] PIN la_data_in[35] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 951.810 24.040 952.130 24.100 ; + RECT 1257.250 24.040 1257.570 24.100 ; + RECT 951.810 23.900 1257.570 24.040 ; + RECT 951.810 23.840 952.130 23.900 ; + RECT 1257.250 23.840 1257.570 23.900 ; + LAYER via ; + RECT 951.840 23.840 952.100 24.100 ; + RECT 1257.280 23.840 1257.540 24.100 ; + LAYER met2 ; + RECT 950.410 260.170 950.690 264.000 ; + RECT 950.410 260.030 952.040 260.170 ; + RECT 950.410 260.000 950.690 260.030 ; + RECT 951.900 24.130 952.040 260.030 ; + RECT 951.840 23.810 952.100 24.130 ; + RECT 1257.280 23.810 1257.540 24.130 ; + RECT 1257.340 2.400 1257.480 23.810 ; + RECT 1257.130 -4.800 1257.690 2.400 ; +======= LAYER met2 ; RECT 1257.130 -4.800 1257.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[35] PIN la_data_in[36] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 967.910 244.020 968.230 244.080 ; + RECT 972.510 244.020 972.830 244.080 ; + RECT 967.910 243.880 972.830 244.020 ; + RECT 967.910 243.820 968.230 243.880 ; + RECT 972.510 243.820 972.830 243.880 ; + RECT 972.510 79.460 972.830 79.520 ; + RECT 1269.670 79.460 1269.990 79.520 ; + RECT 972.510 79.320 1269.990 79.460 ; + RECT 972.510 79.260 972.830 79.320 ; + RECT 1269.670 79.260 1269.990 79.320 ; + LAYER via ; + RECT 967.940 243.820 968.200 244.080 ; + RECT 972.540 243.820 972.800 244.080 ; + RECT 972.540 79.260 972.800 79.520 ; + RECT 1269.700 79.260 1269.960 79.520 ; + LAYER met2 ; + RECT 967.890 260.000 968.170 264.000 ; + RECT 968.000 244.110 968.140 260.000 ; + RECT 967.940 243.790 968.200 244.110 ; + RECT 972.540 243.790 972.800 244.110 ; + RECT 972.600 79.550 972.740 243.790 ; + RECT 972.540 79.230 972.800 79.550 ; + RECT 1269.700 79.230 1269.960 79.550 ; + RECT 1269.760 16.730 1269.900 79.230 ; + RECT 1269.760 16.590 1275.420 16.730 ; + RECT 1275.280 2.400 1275.420 16.590 ; + RECT 1275.070 -4.800 1275.630 2.400 ; +======= LAYER met2 ; RECT 1275.070 -4.800 1275.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[36] PIN la_data_in[37] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 985.850 86.260 986.170 86.320 ; + RECT 1290.370 86.260 1290.690 86.320 ; + RECT 985.850 86.120 1290.690 86.260 ; + RECT 985.850 86.060 986.170 86.120 ; + RECT 1290.370 86.060 1290.690 86.120 ; + LAYER via ; + RECT 985.880 86.060 986.140 86.320 ; + RECT 1290.400 86.060 1290.660 86.320 ; + LAYER met2 ; + RECT 985.830 260.000 986.110 264.000 ; + RECT 985.940 86.350 986.080 260.000 ; + RECT 985.880 86.030 986.140 86.350 ; + RECT 1290.400 86.030 1290.660 86.350 ; + RECT 1290.460 17.410 1290.600 86.030 ; + RECT 1290.460 17.270 1293.360 17.410 ; + RECT 1293.220 2.400 1293.360 17.270 ; + RECT 1293.010 -4.800 1293.570 2.400 ; +======= LAYER met2 ; RECT 1293.010 -4.800 1293.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[37] PIN la_data_in[38] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1007.010 141.340 1007.330 141.400 ; + RECT 1311.530 141.340 1311.850 141.400 ; + RECT 1007.010 141.200 1311.850 141.340 ; + RECT 1007.010 141.140 1007.330 141.200 ; + RECT 1311.530 141.140 1311.850 141.200 ; + LAYER via ; + RECT 1007.040 141.140 1007.300 141.400 ; + RECT 1311.560 141.140 1311.820 141.400 ; + LAYER met2 ; + RECT 1003.770 260.170 1004.050 264.000 ; + RECT 1003.770 260.030 1007.240 260.170 ; + RECT 1003.770 260.000 1004.050 260.030 ; + RECT 1007.100 141.430 1007.240 260.030 ; + RECT 1007.040 141.110 1007.300 141.430 ; + RECT 1311.560 141.110 1311.820 141.430 ; + RECT 1311.620 17.410 1311.760 141.110 ; + RECT 1311.160 17.270 1311.760 17.410 ; + RECT 1311.160 2.400 1311.300 17.270 ; + RECT 1310.950 -4.800 1311.510 2.400 ; +======= LAYER met2 ; RECT 1310.950 -4.800 1311.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[38] PIN la_data_in[39] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1021.730 244.020 1022.050 244.080 ; + RECT 1027.710 244.020 1028.030 244.080 ; + RECT 1021.730 243.880 1028.030 244.020 ; + RECT 1021.730 243.820 1022.050 243.880 ; + RECT 1027.710 243.820 1028.030 243.880 ; + RECT 1027.710 99.860 1028.030 99.920 ; + RECT 1324.870 99.860 1325.190 99.920 ; + RECT 1027.710 99.720 1325.190 99.860 ; + RECT 1027.710 99.660 1028.030 99.720 ; + RECT 1324.870 99.660 1325.190 99.720 ; + LAYER via ; + RECT 1021.760 243.820 1022.020 244.080 ; + RECT 1027.740 243.820 1028.000 244.080 ; + RECT 1027.740 99.660 1028.000 99.920 ; + RECT 1324.900 99.660 1325.160 99.920 ; + LAYER met2 ; + RECT 1021.710 260.000 1021.990 264.000 ; + RECT 1021.820 244.110 1021.960 260.000 ; + RECT 1021.760 243.790 1022.020 244.110 ; + RECT 1027.740 243.790 1028.000 244.110 ; + RECT 1027.800 99.950 1027.940 243.790 ; + RECT 1027.740 99.630 1028.000 99.950 ; + RECT 1324.900 99.630 1325.160 99.950 ; + RECT 1324.960 17.410 1325.100 99.630 ; + RECT 1324.960 17.270 1329.240 17.410 ; + RECT 1329.100 2.400 1329.240 17.270 ; + RECT 1328.890 -4.800 1329.450 2.400 ; +======= LAYER met2 ; RECT 1328.890 -4.800 1329.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[39] PIN la_data_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 379.110 99.860 379.430 99.920 ; + RECT 683.170 99.860 683.490 99.920 ; + RECT 379.110 99.720 683.490 99.860 ; + RECT 379.110 99.660 379.430 99.720 ; + RECT 683.170 99.660 683.490 99.720 ; + LAYER via ; + RECT 379.140 99.660 379.400 99.920 ; + RECT 683.200 99.660 683.460 99.920 ; + LAYER met2 ; + RECT 378.170 260.170 378.450 264.000 ; + RECT 378.170 260.030 379.340 260.170 ; + RECT 378.170 260.000 378.450 260.030 ; + RECT 379.200 99.950 379.340 260.030 ; + RECT 379.140 99.630 379.400 99.950 ; + RECT 683.200 99.630 683.460 99.950 ; + RECT 683.260 16.730 683.400 99.630 ; + RECT 683.260 16.590 686.620 16.730 ; + RECT 686.480 2.400 686.620 16.590 ; + RECT 686.270 -4.800 686.830 2.400 ; +======= LAYER met2 ; RECT 686.270 -4.800 686.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[3] PIN la_data_in[40] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1041.510 93.060 1041.830 93.120 ; + RECT 1345.570 93.060 1345.890 93.120 ; + RECT 1041.510 92.920 1345.890 93.060 ; + RECT 1041.510 92.860 1041.830 92.920 ; + RECT 1345.570 92.860 1345.890 92.920 ; + LAYER via ; + RECT 1041.540 92.860 1041.800 93.120 ; + RECT 1345.600 92.860 1345.860 93.120 ; + LAYER met2 ; + RECT 1039.650 260.170 1039.930 264.000 ; + RECT 1039.650 260.030 1041.740 260.170 ; + RECT 1039.650 260.000 1039.930 260.030 ; + RECT 1041.600 93.150 1041.740 260.030 ; + RECT 1041.540 92.830 1041.800 93.150 ; + RECT 1345.600 92.830 1345.860 93.150 ; + RECT 1345.660 17.410 1345.800 92.830 ; + RECT 1345.660 17.270 1346.720 17.410 ; + RECT 1346.580 2.400 1346.720 17.270 ; + RECT 1346.370 -4.800 1346.930 2.400 ; +======= LAYER met2 ; RECT 1346.370 -4.800 1346.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[40] PIN la_data_in[41] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1057.610 244.020 1057.930 244.080 ; + RECT 1062.210 244.020 1062.530 244.080 ; + RECT 1057.610 243.880 1062.530 244.020 ; + RECT 1057.610 243.820 1057.930 243.880 ; + RECT 1062.210 243.820 1062.530 243.880 ; + RECT 1062.210 107.000 1062.530 107.060 ; + RECT 1359.370 107.000 1359.690 107.060 ; + RECT 1062.210 106.860 1359.690 107.000 ; + RECT 1062.210 106.800 1062.530 106.860 ; + RECT 1359.370 106.800 1359.690 106.860 ; + LAYER via ; + RECT 1057.640 243.820 1057.900 244.080 ; + RECT 1062.240 243.820 1062.500 244.080 ; + RECT 1062.240 106.800 1062.500 107.060 ; + RECT 1359.400 106.800 1359.660 107.060 ; + LAYER met2 ; + RECT 1057.590 260.000 1057.870 264.000 ; + RECT 1057.700 244.110 1057.840 260.000 ; + RECT 1057.640 243.790 1057.900 244.110 ; + RECT 1062.240 243.790 1062.500 244.110 ; + RECT 1062.300 107.090 1062.440 243.790 ; + RECT 1062.240 106.770 1062.500 107.090 ; + RECT 1359.400 106.770 1359.660 107.090 ; + RECT 1359.460 17.410 1359.600 106.770 ; + RECT 1359.460 17.270 1364.660 17.410 ; + RECT 1364.520 2.400 1364.660 17.270 ; + RECT 1364.310 -4.800 1364.870 2.400 ; +======= LAYER met2 ; RECT 1364.310 -4.800 1364.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[41] PIN la_data_in[42] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1075.550 113.800 1075.870 113.860 ; + RECT 1380.070 113.800 1380.390 113.860 ; + RECT 1075.550 113.660 1380.390 113.800 ; + RECT 1075.550 113.600 1075.870 113.660 ; + RECT 1380.070 113.600 1380.390 113.660 ; + LAYER via ; + RECT 1075.580 113.600 1075.840 113.860 ; + RECT 1380.100 113.600 1380.360 113.860 ; + LAYER met2 ; + RECT 1075.530 260.000 1075.810 264.000 ; + RECT 1075.640 113.890 1075.780 260.000 ; + RECT 1075.580 113.570 1075.840 113.890 ; + RECT 1380.100 113.570 1380.360 113.890 ; + RECT 1380.160 17.410 1380.300 113.570 ; + RECT 1380.160 17.270 1382.600 17.410 ; + RECT 1382.460 2.400 1382.600 17.270 ; + RECT 1382.250 -4.800 1382.810 2.400 ; +======= LAYER met2 ; RECT 1382.250 -4.800 1382.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[42] PIN la_data_in[43] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1093.030 244.020 1093.350 244.080 ; + RECT 1096.710 244.020 1097.030 244.080 ; + RECT 1093.030 243.880 1097.030 244.020 ; + RECT 1093.030 243.820 1093.350 243.880 ; + RECT 1096.710 243.820 1097.030 243.880 ; + RECT 1096.710 31.180 1097.030 31.240 ; + RECT 1399.850 31.180 1400.170 31.240 ; + RECT 1096.710 31.040 1400.170 31.180 ; + RECT 1096.710 30.980 1097.030 31.040 ; + RECT 1399.850 30.980 1400.170 31.040 ; + LAYER via ; + RECT 1093.060 243.820 1093.320 244.080 ; + RECT 1096.740 243.820 1097.000 244.080 ; + RECT 1096.740 30.980 1097.000 31.240 ; + RECT 1399.880 30.980 1400.140 31.240 ; + LAYER met2 ; + RECT 1093.010 260.000 1093.290 264.000 ; + RECT 1093.120 244.110 1093.260 260.000 ; + RECT 1093.060 243.790 1093.320 244.110 ; + RECT 1096.740 243.790 1097.000 244.110 ; + RECT 1096.800 31.270 1096.940 243.790 ; + RECT 1096.740 30.950 1097.000 31.270 ; + RECT 1399.880 30.950 1400.140 31.270 ; + RECT 1399.940 30.330 1400.080 30.950 ; + RECT 1399.940 30.190 1400.540 30.330 ; + RECT 1400.400 2.400 1400.540 30.190 ; + RECT 1400.190 -4.800 1400.750 2.400 ; +======= LAYER met2 ; RECT 1400.190 -4.800 1400.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[43] PIN la_data_in[44] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1110.970 244.020 1111.290 244.080 ; + RECT 1117.410 244.020 1117.730 244.080 ; + RECT 1110.970 243.880 1117.730 244.020 ; + RECT 1110.970 243.820 1111.290 243.880 ; + RECT 1117.410 243.820 1117.730 243.880 ; + RECT 1117.410 37.980 1117.730 38.040 ; + RECT 1418.250 37.980 1418.570 38.040 ; + RECT 1117.410 37.840 1418.570 37.980 ; + RECT 1117.410 37.780 1117.730 37.840 ; + RECT 1418.250 37.780 1418.570 37.840 ; + LAYER via ; + RECT 1111.000 243.820 1111.260 244.080 ; + RECT 1117.440 243.820 1117.700 244.080 ; + RECT 1117.440 37.780 1117.700 38.040 ; + RECT 1418.280 37.780 1418.540 38.040 ; + LAYER met2 ; + RECT 1110.950 260.000 1111.230 264.000 ; + RECT 1111.060 244.110 1111.200 260.000 ; + RECT 1111.000 243.790 1111.260 244.110 ; + RECT 1117.440 243.790 1117.700 244.110 ; + RECT 1117.500 38.070 1117.640 243.790 ; + RECT 1117.440 37.750 1117.700 38.070 ; + RECT 1418.280 37.750 1418.540 38.070 ; + RECT 1418.340 2.400 1418.480 37.750 ; + RECT 1418.130 -4.800 1418.690 2.400 ; +======= LAYER met2 ; RECT 1418.130 -4.800 1418.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[44] PIN la_data_in[45] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1131.210 120.600 1131.530 120.660 ; + RECT 1435.730 120.600 1436.050 120.660 ; + RECT 1131.210 120.460 1436.050 120.600 ; + RECT 1131.210 120.400 1131.530 120.460 ; + RECT 1435.730 120.400 1436.050 120.460 ; + LAYER via ; + RECT 1131.240 120.400 1131.500 120.660 ; + RECT 1435.760 120.400 1436.020 120.660 ; + LAYER met2 ; + RECT 1128.890 260.170 1129.170 264.000 ; + RECT 1128.890 260.030 1131.440 260.170 ; + RECT 1128.890 260.000 1129.170 260.030 ; + RECT 1131.300 120.690 1131.440 260.030 ; + RECT 1131.240 120.370 1131.500 120.690 ; + RECT 1435.760 120.370 1436.020 120.690 ; + RECT 1435.820 2.400 1435.960 120.370 ; + RECT 1435.610 -4.800 1436.170 2.400 ; +======= LAYER met2 ; RECT 1435.610 -4.800 1436.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[45] PIN la_data_in[46] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1146.850 244.020 1147.170 244.080 ; + RECT 1151.910 244.020 1152.230 244.080 ; + RECT 1146.850 243.880 1152.230 244.020 ; + RECT 1146.850 243.820 1147.170 243.880 ; + RECT 1151.910 243.820 1152.230 243.880 ; + RECT 1151.910 45.120 1152.230 45.180 ; + RECT 1453.670 45.120 1453.990 45.180 ; + RECT 1151.910 44.980 1453.990 45.120 ; + RECT 1151.910 44.920 1152.230 44.980 ; + RECT 1453.670 44.920 1453.990 44.980 ; + LAYER via ; + RECT 1146.880 243.820 1147.140 244.080 ; + RECT 1151.940 243.820 1152.200 244.080 ; + RECT 1151.940 44.920 1152.200 45.180 ; + RECT 1453.700 44.920 1453.960 45.180 ; + LAYER met2 ; + RECT 1146.830 260.000 1147.110 264.000 ; + RECT 1146.940 244.110 1147.080 260.000 ; + RECT 1146.880 243.790 1147.140 244.110 ; + RECT 1151.940 243.790 1152.200 244.110 ; + RECT 1152.000 45.210 1152.140 243.790 ; + RECT 1151.940 44.890 1152.200 45.210 ; + RECT 1453.700 44.890 1453.960 45.210 ; + RECT 1453.760 2.400 1453.900 44.890 ; + RECT 1453.550 -4.800 1454.110 2.400 ; +======= LAYER met2 ; RECT 1453.550 -4.800 1454.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[46] PIN la_data_in[47] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1165.710 51.580 1166.030 51.640 ; + RECT 1469.770 51.580 1470.090 51.640 ; + RECT 1165.710 51.440 1470.090 51.580 ; + RECT 1165.710 51.380 1166.030 51.440 ; + RECT 1469.770 51.380 1470.090 51.440 ; + LAYER via ; + RECT 1165.740 51.380 1166.000 51.640 ; + RECT 1469.800 51.380 1470.060 51.640 ; + LAYER met2 ; + RECT 1164.770 260.170 1165.050 264.000 ; + RECT 1164.770 260.030 1165.940 260.170 ; + RECT 1164.770 260.000 1165.050 260.030 ; + RECT 1165.800 51.670 1165.940 260.030 ; + RECT 1165.740 51.350 1166.000 51.670 ; + RECT 1469.800 51.350 1470.060 51.670 ; + RECT 1469.860 16.730 1470.000 51.350 ; + RECT 1469.860 16.590 1471.840 16.730 ; + RECT 1471.700 2.400 1471.840 16.590 ; + RECT 1471.490 -4.800 1472.050 2.400 ; +======= LAYER met2 ; RECT 1471.490 -4.800 1472.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[47] PIN la_data_in[48] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1186.410 128.080 1186.730 128.140 ; + RECT 1484.030 128.080 1484.350 128.140 ; + RECT 1186.410 127.940 1484.350 128.080 ; + RECT 1186.410 127.880 1186.730 127.940 ; + RECT 1484.030 127.880 1484.350 127.940 ; + LAYER via ; + RECT 1186.440 127.880 1186.700 128.140 ; + RECT 1484.060 127.880 1484.320 128.140 ; + LAYER met2 ; + RECT 1182.710 260.170 1182.990 264.000 ; + RECT 1182.710 260.030 1186.640 260.170 ; + RECT 1182.710 260.000 1182.990 260.030 ; + RECT 1186.500 128.170 1186.640 260.030 ; + RECT 1186.440 127.850 1186.700 128.170 ; + RECT 1484.060 127.850 1484.320 128.170 ; + RECT 1484.120 17.410 1484.260 127.850 ; + RECT 1484.120 17.270 1489.780 17.410 ; + RECT 1489.640 2.400 1489.780 17.270 ; + RECT 1489.430 -4.800 1489.990 2.400 ; +======= LAYER met2 ; RECT 1489.430 -4.800 1489.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[48] PIN la_data_in[49] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1200.670 241.640 1200.990 241.700 ; + RECT 1207.110 241.640 1207.430 241.700 ; + RECT 1200.670 241.500 1207.430 241.640 ; + RECT 1200.670 241.440 1200.990 241.500 ; + RECT 1207.110 241.440 1207.430 241.500 ; + RECT 1207.110 58.720 1207.430 58.780 ; + RECT 1504.270 58.720 1504.590 58.780 ; + RECT 1207.110 58.580 1504.590 58.720 ; + RECT 1207.110 58.520 1207.430 58.580 ; + RECT 1504.270 58.520 1504.590 58.580 ; + LAYER via ; + RECT 1200.700 241.440 1200.960 241.700 ; + RECT 1207.140 241.440 1207.400 241.700 ; + RECT 1207.140 58.520 1207.400 58.780 ; + RECT 1504.300 58.520 1504.560 58.780 ; + LAYER met2 ; + RECT 1200.650 260.000 1200.930 264.000 ; + RECT 1200.760 241.730 1200.900 260.000 ; + RECT 1200.700 241.410 1200.960 241.730 ; + RECT 1207.140 241.410 1207.400 241.730 ; + RECT 1207.200 58.810 1207.340 241.410 ; + RECT 1207.140 58.490 1207.400 58.810 ; + RECT 1504.300 58.490 1504.560 58.810 ; + RECT 1504.360 17.410 1504.500 58.490 ; + RECT 1504.360 17.270 1507.260 17.410 ; + RECT 1507.120 2.400 1507.260 17.270 ; + RECT 1506.910 -4.800 1507.470 2.400 ; +======= LAYER met2 ; RECT 1506.910 -4.800 1507.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[49] PIN la_data_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 399.810 107.000 400.130 107.060 ; + RECT 704.330 107.000 704.650 107.060 ; + RECT 399.810 106.860 704.650 107.000 ; + RECT 399.810 106.800 400.130 106.860 ; + RECT 704.330 106.800 704.650 106.860 ; + LAYER via ; + RECT 399.840 106.800 400.100 107.060 ; + RECT 704.360 106.800 704.620 107.060 ; + LAYER met2 ; + RECT 396.110 260.170 396.390 264.000 ; + RECT 396.110 260.030 400.040 260.170 ; + RECT 396.110 260.000 396.390 260.030 ; + RECT 399.900 107.090 400.040 260.030 ; + RECT 399.840 106.770 400.100 107.090 ; + RECT 704.360 106.770 704.620 107.090 ; + RECT 704.420 2.400 704.560 106.770 ; + RECT 704.210 -4.800 704.770 2.400 ; +======= LAYER met2 ; RECT 704.210 -4.800 704.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[4] PIN la_data_in[50] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1220.910 134.540 1221.230 134.600 ; + RECT 1525.430 134.540 1525.750 134.600 ; + RECT 1220.910 134.400 1525.750 134.540 ; + RECT 1220.910 134.340 1221.230 134.400 ; + RECT 1525.430 134.340 1525.750 134.400 ; + LAYER via ; + RECT 1220.940 134.340 1221.200 134.600 ; + RECT 1525.460 134.340 1525.720 134.600 ; + LAYER met2 ; + RECT 1218.130 260.170 1218.410 264.000 ; + RECT 1218.130 260.030 1221.140 260.170 ; + RECT 1218.130 260.000 1218.410 260.030 ; + RECT 1221.000 134.630 1221.140 260.030 ; + RECT 1220.940 134.310 1221.200 134.630 ; + RECT 1525.460 134.310 1525.720 134.630 ; + RECT 1525.520 17.410 1525.660 134.310 ; + RECT 1525.060 17.270 1525.660 17.410 ; + RECT 1525.060 2.400 1525.200 17.270 ; + RECT 1524.850 -4.800 1525.410 2.400 ; +======= LAYER met2 ; RECT 1524.850 -4.800 1525.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[50] PIN la_data_in[51] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1236.090 244.020 1236.410 244.080 ; + RECT 1241.610 244.020 1241.930 244.080 ; + RECT 1236.090 243.880 1241.930 244.020 ; + RECT 1236.090 243.820 1236.410 243.880 ; + RECT 1241.610 243.820 1241.930 243.880 ; + RECT 1241.610 72.320 1241.930 72.380 ; + RECT 1538.770 72.320 1539.090 72.380 ; + RECT 1241.610 72.180 1539.090 72.320 ; + RECT 1241.610 72.120 1241.930 72.180 ; + RECT 1538.770 72.120 1539.090 72.180 ; + LAYER via ; + RECT 1236.120 243.820 1236.380 244.080 ; + RECT 1241.640 243.820 1241.900 244.080 ; + RECT 1241.640 72.120 1241.900 72.380 ; + RECT 1538.800 72.120 1539.060 72.380 ; + LAYER met2 ; + RECT 1236.070 260.000 1236.350 264.000 ; + RECT 1236.180 244.110 1236.320 260.000 ; + RECT 1236.120 243.790 1236.380 244.110 ; + RECT 1241.640 243.790 1241.900 244.110 ; + RECT 1241.700 72.410 1241.840 243.790 ; + RECT 1241.640 72.090 1241.900 72.410 ; + RECT 1538.800 72.090 1539.060 72.410 ; + RECT 1538.860 16.730 1539.000 72.090 ; + RECT 1538.860 16.590 1543.140 16.730 ; + RECT 1543.000 2.400 1543.140 16.590 ; + RECT 1542.790 -4.800 1543.350 2.400 ; +======= LAYER met2 ; RECT 1542.790 -4.800 1543.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[51] PIN la_data_in[52] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1255.410 65.520 1255.730 65.580 ; + RECT 1559.470 65.520 1559.790 65.580 ; + RECT 1255.410 65.380 1559.790 65.520 ; + RECT 1255.410 65.320 1255.730 65.380 ; + RECT 1559.470 65.320 1559.790 65.380 ; + LAYER via ; + RECT 1255.440 65.320 1255.700 65.580 ; + RECT 1559.500 65.320 1559.760 65.580 ; + LAYER met2 ; + RECT 1254.010 260.170 1254.290 264.000 ; + RECT 1254.010 260.030 1255.640 260.170 ; + RECT 1254.010 260.000 1254.290 260.030 ; + RECT 1255.500 65.610 1255.640 260.030 ; + RECT 1255.440 65.290 1255.700 65.610 ; + RECT 1559.500 65.290 1559.760 65.610 ; + RECT 1559.560 16.730 1559.700 65.290 ; + RECT 1559.560 16.590 1561.080 16.730 ; + RECT 1560.940 2.400 1561.080 16.590 ; + RECT 1560.730 -4.800 1561.290 2.400 ; +======= LAYER met2 ; RECT 1560.730 -4.800 1561.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[52] PIN la_data_in[53] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1271.970 244.020 1272.290 244.080 ; + RECT 1276.110 244.020 1276.430 244.080 ; + RECT 1271.970 243.880 1276.430 244.020 ; + RECT 1271.970 243.820 1272.290 243.880 ; + RECT 1276.110 243.820 1276.430 243.880 ; + RECT 1276.110 24.380 1276.430 24.440 ; + RECT 1578.790 24.380 1579.110 24.440 ; + RECT 1276.110 24.240 1579.110 24.380 ; + RECT 1276.110 24.180 1276.430 24.240 ; + RECT 1578.790 24.180 1579.110 24.240 ; + LAYER via ; + RECT 1272.000 243.820 1272.260 244.080 ; + RECT 1276.140 243.820 1276.400 244.080 ; + RECT 1276.140 24.180 1276.400 24.440 ; + RECT 1578.820 24.180 1579.080 24.440 ; + LAYER met2 ; + RECT 1271.950 260.000 1272.230 264.000 ; + RECT 1272.060 244.110 1272.200 260.000 ; + RECT 1272.000 243.790 1272.260 244.110 ; + RECT 1276.140 243.790 1276.400 244.110 ; + RECT 1276.200 24.470 1276.340 243.790 ; + RECT 1276.140 24.150 1276.400 24.470 ; + RECT 1578.820 24.150 1579.080 24.470 ; + RECT 1578.880 2.400 1579.020 24.150 ; + RECT 1578.670 -4.800 1579.230 2.400 ; +======= LAYER met2 ; RECT 1578.670 -4.800 1579.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[53] PIN la_data_in[54] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1289.450 79.460 1289.770 79.520 ; + RECT 1593.970 79.460 1594.290 79.520 ; + RECT 1289.450 79.320 1594.290 79.460 ; + RECT 1289.450 79.260 1289.770 79.320 ; + RECT 1593.970 79.260 1594.290 79.320 ; + LAYER via ; + RECT 1289.480 79.260 1289.740 79.520 ; + RECT 1594.000 79.260 1594.260 79.520 ; + LAYER met2 ; + RECT 1289.890 260.170 1290.170 264.000 ; + RECT 1289.540 260.030 1290.170 260.170 ; + RECT 1289.540 79.550 1289.680 260.030 ; + RECT 1289.890 260.000 1290.170 260.030 ; + RECT 1289.480 79.230 1289.740 79.550 ; + RECT 1594.000 79.230 1594.260 79.550 ; + RECT 1594.060 16.730 1594.200 79.230 ; + RECT 1594.060 16.590 1596.500 16.730 ; + RECT 1596.360 2.400 1596.500 16.590 ; + RECT 1596.150 -4.800 1596.710 2.400 ; +======= LAYER met2 ; RECT 1596.150 -4.800 1596.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[54] PIN la_data_in[55] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1310.610 86.260 1310.930 86.320 ; + RECT 1608.230 86.260 1608.550 86.320 ; + RECT 1310.610 86.120 1608.550 86.260 ; + RECT 1310.610 86.060 1310.930 86.120 ; + RECT 1608.230 86.060 1608.550 86.120 ; + RECT 1608.230 38.320 1608.550 38.380 ; + RECT 1614.210 38.320 1614.530 38.380 ; + RECT 1608.230 38.180 1614.530 38.320 ; + RECT 1608.230 38.120 1608.550 38.180 ; + RECT 1614.210 38.120 1614.530 38.180 ; + LAYER via ; + RECT 1310.640 86.060 1310.900 86.320 ; + RECT 1608.260 86.060 1608.520 86.320 ; + RECT 1608.260 38.120 1608.520 38.380 ; + RECT 1614.240 38.120 1614.500 38.380 ; + LAYER met2 ; + RECT 1307.830 260.170 1308.110 264.000 ; + RECT 1307.830 260.030 1310.840 260.170 ; + RECT 1307.830 260.000 1308.110 260.030 ; + RECT 1310.700 86.350 1310.840 260.030 ; + RECT 1310.640 86.030 1310.900 86.350 ; + RECT 1608.260 86.030 1608.520 86.350 ; + RECT 1608.320 38.410 1608.460 86.030 ; + RECT 1608.260 38.090 1608.520 38.410 ; + RECT 1614.240 38.090 1614.500 38.410 ; + RECT 1614.300 2.400 1614.440 38.090 ; + RECT 1614.090 -4.800 1614.650 2.400 ; +======= LAYER met2 ; RECT 1614.090 -4.800 1614.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[55] PIN la_data_in[56] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1325.790 244.020 1326.110 244.080 ; + RECT 1331.310 244.020 1331.630 244.080 ; + RECT 1325.790 243.880 1331.630 244.020 ; + RECT 1325.790 243.820 1326.110 243.880 ; + RECT 1331.310 243.820 1331.630 243.880 ; + RECT 1331.310 99.860 1331.630 99.920 ; + RECT 1628.470 99.860 1628.790 99.920 ; + RECT 1331.310 99.720 1628.790 99.860 ; + RECT 1331.310 99.660 1331.630 99.720 ; + RECT 1628.470 99.660 1628.790 99.720 ; + RECT 1628.470 62.260 1628.790 62.520 ; + RECT 1628.560 62.120 1628.700 62.260 ; + RECT 1632.150 62.120 1632.470 62.180 ; + RECT 1628.560 61.980 1632.470 62.120 ; + RECT 1632.150 61.920 1632.470 61.980 ; + RECT 1632.150 47.980 1632.470 48.240 ; + RECT 1632.240 47.560 1632.380 47.980 ; + RECT 1632.150 47.300 1632.470 47.560 ; + LAYER via ; + RECT 1325.820 243.820 1326.080 244.080 ; + RECT 1331.340 243.820 1331.600 244.080 ; + RECT 1331.340 99.660 1331.600 99.920 ; + RECT 1628.500 99.660 1628.760 99.920 ; + RECT 1628.500 62.260 1628.760 62.520 ; + RECT 1632.180 61.920 1632.440 62.180 ; + RECT 1632.180 47.980 1632.440 48.240 ; + RECT 1632.180 47.300 1632.440 47.560 ; + LAYER met2 ; + RECT 1325.770 260.000 1326.050 264.000 ; + RECT 1325.880 244.110 1326.020 260.000 ; + RECT 1325.820 243.790 1326.080 244.110 ; + RECT 1331.340 243.790 1331.600 244.110 ; + RECT 1331.400 99.950 1331.540 243.790 ; + RECT 1331.340 99.630 1331.600 99.950 ; + RECT 1628.500 99.630 1628.760 99.950 ; + RECT 1628.560 62.550 1628.700 99.630 ; + RECT 1628.500 62.230 1628.760 62.550 ; + RECT 1632.180 61.890 1632.440 62.210 ; + RECT 1632.240 48.270 1632.380 61.890 ; + RECT 1632.180 47.950 1632.440 48.270 ; + RECT 1632.180 47.270 1632.440 47.590 ; + RECT 1632.240 2.400 1632.380 47.270 ; + RECT 1632.030 -4.800 1632.590 2.400 ; +======= LAYER met2 ; RECT 1632.030 -4.800 1632.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[56] PIN la_data_in[57] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1650.165 48.365 1650.335 93.415 ; + LAYER mcon ; + RECT 1650.165 93.245 1650.335 93.415 ; + LAYER met1 ; + RECT 1345.110 93.400 1345.430 93.460 ; + RECT 1650.105 93.400 1650.395 93.445 ; + RECT 1345.110 93.260 1650.395 93.400 ; + RECT 1345.110 93.200 1345.430 93.260 ; + RECT 1650.105 93.215 1650.395 93.260 ; + RECT 1650.090 48.520 1650.410 48.580 ; + RECT 1649.895 48.380 1650.410 48.520 ; + RECT 1650.090 48.320 1650.410 48.380 ; + LAYER via ; + RECT 1345.140 93.200 1345.400 93.460 ; + RECT 1650.120 48.320 1650.380 48.580 ; + LAYER met2 ; + RECT 1343.250 260.170 1343.530 264.000 ; + RECT 1343.250 260.030 1345.340 260.170 ; + RECT 1343.250 260.000 1343.530 260.030 ; + RECT 1345.200 93.490 1345.340 260.030 ; + RECT 1345.140 93.170 1345.400 93.490 ; + RECT 1650.120 48.290 1650.380 48.610 ; + RECT 1650.180 2.400 1650.320 48.290 ; + RECT 1649.970 -4.800 1650.530 2.400 ; +======= LAYER met2 ; RECT 1649.970 -4.800 1650.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[57] PIN la_data_in[58] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1361.210 244.020 1361.530 244.080 ; + RECT 1365.810 244.020 1366.130 244.080 ; + RECT 1361.210 243.880 1366.130 244.020 ; + RECT 1361.210 243.820 1361.530 243.880 ; + RECT 1365.810 243.820 1366.130 243.880 ; + RECT 1365.810 107.000 1366.130 107.060 ; + RECT 1662.970 107.000 1663.290 107.060 ; + RECT 1365.810 106.860 1663.290 107.000 ; + RECT 1365.810 106.800 1366.130 106.860 ; + RECT 1662.970 106.800 1663.290 106.860 ; + LAYER via ; + RECT 1361.240 243.820 1361.500 244.080 ; + RECT 1365.840 243.820 1366.100 244.080 ; + RECT 1365.840 106.800 1366.100 107.060 ; + RECT 1663.000 106.800 1663.260 107.060 ; + LAYER met2 ; + RECT 1361.190 260.000 1361.470 264.000 ; + RECT 1361.300 244.110 1361.440 260.000 ; + RECT 1361.240 243.790 1361.500 244.110 ; + RECT 1365.840 243.790 1366.100 244.110 ; + RECT 1365.900 107.090 1366.040 243.790 ; + RECT 1365.840 106.770 1366.100 107.090 ; + RECT 1663.000 106.770 1663.260 107.090 ; + RECT 1663.060 16.730 1663.200 106.770 ; + RECT 1663.060 16.590 1668.260 16.730 ; + RECT 1668.120 2.400 1668.260 16.590 ; + RECT 1667.910 -4.800 1668.470 2.400 ; +======= LAYER met2 ; RECT 1667.910 -4.800 1668.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[58] PIN la_data_in[59] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1379.610 237.900 1379.930 237.960 ; + RECT 1683.670 237.900 1683.990 237.960 ; + RECT 1379.610 237.760 1683.990 237.900 ; + RECT 1379.610 237.700 1379.930 237.760 ; + RECT 1683.670 237.700 1683.990 237.760 ; + LAYER via ; + RECT 1379.640 237.700 1379.900 237.960 ; + RECT 1683.700 237.700 1683.960 237.960 ; + LAYER met2 ; + RECT 1379.130 260.170 1379.410 264.000 ; + RECT 1379.130 260.030 1379.840 260.170 ; + RECT 1379.130 260.000 1379.410 260.030 ; + RECT 1379.700 237.990 1379.840 260.030 ; + RECT 1379.640 237.670 1379.900 237.990 ; + RECT 1683.700 237.670 1683.960 237.990 ; + RECT 1683.760 17.410 1683.900 237.670 ; + RECT 1683.760 17.270 1685.740 17.410 ; + RECT 1685.600 2.400 1685.740 17.270 ; + RECT 1685.390 -4.800 1685.950 2.400 ; +======= LAYER met2 ; RECT 1685.390 -4.800 1685.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[59] PIN la_data_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 414.070 243.340 414.390 243.400 ; + RECT 420.050 243.340 420.370 243.400 ; + RECT 414.070 243.200 420.370 243.340 ; + RECT 414.070 243.140 414.390 243.200 ; + RECT 420.050 243.140 420.370 243.200 ; + RECT 420.050 113.800 420.370 113.860 ; + RECT 717.670 113.800 717.990 113.860 ; + RECT 420.050 113.660 717.990 113.800 ; + RECT 420.050 113.600 420.370 113.660 ; + RECT 717.670 113.600 717.990 113.660 ; + LAYER via ; + RECT 414.100 243.140 414.360 243.400 ; + RECT 420.080 243.140 420.340 243.400 ; + RECT 420.080 113.600 420.340 113.860 ; + RECT 717.700 113.600 717.960 113.860 ; + LAYER met2 ; + RECT 414.050 260.000 414.330 264.000 ; + RECT 414.160 243.430 414.300 260.000 ; + RECT 414.100 243.110 414.360 243.430 ; + RECT 420.080 243.110 420.340 243.430 ; + RECT 420.140 113.890 420.280 243.110 ; + RECT 420.080 113.570 420.340 113.890 ; + RECT 717.700 113.570 717.960 113.890 ; + RECT 717.760 16.730 717.900 113.570 ; + RECT 717.760 16.590 722.500 16.730 ; + RECT 722.360 2.400 722.500 16.590 ; + RECT 722.150 -4.800 722.710 2.400 ; +======= LAYER met2 ; RECT 722.150 -4.800 722.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[5] PIN la_data_in[60] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1400.310 30.840 1400.630 30.900 ; + RECT 1703.450 30.840 1703.770 30.900 ; + RECT 1400.310 30.700 1703.770 30.840 ; + RECT 1400.310 30.640 1400.630 30.700 ; + RECT 1703.450 30.640 1703.770 30.700 ; + LAYER via ; + RECT 1400.340 30.640 1400.600 30.900 ; + RECT 1703.480 30.640 1703.740 30.900 ; + LAYER met2 ; + RECT 1397.070 260.170 1397.350 264.000 ; + RECT 1397.070 260.030 1400.540 260.170 ; + RECT 1397.070 260.000 1397.350 260.030 ; + RECT 1400.400 30.930 1400.540 260.030 ; + RECT 1400.340 30.610 1400.600 30.930 ; + RECT 1703.480 30.610 1703.740 30.930 ; + RECT 1703.540 2.400 1703.680 30.610 ; + RECT 1703.330 -4.800 1703.890 2.400 ; +======= LAYER met2 ; RECT 1703.330 -4.800 1703.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[60] PIN la_data_in[61] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1415.030 244.020 1415.350 244.080 ; + RECT 1421.010 244.020 1421.330 244.080 ; + RECT 1415.030 243.880 1421.330 244.020 ; + RECT 1415.030 243.820 1415.350 243.880 ; + RECT 1421.010 243.820 1421.330 243.880 ; + RECT 1421.010 37.980 1421.330 38.040 ; + RECT 1721.390 37.980 1721.710 38.040 ; + RECT 1421.010 37.840 1721.710 37.980 ; + RECT 1421.010 37.780 1421.330 37.840 ; + RECT 1721.390 37.780 1721.710 37.840 ; + LAYER via ; + RECT 1415.060 243.820 1415.320 244.080 ; + RECT 1421.040 243.820 1421.300 244.080 ; + RECT 1421.040 37.780 1421.300 38.040 ; + RECT 1721.420 37.780 1721.680 38.040 ; + LAYER met2 ; + RECT 1415.010 260.000 1415.290 264.000 ; + RECT 1415.120 244.110 1415.260 260.000 ; + RECT 1415.060 243.790 1415.320 244.110 ; + RECT 1421.040 243.790 1421.300 244.110 ; + RECT 1421.100 38.070 1421.240 243.790 ; + RECT 1421.040 37.750 1421.300 38.070 ; + RECT 1721.420 37.750 1721.680 38.070 ; + RECT 1721.480 2.400 1721.620 37.750 ; + RECT 1721.270 -4.800 1721.830 2.400 ; +======= LAYER met2 ; RECT 1721.270 -4.800 1721.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[61] PIN la_data_in[62] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1434.810 113.800 1435.130 113.860 ; + RECT 1739.330 113.800 1739.650 113.860 ; + RECT 1434.810 113.660 1739.650 113.800 ; + RECT 1434.810 113.600 1435.130 113.660 ; + RECT 1739.330 113.600 1739.650 113.660 ; + LAYER via ; + RECT 1434.840 113.600 1435.100 113.860 ; + RECT 1739.360 113.600 1739.620 113.860 ; + LAYER met2 ; + RECT 1432.950 260.170 1433.230 264.000 ; + RECT 1432.950 260.030 1435.040 260.170 ; + RECT 1432.950 260.000 1433.230 260.030 ; + RECT 1434.900 113.890 1435.040 260.030 ; + RECT 1434.840 113.570 1435.100 113.890 ; + RECT 1739.360 113.570 1739.620 113.890 ; + RECT 1739.420 2.400 1739.560 113.570 ; + RECT 1739.210 -4.800 1739.770 2.400 ; +======= LAYER met2 ; RECT 1739.210 -4.800 1739.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[62] PIN la_data_in[63] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1450.910 244.020 1451.230 244.080 ; + RECT 1455.510 244.020 1455.830 244.080 ; + RECT 1450.910 243.880 1455.830 244.020 ; + RECT 1450.910 243.820 1451.230 243.880 ; + RECT 1455.510 243.820 1455.830 243.880 ; + RECT 1455.510 44.780 1455.830 44.840 ; + RECT 1756.810 44.780 1757.130 44.840 ; + RECT 1455.510 44.640 1757.130 44.780 ; + RECT 1455.510 44.580 1455.830 44.640 ; + RECT 1756.810 44.580 1757.130 44.640 ; + LAYER via ; + RECT 1450.940 243.820 1451.200 244.080 ; + RECT 1455.540 243.820 1455.800 244.080 ; + RECT 1455.540 44.580 1455.800 44.840 ; + RECT 1756.840 44.580 1757.100 44.840 ; + LAYER met2 ; + RECT 1450.890 260.000 1451.170 264.000 ; + RECT 1451.000 244.110 1451.140 260.000 ; + RECT 1450.940 243.790 1451.200 244.110 ; + RECT 1455.540 243.790 1455.800 244.110 ; + RECT 1455.600 44.870 1455.740 243.790 ; + RECT 1455.540 44.550 1455.800 44.870 ; + RECT 1756.840 44.550 1757.100 44.870 ; + RECT 1756.900 2.400 1757.040 44.550 ; + RECT 1756.690 -4.800 1757.250 2.400 ; +======= LAYER met2 ; RECT 1756.690 -4.800 1757.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[63] PIN la_data_in[64] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1468.390 231.100 1468.710 231.160 ; + RECT 1773.370 231.100 1773.690 231.160 ; + RECT 1468.390 230.960 1773.690 231.100 ; + RECT 1468.390 230.900 1468.710 230.960 ; + RECT 1773.370 230.900 1773.690 230.960 ; + RECT 1773.370 2.960 1773.690 3.020 ; + RECT 1774.750 2.960 1775.070 3.020 ; + RECT 1773.370 2.820 1775.070 2.960 ; + RECT 1773.370 2.760 1773.690 2.820 ; + RECT 1774.750 2.760 1775.070 2.820 ; + LAYER via ; + RECT 1468.420 230.900 1468.680 231.160 ; + RECT 1773.400 230.900 1773.660 231.160 ; + RECT 1773.400 2.760 1773.660 3.020 ; + RECT 1774.780 2.760 1775.040 3.020 ; + LAYER met2 ; + RECT 1468.370 260.000 1468.650 264.000 ; + RECT 1468.480 231.190 1468.620 260.000 ; + RECT 1468.420 230.870 1468.680 231.190 ; + RECT 1773.400 230.870 1773.660 231.190 ; + RECT 1773.460 3.050 1773.600 230.870 ; + RECT 1773.400 2.730 1773.660 3.050 ; + RECT 1774.780 2.730 1775.040 3.050 ; + RECT 1774.840 2.400 1774.980 2.730 ; + RECT 1774.630 -4.800 1775.190 2.400 ; +======= LAYER met2 ; RECT 1774.630 -4.800 1775.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[64] PIN la_data_in[65] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1490.010 51.580 1490.330 51.640 ; + RECT 1787.170 51.580 1787.490 51.640 ; + RECT 1490.010 51.440 1787.490 51.580 ; + RECT 1490.010 51.380 1490.330 51.440 ; + RECT 1787.170 51.380 1787.490 51.440 ; + RECT 1787.630 2.960 1787.950 3.020 ; + RECT 1792.690 2.960 1793.010 3.020 ; + RECT 1787.630 2.820 1793.010 2.960 ; + RECT 1787.630 2.760 1787.950 2.820 ; + RECT 1792.690 2.760 1793.010 2.820 ; + LAYER via ; + RECT 1490.040 51.380 1490.300 51.640 ; + RECT 1787.200 51.380 1787.460 51.640 ; + RECT 1787.660 2.760 1787.920 3.020 ; + RECT 1792.720 2.760 1792.980 3.020 ; + LAYER met2 ; + RECT 1486.310 260.170 1486.590 264.000 ; + RECT 1486.310 260.030 1490.240 260.170 ; + RECT 1486.310 260.000 1486.590 260.030 ; + RECT 1490.100 51.670 1490.240 260.030 ; + RECT 1490.040 51.350 1490.300 51.670 ; + RECT 1787.200 51.350 1787.460 51.670 ; + RECT 1787.260 20.130 1787.400 51.350 ; + RECT 1787.260 19.990 1787.860 20.130 ; + RECT 1787.720 3.050 1787.860 19.990 ; + RECT 1787.660 2.730 1787.920 3.050 ; + RECT 1792.720 2.730 1792.980 3.050 ; + RECT 1792.780 2.400 1792.920 2.730 ; + RECT 1792.570 -4.800 1793.130 2.400 ; +======= LAYER met2 ; RECT 1792.570 -4.800 1793.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[65] PIN la_data_in[66] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1504.270 244.020 1504.590 244.080 ; + RECT 1510.710 244.020 1511.030 244.080 ; + RECT 1504.270 243.880 1511.030 244.020 ; + RECT 1504.270 243.820 1504.590 243.880 ; + RECT 1510.710 243.820 1511.030 243.880 ; + RECT 1510.710 59.060 1511.030 59.120 ; + RECT 1807.870 59.060 1808.190 59.120 ; + RECT 1510.710 58.920 1808.190 59.060 ; + RECT 1510.710 58.860 1511.030 58.920 ; + RECT 1807.870 58.860 1808.190 58.920 ; + RECT 1807.870 2.960 1808.190 3.020 ; + RECT 1810.630 2.960 1810.950 3.020 ; + RECT 1807.870 2.820 1810.950 2.960 ; + RECT 1807.870 2.760 1808.190 2.820 ; + RECT 1810.630 2.760 1810.950 2.820 ; + LAYER via ; + RECT 1504.300 243.820 1504.560 244.080 ; + RECT 1510.740 243.820 1511.000 244.080 ; + RECT 1510.740 58.860 1511.000 59.120 ; + RECT 1807.900 58.860 1808.160 59.120 ; + RECT 1807.900 2.760 1808.160 3.020 ; + RECT 1810.660 2.760 1810.920 3.020 ; + LAYER met2 ; + RECT 1504.250 260.000 1504.530 264.000 ; + RECT 1504.360 244.110 1504.500 260.000 ; + RECT 1504.300 243.790 1504.560 244.110 ; + RECT 1510.740 243.790 1511.000 244.110 ; + RECT 1510.800 59.150 1510.940 243.790 ; + RECT 1510.740 58.830 1511.000 59.150 ; + RECT 1807.900 58.830 1808.160 59.150 ; + RECT 1807.960 3.050 1808.100 58.830 ; + RECT 1807.900 2.730 1808.160 3.050 ; + RECT 1810.660 2.730 1810.920 3.050 ; + RECT 1810.720 2.400 1810.860 2.730 ; + RECT 1810.510 -4.800 1811.070 2.400 ; +======= LAYER met2 ; RECT 1810.510 -4.800 1811.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[66] PIN la_data_in[67] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1524.510 120.600 1524.830 120.660 ; + RECT 1829.030 120.600 1829.350 120.660 ; + RECT 1524.510 120.460 1829.350 120.600 ; + RECT 1524.510 120.400 1524.830 120.460 ; + RECT 1829.030 120.400 1829.350 120.460 ; + LAYER via ; + RECT 1524.540 120.400 1524.800 120.660 ; + RECT 1829.060 120.400 1829.320 120.660 ; + LAYER met2 ; + RECT 1522.190 260.170 1522.470 264.000 ; + RECT 1522.190 260.030 1524.740 260.170 ; + RECT 1522.190 260.000 1522.470 260.030 ; + RECT 1524.600 120.690 1524.740 260.030 ; + RECT 1524.540 120.370 1524.800 120.690 ; + RECT 1829.060 120.370 1829.320 120.690 ; + RECT 1829.120 7.210 1829.260 120.370 ; + RECT 1828.660 7.070 1829.260 7.210 ; + RECT 1828.660 2.400 1828.800 7.070 ; + RECT 1828.450 -4.800 1829.010 2.400 ; +======= LAYER met2 ; RECT 1828.450 -4.800 1829.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[67] PIN la_data_in[68] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1540.150 244.020 1540.470 244.080 ; + RECT 1545.210 244.020 1545.530 244.080 ; + RECT 1540.150 243.880 1545.530 244.020 ; + RECT 1540.150 243.820 1540.470 243.880 ; + RECT 1545.210 243.820 1545.530 243.880 ; + RECT 1545.210 72.320 1545.530 72.380 ; + RECT 1842.370 72.320 1842.690 72.380 ; + RECT 1545.210 72.180 1842.690 72.320 ; + RECT 1545.210 72.120 1545.530 72.180 ; + RECT 1842.370 72.120 1842.690 72.180 ; + LAYER via ; + RECT 1540.180 243.820 1540.440 244.080 ; + RECT 1545.240 243.820 1545.500 244.080 ; + RECT 1545.240 72.120 1545.500 72.380 ; + RECT 1842.400 72.120 1842.660 72.380 ; + LAYER met2 ; + RECT 1540.130 260.000 1540.410 264.000 ; + RECT 1540.240 244.110 1540.380 260.000 ; + RECT 1540.180 243.790 1540.440 244.110 ; + RECT 1545.240 243.790 1545.500 244.110 ; + RECT 1545.300 72.410 1545.440 243.790 ; + RECT 1545.240 72.090 1545.500 72.410 ; + RECT 1842.400 72.090 1842.660 72.410 ; + RECT 1842.460 16.730 1842.600 72.090 ; + RECT 1842.460 16.590 1846.280 16.730 ; + RECT 1846.140 2.400 1846.280 16.590 ; + RECT 1845.930 -4.800 1846.490 2.400 ; +======= LAYER met2 ; RECT 1845.930 -4.800 1846.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[68] PIN la_data_in[69] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1558.090 245.720 1558.410 245.780 ; + RECT 1728.290 245.720 1728.610 245.780 ; + RECT 1558.090 245.580 1728.610 245.720 ; + RECT 1558.090 245.520 1558.410 245.580 ; + RECT 1728.290 245.520 1728.610 245.580 ; + RECT 1728.290 31.180 1728.610 31.240 ; + RECT 1863.990 31.180 1864.310 31.240 ; + RECT 1728.290 31.040 1864.310 31.180 ; + RECT 1728.290 30.980 1728.610 31.040 ; + RECT 1863.990 30.980 1864.310 31.040 ; + LAYER via ; + RECT 1558.120 245.520 1558.380 245.780 ; + RECT 1728.320 245.520 1728.580 245.780 ; + RECT 1728.320 30.980 1728.580 31.240 ; + RECT 1864.020 30.980 1864.280 31.240 ; + LAYER met2 ; + RECT 1558.070 260.000 1558.350 264.000 ; + RECT 1558.180 245.810 1558.320 260.000 ; + RECT 1558.120 245.490 1558.380 245.810 ; + RECT 1728.320 245.490 1728.580 245.810 ; + RECT 1728.380 31.270 1728.520 245.490 ; + RECT 1728.320 30.950 1728.580 31.270 ; + RECT 1864.020 30.950 1864.280 31.270 ; + RECT 1864.080 2.400 1864.220 30.950 ; + RECT 1863.870 -4.800 1864.430 2.400 ; +======= LAYER met2 ; RECT 1863.870 -4.800 1864.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[69] PIN la_data_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 434.310 120.600 434.630 120.660 ; + RECT 738.370 120.600 738.690 120.660 ; + RECT 434.310 120.460 738.690 120.600 ; + RECT 434.310 120.400 434.630 120.460 ; + RECT 738.370 120.400 738.690 120.460 ; + LAYER via ; + RECT 434.340 120.400 434.600 120.660 ; + RECT 738.400 120.400 738.660 120.660 ; + LAYER met2 ; + RECT 431.990 260.170 432.270 264.000 ; + RECT 431.990 260.030 434.540 260.170 ; + RECT 431.990 260.000 432.270 260.030 ; + RECT 434.400 120.690 434.540 260.030 ; + RECT 434.340 120.370 434.600 120.690 ; + RECT 738.400 120.370 738.660 120.690 ; + RECT 738.460 16.730 738.600 120.370 ; + RECT 738.460 16.590 740.440 16.730 ; + RECT 740.300 2.400 740.440 16.590 ; + RECT 740.090 -4.800 740.650 2.400 ; +======= LAYER met2 ; RECT 740.090 -4.800 740.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[6] PIN la_data_in[70] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1576.030 243.680 1576.350 243.740 ; + RECT 1579.710 243.680 1580.030 243.740 ; + RECT 1576.030 243.540 1580.030 243.680 ; + RECT 1576.030 243.480 1576.350 243.540 ; + RECT 1579.710 243.480 1580.030 243.540 ; + RECT 1579.710 65.520 1580.030 65.580 ; + RECT 1876.870 65.520 1877.190 65.580 ; + RECT 1579.710 65.380 1877.190 65.520 ; + RECT 1579.710 65.320 1580.030 65.380 ; + RECT 1876.870 65.320 1877.190 65.380 ; + RECT 1876.870 62.120 1877.190 62.180 ; + RECT 1881.930 62.120 1882.250 62.180 ; + RECT 1876.870 61.980 1882.250 62.120 ; + RECT 1876.870 61.920 1877.190 61.980 ; + RECT 1881.930 61.920 1882.250 61.980 ; + LAYER via ; + RECT 1576.060 243.480 1576.320 243.740 ; + RECT 1579.740 243.480 1580.000 243.740 ; + RECT 1579.740 65.320 1580.000 65.580 ; + RECT 1876.900 65.320 1877.160 65.580 ; + RECT 1876.900 61.920 1877.160 62.180 ; + RECT 1881.960 61.920 1882.220 62.180 ; + LAYER met2 ; + RECT 1576.010 260.000 1576.290 264.000 ; + RECT 1576.120 243.770 1576.260 260.000 ; + RECT 1576.060 243.450 1576.320 243.770 ; + RECT 1579.740 243.450 1580.000 243.770 ; + RECT 1579.800 65.610 1579.940 243.450 ; + RECT 1579.740 65.290 1580.000 65.610 ; + RECT 1876.900 65.290 1877.160 65.610 ; + RECT 1876.960 62.210 1877.100 65.290 ; + RECT 1876.900 61.890 1877.160 62.210 ; + RECT 1881.960 61.890 1882.220 62.210 ; + RECT 1882.020 2.400 1882.160 61.890 ; + RECT 1881.810 -4.800 1882.370 2.400 ; +======= LAYER met2 ; RECT 1881.810 -4.800 1882.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[70] PIN la_data_in[71] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1593.050 79.800 1593.370 79.860 ; + RECT 1897.570 79.800 1897.890 79.860 ; + RECT 1593.050 79.660 1897.890 79.800 ; + RECT 1593.050 79.600 1593.370 79.660 ; + RECT 1897.570 79.600 1897.890 79.660 ; + LAYER via ; + RECT 1593.080 79.600 1593.340 79.860 ; + RECT 1897.600 79.600 1897.860 79.860 ; + LAYER met2 ; + RECT 1593.490 260.170 1593.770 264.000 ; + RECT 1593.140 260.030 1593.770 260.170 ; + RECT 1593.140 79.890 1593.280 260.030 ; + RECT 1593.490 260.000 1593.770 260.030 ; + RECT 1593.080 79.570 1593.340 79.890 ; + RECT 1897.600 79.570 1897.860 79.890 ; + RECT 1897.660 16.730 1897.800 79.570 ; + RECT 1897.660 16.590 1900.100 16.730 ; + RECT 1899.960 2.400 1900.100 16.590 ; + RECT 1899.750 -4.800 1900.310 2.400 ; +======= LAYER met2 ; RECT 1899.750 -4.800 1900.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[71] PIN la_data_in[72] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1614.210 86.260 1614.530 86.320 ; + RECT 1911.830 86.260 1912.150 86.320 ; + RECT 1614.210 86.120 1912.150 86.260 ; + RECT 1614.210 86.060 1614.530 86.120 ; + RECT 1911.830 86.060 1912.150 86.120 ; + RECT 1911.830 17.920 1912.150 17.980 ; + RECT 1917.810 17.920 1918.130 17.980 ; + RECT 1911.830 17.780 1918.130 17.920 ; + RECT 1911.830 17.720 1912.150 17.780 ; + RECT 1917.810 17.720 1918.130 17.780 ; + LAYER via ; + RECT 1614.240 86.060 1614.500 86.320 ; + RECT 1911.860 86.060 1912.120 86.320 ; + RECT 1911.860 17.720 1912.120 17.980 ; + RECT 1917.840 17.720 1918.100 17.980 ; + LAYER met2 ; + RECT 1611.430 260.170 1611.710 264.000 ; + RECT 1611.430 260.030 1614.440 260.170 ; + RECT 1611.430 260.000 1611.710 260.030 ; + RECT 1614.300 86.350 1614.440 260.030 ; + RECT 1614.240 86.030 1614.500 86.350 ; + RECT 1911.860 86.030 1912.120 86.350 ; + RECT 1911.920 18.010 1912.060 86.030 ; + RECT 1911.860 17.690 1912.120 18.010 ; + RECT 1917.840 17.690 1918.100 18.010 ; + RECT 1917.900 2.400 1918.040 17.690 ; + RECT 1917.690 -4.800 1918.250 2.400 ; +======= LAYER met2 ; RECT 1917.690 -4.800 1918.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[72] PIN la_data_in[73] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1629.390 244.020 1629.710 244.080 ; + RECT 1634.910 244.020 1635.230 244.080 ; + RECT 1629.390 243.880 1635.230 244.020 ; + RECT 1629.390 243.820 1629.710 243.880 ; + RECT 1634.910 243.820 1635.230 243.880 ; + RECT 1634.910 99.860 1635.230 99.920 ; + RECT 1932.070 99.860 1932.390 99.920 ; + RECT 1634.910 99.720 1932.390 99.860 ; + RECT 1634.910 99.660 1635.230 99.720 ; + RECT 1932.070 99.660 1932.390 99.720 ; + RECT 1932.070 2.960 1932.390 3.020 ; + RECT 1935.290 2.960 1935.610 3.020 ; + RECT 1932.070 2.820 1935.610 2.960 ; + RECT 1932.070 2.760 1932.390 2.820 ; + RECT 1935.290 2.760 1935.610 2.820 ; + LAYER via ; + RECT 1629.420 243.820 1629.680 244.080 ; + RECT 1634.940 243.820 1635.200 244.080 ; + RECT 1634.940 99.660 1635.200 99.920 ; + RECT 1932.100 99.660 1932.360 99.920 ; + RECT 1932.100 2.760 1932.360 3.020 ; + RECT 1935.320 2.760 1935.580 3.020 ; + LAYER met2 ; + RECT 1629.370 260.000 1629.650 264.000 ; + RECT 1629.480 244.110 1629.620 260.000 ; + RECT 1629.420 243.790 1629.680 244.110 ; + RECT 1634.940 243.790 1635.200 244.110 ; + RECT 1635.000 99.950 1635.140 243.790 ; + RECT 1634.940 99.630 1635.200 99.950 ; + RECT 1932.100 99.630 1932.360 99.950 ; + RECT 1932.160 3.050 1932.300 99.630 ; + RECT 1932.100 2.730 1932.360 3.050 ; + RECT 1935.320 2.730 1935.580 3.050 ; + RECT 1935.380 2.400 1935.520 2.730 ; + RECT 1935.170 -4.800 1935.730 2.400 ; +======= LAYER met2 ; RECT 1935.170 -4.800 1935.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[73] PIN la_data_in[74] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1647.330 244.020 1647.650 244.080 ; + RECT 1652.390 244.020 1652.710 244.080 ; + RECT 1647.330 243.880 1652.710 244.020 ; + RECT 1647.330 243.820 1647.650 243.880 ; + RECT 1652.390 243.820 1652.710 243.880 ; + RECT 1652.390 93.060 1652.710 93.120 ; + RECT 1953.230 93.060 1953.550 93.120 ; + RECT 1652.390 92.920 1953.550 93.060 ; + RECT 1652.390 92.860 1652.710 92.920 ; + RECT 1953.230 92.860 1953.550 92.920 ; + LAYER via ; + RECT 1647.360 243.820 1647.620 244.080 ; + RECT 1652.420 243.820 1652.680 244.080 ; + RECT 1652.420 92.860 1652.680 93.120 ; + RECT 1953.260 92.860 1953.520 93.120 ; + LAYER met2 ; + RECT 1647.310 260.000 1647.590 264.000 ; + RECT 1647.420 244.110 1647.560 260.000 ; + RECT 1647.360 243.790 1647.620 244.110 ; + RECT 1652.420 243.790 1652.680 244.110 ; + RECT 1652.480 93.150 1652.620 243.790 ; + RECT 1652.420 92.830 1652.680 93.150 ; + RECT 1953.260 92.830 1953.520 93.150 ; + RECT 1953.320 2.400 1953.460 92.830 ; + RECT 1953.110 -4.800 1953.670 2.400 ; +======= LAYER met2 ; RECT 1953.110 -4.800 1953.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[74] PIN la_data_in[75] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1665.270 244.020 1665.590 244.080 ; + RECT 1669.410 244.020 1669.730 244.080 ; + RECT 1665.270 243.880 1669.730 244.020 ; + RECT 1665.270 243.820 1665.590 243.880 ; + RECT 1669.410 243.820 1669.730 243.880 ; + RECT 1669.410 107.000 1669.730 107.060 ; + RECT 1966.570 107.000 1966.890 107.060 ; + RECT 1669.410 106.860 1966.890 107.000 ; + RECT 1669.410 106.800 1669.730 106.860 ; + RECT 1966.570 106.800 1966.890 106.860 ; + RECT 1966.570 62.120 1966.890 62.180 ; + RECT 1971.170 62.120 1971.490 62.180 ; + RECT 1966.570 61.980 1971.490 62.120 ; + RECT 1966.570 61.920 1966.890 61.980 ; + RECT 1971.170 61.920 1971.490 61.980 ; + LAYER via ; + RECT 1665.300 243.820 1665.560 244.080 ; + RECT 1669.440 243.820 1669.700 244.080 ; + RECT 1669.440 106.800 1669.700 107.060 ; + RECT 1966.600 106.800 1966.860 107.060 ; + RECT 1966.600 61.920 1966.860 62.180 ; + RECT 1971.200 61.920 1971.460 62.180 ; + LAYER met2 ; + RECT 1665.250 260.000 1665.530 264.000 ; + RECT 1665.360 244.110 1665.500 260.000 ; + RECT 1665.300 243.790 1665.560 244.110 ; + RECT 1669.440 243.790 1669.700 244.110 ; + RECT 1669.500 107.090 1669.640 243.790 ; + RECT 1669.440 106.770 1669.700 107.090 ; + RECT 1966.600 106.770 1966.860 107.090 ; + RECT 1966.660 62.210 1966.800 106.770 ; + RECT 1966.600 61.890 1966.860 62.210 ; + RECT 1971.200 61.890 1971.460 62.210 ; + RECT 1971.260 2.400 1971.400 61.890 ; + RECT 1971.050 -4.800 1971.610 2.400 ; +======= LAYER met2 ; RECT 1971.050 -4.800 1971.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[75] PIN la_data_in[76] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1987.345 48.365 1987.515 96.475 ; + LAYER mcon ; + RECT 1987.345 96.305 1987.515 96.475 ; + LAYER met1 ; + RECT 1682.750 127.740 1683.070 127.800 ; + RECT 1987.730 127.740 1988.050 127.800 ; + RECT 1682.750 127.600 1988.050 127.740 ; + RECT 1682.750 127.540 1683.070 127.600 ; + RECT 1987.730 127.540 1988.050 127.600 ; + RECT 1987.270 96.460 1987.590 96.520 ; + RECT 1987.075 96.320 1987.590 96.460 ; + RECT 1987.270 96.260 1987.590 96.320 ; + RECT 1987.285 48.520 1987.575 48.565 ; + RECT 1989.110 48.520 1989.430 48.580 ; + RECT 1987.285 48.380 1989.430 48.520 ; + RECT 1987.285 48.335 1987.575 48.380 ; + RECT 1989.110 48.320 1989.430 48.380 ; + LAYER via ; + RECT 1682.780 127.540 1683.040 127.800 ; + RECT 1987.760 127.540 1988.020 127.800 ; + RECT 1987.300 96.260 1987.560 96.520 ; + RECT 1989.140 48.320 1989.400 48.580 ; + LAYER met2 ; + RECT 1683.190 260.170 1683.470 264.000 ; + RECT 1682.840 260.030 1683.470 260.170 ; + RECT 1682.840 127.830 1682.980 260.030 ; + RECT 1683.190 260.000 1683.470 260.030 ; + RECT 1682.780 127.510 1683.040 127.830 ; + RECT 1987.760 127.510 1988.020 127.830 ; + RECT 1987.820 96.970 1987.960 127.510 ; + RECT 1987.360 96.830 1987.960 96.970 ; + RECT 1987.360 96.550 1987.500 96.830 ; + RECT 1987.300 96.230 1987.560 96.550 ; + RECT 1989.140 48.290 1989.400 48.610 ; + RECT 1989.200 2.400 1989.340 48.290 ; + RECT 1988.990 -4.800 1989.550 2.400 ; +======= LAYER met2 ; RECT 1988.990 -4.800 1989.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[76] PIN la_data_in[77] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1703.910 38.320 1704.230 38.380 ; + RECT 2006.590 38.320 2006.910 38.380 ; + RECT 1703.910 38.180 2006.910 38.320 ; + RECT 1703.910 38.120 1704.230 38.180 ; + RECT 2006.590 38.120 2006.910 38.180 ; + LAYER via ; + RECT 1703.940 38.120 1704.200 38.380 ; + RECT 2006.620 38.120 2006.880 38.380 ; + LAYER met2 ; + RECT 1701.130 260.170 1701.410 264.000 ; + RECT 1701.130 260.030 1704.140 260.170 ; + RECT 1701.130 260.000 1701.410 260.030 ; + RECT 1704.000 38.410 1704.140 260.030 ; + RECT 1703.940 38.090 1704.200 38.410 ; + RECT 2006.620 38.090 2006.880 38.410 ; + RECT 2006.680 2.400 2006.820 38.090 ; + RECT 2006.470 -4.800 2007.030 2.400 ; +======= LAYER met2 ; RECT 2006.470 -4.800 2007.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[77] PIN la_data_in[78] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1718.630 244.020 1718.950 244.080 ; + RECT 1724.150 244.020 1724.470 244.080 ; + RECT 1718.630 243.880 1724.470 244.020 ; + RECT 1718.630 243.820 1718.950 243.880 ; + RECT 1724.150 243.820 1724.470 243.880 ; + RECT 1724.150 134.540 1724.470 134.600 ; + RECT 2021.770 134.540 2022.090 134.600 ; + RECT 1724.150 134.400 2022.090 134.540 ; + RECT 1724.150 134.340 1724.470 134.400 ; + RECT 2021.770 134.340 2022.090 134.400 ; + LAYER via ; + RECT 1718.660 243.820 1718.920 244.080 ; + RECT 1724.180 243.820 1724.440 244.080 ; + RECT 1724.180 134.340 1724.440 134.600 ; + RECT 2021.800 134.340 2022.060 134.600 ; + LAYER met2 ; + RECT 1718.610 260.000 1718.890 264.000 ; + RECT 1718.720 244.110 1718.860 260.000 ; + RECT 1718.660 243.790 1718.920 244.110 ; + RECT 1724.180 243.790 1724.440 244.110 ; + RECT 1724.240 134.630 1724.380 243.790 ; + RECT 1724.180 134.310 1724.440 134.630 ; + RECT 2021.800 134.310 2022.060 134.630 ; + RECT 2021.860 16.730 2022.000 134.310 ; + RECT 2021.860 16.590 2024.760 16.730 ; + RECT 2024.620 2.400 2024.760 16.590 ; + RECT 2024.410 -4.800 2024.970 2.400 ; +======= LAYER met2 ; RECT 2024.410 -4.800 2024.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[78] PIN la_data_in[79] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1736.570 237.900 1736.890 237.960 ; + RECT 2042.470 237.900 2042.790 237.960 ; + RECT 1736.570 237.760 2042.790 237.900 ; + RECT 1736.570 237.700 1736.890 237.760 ; + RECT 2042.470 237.700 2042.790 237.760 ; + LAYER via ; + RECT 1736.600 237.700 1736.860 237.960 ; + RECT 2042.500 237.700 2042.760 237.960 ; + LAYER met2 ; + RECT 1736.550 260.000 1736.830 264.000 ; + RECT 1736.660 237.990 1736.800 260.000 ; + RECT 1736.600 237.670 1736.860 237.990 ; + RECT 2042.500 237.670 2042.760 237.990 ; + RECT 2042.560 2.400 2042.700 237.670 ; + RECT 2042.350 -4.800 2042.910 2.400 ; +======= LAYER met2 ; RECT 2042.350 -4.800 2042.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[79] PIN la_data_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 449.490 244.020 449.810 244.080 ; + RECT 455.010 244.020 455.330 244.080 ; + RECT 449.490 243.880 455.330 244.020 ; + RECT 449.490 243.820 449.810 243.880 ; + RECT 455.010 243.820 455.330 243.880 ; + RECT 455.010 127.740 455.330 127.800 ; + RECT 752.630 127.740 752.950 127.800 ; + RECT 455.010 127.600 752.950 127.740 ; + RECT 455.010 127.540 455.330 127.600 ; + RECT 752.630 127.540 752.950 127.600 ; + RECT 752.630 18.940 752.950 19.000 ; + RECT 757.690 18.940 758.010 19.000 ; + RECT 752.630 18.800 758.010 18.940 ; + RECT 752.630 18.740 752.950 18.800 ; + RECT 757.690 18.740 758.010 18.800 ; + LAYER via ; + RECT 449.520 243.820 449.780 244.080 ; + RECT 455.040 243.820 455.300 244.080 ; + RECT 455.040 127.540 455.300 127.800 ; + RECT 752.660 127.540 752.920 127.800 ; + RECT 752.660 18.740 752.920 19.000 ; + RECT 757.720 18.740 757.980 19.000 ; + LAYER met2 ; + RECT 449.470 260.000 449.750 264.000 ; + RECT 449.580 244.110 449.720 260.000 ; + RECT 449.520 243.790 449.780 244.110 ; + RECT 455.040 243.790 455.300 244.110 ; + RECT 455.100 127.830 455.240 243.790 ; + RECT 455.040 127.510 455.300 127.830 ; + RECT 752.660 127.510 752.920 127.830 ; + RECT 752.720 19.030 752.860 127.510 ; + RECT 752.660 18.710 752.920 19.030 ; + RECT 757.720 18.710 757.980 19.030 ; + RECT 757.780 2.400 757.920 18.710 ; + RECT 757.570 -4.800 758.130 2.400 ; +======= LAYER met2 ; RECT 757.570 -4.800 758.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[7] PIN la_data_in[80] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1754.510 244.020 1754.830 244.080 ; + RECT 1759.110 244.020 1759.430 244.080 ; + RECT 1754.510 243.880 1759.430 244.020 ; + RECT 1754.510 243.820 1754.830 243.880 ; + RECT 1759.110 243.820 1759.430 243.880 ; + RECT 1759.110 44.780 1759.430 44.840 ; + RECT 2060.410 44.780 2060.730 44.840 ; + RECT 1759.110 44.640 2060.730 44.780 ; + RECT 1759.110 44.580 1759.430 44.640 ; + RECT 2060.410 44.580 2060.730 44.640 ; + LAYER via ; + RECT 1754.540 243.820 1754.800 244.080 ; + RECT 1759.140 243.820 1759.400 244.080 ; + RECT 1759.140 44.580 1759.400 44.840 ; + RECT 2060.440 44.580 2060.700 44.840 ; + LAYER met2 ; + RECT 1754.490 260.000 1754.770 264.000 ; + RECT 1754.600 244.110 1754.740 260.000 ; + RECT 1754.540 243.790 1754.800 244.110 ; + RECT 1759.140 243.790 1759.400 244.110 ; + RECT 1759.200 44.870 1759.340 243.790 ; + RECT 1759.140 44.550 1759.400 44.870 ; + RECT 2060.440 44.550 2060.700 44.870 ; + RECT 2060.500 2.400 2060.640 44.550 ; + RECT 2060.290 -4.800 2060.850 2.400 ; +======= LAYER met2 ; RECT 2060.290 -4.800 2060.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[80] PIN la_data_in[81] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1772.450 245.040 1772.770 245.100 ; + RECT 1838.690 245.040 1839.010 245.100 ; + RECT 1772.450 244.900 1839.010 245.040 ; + RECT 1772.450 244.840 1772.770 244.900 ; + RECT 1838.690 244.840 1839.010 244.900 ; + RECT 1838.690 51.580 1839.010 51.640 ; + RECT 2076.970 51.580 2077.290 51.640 ; + RECT 1838.690 51.440 2077.290 51.580 ; + RECT 1838.690 51.380 1839.010 51.440 ; + RECT 2076.970 51.380 2077.290 51.440 ; + LAYER via ; + RECT 1772.480 244.840 1772.740 245.100 ; + RECT 1838.720 244.840 1838.980 245.100 ; + RECT 1838.720 51.380 1838.980 51.640 ; + RECT 2077.000 51.380 2077.260 51.640 ; + LAYER met2 ; + RECT 1772.430 260.000 1772.710 264.000 ; + RECT 1772.540 245.130 1772.680 260.000 ; + RECT 1772.480 244.810 1772.740 245.130 ; + RECT 1838.720 244.810 1838.980 245.130 ; + RECT 1838.780 51.670 1838.920 244.810 ; + RECT 1838.720 51.350 1838.980 51.670 ; + RECT 2077.000 51.350 2077.260 51.670 ; + RECT 2077.060 4.490 2077.200 51.350 ; + RECT 2077.060 4.350 2078.580 4.490 ; + RECT 2078.440 2.400 2078.580 4.350 ; + RECT 2078.230 -4.800 2078.790 2.400 ; +======= LAYER met2 ; RECT 2078.230 -4.800 2078.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[81] PIN la_data_in[82] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1793.610 25.060 1793.930 25.120 ; + RECT 2095.830 25.060 2096.150 25.120 ; + RECT 1793.610 24.920 2096.150 25.060 ; + RECT 1793.610 24.860 1793.930 24.920 ; + RECT 2095.830 24.860 2096.150 24.920 ; + LAYER via ; + RECT 1793.640 24.860 1793.900 25.120 ; + RECT 2095.860 24.860 2096.120 25.120 ; + LAYER met2 ; + RECT 1790.370 260.170 1790.650 264.000 ; + RECT 1790.370 260.030 1793.840 260.170 ; + RECT 1790.370 260.000 1790.650 260.030 ; + RECT 1793.700 25.150 1793.840 260.030 ; + RECT 1793.640 24.830 1793.900 25.150 ; + RECT 2095.860 24.830 2096.120 25.150 ; + RECT 2095.920 2.400 2096.060 24.830 ; + RECT 2095.710 -4.800 2096.270 2.400 ; +======= LAYER met2 ; RECT 2095.710 -4.800 2096.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[82] PIN la_data_in[83] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1808.330 244.020 1808.650 244.080 ; + RECT 1814.310 244.020 1814.630 244.080 ; + RECT 1808.330 243.880 1814.630 244.020 ; + RECT 1808.330 243.820 1808.650 243.880 ; + RECT 1814.310 243.820 1814.630 243.880 ; + RECT 1814.310 26.420 1814.630 26.480 ; + RECT 2113.770 26.420 2114.090 26.480 ; + RECT 1814.310 26.280 2114.090 26.420 ; + RECT 1814.310 26.220 1814.630 26.280 ; + RECT 2113.770 26.220 2114.090 26.280 ; + LAYER via ; + RECT 1808.360 243.820 1808.620 244.080 ; + RECT 1814.340 243.820 1814.600 244.080 ; + RECT 1814.340 26.220 1814.600 26.480 ; + RECT 2113.800 26.220 2114.060 26.480 ; + LAYER met2 ; + RECT 1808.310 260.000 1808.590 264.000 ; + RECT 1808.420 244.110 1808.560 260.000 ; + RECT 1808.360 243.790 1808.620 244.110 ; + RECT 1814.340 243.790 1814.600 244.110 ; + RECT 1814.400 26.510 1814.540 243.790 ; + RECT 1814.340 26.190 1814.600 26.510 ; + RECT 2113.800 26.190 2114.060 26.510 ; + RECT 2113.860 2.400 2114.000 26.190 ; + RECT 2113.650 -4.800 2114.210 2.400 ; +======= LAYER met2 ; RECT 2113.650 -4.800 2114.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[83] PIN la_data_in[84] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1826.270 231.100 1826.590 231.160 ; + RECT 2125.270 231.100 2125.590 231.160 ; + RECT 1826.270 230.960 2125.590 231.100 ; + RECT 1826.270 230.900 1826.590 230.960 ; + RECT 2125.270 230.900 2125.590 230.960 ; + RECT 2125.270 17.580 2125.590 17.640 ; + RECT 2131.710 17.580 2132.030 17.640 ; + RECT 2125.270 17.440 2132.030 17.580 ; + RECT 2125.270 17.380 2125.590 17.440 ; + RECT 2131.710 17.380 2132.030 17.440 ; + LAYER via ; + RECT 1826.300 230.900 1826.560 231.160 ; + RECT 2125.300 230.900 2125.560 231.160 ; + RECT 2125.300 17.380 2125.560 17.640 ; + RECT 2131.740 17.380 2132.000 17.640 ; + LAYER met2 ; + RECT 1826.250 260.000 1826.530 264.000 ; + RECT 1826.360 231.190 1826.500 260.000 ; + RECT 1826.300 230.870 1826.560 231.190 ; + RECT 2125.300 230.870 2125.560 231.190 ; + RECT 2125.360 17.670 2125.500 230.870 ; + RECT 2125.300 17.350 2125.560 17.670 ; + RECT 2131.740 17.350 2132.000 17.670 ; + RECT 2131.800 2.400 2131.940 17.350 ; + RECT 2131.590 -4.800 2132.150 2.400 ; +======= LAYER met2 ; RECT 2131.590 -4.800 2132.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[84] PIN la_data_in[85] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1844.210 241.640 1844.530 241.700 ; + RECT 1848.810 241.640 1849.130 241.700 ; + RECT 1844.210 241.500 1849.130 241.640 ; + RECT 1844.210 241.440 1844.530 241.500 ; + RECT 1848.810 241.440 1849.130 241.500 ; + RECT 1848.810 26.080 1849.130 26.140 ; + RECT 2149.650 26.080 2149.970 26.140 ; + RECT 1848.810 25.940 2149.970 26.080 ; + RECT 1848.810 25.880 1849.130 25.940 ; + RECT 2149.650 25.880 2149.970 25.940 ; + LAYER via ; + RECT 1844.240 241.440 1844.500 241.700 ; + RECT 1848.840 241.440 1849.100 241.700 ; + RECT 1848.840 25.880 1849.100 26.140 ; + RECT 2149.680 25.880 2149.940 26.140 ; + LAYER met2 ; + RECT 1844.190 260.000 1844.470 264.000 ; + RECT 1844.300 241.730 1844.440 260.000 ; + RECT 1844.240 241.410 1844.500 241.730 ; + RECT 1848.840 241.410 1849.100 241.730 ; + RECT 1848.900 26.170 1849.040 241.410 ; + RECT 1848.840 25.850 1849.100 26.170 ; + RECT 2149.680 25.850 2149.940 26.170 ; + RECT 2149.740 2.400 2149.880 25.850 ; + RECT 2149.530 -4.800 2150.090 2.400 ; +======= LAYER met2 ; RECT 2149.530 -4.800 2150.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[85] PIN la_data_in[86] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1883.845 23.885 1884.015 24.735 ; + RECT 1931.685 23.545 1931.855 24.735 ; + RECT 1932.145 23.205 1933.235 23.375 ; + RECT 2077.045 22.525 2077.215 23.375 ; + RECT 2124.885 22.525 2125.055 23.715 ; + RECT 2125.345 11.645 2125.515 23.375 ; + LAYER mcon ; + RECT 1883.845 24.565 1884.015 24.735 ; + RECT 1931.685 24.565 1931.855 24.735 ; + RECT 2124.885 23.545 2125.055 23.715 ; + RECT 1933.065 23.205 1933.235 23.375 ; + RECT 2077.045 23.205 2077.215 23.375 ; + RECT 2125.345 23.205 2125.515 23.375 ; + LAYER met1 ; + RECT 1883.785 24.720 1884.075 24.765 ; + RECT 1931.625 24.720 1931.915 24.765 ; + RECT 1883.785 24.580 1931.915 24.720 ; + RECT 1883.785 24.535 1884.075 24.580 ; + RECT 1931.625 24.535 1931.915 24.580 ; + RECT 1862.610 24.040 1862.930 24.100 ; + RECT 1883.785 24.040 1884.075 24.085 ; + RECT 1862.610 23.900 1884.075 24.040 ; + RECT 1862.610 23.840 1862.930 23.900 ; + RECT 1883.785 23.855 1884.075 23.900 ; + RECT 1931.625 23.700 1931.915 23.745 ; + RECT 2124.825 23.700 2125.115 23.745 ; + RECT 1931.625 23.560 1932.300 23.700 ; + RECT 1931.625 23.515 1931.915 23.560 ; + RECT 1932.160 23.405 1932.300 23.560 ; + RECT 2014.500 23.560 2041.780 23.700 ; + RECT 1932.085 23.175 1932.375 23.405 ; + RECT 1933.005 23.360 1933.295 23.405 ; + RECT 2014.500 23.360 2014.640 23.560 ; + RECT 1933.005 23.220 2014.640 23.360 ; + RECT 2041.640 23.360 2041.780 23.560 ; + RECT 2124.825 23.560 2125.500 23.700 ; + RECT 2124.825 23.515 2125.115 23.560 ; + RECT 2125.360 23.405 2125.500 23.560 ; + RECT 2076.985 23.360 2077.275 23.405 ; + RECT 2041.640 23.220 2077.275 23.360 ; + RECT 1933.005 23.175 1933.295 23.220 ; + RECT 2076.985 23.175 2077.275 23.220 ; + RECT 2125.285 23.175 2125.575 23.405 ; + RECT 2076.985 22.680 2077.275 22.725 ; + RECT 2124.825 22.680 2125.115 22.725 ; + RECT 2076.985 22.540 2125.115 22.680 ; + RECT 2076.985 22.495 2077.275 22.540 ; + RECT 2124.825 22.495 2125.115 22.540 ; + RECT 2125.285 11.800 2125.575 11.845 ; + RECT 2167.590 11.800 2167.910 11.860 ; + RECT 2125.285 11.660 2167.910 11.800 ; + RECT 2125.285 11.615 2125.575 11.660 ; + RECT 2167.590 11.600 2167.910 11.660 ; + LAYER via ; + RECT 1862.640 23.840 1862.900 24.100 ; + RECT 2167.620 11.600 2167.880 11.860 ; + LAYER met2 ; + RECT 1861.670 260.170 1861.950 264.000 ; + RECT 1861.670 260.030 1862.840 260.170 ; + RECT 1861.670 260.000 1861.950 260.030 ; + RECT 1862.700 24.130 1862.840 260.030 ; + RECT 1862.640 23.810 1862.900 24.130 ; + RECT 2167.620 11.570 2167.880 11.890 ; + RECT 2167.680 2.400 2167.820 11.570 ; + RECT 2167.470 -4.800 2168.030 2.400 ; +======= LAYER met2 ; RECT 2167.470 -4.800 2168.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[86] PIN la_data_in[87] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1879.630 243.680 1879.950 243.740 ; + RECT 1883.310 243.680 1883.630 243.740 ; + RECT 1879.630 243.540 1883.630 243.680 ; + RECT 1879.630 243.480 1879.950 243.540 ; + RECT 1883.310 243.480 1883.630 243.540 ; + RECT 1883.310 58.720 1883.630 58.780 ; + RECT 2185.070 58.720 2185.390 58.780 ; + RECT 1883.310 58.580 2185.390 58.720 ; + RECT 1883.310 58.520 1883.630 58.580 ; + RECT 2185.070 58.520 2185.390 58.580 ; + LAYER via ; + RECT 1879.660 243.480 1879.920 243.740 ; + RECT 1883.340 243.480 1883.600 243.740 ; + RECT 1883.340 58.520 1883.600 58.780 ; + RECT 2185.100 58.520 2185.360 58.780 ; + LAYER met2 ; + RECT 1879.610 260.000 1879.890 264.000 ; + RECT 1879.720 243.770 1879.860 260.000 ; + RECT 1879.660 243.450 1879.920 243.770 ; + RECT 1883.340 243.450 1883.600 243.770 ; + RECT 1883.400 58.810 1883.540 243.450 ; + RECT 1883.340 58.490 1883.600 58.810 ; + RECT 2185.100 58.490 2185.360 58.810 ; + RECT 2185.160 2.400 2185.300 58.490 ; + RECT 2184.950 -4.800 2185.510 2.400 ; +======= LAYER met2 ; RECT 2184.950 -4.800 2185.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[87] PIN la_data_in[88] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1897.570 244.020 1897.890 244.080 ; + RECT 1904.010 244.020 1904.330 244.080 ; + RECT 1897.570 243.880 1904.330 244.020 ; + RECT 1897.570 243.820 1897.890 243.880 ; + RECT 1904.010 243.820 1904.330 243.880 ; + RECT 1904.010 25.400 1904.330 25.460 ; + RECT 2203.010 25.400 2203.330 25.460 ; + RECT 1904.010 25.260 2203.330 25.400 ; + RECT 1904.010 25.200 1904.330 25.260 ; + RECT 2203.010 25.200 2203.330 25.260 ; + LAYER via ; + RECT 1897.600 243.820 1897.860 244.080 ; + RECT 1904.040 243.820 1904.300 244.080 ; + RECT 1904.040 25.200 1904.300 25.460 ; + RECT 2203.040 25.200 2203.300 25.460 ; + LAYER met2 ; + RECT 1897.550 260.000 1897.830 264.000 ; + RECT 1897.660 244.110 1897.800 260.000 ; + RECT 1897.600 243.790 1897.860 244.110 ; + RECT 1904.040 243.790 1904.300 244.110 ; + RECT 1904.100 25.490 1904.240 243.790 ; + RECT 1904.040 25.170 1904.300 25.490 ; + RECT 2203.040 25.170 2203.300 25.490 ; + RECT 2203.100 2.400 2203.240 25.170 ; + RECT 2202.890 -4.800 2203.450 2.400 ; +======= LAYER met2 ; RECT 2202.890 -4.800 2203.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[88] PIN la_data_in[89] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1915.510 243.340 1915.830 243.400 ; + RECT 1921.490 243.340 1921.810 243.400 ; + RECT 1915.510 243.200 1921.810 243.340 ; + RECT 1915.510 243.140 1915.830 243.200 ; + RECT 1921.490 243.140 1921.810 243.200 ; + RECT 1921.490 65.520 1921.810 65.580 ; + RECT 2215.430 65.520 2215.750 65.580 ; + RECT 1921.490 65.380 2215.750 65.520 ; + RECT 1921.490 65.320 1921.810 65.380 ; + RECT 2215.430 65.320 2215.750 65.380 ; + RECT 2215.430 20.640 2215.750 20.700 ; + RECT 2220.950 20.640 2221.270 20.700 ; + RECT 2215.430 20.500 2221.270 20.640 ; + RECT 2215.430 20.440 2215.750 20.500 ; + RECT 2220.950 20.440 2221.270 20.500 ; + LAYER via ; + RECT 1915.540 243.140 1915.800 243.400 ; + RECT 1921.520 243.140 1921.780 243.400 ; + RECT 1921.520 65.320 1921.780 65.580 ; + RECT 2215.460 65.320 2215.720 65.580 ; + RECT 2215.460 20.440 2215.720 20.700 ; + RECT 2220.980 20.440 2221.240 20.700 ; + LAYER met2 ; + RECT 1915.490 260.000 1915.770 264.000 ; + RECT 1915.600 243.430 1915.740 260.000 ; + RECT 1915.540 243.110 1915.800 243.430 ; + RECT 1921.520 243.110 1921.780 243.430 ; + RECT 1921.580 65.610 1921.720 243.110 ; + RECT 1921.520 65.290 1921.780 65.610 ; + RECT 2215.460 65.290 2215.720 65.610 ; + RECT 2215.520 20.730 2215.660 65.290 ; + RECT 2215.460 20.410 2215.720 20.730 ; + RECT 2220.980 20.410 2221.240 20.730 ; + RECT 2221.040 2.400 2221.180 20.410 ; + RECT 2220.830 -4.800 2221.390 2.400 ; +======= LAYER met2 ; RECT 2220.830 -4.800 2221.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[89] PIN la_data_in[8] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 468.810 134.540 469.130 134.600 ; + RECT 772.870 134.540 773.190 134.600 ; + RECT 468.810 134.400 773.190 134.540 ; + RECT 468.810 134.340 469.130 134.400 ; + RECT 772.870 134.340 773.190 134.400 ; + LAYER via ; + RECT 468.840 134.340 469.100 134.600 ; + RECT 772.900 134.340 773.160 134.600 ; + LAYER met2 ; + RECT 467.410 260.170 467.690 264.000 ; + RECT 467.410 260.030 469.040 260.170 ; + RECT 467.410 260.000 467.690 260.030 ; + RECT 468.900 134.630 469.040 260.030 ; + RECT 468.840 134.310 469.100 134.630 ; + RECT 772.900 134.310 773.160 134.630 ; + RECT 772.960 16.730 773.100 134.310 ; + RECT 772.960 16.590 775.860 16.730 ; + RECT 775.720 2.400 775.860 16.590 ; + RECT 775.510 -4.800 776.070 2.400 ; +======= LAYER met2 ; RECT 775.510 -4.800 776.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[8] PIN la_data_in[90] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1933.450 244.020 1933.770 244.080 ; + RECT 1938.510 244.020 1938.830 244.080 ; + RECT 1933.450 243.880 1938.830 244.020 ; + RECT 1933.450 243.820 1933.770 243.880 ; + RECT 1938.510 243.820 1938.830 243.880 ; + RECT 1938.510 24.720 1938.830 24.780 ; + RECT 2238.890 24.720 2239.210 24.780 ; + RECT 1938.510 24.580 2239.210 24.720 ; + RECT 1938.510 24.520 1938.830 24.580 ; + RECT 2238.890 24.520 2239.210 24.580 ; + LAYER via ; + RECT 1933.480 243.820 1933.740 244.080 ; + RECT 1938.540 243.820 1938.800 244.080 ; + RECT 1938.540 24.520 1938.800 24.780 ; + RECT 2238.920 24.520 2239.180 24.780 ; + LAYER met2 ; + RECT 1933.430 260.000 1933.710 264.000 ; + RECT 1933.540 244.110 1933.680 260.000 ; + RECT 1933.480 243.790 1933.740 244.110 ; + RECT 1938.540 243.790 1938.800 244.110 ; + RECT 1938.600 24.810 1938.740 243.790 ; + RECT 1938.540 24.490 1938.800 24.810 ; + RECT 2238.920 24.490 2239.180 24.810 ; + RECT 2238.980 2.400 2239.120 24.490 ; + RECT 2238.770 -4.800 2239.330 2.400 ; +======= LAYER met2 ; RECT 2238.770 -4.800 2239.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[90] PIN la_data_in[91] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 2014.945 23.205 2015.115 24.395 ; + RECT 2031.965 23.205 2032.135 24.395 ; + RECT 2111.545 24.225 2111.715 25.075 ; + RECT 2140.985 24.225 2141.155 25.075 ; + LAYER mcon ; + RECT 2111.545 24.905 2111.715 25.075 ; + RECT 2014.945 24.225 2015.115 24.395 ; + RECT 2031.965 24.225 2032.135 24.395 ; + RECT 2140.985 24.905 2141.155 25.075 ; + LAYER met1 ; + RECT 2111.485 25.060 2111.775 25.105 ; + RECT 2140.925 25.060 2141.215 25.105 ; + RECT 2111.485 24.920 2141.215 25.060 ; + RECT 2111.485 24.875 2111.775 24.920 ; + RECT 2140.925 24.875 2141.215 24.920 ; + RECT 1952.310 24.380 1952.630 24.440 ; + RECT 2014.885 24.380 2015.175 24.425 ; + RECT 1952.310 24.240 2015.175 24.380 ; + RECT 1952.310 24.180 1952.630 24.240 ; + RECT 2014.885 24.195 2015.175 24.240 ; + RECT 2031.905 24.380 2032.195 24.425 ; + RECT 2111.485 24.380 2111.775 24.425 ; + RECT 2031.905 24.240 2111.775 24.380 ; + RECT 2031.905 24.195 2032.195 24.240 ; + RECT 2111.485 24.195 2111.775 24.240 ; + RECT 2140.925 24.380 2141.215 24.425 ; + RECT 2140.925 24.240 2208.300 24.380 ; + RECT 2140.925 24.195 2141.215 24.240 ; + RECT 2208.160 23.700 2208.300 24.240 ; + RECT 2256.830 23.700 2257.150 23.760 ; + RECT 2208.160 23.560 2257.150 23.700 ; + RECT 2256.830 23.500 2257.150 23.560 ; + RECT 2014.885 23.360 2015.175 23.405 ; + RECT 2031.905 23.360 2032.195 23.405 ; + RECT 2014.885 23.220 2032.195 23.360 ; + RECT 2014.885 23.175 2015.175 23.220 ; + RECT 2031.905 23.175 2032.195 23.220 ; + LAYER via ; + RECT 1952.340 24.180 1952.600 24.440 ; + RECT 2256.860 23.500 2257.120 23.760 ; + LAYER met2 ; + RECT 1951.370 260.170 1951.650 264.000 ; + RECT 1951.370 260.030 1952.540 260.170 ; + RECT 1951.370 260.000 1951.650 260.030 ; + RECT 1952.400 24.470 1952.540 260.030 ; + RECT 1952.340 24.150 1952.600 24.470 ; + RECT 2256.860 23.470 2257.120 23.790 ; + RECT 2256.920 12.650 2257.060 23.470 ; + RECT 2256.460 12.510 2257.060 12.650 ; + RECT 2256.460 2.400 2256.600 12.510 ; + RECT 2256.250 -4.800 2256.810 2.400 ; +======= LAYER met2 ; RECT 2256.250 -4.800 2256.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[91] PIN la_data_in[92] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1973.010 25.740 1973.330 25.800 ; + RECT 2274.310 25.740 2274.630 25.800 ; + RECT 1973.010 25.600 2274.630 25.740 ; + RECT 1973.010 25.540 1973.330 25.600 ; + RECT 2274.310 25.540 2274.630 25.600 ; + LAYER via ; + RECT 1973.040 25.540 1973.300 25.800 ; + RECT 2274.340 25.540 2274.600 25.800 ; + LAYER met2 ; + RECT 1969.310 260.170 1969.590 264.000 ; + RECT 1969.310 260.030 1973.240 260.170 ; + RECT 1969.310 260.000 1969.590 260.030 ; + RECT 1973.100 25.830 1973.240 260.030 ; + RECT 1973.040 25.510 1973.300 25.830 ; + RECT 2274.340 25.510 2274.600 25.830 ; + RECT 2274.400 2.400 2274.540 25.510 ; + RECT 2274.190 -4.800 2274.750 2.400 ; +======= LAYER met2 ; RECT 2274.190 -4.800 2274.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[92] PIN la_data_in[93] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1986.810 72.320 1987.130 72.380 ; + RECT 2290.870 72.320 2291.190 72.380 ; + RECT 1986.810 72.180 2291.190 72.320 ; + RECT 1986.810 72.120 1987.130 72.180 ; + RECT 2290.870 72.120 2291.190 72.180 ; + LAYER via ; + RECT 1986.840 72.120 1987.100 72.380 ; + RECT 2290.900 72.120 2291.160 72.380 ; + LAYER met2 ; + RECT 1986.790 260.000 1987.070 264.000 ; + RECT 1986.900 72.410 1987.040 260.000 ; + RECT 1986.840 72.090 1987.100 72.410 ; + RECT 2290.900 72.090 2291.160 72.410 ; + RECT 2290.960 3.130 2291.100 72.090 ; + RECT 2290.960 2.990 2292.480 3.130 ; + RECT 2292.340 2.400 2292.480 2.990 ; + RECT 2292.130 -4.800 2292.690 2.400 ; +======= LAYER met2 ; RECT 2292.130 -4.800 2292.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[93] PIN la_data_in[94] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2007.510 217.160 2007.830 217.220 ; + RECT 2304.670 217.160 2304.990 217.220 ; + RECT 2007.510 217.020 2304.990 217.160 ; + RECT 2007.510 216.960 2007.830 217.020 ; + RECT 2304.670 216.960 2304.990 217.020 ; + LAYER via ; + RECT 2007.540 216.960 2007.800 217.220 ; + RECT 2304.700 216.960 2304.960 217.220 ; + LAYER met2 ; + RECT 2004.730 260.170 2005.010 264.000 ; + RECT 2004.730 260.030 2007.740 260.170 ; + RECT 2004.730 260.000 2005.010 260.030 ; + RECT 2007.600 217.250 2007.740 260.030 ; + RECT 2007.540 216.930 2007.800 217.250 ; + RECT 2304.700 216.930 2304.960 217.250 ; + RECT 2304.760 16.730 2304.900 216.930 ; + RECT 2304.760 16.590 2310.420 16.730 ; + RECT 2310.280 2.400 2310.420 16.590 ; + RECT 2310.070 -4.800 2310.630 2.400 ; +======= LAYER met2 ; RECT 2310.070 -4.800 2310.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[94] PIN la_data_in[95] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2022.690 243.340 2023.010 243.400 ; + RECT 2028.210 243.340 2028.530 243.400 ; + RECT 2022.690 243.200 2028.530 243.340 ; + RECT 2022.690 243.140 2023.010 243.200 ; + RECT 2028.210 243.140 2028.530 243.200 ; + RECT 2028.210 79.460 2028.530 79.520 ; + RECT 2325.370 79.460 2325.690 79.520 ; + RECT 2028.210 79.320 2325.690 79.460 ; + RECT 2028.210 79.260 2028.530 79.320 ; + RECT 2325.370 79.260 2325.690 79.320 ; + LAYER via ; + RECT 2022.720 243.140 2022.980 243.400 ; + RECT 2028.240 243.140 2028.500 243.400 ; + RECT 2028.240 79.260 2028.500 79.520 ; + RECT 2325.400 79.260 2325.660 79.520 ; + LAYER met2 ; + RECT 2022.670 260.000 2022.950 264.000 ; + RECT 2022.780 243.430 2022.920 260.000 ; + RECT 2022.720 243.110 2022.980 243.430 ; + RECT 2028.240 243.110 2028.500 243.430 ; + RECT 2028.300 79.550 2028.440 243.110 ; + RECT 2028.240 79.230 2028.500 79.550 ; + RECT 2325.400 79.230 2325.660 79.550 ; + RECT 2325.460 9.250 2325.600 79.230 ; + RECT 2325.460 9.110 2328.360 9.250 ; + RECT 2328.220 2.400 2328.360 9.110 ; + RECT 2328.010 -4.800 2328.570 2.400 ; +======= LAYER met2 ; RECT 2328.010 -4.800 2328.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[95] PIN la_data_in[96] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2042.010 86.260 2042.330 86.320 ; + RECT 2339.170 86.260 2339.490 86.320 ; + RECT 2042.010 86.120 2339.490 86.260 ; + RECT 2042.010 86.060 2042.330 86.120 ; + RECT 2339.170 86.060 2339.490 86.120 ; + RECT 2339.170 18.260 2339.490 18.320 ; + RECT 2345.610 18.260 2345.930 18.320 ; + RECT 2339.170 18.120 2345.930 18.260 ; + RECT 2339.170 18.060 2339.490 18.120 ; + RECT 2345.610 18.060 2345.930 18.120 ; + LAYER via ; + RECT 2042.040 86.060 2042.300 86.320 ; + RECT 2339.200 86.060 2339.460 86.320 ; + RECT 2339.200 18.060 2339.460 18.320 ; + RECT 2345.640 18.060 2345.900 18.320 ; + LAYER met2 ; + RECT 2040.610 260.170 2040.890 264.000 ; + RECT 2040.610 260.030 2042.240 260.170 ; + RECT 2040.610 260.000 2040.890 260.030 ; + RECT 2042.100 86.350 2042.240 260.030 ; + RECT 2042.040 86.030 2042.300 86.350 ; + RECT 2339.200 86.030 2339.460 86.350 ; + RECT 2339.260 18.350 2339.400 86.030 ; + RECT 2339.200 18.030 2339.460 18.350 ; + RECT 2345.640 18.030 2345.900 18.350 ; + RECT 2345.700 2.400 2345.840 18.030 ; + RECT 2345.490 -4.800 2346.050 2.400 ; +======= LAYER met2 ; RECT 2345.490 -4.800 2346.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[96] PIN la_data_in[97] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2058.570 242.320 2058.890 242.380 ; + RECT 2062.710 242.320 2063.030 242.380 ; + RECT 2058.570 242.180 2063.030 242.320 ; + RECT 2058.570 242.120 2058.890 242.180 ; + RECT 2062.710 242.120 2063.030 242.180 ; + RECT 2062.710 93.060 2063.030 93.120 ; + RECT 2359.870 93.060 2360.190 93.120 ; + RECT 2062.710 92.920 2360.190 93.060 ; + RECT 2062.710 92.860 2063.030 92.920 ; + RECT 2359.870 92.860 2360.190 92.920 ; + RECT 2359.870 2.960 2360.190 3.020 ; + RECT 2363.550 2.960 2363.870 3.020 ; + RECT 2359.870 2.820 2363.870 2.960 ; + RECT 2359.870 2.760 2360.190 2.820 ; + RECT 2363.550 2.760 2363.870 2.820 ; + LAYER via ; + RECT 2058.600 242.120 2058.860 242.380 ; + RECT 2062.740 242.120 2063.000 242.380 ; + RECT 2062.740 92.860 2063.000 93.120 ; + RECT 2359.900 92.860 2360.160 93.120 ; + RECT 2359.900 2.760 2360.160 3.020 ; + RECT 2363.580 2.760 2363.840 3.020 ; + LAYER met2 ; + RECT 2058.550 260.000 2058.830 264.000 ; + RECT 2058.660 242.410 2058.800 260.000 ; + RECT 2058.600 242.090 2058.860 242.410 ; + RECT 2062.740 242.090 2063.000 242.410 ; + RECT 2062.800 93.150 2062.940 242.090 ; + RECT 2062.740 92.830 2063.000 93.150 ; + RECT 2359.900 92.830 2360.160 93.150 ; + RECT 2359.960 3.050 2360.100 92.830 ; + RECT 2359.900 2.730 2360.160 3.050 ; + RECT 2363.580 2.730 2363.840 3.050 ; + RECT 2363.640 2.400 2363.780 2.730 ; + RECT 2363.430 -4.800 2363.990 2.400 ; +======= LAYER met2 ; RECT 2363.430 -4.800 2363.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[97] PIN la_data_in[98] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2076.050 210.360 2076.370 210.420 ; + RECT 2380.570 210.360 2380.890 210.420 ; + RECT 2076.050 210.220 2380.890 210.360 ; + RECT 2076.050 210.160 2076.370 210.220 ; + RECT 2380.570 210.160 2380.890 210.220 ; + LAYER via ; + RECT 2076.080 210.160 2076.340 210.420 ; + RECT 2380.600 210.160 2380.860 210.420 ; + LAYER met2 ; + RECT 2076.490 260.170 2076.770 264.000 ; + RECT 2076.140 260.030 2076.770 260.170 ; + RECT 2076.140 210.450 2076.280 260.030 ; + RECT 2076.490 260.000 2076.770 260.030 ; + RECT 2076.080 210.130 2076.340 210.450 ; + RECT 2380.600 210.130 2380.860 210.450 ; + RECT 2380.660 3.130 2380.800 210.130 ; + RECT 2380.660 2.990 2381.720 3.130 ; + RECT 2381.580 2.400 2381.720 2.990 ; + RECT 2381.370 -4.800 2381.930 2.400 ; +======= LAYER met2 ; RECT 2381.370 -4.800 2381.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[98] PIN la_data_in[99] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2097.210 203.560 2097.530 203.620 ; + RECT 2394.370 203.560 2394.690 203.620 ; + RECT 2097.210 203.420 2394.690 203.560 ; + RECT 2097.210 203.360 2097.530 203.420 ; + RECT 2394.370 203.360 2394.690 203.420 ; + RECT 2394.370 2.960 2394.690 3.020 ; + RECT 2399.430 2.960 2399.750 3.020 ; + RECT 2394.370 2.820 2399.750 2.960 ; + RECT 2394.370 2.760 2394.690 2.820 ; + RECT 2399.430 2.760 2399.750 2.820 ; + LAYER via ; + RECT 2097.240 203.360 2097.500 203.620 ; + RECT 2394.400 203.360 2394.660 203.620 ; + RECT 2394.400 2.760 2394.660 3.020 ; + RECT 2399.460 2.760 2399.720 3.020 ; + LAYER met2 ; + RECT 2094.430 260.170 2094.710 264.000 ; + RECT 2094.430 260.030 2097.440 260.170 ; + RECT 2094.430 260.000 2094.710 260.030 ; + RECT 2097.300 203.650 2097.440 260.030 ; + RECT 2097.240 203.330 2097.500 203.650 ; + RECT 2394.400 203.330 2394.660 203.650 ; + RECT 2394.460 3.050 2394.600 203.330 ; + RECT 2394.400 2.730 2394.660 3.050 ; + RECT 2399.460 2.730 2399.720 3.050 ; + RECT 2399.520 2.400 2399.660 2.730 ; + RECT 2399.310 -4.800 2399.870 2.400 ; +======= LAYER met2 ; RECT 2399.310 -4.800 2399.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[99] PIN la_data_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 485.370 244.020 485.690 244.080 ; + RECT 489.510 244.020 489.830 244.080 ; + RECT 485.370 243.880 489.830 244.020 ; + RECT 485.370 243.820 485.690 243.880 ; + RECT 489.510 243.820 489.830 243.880 ; + RECT 489.510 141.340 489.830 141.400 ; + RECT 794.030 141.340 794.350 141.400 ; + RECT 489.510 141.200 794.350 141.340 ; + RECT 489.510 141.140 489.830 141.200 ; + RECT 794.030 141.140 794.350 141.200 ; + LAYER via ; + RECT 485.400 243.820 485.660 244.080 ; + RECT 489.540 243.820 489.800 244.080 ; + RECT 489.540 141.140 489.800 141.400 ; + RECT 794.060 141.140 794.320 141.400 ; + LAYER met2 ; + RECT 485.350 260.000 485.630 264.000 ; + RECT 485.460 244.110 485.600 260.000 ; + RECT 485.400 243.790 485.660 244.110 ; + RECT 489.540 243.790 489.800 244.110 ; + RECT 489.600 141.430 489.740 243.790 ; + RECT 489.540 141.110 489.800 141.430 ; + RECT 794.060 141.110 794.320 141.430 ; + RECT 794.120 7.890 794.260 141.110 ; + RECT 793.660 7.750 794.260 7.890 ; + RECT 793.660 2.400 793.800 7.750 ; + RECT 793.450 -4.800 794.010 2.400 ; +======= LAYER met2 ; RECT 793.450 -4.800 794.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_in[9] PIN la_data_out[0] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 330.350 244.020 330.670 244.080 ; + RECT 334.490 244.020 334.810 244.080 ; + RECT 330.350 243.880 334.810 244.020 ; + RECT 330.350 243.820 330.670 243.880 ; + RECT 334.490 243.820 334.810 243.880 ; + RECT 334.490 79.460 334.810 79.520 ; + RECT 634.870 79.460 635.190 79.520 ; + RECT 334.490 79.320 635.190 79.460 ; + RECT 334.490 79.260 334.810 79.320 ; + RECT 634.870 79.260 635.190 79.320 ; + LAYER via ; + RECT 330.380 243.820 330.640 244.080 ; + RECT 334.520 243.820 334.780 244.080 ; + RECT 334.520 79.260 334.780 79.520 ; + RECT 634.900 79.260 635.160 79.520 ; + LAYER met2 ; + RECT 330.330 260.000 330.610 264.000 ; + RECT 330.440 244.110 330.580 260.000 ; + RECT 330.380 243.790 330.640 244.110 ; + RECT 334.520 243.790 334.780 244.110 ; + RECT 334.580 79.550 334.720 243.790 ; + RECT 334.520 79.230 334.780 79.550 ; + RECT 634.900 79.230 635.160 79.550 ; + RECT 634.960 17.410 635.100 79.230 ; + RECT 634.960 17.270 639.240 17.410 ; + RECT 639.100 2.400 639.240 17.270 ; + RECT 638.890 -4.800 639.450 2.400 ; +======= LAYER met2 ; RECT 638.890 -4.800 639.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[0] PIN la_data_out[100] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2117.450 99.860 2117.770 99.920 ; + RECT 2421.970 99.860 2422.290 99.920 ; + RECT 2117.450 99.720 2422.290 99.860 ; + RECT 2117.450 99.660 2117.770 99.720 ; + RECT 2421.970 99.660 2422.290 99.720 ; + LAYER via ; + RECT 2117.480 99.660 2117.740 99.920 ; + RECT 2422.000 99.660 2422.260 99.920 ; + LAYER met2 ; + RECT 2117.890 260.170 2118.170 264.000 ; + RECT 2117.540 260.030 2118.170 260.170 ; + RECT 2117.540 99.950 2117.680 260.030 ; + RECT 2117.890 260.000 2118.170 260.030 ; + RECT 2117.480 99.630 2117.740 99.950 ; + RECT 2422.000 99.630 2422.260 99.950 ; + RECT 2422.060 17.410 2422.200 99.630 ; + RECT 2422.060 17.270 2423.120 17.410 ; + RECT 2422.980 2.400 2423.120 17.270 ; + RECT 2422.770 -4.800 2423.330 2.400 ; +======= LAYER met2 ; RECT 2422.770 -4.800 2423.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[100] PIN la_data_out[101] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2138.610 107.340 2138.930 107.400 ; + RECT 2435.770 107.340 2436.090 107.400 ; + RECT 2138.610 107.200 2436.090 107.340 ; + RECT 2138.610 107.140 2138.930 107.200 ; + RECT 2435.770 107.140 2436.090 107.200 ; + LAYER via ; + RECT 2138.640 107.140 2138.900 107.400 ; + RECT 2435.800 107.140 2436.060 107.400 ; + LAYER met2 ; + RECT 2135.830 260.170 2136.110 264.000 ; + RECT 2135.830 260.030 2138.840 260.170 ; + RECT 2135.830 260.000 2136.110 260.030 ; + RECT 2138.700 107.430 2138.840 260.030 ; + RECT 2138.640 107.110 2138.900 107.430 ; + RECT 2435.800 107.110 2436.060 107.430 ; + RECT 2435.860 17.410 2436.000 107.110 ; + RECT 2435.860 17.270 2441.060 17.410 ; + RECT 2440.920 2.400 2441.060 17.270 ; + RECT 2440.710 -4.800 2441.270 2.400 ; +======= LAYER met2 ; RECT 2440.710 -4.800 2441.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[101] PIN la_data_out[102] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2153.790 244.020 2154.110 244.080 ; + RECT 2159.310 244.020 2159.630 244.080 ; + RECT 2153.790 243.880 2159.630 244.020 ; + RECT 2153.790 243.820 2154.110 243.880 ; + RECT 2159.310 243.820 2159.630 243.880 ; + RECT 2159.310 114.140 2159.630 114.200 ; + RECT 2456.470 114.140 2456.790 114.200 ; + RECT 2159.310 114.000 2456.790 114.140 ; + RECT 2159.310 113.940 2159.630 114.000 ; + RECT 2456.470 113.940 2456.790 114.000 ; + LAYER via ; + RECT 2153.820 243.820 2154.080 244.080 ; + RECT 2159.340 243.820 2159.600 244.080 ; + RECT 2159.340 113.940 2159.600 114.200 ; + RECT 2456.500 113.940 2456.760 114.200 ; + LAYER met2 ; + RECT 2153.770 260.000 2154.050 264.000 ; + RECT 2153.880 244.110 2154.020 260.000 ; + RECT 2153.820 243.790 2154.080 244.110 ; + RECT 2159.340 243.790 2159.600 244.110 ; + RECT 2159.400 114.230 2159.540 243.790 ; + RECT 2159.340 113.910 2159.600 114.230 ; + RECT 2456.500 113.910 2456.760 114.230 ; + RECT 2456.560 17.410 2456.700 113.910 ; + RECT 2456.560 17.270 2459.000 17.410 ; + RECT 2458.860 2.400 2459.000 17.270 ; + RECT 2458.650 -4.800 2459.210 2.400 ; +======= LAYER met2 ; RECT 2458.650 -4.800 2459.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[102] PIN la_data_out[103] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2173.110 120.600 2173.430 120.660 ; + RECT 2470.730 120.600 2471.050 120.660 ; + RECT 2173.110 120.460 2471.050 120.600 ; + RECT 2173.110 120.400 2173.430 120.460 ; + RECT 2470.730 120.400 2471.050 120.460 ; + RECT 2470.730 17.920 2471.050 17.980 ; + RECT 2476.710 17.920 2477.030 17.980 ; + RECT 2470.730 17.780 2477.030 17.920 ; + RECT 2470.730 17.720 2471.050 17.780 ; + RECT 2476.710 17.720 2477.030 17.780 ; + LAYER via ; + RECT 2173.140 120.400 2173.400 120.660 ; + RECT 2470.760 120.400 2471.020 120.660 ; + RECT 2470.760 17.720 2471.020 17.980 ; + RECT 2476.740 17.720 2477.000 17.980 ; + LAYER met2 ; + RECT 2171.710 260.170 2171.990 264.000 ; + RECT 2171.710 260.030 2173.340 260.170 ; + RECT 2171.710 260.000 2171.990 260.030 ; + RECT 2173.200 120.690 2173.340 260.030 ; + RECT 2173.140 120.370 2173.400 120.690 ; + RECT 2470.760 120.370 2471.020 120.690 ; + RECT 2470.820 18.010 2470.960 120.370 ; + RECT 2470.760 17.690 2471.020 18.010 ; + RECT 2476.740 17.690 2477.000 18.010 ; + RECT 2476.800 2.400 2476.940 17.690 ; + RECT 2476.590 -4.800 2477.150 2.400 ; +======= LAYER met2 ; RECT 2476.590 -4.800 2477.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[103] PIN la_data_out[104] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2189.670 242.320 2189.990 242.380 ; + RECT 2193.810 242.320 2194.130 242.380 ; + RECT 2189.670 242.180 2194.130 242.320 ; + RECT 2189.670 242.120 2189.990 242.180 ; + RECT 2193.810 242.120 2194.130 242.180 ; + RECT 2193.810 128.420 2194.130 128.480 ; + RECT 2490.970 128.420 2491.290 128.480 ; + RECT 2193.810 128.280 2491.290 128.420 ; + RECT 2193.810 128.220 2194.130 128.280 ; + RECT 2490.970 128.220 2491.290 128.280 ; + LAYER via ; + RECT 2189.700 242.120 2189.960 242.380 ; + RECT 2193.840 242.120 2194.100 242.380 ; + RECT 2193.840 128.220 2194.100 128.480 ; + RECT 2491.000 128.220 2491.260 128.480 ; + LAYER met2 ; + RECT 2189.650 260.000 2189.930 264.000 ; + RECT 2189.760 242.410 2189.900 260.000 ; + RECT 2189.700 242.090 2189.960 242.410 ; + RECT 2193.840 242.090 2194.100 242.410 ; + RECT 2193.900 128.510 2194.040 242.090 ; + RECT 2193.840 128.190 2194.100 128.510 ; + RECT 2491.000 128.190 2491.260 128.510 ; + RECT 2491.060 17.410 2491.200 128.190 ; + RECT 2491.060 17.270 2494.880 17.410 ; + RECT 2494.740 2.400 2494.880 17.270 ; + RECT 2494.530 -4.800 2495.090 2.400 ; +======= LAYER met2 ; RECT 2494.530 -4.800 2495.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[104] PIN la_data_out[105] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2207.150 148.140 2207.470 148.200 ; + RECT 2512.130 148.140 2512.450 148.200 ; + RECT 2207.150 148.000 2512.450 148.140 ; + RECT 2207.150 147.940 2207.470 148.000 ; + RECT 2512.130 147.940 2512.450 148.000 ; + LAYER via ; + RECT 2207.180 147.940 2207.440 148.200 ; + RECT 2512.160 147.940 2512.420 148.200 ; + LAYER met2 ; + RECT 2207.590 260.170 2207.870 264.000 ; + RECT 2207.240 260.030 2207.870 260.170 ; + RECT 2207.240 148.230 2207.380 260.030 ; + RECT 2207.590 260.000 2207.870 260.030 ; + RECT 2207.180 147.910 2207.440 148.230 ; + RECT 2512.160 147.910 2512.420 148.230 ; + RECT 2512.220 2.400 2512.360 147.910 ; + RECT 2512.010 -4.800 2512.570 2.400 ; +======= LAYER met2 ; RECT 2512.010 -4.800 2512.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[105] PIN la_data_out[106] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2228.310 135.220 2228.630 135.280 ; + RECT 2525.470 135.220 2525.790 135.280 ; + RECT 2228.310 135.080 2525.790 135.220 ; + RECT 2228.310 135.020 2228.630 135.080 ; + RECT 2525.470 135.020 2525.790 135.080 ; + LAYER via ; + RECT 2228.340 135.020 2228.600 135.280 ; + RECT 2525.500 135.020 2525.760 135.280 ; + LAYER met2 ; + RECT 2225.530 260.170 2225.810 264.000 ; + RECT 2225.530 260.030 2228.540 260.170 ; + RECT 2225.530 260.000 2225.810 260.030 ; + RECT 2228.400 135.310 2228.540 260.030 ; + RECT 2228.340 134.990 2228.600 135.310 ; + RECT 2525.500 134.990 2525.760 135.310 ; + RECT 2525.560 16.730 2525.700 134.990 ; + RECT 2525.560 16.590 2530.300 16.730 ; + RECT 2530.160 2.400 2530.300 16.590 ; + RECT 2529.950 -4.800 2530.510 2.400 ; +======= LAYER met2 ; RECT 2529.950 -4.800 2530.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[106] PIN la_data_out[107] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2243.030 244.020 2243.350 244.080 ; + RECT 2248.550 244.020 2248.870 244.080 ; + RECT 2243.030 243.880 2248.870 244.020 ; + RECT 2243.030 243.820 2243.350 243.880 ; + RECT 2248.550 243.820 2248.870 243.880 ; + RECT 2248.550 141.680 2248.870 141.740 ; + RECT 2546.170 141.680 2546.490 141.740 ; + RECT 2248.550 141.540 2546.490 141.680 ; + RECT 2248.550 141.480 2248.870 141.540 ; + RECT 2546.170 141.480 2546.490 141.540 ; + LAYER via ; + RECT 2243.060 243.820 2243.320 244.080 ; + RECT 2248.580 243.820 2248.840 244.080 ; + RECT 2248.580 141.480 2248.840 141.740 ; + RECT 2546.200 141.480 2546.460 141.740 ; + LAYER met2 ; + RECT 2243.010 260.000 2243.290 264.000 ; + RECT 2243.120 244.110 2243.260 260.000 ; + RECT 2243.060 243.790 2243.320 244.110 ; + RECT 2248.580 243.790 2248.840 244.110 ; + RECT 2248.640 141.770 2248.780 243.790 ; + RECT 2248.580 141.450 2248.840 141.770 ; + RECT 2546.200 141.450 2546.460 141.770 ; + RECT 2546.260 16.730 2546.400 141.450 ; + RECT 2546.260 16.590 2548.240 16.730 ; + RECT 2548.100 2.400 2548.240 16.590 ; + RECT 2547.890 -4.800 2548.450 2.400 ; +======= LAYER met2 ; RECT 2547.890 -4.800 2548.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[107] PIN la_data_out[108] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2262.810 155.280 2263.130 155.340 ; + RECT 2560.430 155.280 2560.750 155.340 ; + RECT 2262.810 155.140 2560.750 155.280 ; + RECT 2262.810 155.080 2263.130 155.140 ; + RECT 2560.430 155.080 2560.750 155.140 ; + LAYER via ; + RECT 2262.840 155.080 2263.100 155.340 ; + RECT 2560.460 155.080 2560.720 155.340 ; + LAYER met2 ; + RECT 2260.950 260.170 2261.230 264.000 ; + RECT 2260.950 260.030 2263.040 260.170 ; + RECT 2260.950 260.000 2261.230 260.030 ; + RECT 2262.900 155.370 2263.040 260.030 ; + RECT 2262.840 155.050 2263.100 155.370 ; + RECT 2560.460 155.050 2560.720 155.370 ; + RECT 2560.520 16.730 2560.660 155.050 ; + RECT 2560.520 16.590 2566.180 16.730 ; + RECT 2566.040 2.400 2566.180 16.590 ; + RECT 2565.830 -4.800 2566.390 2.400 ; +======= LAYER met2 ; RECT 2565.830 -4.800 2566.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[108] PIN la_data_out[109] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2278.910 244.020 2279.230 244.080 ; + RECT 2283.510 244.020 2283.830 244.080 ; + RECT 2278.910 243.880 2283.830 244.020 ; + RECT 2278.910 243.820 2279.230 243.880 ; + RECT 2283.510 243.820 2283.830 243.880 ; + RECT 2283.510 162.080 2283.830 162.140 ; + RECT 2580.670 162.080 2580.990 162.140 ; + RECT 2283.510 161.940 2580.990 162.080 ; + RECT 2283.510 161.880 2283.830 161.940 ; + RECT 2580.670 161.880 2580.990 161.940 ; + LAYER via ; + RECT 2278.940 243.820 2279.200 244.080 ; + RECT 2283.540 243.820 2283.800 244.080 ; + RECT 2283.540 161.880 2283.800 162.140 ; + RECT 2580.700 161.880 2580.960 162.140 ; + LAYER met2 ; + RECT 2278.890 260.000 2279.170 264.000 ; + RECT 2279.000 244.110 2279.140 260.000 ; + RECT 2278.940 243.790 2279.200 244.110 ; + RECT 2283.540 243.790 2283.800 244.110 ; + RECT 2283.600 162.170 2283.740 243.790 ; + RECT 2283.540 161.850 2283.800 162.170 ; + RECT 2580.700 161.850 2580.960 162.170 ; + RECT 2580.760 16.730 2580.900 161.850 ; + RECT 2580.760 16.590 2584.120 16.730 ; + RECT 2583.980 2.400 2584.120 16.590 ; + RECT 2583.770 -4.800 2584.330 2.400 ; +======= LAYER met2 ; RECT 2583.770 -4.800 2584.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[109] PIN la_data_out[10] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 510.210 148.140 510.530 148.200 ; + RECT 814.270 148.140 814.590 148.200 ; + RECT 510.210 148.000 814.590 148.140 ; + RECT 510.210 147.940 510.530 148.000 ; + RECT 814.270 147.940 814.590 148.000 ; + LAYER via ; + RECT 510.240 147.940 510.500 148.200 ; + RECT 814.300 147.940 814.560 148.200 ; + LAYER met2 ; + RECT 509.270 260.170 509.550 264.000 ; + RECT 509.270 260.030 510.440 260.170 ; + RECT 509.270 260.000 509.550 260.030 ; + RECT 510.300 148.230 510.440 260.030 ; + RECT 510.240 147.910 510.500 148.230 ; + RECT 814.300 147.910 814.560 148.230 ; + RECT 814.360 17.410 814.500 147.910 ; + RECT 814.360 17.270 817.720 17.410 ; + RECT 817.580 2.400 817.720 17.270 ; + RECT 817.370 -4.800 817.930 2.400 ; +======= LAYER met2 ; RECT 817.370 -4.800 817.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[10] PIN la_data_out[110] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2296.850 168.880 2297.170 168.940 ; + RECT 2601.830 168.880 2602.150 168.940 ; + RECT 2296.850 168.740 2602.150 168.880 ; + RECT 2296.850 168.680 2297.170 168.740 ; + RECT 2601.830 168.680 2602.150 168.740 ; + LAYER via ; + RECT 2296.880 168.680 2297.140 168.940 ; + RECT 2601.860 168.680 2602.120 168.940 ; + LAYER met2 ; + RECT 2296.830 260.000 2297.110 264.000 ; + RECT 2296.940 168.970 2297.080 260.000 ; + RECT 2296.880 168.650 2297.140 168.970 ; + RECT 2601.860 168.650 2602.120 168.970 ; + RECT 2601.920 17.410 2602.060 168.650 ; + RECT 2601.460 17.270 2602.060 17.410 ; + RECT 2601.460 2.400 2601.600 17.270 ; + RECT 2601.250 -4.800 2601.810 2.400 ; +======= LAYER met2 ; RECT 2601.250 -4.800 2601.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[110] PIN la_data_out[111] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2318.010 25.740 2318.330 25.800 ; + RECT 2619.310 25.740 2619.630 25.800 ; + RECT 2318.010 25.600 2619.630 25.740 ; + RECT 2318.010 25.540 2318.330 25.600 ; + RECT 2619.310 25.540 2619.630 25.600 ; + LAYER via ; + RECT 2318.040 25.540 2318.300 25.800 ; + RECT 2619.340 25.540 2619.600 25.800 ; + LAYER met2 ; + RECT 2314.770 260.170 2315.050 264.000 ; + RECT 2314.770 260.030 2318.240 260.170 ; + RECT 2314.770 260.000 2315.050 260.030 ; + RECT 2318.100 25.830 2318.240 260.030 ; + RECT 2318.040 25.510 2318.300 25.830 ; + RECT 2619.340 25.510 2619.600 25.830 ; + RECT 2619.400 2.400 2619.540 25.510 ; + RECT 2619.190 -4.800 2619.750 2.400 ; +======= LAYER met2 ; RECT 2619.190 -4.800 2619.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[111] PIN la_data_out[112] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2332.730 244.020 2333.050 244.080 ; + RECT 2338.710 244.020 2339.030 244.080 ; + RECT 2332.730 243.880 2339.030 244.020 ; + RECT 2332.730 243.820 2333.050 243.880 ; + RECT 2338.710 243.820 2339.030 243.880 ; + RECT 2338.710 176.020 2339.030 176.080 ; + RECT 2635.870 176.020 2636.190 176.080 ; + RECT 2338.710 175.880 2636.190 176.020 ; + RECT 2338.710 175.820 2339.030 175.880 ; + RECT 2635.870 175.820 2636.190 175.880 ; + LAYER via ; + RECT 2332.760 243.820 2333.020 244.080 ; + RECT 2338.740 243.820 2339.000 244.080 ; + RECT 2338.740 175.820 2339.000 176.080 ; + RECT 2635.900 175.820 2636.160 176.080 ; + LAYER met2 ; + RECT 2332.710 260.000 2332.990 264.000 ; + RECT 2332.820 244.110 2332.960 260.000 ; + RECT 2332.760 243.790 2333.020 244.110 ; + RECT 2338.740 243.790 2339.000 244.110 ; + RECT 2338.800 176.110 2338.940 243.790 ; + RECT 2338.740 175.790 2339.000 176.110 ; + RECT 2635.900 175.790 2636.160 176.110 ; + RECT 2635.960 16.730 2636.100 175.790 ; + RECT 2635.960 16.590 2637.480 16.730 ; + RECT 2637.340 2.400 2637.480 16.590 ; + RECT 2637.130 -4.800 2637.690 2.400 ; +======= LAYER met2 ; RECT 2637.130 -4.800 2637.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[112] PIN la_data_out[113] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2352.510 182.820 2352.830 182.880 ; + RECT 2649.670 182.820 2649.990 182.880 ; + RECT 2352.510 182.680 2649.990 182.820 ; + RECT 2352.510 182.620 2352.830 182.680 ; + RECT 2649.670 182.620 2649.990 182.680 ; + LAYER via ; + RECT 2352.540 182.620 2352.800 182.880 ; + RECT 2649.700 182.620 2649.960 182.880 ; + LAYER met2 ; + RECT 2350.650 260.170 2350.930 264.000 ; + RECT 2350.650 260.030 2352.740 260.170 ; + RECT 2350.650 260.000 2350.930 260.030 ; + RECT 2352.600 182.910 2352.740 260.030 ; + RECT 2352.540 182.590 2352.800 182.910 ; + RECT 2649.700 182.590 2649.960 182.910 ; + RECT 2649.760 17.410 2649.900 182.590 ; + RECT 2649.760 17.270 2655.420 17.410 ; + RECT 2655.280 2.400 2655.420 17.270 ; + RECT 2655.070 -4.800 2655.630 2.400 ; +======= LAYER met2 ; RECT 2655.070 -4.800 2655.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[113] PIN la_data_out[114] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2368.150 244.020 2368.470 244.080 ; + RECT 2373.210 244.020 2373.530 244.080 ; + RECT 2368.150 243.880 2373.530 244.020 ; + RECT 2368.150 243.820 2368.470 243.880 ; + RECT 2373.210 243.820 2373.530 243.880 ; + RECT 2373.210 93.060 2373.530 93.120 ; + RECT 2670.370 93.060 2670.690 93.120 ; + RECT 2373.210 92.920 2670.690 93.060 ; + RECT 2373.210 92.860 2373.530 92.920 ; + RECT 2670.370 92.860 2670.690 92.920 ; + LAYER via ; + RECT 2368.180 243.820 2368.440 244.080 ; + RECT 2373.240 243.820 2373.500 244.080 ; + RECT 2373.240 92.860 2373.500 93.120 ; + RECT 2670.400 92.860 2670.660 93.120 ; + LAYER met2 ; + RECT 2368.130 260.000 2368.410 264.000 ; + RECT 2368.240 244.110 2368.380 260.000 ; + RECT 2368.180 243.790 2368.440 244.110 ; + RECT 2373.240 243.790 2373.500 244.110 ; + RECT 2373.300 93.150 2373.440 243.790 ; + RECT 2373.240 92.830 2373.500 93.150 ; + RECT 2670.400 92.830 2670.660 93.150 ; + RECT 2670.460 17.410 2670.600 92.830 ; + RECT 2670.460 17.270 2672.900 17.410 ; + RECT 2672.760 2.400 2672.900 17.270 ; + RECT 2672.550 -4.800 2673.110 2.400 ; +======= LAYER met2 ; RECT 2672.550 -4.800 2673.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[114] PIN la_data_out[115] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2386.090 248.440 2386.410 248.500 ; + RECT 2411.390 248.440 2411.710 248.500 ; + RECT 2386.090 248.300 2411.710 248.440 ; + RECT 2386.090 248.240 2386.410 248.300 ; + RECT 2411.390 248.240 2411.710 248.300 ; + RECT 2411.390 38.320 2411.710 38.380 ; + RECT 2690.610 38.320 2690.930 38.380 ; + RECT 2411.390 38.180 2690.930 38.320 ; + RECT 2411.390 38.120 2411.710 38.180 ; + RECT 2690.610 38.120 2690.930 38.180 ; + LAYER via ; + RECT 2386.120 248.240 2386.380 248.500 ; + RECT 2411.420 248.240 2411.680 248.500 ; + RECT 2411.420 38.120 2411.680 38.380 ; + RECT 2690.640 38.120 2690.900 38.380 ; + LAYER met2 ; + RECT 2386.070 260.000 2386.350 264.000 ; + RECT 2386.180 248.530 2386.320 260.000 ; + RECT 2386.120 248.210 2386.380 248.530 ; + RECT 2411.420 248.210 2411.680 248.530 ; + RECT 2411.480 38.410 2411.620 248.210 ; + RECT 2411.420 38.090 2411.680 38.410 ; + RECT 2690.640 38.090 2690.900 38.410 ; + RECT 2690.700 2.400 2690.840 38.090 ; + RECT 2690.490 -4.800 2691.050 2.400 ; +======= LAYER met2 ; RECT 2690.490 -4.800 2691.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[115] PIN la_data_out[116] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2404.030 244.020 2404.350 244.080 ; + RECT 2407.710 244.020 2408.030 244.080 ; + RECT 2404.030 243.880 2408.030 244.020 ; + RECT 2404.030 243.820 2404.350 243.880 ; + RECT 2407.710 243.820 2408.030 243.880 ; + RECT 2407.710 100.200 2408.030 100.260 ; + RECT 2704.870 100.200 2705.190 100.260 ; + RECT 2407.710 100.060 2705.190 100.200 ; + RECT 2407.710 100.000 2408.030 100.060 ; + RECT 2704.870 100.000 2705.190 100.060 ; + LAYER via ; + RECT 2404.060 243.820 2404.320 244.080 ; + RECT 2407.740 243.820 2408.000 244.080 ; + RECT 2407.740 100.000 2408.000 100.260 ; + RECT 2704.900 100.000 2705.160 100.260 ; + LAYER met2 ; + RECT 2404.010 260.000 2404.290 264.000 ; + RECT 2404.120 244.110 2404.260 260.000 ; + RECT 2404.060 243.790 2404.320 244.110 ; + RECT 2407.740 243.790 2408.000 244.110 ; + RECT 2407.800 100.290 2407.940 243.790 ; + RECT 2407.740 99.970 2408.000 100.290 ; + RECT 2704.900 99.970 2705.160 100.290 ; + RECT 2704.960 17.410 2705.100 99.970 ; + RECT 2704.960 17.270 2708.780 17.410 ; + RECT 2708.640 2.400 2708.780 17.270 ; + RECT 2708.430 -4.800 2708.990 2.400 ; +======= LAYER met2 ; RECT 2708.430 -4.800 2708.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[116] PIN la_data_out[117] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2421.970 241.640 2422.290 241.700 ; + RECT 2427.950 241.640 2428.270 241.700 ; + RECT 2421.970 241.500 2428.270 241.640 ; + RECT 2421.970 241.440 2422.290 241.500 ; + RECT 2427.950 241.440 2428.270 241.500 ; + RECT 2427.950 107.000 2428.270 107.060 ; + RECT 2725.570 107.000 2725.890 107.060 ; + RECT 2427.950 106.860 2725.890 107.000 ; + RECT 2427.950 106.800 2428.270 106.860 ; + RECT 2725.570 106.800 2725.890 106.860 ; + LAYER via ; + RECT 2422.000 241.440 2422.260 241.700 ; + RECT 2427.980 241.440 2428.240 241.700 ; + RECT 2427.980 106.800 2428.240 107.060 ; + RECT 2725.600 106.800 2725.860 107.060 ; + LAYER met2 ; + RECT 2421.950 260.000 2422.230 264.000 ; + RECT 2422.060 241.730 2422.200 260.000 ; + RECT 2422.000 241.410 2422.260 241.730 ; + RECT 2427.980 241.410 2428.240 241.730 ; + RECT 2428.040 107.090 2428.180 241.410 ; + RECT 2427.980 106.770 2428.240 107.090 ; + RECT 2725.600 106.770 2725.860 107.090 ; + RECT 2725.660 17.410 2725.800 106.770 ; + RECT 2725.660 17.270 2726.720 17.410 ; + RECT 2726.580 2.400 2726.720 17.270 ; + RECT 2726.370 -4.800 2726.930 2.400 ; +======= LAYER met2 ; RECT 2726.370 -4.800 2726.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[117] PIN la_data_out[118] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2442.210 113.800 2442.530 113.860 ; + RECT 2739.370 113.800 2739.690 113.860 ; + RECT 2442.210 113.660 2739.690 113.800 ; + RECT 2442.210 113.600 2442.530 113.660 ; + RECT 2739.370 113.600 2739.690 113.660 ; + LAYER via ; + RECT 2442.240 113.600 2442.500 113.860 ; + RECT 2739.400 113.600 2739.660 113.860 ; + LAYER met2 ; + RECT 2439.890 260.170 2440.170 264.000 ; + RECT 2439.890 260.030 2442.440 260.170 ; + RECT 2439.890 260.000 2440.170 260.030 ; + RECT 2442.300 113.890 2442.440 260.030 ; + RECT 2442.240 113.570 2442.500 113.890 ; + RECT 2739.400 113.570 2739.660 113.890 ; + RECT 2739.460 17.410 2739.600 113.570 ; + RECT 2739.460 17.270 2744.660 17.410 ; + RECT 2744.520 2.400 2744.660 17.270 ; + RECT 2744.310 -4.800 2744.870 2.400 ; +======= LAYER met2 ; RECT 2744.310 -4.800 2744.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[118] PIN la_data_out[119] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2457.850 244.020 2458.170 244.080 ; + RECT 2462.910 244.020 2463.230 244.080 ; + RECT 2457.850 243.880 2463.230 244.020 ; + RECT 2457.850 243.820 2458.170 243.880 ; + RECT 2462.910 243.820 2463.230 243.880 ; + RECT 2462.910 120.940 2463.230 121.000 ; + RECT 2760.070 120.940 2760.390 121.000 ; + RECT 2462.910 120.800 2760.390 120.940 ; + RECT 2462.910 120.740 2463.230 120.800 ; + RECT 2760.070 120.740 2760.390 120.800 ; + LAYER via ; + RECT 2457.880 243.820 2458.140 244.080 ; + RECT 2462.940 243.820 2463.200 244.080 ; + RECT 2462.940 120.740 2463.200 121.000 ; + RECT 2760.100 120.740 2760.360 121.000 ; + LAYER met2 ; + RECT 2457.830 260.000 2458.110 264.000 ; + RECT 2457.940 244.110 2458.080 260.000 ; + RECT 2457.880 243.790 2458.140 244.110 ; + RECT 2462.940 243.790 2463.200 244.110 ; + RECT 2463.000 121.030 2463.140 243.790 ; + RECT 2462.940 120.710 2463.200 121.030 ; + RECT 2760.100 120.710 2760.360 121.030 ; + RECT 2760.160 17.410 2760.300 120.710 ; + RECT 2760.160 17.270 2762.140 17.410 ; + RECT 2762.000 2.400 2762.140 17.270 ; + RECT 2761.790 -4.800 2762.350 2.400 ; +======= LAYER met2 ; RECT 2761.790 -4.800 2762.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[119] PIN la_data_out[11] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 527.230 244.020 527.550 244.080 ; + RECT 530.910 244.020 531.230 244.080 ; + RECT 527.230 243.880 531.230 244.020 ; + RECT 527.230 243.820 527.550 243.880 ; + RECT 530.910 243.820 531.230 243.880 ; + RECT 530.910 155.280 531.230 155.340 ; + RECT 835.430 155.280 835.750 155.340 ; + RECT 530.910 155.140 835.750 155.280 ; + RECT 530.910 155.080 531.230 155.140 ; + RECT 835.430 155.080 835.750 155.140 ; + LAYER via ; + RECT 527.260 243.820 527.520 244.080 ; + RECT 530.940 243.820 531.200 244.080 ; + RECT 530.940 155.080 531.200 155.340 ; + RECT 835.460 155.080 835.720 155.340 ; + LAYER met2 ; + RECT 527.210 260.000 527.490 264.000 ; + RECT 527.320 244.110 527.460 260.000 ; + RECT 527.260 243.790 527.520 244.110 ; + RECT 530.940 243.790 531.200 244.110 ; + RECT 531.000 155.370 531.140 243.790 ; + RECT 530.940 155.050 531.200 155.370 ; + RECT 835.460 155.050 835.720 155.370 ; + RECT 835.520 2.400 835.660 155.050 ; + RECT 835.310 -4.800 835.870 2.400 ; +======= LAYER met2 ; RECT 835.310 -4.800 835.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[11] PIN la_data_out[120] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2476.710 127.740 2477.030 127.800 ; + RECT 2774.330 127.740 2774.650 127.800 ; + RECT 2476.710 127.600 2774.650 127.740 ; + RECT 2476.710 127.540 2477.030 127.600 ; + RECT 2774.330 127.540 2774.650 127.600 ; + LAYER via ; + RECT 2476.740 127.540 2477.000 127.800 ; + RECT 2774.360 127.540 2774.620 127.800 ; + LAYER met2 ; + RECT 2475.770 260.170 2476.050 264.000 ; + RECT 2475.770 260.030 2476.940 260.170 ; + RECT 2475.770 260.000 2476.050 260.030 ; + RECT 2476.800 127.830 2476.940 260.030 ; + RECT 2476.740 127.510 2477.000 127.830 ; + RECT 2774.360 127.510 2774.620 127.830 ; + RECT 2774.420 17.410 2774.560 127.510 ; + RECT 2774.420 17.270 2780.080 17.410 ; + RECT 2779.940 2.400 2780.080 17.270 ; + RECT 2779.730 -4.800 2780.290 2.400 ; +======= LAYER met2 ; RECT 2779.730 -4.800 2780.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[120] PIN la_data_out[121] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2493.270 244.020 2493.590 244.080 ; + RECT 2497.410 244.020 2497.730 244.080 ; + RECT 2493.270 243.880 2497.730 244.020 ; + RECT 2493.270 243.820 2493.590 243.880 ; + RECT 2497.410 243.820 2497.730 243.880 ; + RECT 2497.410 44.780 2497.730 44.840 ; + RECT 2797.790 44.780 2798.110 44.840 ; + RECT 2497.410 44.640 2798.110 44.780 ; + RECT 2497.410 44.580 2497.730 44.640 ; + RECT 2797.790 44.580 2798.110 44.640 ; + LAYER via ; + RECT 2493.300 243.820 2493.560 244.080 ; + RECT 2497.440 243.820 2497.700 244.080 ; + RECT 2497.440 44.580 2497.700 44.840 ; + RECT 2797.820 44.580 2798.080 44.840 ; + LAYER met2 ; + RECT 2493.250 260.000 2493.530 264.000 ; + RECT 2493.360 244.110 2493.500 260.000 ; + RECT 2493.300 243.790 2493.560 244.110 ; + RECT 2497.440 243.790 2497.700 244.110 ; + RECT 2497.500 44.870 2497.640 243.790 ; + RECT 2497.440 44.550 2497.700 44.870 ; + RECT 2797.820 44.550 2798.080 44.870 ; + RECT 2797.880 2.400 2798.020 44.550 ; + RECT 2797.670 -4.800 2798.230 2.400 ; +======= LAYER met2 ; RECT 2797.670 -4.800 2798.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[121] PIN la_data_out[122] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2510.750 134.540 2511.070 134.600 ; + RECT 2815.730 134.540 2816.050 134.600 ; + RECT 2510.750 134.400 2816.050 134.540 ; + RECT 2510.750 134.340 2511.070 134.400 ; + RECT 2815.730 134.340 2816.050 134.400 ; + LAYER via ; + RECT 2510.780 134.340 2511.040 134.600 ; + RECT 2815.760 134.340 2816.020 134.600 ; + LAYER met2 ; + RECT 2511.190 260.170 2511.470 264.000 ; + RECT 2510.840 260.030 2511.470 260.170 ; + RECT 2510.840 134.630 2510.980 260.030 ; + RECT 2511.190 260.000 2511.470 260.030 ; + RECT 2510.780 134.310 2511.040 134.630 ; + RECT 2815.760 134.310 2816.020 134.630 ; + RECT 2815.820 2.400 2815.960 134.310 ; + RECT 2815.610 -4.800 2816.170 2.400 ; +======= LAYER met2 ; RECT 2815.610 -4.800 2816.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[122] PIN la_data_out[123] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2531.910 141.340 2532.230 141.400 ; + RECT 2829.070 141.340 2829.390 141.400 ; + RECT 2531.910 141.200 2829.390 141.340 ; + RECT 2531.910 141.140 2532.230 141.200 ; + RECT 2829.070 141.140 2829.390 141.200 ; + RECT 2829.070 2.960 2829.390 3.020 ; + RECT 2833.670 2.960 2833.990 3.020 ; + RECT 2829.070 2.820 2833.990 2.960 ; + RECT 2829.070 2.760 2829.390 2.820 ; + RECT 2833.670 2.760 2833.990 2.820 ; + LAYER via ; + RECT 2531.940 141.140 2532.200 141.400 ; + RECT 2829.100 141.140 2829.360 141.400 ; + RECT 2829.100 2.760 2829.360 3.020 ; + RECT 2833.700 2.760 2833.960 3.020 ; + LAYER met2 ; + RECT 2529.130 260.170 2529.410 264.000 ; + RECT 2529.130 260.030 2532.140 260.170 ; + RECT 2529.130 260.000 2529.410 260.030 ; + RECT 2532.000 141.430 2532.140 260.030 ; + RECT 2531.940 141.110 2532.200 141.430 ; + RECT 2829.100 141.110 2829.360 141.430 ; + RECT 2829.160 3.050 2829.300 141.110 ; + RECT 2829.100 2.730 2829.360 3.050 ; + RECT 2833.700 2.730 2833.960 3.050 ; + RECT 2833.760 2.400 2833.900 2.730 ; + RECT 2833.550 -4.800 2834.110 2.400 ; +======= LAYER met2 ; RECT 2833.550 -4.800 2834.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[123] PIN la_data_out[124] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2547.090 244.020 2547.410 244.080 ; + RECT 2552.610 244.020 2552.930 244.080 ; + RECT 2547.090 243.880 2552.930 244.020 ; + RECT 2547.090 243.820 2547.410 243.880 ; + RECT 2552.610 243.820 2552.930 243.880 ; + RECT 2552.610 155.620 2552.930 155.680 ; + RECT 2849.770 155.620 2850.090 155.680 ; + RECT 2552.610 155.480 2850.090 155.620 ; + RECT 2552.610 155.420 2552.930 155.480 ; + RECT 2849.770 155.420 2850.090 155.480 ; + LAYER via ; + RECT 2547.120 243.820 2547.380 244.080 ; + RECT 2552.640 243.820 2552.900 244.080 ; + RECT 2552.640 155.420 2552.900 155.680 ; + RECT 2849.800 155.420 2850.060 155.680 ; + LAYER met2 ; + RECT 2547.070 260.000 2547.350 264.000 ; + RECT 2547.180 244.110 2547.320 260.000 ; + RECT 2547.120 243.790 2547.380 244.110 ; + RECT 2552.640 243.790 2552.900 244.110 ; + RECT 2552.700 155.710 2552.840 243.790 ; + RECT 2552.640 155.390 2552.900 155.710 ; + RECT 2849.800 155.390 2850.060 155.710 ; + RECT 2849.860 17.410 2850.000 155.390 ; + RECT 2849.860 17.270 2851.380 17.410 ; + RECT 2851.240 2.400 2851.380 17.270 ; + RECT 2851.030 -4.800 2851.590 2.400 ; +======= LAYER met2 ; RECT 2851.030 -4.800 2851.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[124] PIN la_data_out[125] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2566.410 18.600 2566.730 18.660 ; + RECT 2869.090 18.600 2869.410 18.660 ; + RECT 2566.410 18.460 2869.410 18.600 ; + RECT 2566.410 18.400 2566.730 18.460 ; + RECT 2869.090 18.400 2869.410 18.460 ; + LAYER via ; + RECT 2566.440 18.400 2566.700 18.660 ; + RECT 2869.120 18.400 2869.380 18.660 ; + LAYER met2 ; + RECT 2565.010 260.170 2565.290 264.000 ; + RECT 2565.010 260.030 2566.640 260.170 ; + RECT 2565.010 260.000 2565.290 260.030 ; + RECT 2566.500 18.690 2566.640 260.030 ; + RECT 2566.440 18.370 2566.700 18.690 ; + RECT 2869.120 18.370 2869.380 18.690 ; + RECT 2869.180 2.400 2869.320 18.370 ; + RECT 2868.970 -4.800 2869.530 2.400 ; +======= LAYER met2 ; RECT 2868.970 -4.800 2869.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[125] PIN la_data_out[126] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2582.970 244.020 2583.290 244.080 ; + RECT 2587.110 244.020 2587.430 244.080 ; + RECT 2582.970 243.880 2587.430 244.020 ; + RECT 2582.970 243.820 2583.290 243.880 ; + RECT 2587.110 243.820 2587.430 243.880 ; + RECT 2587.110 17.240 2587.430 17.300 ; + RECT 2887.030 17.240 2887.350 17.300 ; + RECT 2587.110 17.100 2887.350 17.240 ; + RECT 2587.110 17.040 2587.430 17.100 ; + RECT 2887.030 17.040 2887.350 17.100 ; + LAYER via ; + RECT 2583.000 243.820 2583.260 244.080 ; + RECT 2587.140 243.820 2587.400 244.080 ; + RECT 2587.140 17.040 2587.400 17.300 ; + RECT 2887.060 17.040 2887.320 17.300 ; + LAYER met2 ; + RECT 2582.950 260.000 2583.230 264.000 ; + RECT 2583.060 244.110 2583.200 260.000 ; + RECT 2583.000 243.790 2583.260 244.110 ; + RECT 2587.140 243.790 2587.400 244.110 ; + RECT 2587.200 17.330 2587.340 243.790 ; + RECT 2587.140 17.010 2587.400 17.330 ; + RECT 2887.060 17.010 2887.320 17.330 ; + RECT 2887.120 2.400 2887.260 17.010 ; + RECT 2886.910 -4.800 2887.470 2.400 ; +======= LAYER met2 ; RECT 2886.910 -4.800 2887.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[126] PIN la_data_out[127] @@ -2436,847 +10575,3828 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 2600.890 260.000 2601.170 264.000 ; + RECT 2601.000 16.845 2601.140 260.000 ; + RECT 2600.930 16.475 2601.210 16.845 ; + RECT 2904.990 16.475 2905.270 16.845 ; + RECT 2905.060 2.400 2905.200 16.475 ; + RECT 2904.850 -4.800 2905.410 2.400 ; + LAYER via2 ; + RECT 2600.930 16.520 2601.210 16.800 ; + RECT 2904.990 16.520 2905.270 16.800 ; + LAYER met3 ; + RECT 2600.905 16.810 2601.235 16.825 ; + RECT 2904.965 16.810 2905.295 16.825 ; + RECT 2600.905 16.510 2905.295 16.810 ; + RECT 2600.905 16.495 2601.235 16.510 ; + RECT 2904.965 16.495 2905.295 16.510 ; +======= RECT 2904.850 -4.800 2905.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[127] PIN la_data_out[12] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 545.170 244.020 545.490 244.080 ; + RECT 551.610 244.020 551.930 244.080 ; + RECT 545.170 243.880 551.930 244.020 ; + RECT 545.170 243.820 545.490 243.880 ; + RECT 551.610 243.820 551.930 243.880 ; + RECT 551.610 162.080 551.930 162.140 ; + RECT 848.770 162.080 849.090 162.140 ; + RECT 551.610 161.940 849.090 162.080 ; + RECT 551.610 161.880 551.930 161.940 ; + RECT 848.770 161.880 849.090 161.940 ; + LAYER via ; + RECT 545.200 243.820 545.460 244.080 ; + RECT 551.640 243.820 551.900 244.080 ; + RECT 551.640 161.880 551.900 162.140 ; + RECT 848.800 161.880 849.060 162.140 ; + LAYER met2 ; + RECT 545.150 260.000 545.430 264.000 ; + RECT 545.260 244.110 545.400 260.000 ; + RECT 545.200 243.790 545.460 244.110 ; + RECT 551.640 243.790 551.900 244.110 ; + RECT 551.700 162.170 551.840 243.790 ; + RECT 551.640 161.850 551.900 162.170 ; + RECT 848.800 161.850 849.060 162.170 ; + RECT 848.860 17.410 849.000 161.850 ; + RECT 848.860 17.270 853.140 17.410 ; + RECT 853.000 2.400 853.140 17.270 ; + RECT 852.790 -4.800 853.350 2.400 ; +======= LAYER met2 ; RECT 852.790 -4.800 853.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[12] PIN la_data_out[13] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 563.110 231.440 563.430 231.500 ; + RECT 869.470 231.440 869.790 231.500 ; + RECT 563.110 231.300 869.790 231.440 ; + RECT 563.110 231.240 563.430 231.300 ; + RECT 869.470 231.240 869.790 231.300 ; + LAYER via ; + RECT 563.140 231.240 563.400 231.500 ; + RECT 869.500 231.240 869.760 231.500 ; + LAYER met2 ; + RECT 563.090 260.000 563.370 264.000 ; + RECT 563.200 231.530 563.340 260.000 ; + RECT 563.140 231.210 563.400 231.530 ; + RECT 869.500 231.210 869.760 231.530 ; + RECT 869.560 16.730 869.700 231.210 ; + RECT 869.560 16.590 871.080 16.730 ; + RECT 870.940 2.400 871.080 16.590 ; + RECT 870.730 -4.800 871.290 2.400 ; +======= LAYER met2 ; RECT 870.730 -4.800 871.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[13] PIN la_data_out[14] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 580.590 244.020 580.910 244.080 ; + RECT 586.110 244.020 586.430 244.080 ; + RECT 580.590 243.880 586.430 244.020 ; + RECT 580.590 243.820 580.910 243.880 ; + RECT 586.110 243.820 586.430 243.880 ; + RECT 586.110 168.880 586.430 168.940 ; + RECT 883.270 168.880 883.590 168.940 ; + RECT 586.110 168.740 883.590 168.880 ; + RECT 586.110 168.680 586.430 168.740 ; + RECT 883.270 168.680 883.590 168.740 ; + LAYER via ; + RECT 580.620 243.820 580.880 244.080 ; + RECT 586.140 243.820 586.400 244.080 ; + RECT 586.140 168.680 586.400 168.940 ; + RECT 883.300 168.680 883.560 168.940 ; + LAYER met2 ; + RECT 580.570 260.000 580.850 264.000 ; + RECT 580.680 244.110 580.820 260.000 ; + RECT 580.620 243.790 580.880 244.110 ; + RECT 586.140 243.790 586.400 244.110 ; + RECT 586.200 168.970 586.340 243.790 ; + RECT 586.140 168.650 586.400 168.970 ; + RECT 883.300 168.650 883.560 168.970 ; + RECT 883.360 16.730 883.500 168.650 ; + RECT 883.360 16.590 889.020 16.730 ; + RECT 888.880 2.400 889.020 16.590 ; + RECT 888.670 -4.800 889.230 2.400 ; +======= LAYER met2 ; RECT 888.670 -4.800 889.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[14] PIN la_data_out[15] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 599.910 176.020 600.230 176.080 ; + RECT 903.970 176.020 904.290 176.080 ; + RECT 599.910 175.880 904.290 176.020 ; + RECT 599.910 175.820 600.230 175.880 ; + RECT 903.970 175.820 904.290 175.880 ; + LAYER via ; + RECT 599.940 175.820 600.200 176.080 ; + RECT 904.000 175.820 904.260 176.080 ; + LAYER met2 ; + RECT 598.510 260.170 598.790 264.000 ; + RECT 598.510 260.030 600.140 260.170 ; + RECT 598.510 260.000 598.790 260.030 ; + RECT 600.000 176.110 600.140 260.030 ; + RECT 599.940 175.790 600.200 176.110 ; + RECT 904.000 175.790 904.260 176.110 ; + RECT 904.060 16.730 904.200 175.790 ; + RECT 904.060 16.590 906.960 16.730 ; + RECT 906.820 2.400 906.960 16.590 ; + RECT 906.610 -4.800 907.170 2.400 ; +======= LAYER met2 ; RECT 906.610 -4.800 907.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[15] PIN la_data_out[16] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 616.470 244.020 616.790 244.080 ; + RECT 620.610 244.020 620.930 244.080 ; + RECT 616.470 243.880 620.930 244.020 ; + RECT 616.470 243.820 616.790 243.880 ; + RECT 620.610 243.820 620.930 243.880 ; + RECT 620.610 182.820 620.930 182.880 ; + RECT 917.770 182.820 918.090 182.880 ; + RECT 620.610 182.680 918.090 182.820 ; + RECT 620.610 182.620 620.930 182.680 ; + RECT 917.770 182.620 918.090 182.680 ; + RECT 917.770 17.920 918.090 17.980 ; + RECT 924.210 17.920 924.530 17.980 ; + RECT 917.770 17.780 924.530 17.920 ; + RECT 917.770 17.720 918.090 17.780 ; + RECT 924.210 17.720 924.530 17.780 ; + LAYER via ; + RECT 616.500 243.820 616.760 244.080 ; + RECT 620.640 243.820 620.900 244.080 ; + RECT 620.640 182.620 620.900 182.880 ; + RECT 917.800 182.620 918.060 182.880 ; + RECT 917.800 17.720 918.060 17.980 ; + RECT 924.240 17.720 924.500 17.980 ; + LAYER met2 ; + RECT 616.450 260.000 616.730 264.000 ; + RECT 616.560 244.110 616.700 260.000 ; + RECT 616.500 243.790 616.760 244.110 ; + RECT 620.640 243.790 620.900 244.110 ; + RECT 620.700 182.910 620.840 243.790 ; + RECT 620.640 182.590 620.900 182.910 ; + RECT 917.800 182.590 918.060 182.910 ; + RECT 917.860 18.010 918.000 182.590 ; + RECT 917.800 17.690 918.060 18.010 ; + RECT 924.240 17.690 924.500 18.010 ; + RECT 924.300 2.400 924.440 17.690 ; + RECT 924.090 -4.800 924.650 2.400 ; +======= LAYER met2 ; RECT 924.090 -4.800 924.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[16] PIN la_data_out[17] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 633.950 196.760 634.270 196.820 ; + RECT 938.470 196.760 938.790 196.820 ; + RECT 633.950 196.620 938.790 196.760 ; + RECT 633.950 196.560 634.270 196.620 ; + RECT 938.470 196.560 938.790 196.620 ; + LAYER via ; + RECT 633.980 196.560 634.240 196.820 ; + RECT 938.500 196.560 938.760 196.820 ; + LAYER met2 ; + RECT 634.390 260.170 634.670 264.000 ; + RECT 634.040 260.030 634.670 260.170 ; + RECT 634.040 196.850 634.180 260.030 ; + RECT 634.390 260.000 634.670 260.030 ; + RECT 633.980 196.530 634.240 196.850 ; + RECT 938.500 196.530 938.760 196.850 ; + RECT 938.560 16.730 938.700 196.530 ; + RECT 938.560 16.590 942.380 16.730 ; + RECT 942.240 2.400 942.380 16.590 ; + RECT 942.030 -4.800 942.590 2.400 ; +======= LAYER met2 ; RECT 942.030 -4.800 942.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[17] PIN la_data_out[18] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 655.110 224.300 655.430 224.360 ; + RECT 959.170 224.300 959.490 224.360 ; + RECT 655.110 224.160 959.490 224.300 ; + RECT 655.110 224.100 655.430 224.160 ; + RECT 959.170 224.100 959.490 224.160 ; + LAYER via ; + RECT 655.140 224.100 655.400 224.360 ; + RECT 959.200 224.100 959.460 224.360 ; + LAYER met2 ; + RECT 652.330 260.170 652.610 264.000 ; + RECT 652.330 260.030 655.340 260.170 ; + RECT 652.330 260.000 652.610 260.030 ; + RECT 655.200 224.390 655.340 260.030 ; + RECT 655.140 224.070 655.400 224.390 ; + RECT 959.200 224.070 959.460 224.390 ; + RECT 959.260 16.730 959.400 224.070 ; + RECT 959.260 16.590 960.320 16.730 ; + RECT 960.180 2.400 960.320 16.590 ; + RECT 959.970 -4.800 960.530 2.400 ; +======= LAYER met2 ; RECT 959.970 -4.800 960.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[18] PIN la_data_out[19] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 670.290 244.020 670.610 244.080 ; + RECT 675.810 244.020 676.130 244.080 ; + RECT 670.290 243.880 676.130 244.020 ; + RECT 670.290 243.820 670.610 243.880 ; + RECT 675.810 243.820 676.130 243.880 ; + RECT 675.810 189.620 676.130 189.680 ; + RECT 972.970 189.620 973.290 189.680 ; + RECT 675.810 189.480 973.290 189.620 ; + RECT 675.810 189.420 676.130 189.480 ; + RECT 972.970 189.420 973.290 189.480 ; + LAYER via ; + RECT 670.320 243.820 670.580 244.080 ; + RECT 675.840 243.820 676.100 244.080 ; + RECT 675.840 189.420 676.100 189.680 ; + RECT 973.000 189.420 973.260 189.680 ; + LAYER met2 ; + RECT 670.270 260.000 670.550 264.000 ; + RECT 670.380 244.110 670.520 260.000 ; + RECT 670.320 243.790 670.580 244.110 ; + RECT 675.840 243.790 676.100 244.110 ; + RECT 675.900 189.710 676.040 243.790 ; + RECT 675.840 189.390 676.100 189.710 ; + RECT 973.000 189.390 973.260 189.710 ; + RECT 973.060 16.730 973.200 189.390 ; + RECT 973.060 16.590 978.260 16.730 ; + RECT 978.120 2.400 978.260 16.590 ; + RECT 977.910 -4.800 978.470 2.400 ; +======= LAYER met2 ; RECT 977.910 -4.800 978.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[19] PIN la_data_out[1] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 351.510 189.620 351.830 189.680 ; + RECT 655.570 189.620 655.890 189.680 ; + RECT 351.510 189.480 655.890 189.620 ; + RECT 351.510 189.420 351.830 189.480 ; + RECT 655.570 189.420 655.890 189.480 ; + LAYER via ; + RECT 351.540 189.420 351.800 189.680 ; + RECT 655.600 189.420 655.860 189.680 ; + LAYER met2 ; + RECT 348.270 260.170 348.550 264.000 ; + RECT 348.270 260.030 351.740 260.170 ; + RECT 348.270 260.000 348.550 260.030 ; + RECT 351.600 189.710 351.740 260.030 ; + RECT 351.540 189.390 351.800 189.710 ; + RECT 655.600 189.390 655.860 189.710 ; + RECT 655.660 17.410 655.800 189.390 ; + RECT 655.660 17.270 657.180 17.410 ; + RECT 657.040 2.400 657.180 17.270 ; + RECT 656.830 -4.800 657.390 2.400 ; +======= LAYER met2 ; RECT 656.830 -4.800 657.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[1] PIN la_data_out[20] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 689.610 37.980 689.930 38.040 ; + RECT 995.970 37.980 996.290 38.040 ; + RECT 689.610 37.840 996.290 37.980 ; + RECT 689.610 37.780 689.930 37.840 ; + RECT 995.970 37.780 996.290 37.840 ; + LAYER via ; + RECT 689.640 37.780 689.900 38.040 ; + RECT 996.000 37.780 996.260 38.040 ; + LAYER met2 ; + RECT 688.210 260.170 688.490 264.000 ; + RECT 688.210 260.030 689.840 260.170 ; + RECT 688.210 260.000 688.490 260.030 ; + RECT 689.700 38.070 689.840 260.030 ; + RECT 689.640 37.750 689.900 38.070 ; + RECT 996.000 37.750 996.260 38.070 ; + RECT 996.060 2.400 996.200 37.750 ; + RECT 995.850 -4.800 996.410 2.400 ; +======= LAYER met2 ; RECT 995.850 -4.800 996.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[20] PIN la_data_out[21] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 705.710 244.020 706.030 244.080 ; + RECT 710.310 244.020 710.630 244.080 ; + RECT 705.710 243.880 710.630 244.020 ; + RECT 705.710 243.820 706.030 243.880 ; + RECT 710.310 243.820 710.630 243.880 ; + RECT 710.310 203.900 710.630 203.960 ; + RECT 1007.470 203.900 1007.790 203.960 ; + RECT 710.310 203.760 1007.790 203.900 ; + RECT 710.310 203.700 710.630 203.760 ; + RECT 1007.470 203.700 1007.790 203.760 ; + RECT 1007.470 17.920 1007.790 17.980 ; + RECT 1013.450 17.920 1013.770 17.980 ; + RECT 1007.470 17.780 1013.770 17.920 ; + RECT 1007.470 17.720 1007.790 17.780 ; + RECT 1013.450 17.720 1013.770 17.780 ; + LAYER via ; + RECT 705.740 243.820 706.000 244.080 ; + RECT 710.340 243.820 710.600 244.080 ; + RECT 710.340 203.700 710.600 203.960 ; + RECT 1007.500 203.700 1007.760 203.960 ; + RECT 1007.500 17.720 1007.760 17.980 ; + RECT 1013.480 17.720 1013.740 17.980 ; + LAYER met2 ; + RECT 705.690 260.000 705.970 264.000 ; + RECT 705.800 244.110 705.940 260.000 ; + RECT 705.740 243.790 706.000 244.110 ; + RECT 710.340 243.790 710.600 244.110 ; + RECT 710.400 203.990 710.540 243.790 ; + RECT 710.340 203.670 710.600 203.990 ; + RECT 1007.500 203.670 1007.760 203.990 ; + RECT 1007.560 18.010 1007.700 203.670 ; + RECT 1007.500 17.690 1007.760 18.010 ; + RECT 1013.480 17.690 1013.740 18.010 ; + RECT 1013.540 2.400 1013.680 17.690 ; + RECT 1013.330 -4.800 1013.890 2.400 ; +======= LAYER met2 ; RECT 1013.330 -4.800 1013.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[21] PIN la_data_out[22] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 723.650 210.360 723.970 210.420 ; + RECT 1028.170 210.360 1028.490 210.420 ; + RECT 723.650 210.220 1028.490 210.360 ; + RECT 723.650 210.160 723.970 210.220 ; + RECT 1028.170 210.160 1028.490 210.220 ; + LAYER via ; + RECT 723.680 210.160 723.940 210.420 ; + RECT 1028.200 210.160 1028.460 210.420 ; + LAYER met2 ; + RECT 723.630 260.000 723.910 264.000 ; + RECT 723.740 210.450 723.880 260.000 ; + RECT 723.680 210.130 723.940 210.450 ; + RECT 1028.200 210.130 1028.460 210.450 ; + RECT 1028.260 16.730 1028.400 210.130 ; + RECT 1028.260 16.590 1031.620 16.730 ; + RECT 1031.480 2.400 1031.620 16.590 ; + RECT 1031.270 -4.800 1031.830 2.400 ; +======= LAYER met2 ; RECT 1031.270 -4.800 1031.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[22] PIN la_data_out[23] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 744.810 217.160 745.130 217.220 ; + RECT 1049.330 217.160 1049.650 217.220 ; + RECT 744.810 217.020 1049.650 217.160 ; + RECT 744.810 216.960 745.130 217.020 ; + RECT 1049.330 216.960 1049.650 217.020 ; + LAYER via ; + RECT 744.840 216.960 745.100 217.220 ; + RECT 1049.360 216.960 1049.620 217.220 ; + LAYER met2 ; + RECT 741.570 260.170 741.850 264.000 ; + RECT 741.570 260.030 745.040 260.170 ; + RECT 741.570 260.000 741.850 260.030 ; + RECT 744.900 217.250 745.040 260.030 ; + RECT 744.840 216.930 745.100 217.250 ; + RECT 1049.360 216.930 1049.620 217.250 ; + RECT 1049.420 2.400 1049.560 216.930 ; + RECT 1049.210 -4.800 1049.770 2.400 ; +======= LAYER met2 ; RECT 1049.210 -4.800 1049.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[23] PIN la_data_out[24] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 759.530 244.020 759.850 244.080 ; + RECT 765.050 244.020 765.370 244.080 ; + RECT 759.530 243.880 765.370 244.020 ; + RECT 759.530 243.820 759.850 243.880 ; + RECT 765.050 243.820 765.370 243.880 ; + RECT 765.050 148.480 765.370 148.540 ; + RECT 1062.670 148.480 1062.990 148.540 ; + RECT 765.050 148.340 1062.990 148.480 ; + RECT 765.050 148.280 765.370 148.340 ; + RECT 1062.670 148.280 1062.990 148.340 ; + LAYER via ; + RECT 759.560 243.820 759.820 244.080 ; + RECT 765.080 243.820 765.340 244.080 ; + RECT 765.080 148.280 765.340 148.540 ; + RECT 1062.700 148.280 1062.960 148.540 ; + LAYER met2 ; + RECT 759.510 260.000 759.790 264.000 ; + RECT 759.620 244.110 759.760 260.000 ; + RECT 759.560 243.790 759.820 244.110 ; + RECT 765.080 243.790 765.340 244.110 ; + RECT 765.140 148.570 765.280 243.790 ; + RECT 765.080 148.250 765.340 148.570 ; + RECT 1062.700 148.250 1062.960 148.570 ; + RECT 1062.760 16.730 1062.900 148.250 ; + RECT 1062.760 16.590 1067.500 16.730 ; + RECT 1067.360 2.400 1067.500 16.590 ; + RECT 1067.150 -4.800 1067.710 2.400 ; +======= LAYER met2 ; RECT 1067.150 -4.800 1067.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[24] PIN la_data_out[25] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 779.310 155.620 779.630 155.680 ; + RECT 1083.370 155.620 1083.690 155.680 ; + RECT 779.310 155.480 1083.690 155.620 ; + RECT 779.310 155.420 779.630 155.480 ; + RECT 1083.370 155.420 1083.690 155.480 ; + LAYER via ; + RECT 779.340 155.420 779.600 155.680 ; + RECT 1083.400 155.420 1083.660 155.680 ; + LAYER met2 ; + RECT 777.450 260.170 777.730 264.000 ; + RECT 777.450 260.030 779.540 260.170 ; + RECT 777.450 260.000 777.730 260.030 ; + RECT 779.400 155.710 779.540 260.030 ; + RECT 779.340 155.390 779.600 155.710 ; + RECT 1083.400 155.390 1083.660 155.710 ; + RECT 1083.460 16.730 1083.600 155.390 ; + RECT 1083.460 16.590 1085.440 16.730 ; + RECT 1085.300 2.400 1085.440 16.590 ; + RECT 1085.090 -4.800 1085.650 2.400 ; +======= LAYER met2 ; RECT 1085.090 -4.800 1085.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[25] PIN la_data_out[26] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 795.410 244.020 795.730 244.080 ; + RECT 800.010 244.020 800.330 244.080 ; + RECT 795.410 243.880 800.330 244.020 ; + RECT 795.410 243.820 795.730 243.880 ; + RECT 800.010 243.820 800.330 243.880 ; + RECT 800.010 162.420 800.330 162.480 ; + RECT 1097.170 162.420 1097.490 162.480 ; + RECT 800.010 162.280 1097.490 162.420 ; + RECT 800.010 162.220 800.330 162.280 ; + RECT 1097.170 162.220 1097.490 162.280 ; + LAYER via ; + RECT 795.440 243.820 795.700 244.080 ; + RECT 800.040 243.820 800.300 244.080 ; + RECT 800.040 162.220 800.300 162.480 ; + RECT 1097.200 162.220 1097.460 162.480 ; + LAYER met2 ; + RECT 795.390 260.000 795.670 264.000 ; + RECT 795.500 244.110 795.640 260.000 ; + RECT 795.440 243.790 795.700 244.110 ; + RECT 800.040 243.790 800.300 244.110 ; + RECT 800.100 162.510 800.240 243.790 ; + RECT 800.040 162.190 800.300 162.510 ; + RECT 1097.200 162.190 1097.460 162.510 ; + RECT 1097.260 16.730 1097.400 162.190 ; + RECT 1097.260 16.590 1102.920 16.730 ; + RECT 1102.780 2.400 1102.920 16.590 ; + RECT 1102.570 -4.800 1103.130 2.400 ; +======= LAYER met2 ; RECT 1102.570 -4.800 1103.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[26] PIN la_data_out[27] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 813.350 231.100 813.670 231.160 ; + RECT 1117.870 231.100 1118.190 231.160 ; + RECT 813.350 230.960 1118.190 231.100 ; + RECT 813.350 230.900 813.670 230.960 ; + RECT 1117.870 230.900 1118.190 230.960 ; + LAYER via ; + RECT 813.380 230.900 813.640 231.160 ; + RECT 1117.900 230.900 1118.160 231.160 ; + LAYER met2 ; + RECT 813.330 260.000 813.610 264.000 ; + RECT 813.440 231.190 813.580 260.000 ; + RECT 813.380 230.870 813.640 231.190 ; + RECT 1117.900 230.870 1118.160 231.190 ; + RECT 1117.960 16.730 1118.100 230.870 ; + RECT 1117.960 16.590 1120.860 16.730 ; + RECT 1120.720 2.400 1120.860 16.590 ; + RECT 1120.510 -4.800 1121.070 2.400 ; +======= LAYER met2 ; RECT 1120.510 -4.800 1121.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[27] PIN la_data_out[28] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 830.830 242.660 831.150 242.720 ; + RECT 838.190 242.660 838.510 242.720 ; + RECT 830.830 242.520 838.510 242.660 ; + RECT 830.830 242.460 831.150 242.520 ; + RECT 838.190 242.460 838.510 242.520 ; + RECT 838.190 169.220 838.510 169.280 ; + RECT 1139.030 169.220 1139.350 169.280 ; + RECT 838.190 169.080 1139.350 169.220 ; + RECT 838.190 169.020 838.510 169.080 ; + RECT 1139.030 169.020 1139.350 169.080 ; + LAYER via ; + RECT 830.860 242.460 831.120 242.720 ; + RECT 838.220 242.460 838.480 242.720 ; + RECT 838.220 169.020 838.480 169.280 ; + RECT 1139.060 169.020 1139.320 169.280 ; + LAYER met2 ; + RECT 830.810 260.000 831.090 264.000 ; + RECT 830.920 242.750 831.060 260.000 ; + RECT 830.860 242.430 831.120 242.750 ; + RECT 838.220 242.430 838.480 242.750 ; + RECT 838.280 169.310 838.420 242.430 ; + RECT 838.220 168.990 838.480 169.310 ; + RECT 1139.060 168.990 1139.320 169.310 ; + RECT 1139.120 17.410 1139.260 168.990 ; + RECT 1138.660 17.270 1139.260 17.410 ; + RECT 1138.660 2.400 1138.800 17.270 ; + RECT 1138.450 -4.800 1139.010 2.400 ; +======= LAYER met2 ; RECT 1138.450 -4.800 1139.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[28] PIN la_data_out[29] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 848.770 244.020 849.090 244.080 ; + RECT 854.750 244.020 855.070 244.080 ; + RECT 848.770 243.880 855.070 244.020 ; + RECT 848.770 243.820 849.090 243.880 ; + RECT 854.750 243.820 855.070 243.880 ; + RECT 854.750 176.360 855.070 176.420 ; + RECT 1152.370 176.360 1152.690 176.420 ; + RECT 854.750 176.220 1152.690 176.360 ; + RECT 854.750 176.160 855.070 176.220 ; + RECT 1152.370 176.160 1152.690 176.220 ; + LAYER via ; + RECT 848.800 243.820 849.060 244.080 ; + RECT 854.780 243.820 855.040 244.080 ; + RECT 854.780 176.160 855.040 176.420 ; + RECT 1152.400 176.160 1152.660 176.420 ; + LAYER met2 ; + RECT 848.750 260.000 849.030 264.000 ; + RECT 848.860 244.110 849.000 260.000 ; + RECT 848.800 243.790 849.060 244.110 ; + RECT 854.780 243.790 855.040 244.110 ; + RECT 854.840 176.450 854.980 243.790 ; + RECT 854.780 176.130 855.040 176.450 ; + RECT 1152.400 176.130 1152.660 176.450 ; + RECT 1152.460 17.410 1152.600 176.130 ; + RECT 1152.460 17.270 1156.740 17.410 ; + RECT 1156.600 2.400 1156.740 17.270 ; + RECT 1156.390 -4.800 1156.950 2.400 ; +======= LAYER met2 ; RECT 1156.390 -4.800 1156.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[29] PIN la_data_out[2] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 366.230 244.020 366.550 244.080 ; + RECT 372.210 244.020 372.530 244.080 ; + RECT 366.230 243.880 372.530 244.020 ; + RECT 366.230 243.820 366.550 243.880 ; + RECT 372.210 243.820 372.530 243.880 ; + RECT 372.210 203.560 372.530 203.620 ; + RECT 669.370 203.560 669.690 203.620 ; + RECT 372.210 203.420 669.690 203.560 ; + RECT 372.210 203.360 372.530 203.420 ; + RECT 669.370 203.360 669.690 203.420 ; + LAYER via ; + RECT 366.260 243.820 366.520 244.080 ; + RECT 372.240 243.820 372.500 244.080 ; + RECT 372.240 203.360 372.500 203.620 ; + RECT 669.400 203.360 669.660 203.620 ; + LAYER met2 ; + RECT 366.210 260.000 366.490 264.000 ; + RECT 366.320 244.110 366.460 260.000 ; + RECT 366.260 243.790 366.520 244.110 ; + RECT 372.240 243.790 372.500 244.110 ; + RECT 372.300 203.650 372.440 243.790 ; + RECT 372.240 203.330 372.500 203.650 ; + RECT 669.400 203.330 669.660 203.650 ; + RECT 669.460 16.730 669.600 203.330 ; + RECT 669.460 16.590 674.660 16.730 ; + RECT 674.520 2.400 674.660 16.590 ; + RECT 674.310 -4.800 674.870 2.400 ; +======= LAYER met2 ; RECT 674.310 -4.800 674.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[2] PIN la_data_out[30] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 869.010 24.380 869.330 24.440 ; + RECT 1173.990 24.380 1174.310 24.440 ; + RECT 869.010 24.240 1174.310 24.380 ; + RECT 869.010 24.180 869.330 24.240 ; + RECT 1173.990 24.180 1174.310 24.240 ; + LAYER via ; + RECT 869.040 24.180 869.300 24.440 ; + RECT 1174.020 24.180 1174.280 24.440 ; + LAYER met2 ; + RECT 866.690 260.170 866.970 264.000 ; + RECT 866.690 260.030 869.240 260.170 ; + RECT 866.690 260.000 866.970 260.030 ; + RECT 869.100 24.470 869.240 260.030 ; + RECT 869.040 24.150 869.300 24.470 ; + RECT 1174.020 24.150 1174.280 24.470 ; + RECT 1174.080 2.400 1174.220 24.150 ; + RECT 1173.870 -4.800 1174.430 2.400 ; +======= LAYER met2 ; RECT 1173.870 -4.800 1174.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[30] PIN la_data_out[31] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 884.650 244.020 884.970 244.080 ; + RECT 889.710 244.020 890.030 244.080 ; + RECT 884.650 243.880 890.030 244.020 ; + RECT 884.650 243.820 884.970 243.880 ; + RECT 889.710 243.820 890.030 243.880 ; + RECT 889.710 183.500 890.030 183.560 ; + RECT 1186.870 183.500 1187.190 183.560 ; + RECT 889.710 183.360 1187.190 183.500 ; + RECT 889.710 183.300 890.030 183.360 ; + RECT 1186.870 183.300 1187.190 183.360 ; + LAYER via ; + RECT 884.680 243.820 884.940 244.080 ; + RECT 889.740 243.820 890.000 244.080 ; + RECT 889.740 183.300 890.000 183.560 ; + RECT 1186.900 183.300 1187.160 183.560 ; + LAYER met2 ; + RECT 884.630 260.000 884.910 264.000 ; + RECT 884.740 244.110 884.880 260.000 ; + RECT 884.680 243.790 884.940 244.110 ; + RECT 889.740 243.790 890.000 244.110 ; + RECT 889.800 183.590 889.940 243.790 ; + RECT 889.740 183.270 890.000 183.590 ; + RECT 1186.900 183.270 1187.160 183.590 ; + RECT 1186.960 17.410 1187.100 183.270 ; + RECT 1186.960 17.270 1192.160 17.410 ; + RECT 1192.020 2.400 1192.160 17.270 ; + RECT 1191.810 -4.800 1192.370 2.400 ; +======= LAYER met2 ; RECT 1191.810 -4.800 1192.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[31] PIN la_data_out[32] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 903.510 197.100 903.830 197.160 ; + RECT 1207.570 197.100 1207.890 197.160 ; + RECT 903.510 196.960 1207.890 197.100 ; + RECT 903.510 196.900 903.830 196.960 ; + RECT 1207.570 196.900 1207.890 196.960 ; + LAYER via ; + RECT 903.540 196.900 903.800 197.160 ; + RECT 1207.600 196.900 1207.860 197.160 ; + LAYER met2 ; + RECT 902.570 260.170 902.850 264.000 ; + RECT 902.570 260.030 903.740 260.170 ; + RECT 902.570 260.000 902.850 260.030 ; + RECT 903.600 197.190 903.740 260.030 ; + RECT 903.540 196.870 903.800 197.190 ; + RECT 1207.600 196.870 1207.860 197.190 ; + RECT 1207.660 16.730 1207.800 196.870 ; + RECT 1207.660 16.590 1210.100 16.730 ; + RECT 1209.960 2.400 1210.100 16.590 ; + RECT 1209.750 -4.800 1210.310 2.400 ; +======= LAYER met2 ; RECT 1209.750 -4.800 1210.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[32] PIN la_data_out[33] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 924.210 224.980 924.530 225.040 ; + RECT 1221.370 224.980 1221.690 225.040 ; + RECT 924.210 224.840 1221.690 224.980 ; + RECT 924.210 224.780 924.530 224.840 ; + RECT 1221.370 224.780 1221.690 224.840 ; + RECT 1221.370 17.580 1221.690 17.640 ; + RECT 1227.810 17.580 1228.130 17.640 ; + RECT 1221.370 17.440 1228.130 17.580 ; + RECT 1221.370 17.380 1221.690 17.440 ; + RECT 1227.810 17.380 1228.130 17.440 ; + LAYER via ; + RECT 924.240 224.780 924.500 225.040 ; + RECT 1221.400 224.780 1221.660 225.040 ; + RECT 1221.400 17.380 1221.660 17.640 ; + RECT 1227.840 17.380 1228.100 17.640 ; + LAYER met2 ; + RECT 920.510 260.170 920.790 264.000 ; + RECT 920.510 260.030 924.440 260.170 ; + RECT 920.510 260.000 920.790 260.030 ; + RECT 924.300 225.070 924.440 260.030 ; + RECT 924.240 224.750 924.500 225.070 ; + RECT 1221.400 224.750 1221.660 225.070 ; + RECT 1221.460 17.670 1221.600 224.750 ; + RECT 1221.400 17.350 1221.660 17.670 ; + RECT 1227.840 17.350 1228.100 17.670 ; + RECT 1227.900 2.400 1228.040 17.350 ; + RECT 1227.690 -4.800 1228.250 2.400 ; +======= LAYER met2 ; RECT 1227.690 -4.800 1228.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[33] PIN la_data_out[34] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 938.470 244.020 938.790 244.080 ; + RECT 944.910 244.020 945.230 244.080 ; + RECT 938.470 243.880 945.230 244.020 ; + RECT 938.470 243.820 938.790 243.880 ; + RECT 944.910 243.820 945.230 243.880 ; + RECT 944.910 189.960 945.230 190.020 ; + RECT 1242.070 189.960 1242.390 190.020 ; + RECT 944.910 189.820 1242.390 189.960 ; + RECT 944.910 189.760 945.230 189.820 ; + RECT 1242.070 189.760 1242.390 189.820 ; + LAYER via ; + RECT 938.500 243.820 938.760 244.080 ; + RECT 944.940 243.820 945.200 244.080 ; + RECT 944.940 189.760 945.200 190.020 ; + RECT 1242.100 189.760 1242.360 190.020 ; + LAYER met2 ; + RECT 938.450 260.000 938.730 264.000 ; + RECT 938.560 244.110 938.700 260.000 ; + RECT 938.500 243.790 938.760 244.110 ; + RECT 944.940 243.790 945.200 244.110 ; + RECT 945.000 190.050 945.140 243.790 ; + RECT 944.940 189.730 945.200 190.050 ; + RECT 1242.100 189.730 1242.360 190.050 ; + RECT 1242.160 16.730 1242.300 189.730 ; + RECT 1242.160 16.590 1245.980 16.730 ; + RECT 1245.840 2.400 1245.980 16.590 ; + RECT 1245.630 -4.800 1246.190 2.400 ; +======= LAYER met2 ; RECT 1245.630 -4.800 1246.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[34] PIN la_data_out[35] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 958.710 148.140 959.030 148.200 ; + RECT 1263.230 148.140 1263.550 148.200 ; + RECT 958.710 148.000 1263.550 148.140 ; + RECT 958.710 147.940 959.030 148.000 ; + RECT 1263.230 147.940 1263.550 148.000 ; + LAYER via ; + RECT 958.740 147.940 959.000 148.200 ; + RECT 1263.260 147.940 1263.520 148.200 ; + LAYER met2 ; + RECT 955.930 260.170 956.210 264.000 ; + RECT 955.930 260.030 958.940 260.170 ; + RECT 955.930 260.000 956.210 260.030 ; + RECT 958.800 148.230 958.940 260.030 ; + RECT 958.740 147.910 959.000 148.230 ; + RECT 1263.260 147.910 1263.520 148.230 ; + RECT 1263.320 2.400 1263.460 147.910 ; + RECT 1263.110 -4.800 1263.670 2.400 ; +======= LAYER met2 ; RECT 1263.110 -4.800 1263.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[35] PIN la_data_out[36] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 973.890 238.240 974.210 238.300 ; + RECT 1276.570 238.240 1276.890 238.300 ; + RECT 973.890 238.100 1276.890 238.240 ; + RECT 973.890 238.040 974.210 238.100 ; + RECT 1276.570 238.040 1276.890 238.100 ; + LAYER via ; + RECT 973.920 238.040 974.180 238.300 ; + RECT 1276.600 238.040 1276.860 238.300 ; + LAYER met2 ; + RECT 973.870 260.000 974.150 264.000 ; + RECT 973.980 238.330 974.120 260.000 ; + RECT 973.920 238.010 974.180 238.330 ; + RECT 1276.600 238.010 1276.860 238.330 ; + RECT 1276.660 16.730 1276.800 238.010 ; + RECT 1276.660 16.590 1281.400 16.730 ; + RECT 1281.260 2.400 1281.400 16.590 ; + RECT 1281.050 -4.800 1281.610 2.400 ; +======= LAYER met2 ; RECT 1281.050 -4.800 1281.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[36] PIN la_data_out[37] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 993.210 203.560 993.530 203.620 ; + RECT 1297.270 203.560 1297.590 203.620 ; + RECT 993.210 203.420 1297.590 203.560 ; + RECT 993.210 203.360 993.530 203.420 ; + RECT 1297.270 203.360 1297.590 203.420 ; + LAYER via ; + RECT 993.240 203.360 993.500 203.620 ; + RECT 1297.300 203.360 1297.560 203.620 ; + LAYER met2 ; + RECT 991.810 260.170 992.090 264.000 ; + RECT 991.810 260.030 993.440 260.170 ; + RECT 991.810 260.000 992.090 260.030 ; + RECT 993.300 203.650 993.440 260.030 ; + RECT 993.240 203.330 993.500 203.650 ; + RECT 1297.300 203.330 1297.560 203.650 ; + RECT 1297.360 17.410 1297.500 203.330 ; + RECT 1297.360 17.270 1299.340 17.410 ; + RECT 1299.200 2.400 1299.340 17.270 ; + RECT 1298.990 -4.800 1299.550 2.400 ; +======= LAYER met2 ; RECT 1298.990 -4.800 1299.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[37] PIN la_data_out[38] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1009.770 244.020 1010.090 244.080 ; + RECT 1013.910 244.020 1014.230 244.080 ; + RECT 1009.770 243.880 1014.230 244.020 ; + RECT 1009.770 243.820 1010.090 243.880 ; + RECT 1013.910 243.820 1014.230 243.880 ; + RECT 1013.910 210.700 1014.230 210.760 ; + RECT 1311.070 210.700 1311.390 210.760 ; + RECT 1013.910 210.560 1311.390 210.700 ; + RECT 1013.910 210.500 1014.230 210.560 ; + RECT 1311.070 210.500 1311.390 210.560 ; + RECT 1311.070 19.620 1311.390 19.680 ; + RECT 1317.050 19.620 1317.370 19.680 ; + RECT 1311.070 19.480 1317.370 19.620 ; + RECT 1311.070 19.420 1311.390 19.480 ; + RECT 1317.050 19.420 1317.370 19.480 ; + LAYER via ; + RECT 1009.800 243.820 1010.060 244.080 ; + RECT 1013.940 243.820 1014.200 244.080 ; + RECT 1013.940 210.500 1014.200 210.760 ; + RECT 1311.100 210.500 1311.360 210.760 ; + RECT 1311.100 19.420 1311.360 19.680 ; + RECT 1317.080 19.420 1317.340 19.680 ; + LAYER met2 ; + RECT 1009.750 260.000 1010.030 264.000 ; + RECT 1009.860 244.110 1010.000 260.000 ; + RECT 1009.800 243.790 1010.060 244.110 ; + RECT 1013.940 243.790 1014.200 244.110 ; + RECT 1014.000 210.790 1014.140 243.790 ; + RECT 1013.940 210.470 1014.200 210.790 ; + RECT 1311.100 210.470 1311.360 210.790 ; + RECT 1311.160 19.710 1311.300 210.470 ; + RECT 1311.100 19.390 1311.360 19.710 ; + RECT 1317.080 19.390 1317.340 19.710 ; + RECT 1317.140 2.400 1317.280 19.390 ; + RECT 1316.930 -4.800 1317.490 2.400 ; +======= LAYER met2 ; RECT 1316.930 -4.800 1317.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[38] PIN la_data_out[39] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1027.250 155.280 1027.570 155.340 ; + RECT 1331.770 155.280 1332.090 155.340 ; + RECT 1027.250 155.140 1332.090 155.280 ; + RECT 1027.250 155.080 1027.570 155.140 ; + RECT 1331.770 155.080 1332.090 155.140 ; + LAYER via ; + RECT 1027.280 155.080 1027.540 155.340 ; + RECT 1331.800 155.080 1332.060 155.340 ; + LAYER met2 ; + RECT 1027.690 260.170 1027.970 264.000 ; + RECT 1027.340 260.030 1027.970 260.170 ; + RECT 1027.340 155.370 1027.480 260.030 ; + RECT 1027.690 260.000 1027.970 260.030 ; + RECT 1027.280 155.050 1027.540 155.370 ; + RECT 1331.800 155.050 1332.060 155.370 ; + RECT 1331.860 17.410 1332.000 155.050 ; + RECT 1331.860 17.270 1335.220 17.410 ; + RECT 1335.080 2.400 1335.220 17.270 ; + RECT 1334.870 -4.800 1335.430 2.400 ; +======= LAYER met2 ; RECT 1334.870 -4.800 1335.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[39] PIN la_data_out[3] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 384.170 238.240 384.490 238.300 ; + RECT 690.070 238.240 690.390 238.300 ; + RECT 384.170 238.100 690.390 238.240 ; + RECT 384.170 238.040 384.490 238.100 ; + RECT 690.070 238.040 690.390 238.100 ; + LAYER via ; + RECT 384.200 238.040 384.460 238.300 ; + RECT 690.100 238.040 690.360 238.300 ; + LAYER met2 ; + RECT 384.150 260.000 384.430 264.000 ; + RECT 384.260 238.330 384.400 260.000 ; + RECT 384.200 238.010 384.460 238.330 ; + RECT 690.100 238.010 690.360 238.330 ; + RECT 690.160 16.730 690.300 238.010 ; + RECT 690.160 16.590 692.600 16.730 ; + RECT 692.460 2.400 692.600 16.590 ; + RECT 692.250 -4.800 692.810 2.400 ; +======= LAYER met2 ; RECT 692.250 -4.800 692.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[3] PIN la_data_out[40] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1048.410 30.840 1048.730 30.900 ; + RECT 1352.930 30.840 1353.250 30.900 ; + RECT 1048.410 30.700 1353.250 30.840 ; + RECT 1048.410 30.640 1048.730 30.700 ; + RECT 1352.930 30.640 1353.250 30.700 ; + LAYER via ; + RECT 1048.440 30.640 1048.700 30.900 ; + RECT 1352.960 30.640 1353.220 30.900 ; + LAYER met2 ; + RECT 1045.630 260.170 1045.910 264.000 ; + RECT 1045.630 260.030 1048.640 260.170 ; + RECT 1045.630 260.000 1045.910 260.030 ; + RECT 1048.500 30.930 1048.640 260.030 ; + RECT 1048.440 30.610 1048.700 30.930 ; + RECT 1352.960 30.610 1353.220 30.930 ; + RECT 1353.020 16.050 1353.160 30.610 ; + RECT 1352.560 15.910 1353.160 16.050 ; + RECT 1352.560 2.400 1352.700 15.910 ; + RECT 1352.350 -4.800 1352.910 2.400 ; +======= LAYER met2 ; RECT 1352.350 -4.800 1352.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[40] PIN la_data_out[41] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1063.590 244.020 1063.910 244.080 ; + RECT 1069.110 244.020 1069.430 244.080 ; + RECT 1063.590 243.880 1069.430 244.020 ; + RECT 1063.590 243.820 1063.910 243.880 ; + RECT 1069.110 243.820 1069.430 243.880 ; + RECT 1069.110 217.160 1069.430 217.220 ; + RECT 1366.270 217.160 1366.590 217.220 ; + RECT 1069.110 217.020 1366.590 217.160 ; + RECT 1069.110 216.960 1069.430 217.020 ; + RECT 1366.270 216.960 1366.590 217.020 ; + LAYER via ; + RECT 1063.620 243.820 1063.880 244.080 ; + RECT 1069.140 243.820 1069.400 244.080 ; + RECT 1069.140 216.960 1069.400 217.220 ; + RECT 1366.300 216.960 1366.560 217.220 ; + LAYER met2 ; + RECT 1063.570 260.000 1063.850 264.000 ; + RECT 1063.680 244.110 1063.820 260.000 ; + RECT 1063.620 243.790 1063.880 244.110 ; + RECT 1069.140 243.790 1069.400 244.110 ; + RECT 1069.200 217.250 1069.340 243.790 ; + RECT 1069.140 216.930 1069.400 217.250 ; + RECT 1366.300 216.930 1366.560 217.250 ; + RECT 1366.360 17.410 1366.500 216.930 ; + RECT 1366.360 17.270 1370.640 17.410 ; + RECT 1370.500 2.400 1370.640 17.270 ; + RECT 1370.290 -4.800 1370.850 2.400 ; +======= LAYER met2 ; RECT 1370.290 -4.800 1370.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[41] PIN la_data_out[42] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1082.910 162.080 1083.230 162.140 ; + RECT 1386.970 162.080 1387.290 162.140 ; + RECT 1082.910 161.940 1387.290 162.080 ; + RECT 1082.910 161.880 1083.230 161.940 ; + RECT 1386.970 161.880 1387.290 161.940 ; + LAYER via ; + RECT 1082.940 161.880 1083.200 162.140 ; + RECT 1387.000 161.880 1387.260 162.140 ; + LAYER met2 ; + RECT 1081.050 260.170 1081.330 264.000 ; + RECT 1081.050 260.030 1083.140 260.170 ; + RECT 1081.050 260.000 1081.330 260.030 ; + RECT 1083.000 162.170 1083.140 260.030 ; + RECT 1082.940 161.850 1083.200 162.170 ; + RECT 1387.000 161.850 1387.260 162.170 ; + RECT 1387.060 16.900 1387.200 161.850 ; + RECT 1387.060 16.760 1388.580 16.900 ; + RECT 1388.440 2.400 1388.580 16.760 ; + RECT 1388.230 -4.800 1388.790 2.400 ; +======= LAYER met2 ; RECT 1388.230 -4.800 1388.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[42] PIN la_data_out[43] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1099.010 231.780 1099.330 231.840 ; + RECT 1400.770 231.780 1401.090 231.840 ; + RECT 1099.010 231.640 1401.090 231.780 ; + RECT 1099.010 231.580 1099.330 231.640 ; + RECT 1400.770 231.580 1401.090 231.640 ; + LAYER via ; + RECT 1099.040 231.580 1099.300 231.840 ; + RECT 1400.800 231.580 1401.060 231.840 ; + LAYER met2 ; + RECT 1098.990 260.000 1099.270 264.000 ; + RECT 1099.100 231.870 1099.240 260.000 ; + RECT 1099.040 231.550 1099.300 231.870 ; + RECT 1400.800 231.550 1401.060 231.870 ; + RECT 1400.860 16.900 1401.000 231.550 ; + RECT 1400.860 16.760 1406.520 16.900 ; + RECT 1406.380 2.400 1406.520 16.760 ; + RECT 1406.170 -4.800 1406.730 2.400 ; +======= LAYER met2 ; RECT 1406.170 -4.800 1406.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[43] PIN la_data_out[44] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1116.950 168.880 1117.270 168.940 ; + RECT 1421.470 168.880 1421.790 168.940 ; + RECT 1116.950 168.740 1421.790 168.880 ; + RECT 1116.950 168.680 1117.270 168.740 ; + RECT 1421.470 168.680 1421.790 168.740 ; + LAYER via ; + RECT 1116.980 168.680 1117.240 168.940 ; + RECT 1421.500 168.680 1421.760 168.940 ; + LAYER met2 ; + RECT 1116.930 260.000 1117.210 264.000 ; + RECT 1117.040 168.970 1117.180 260.000 ; + RECT 1116.980 168.650 1117.240 168.970 ; + RECT 1421.500 168.650 1421.760 168.970 ; + RECT 1421.560 16.900 1421.700 168.650 ; + RECT 1421.560 16.760 1424.000 16.900 ; + RECT 1423.860 2.400 1424.000 16.760 ; + RECT 1423.650 -4.800 1424.210 2.400 ; +======= LAYER met2 ; RECT 1423.650 -4.800 1424.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[44] PIN la_data_out[45] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1138.110 176.700 1138.430 176.760 ; + RECT 1435.270 176.700 1435.590 176.760 ; + RECT 1138.110 176.560 1435.590 176.700 ; + RECT 1138.110 176.500 1138.430 176.560 ; + RECT 1435.270 176.500 1435.590 176.560 ; + RECT 1435.270 16.900 1435.590 16.960 ; + RECT 1441.710 16.900 1442.030 16.960 ; + RECT 1435.270 16.760 1442.030 16.900 ; + RECT 1435.270 16.700 1435.590 16.760 ; + RECT 1441.710 16.700 1442.030 16.760 ; + LAYER via ; + RECT 1138.140 176.500 1138.400 176.760 ; + RECT 1435.300 176.500 1435.560 176.760 ; + RECT 1435.300 16.700 1435.560 16.960 ; + RECT 1441.740 16.700 1442.000 16.960 ; + LAYER met2 ; + RECT 1134.870 260.170 1135.150 264.000 ; + RECT 1134.870 260.030 1138.340 260.170 ; + RECT 1134.870 260.000 1135.150 260.030 ; + RECT 1138.200 176.790 1138.340 260.030 ; + RECT 1138.140 176.470 1138.400 176.790 ; + RECT 1435.300 176.470 1435.560 176.790 ; + RECT 1435.360 16.990 1435.500 176.470 ; + RECT 1435.300 16.670 1435.560 16.990 ; + RECT 1441.740 16.670 1442.000 16.990 ; + RECT 1441.800 2.400 1441.940 16.670 ; + RECT 1441.590 -4.800 1442.150 2.400 ; +======= LAYER met2 ; RECT 1441.590 -4.800 1442.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[45] PIN la_data_out[46] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1152.830 243.340 1153.150 243.400 ; + RECT 1158.350 243.340 1158.670 243.400 ; + RECT 1152.830 243.200 1158.670 243.340 ; + RECT 1152.830 243.140 1153.150 243.200 ; + RECT 1158.350 243.140 1158.670 243.200 ; + RECT 1158.350 183.160 1158.670 183.220 ; + RECT 1455.970 183.160 1456.290 183.220 ; + RECT 1158.350 183.020 1456.290 183.160 ; + RECT 1158.350 182.960 1158.670 183.020 ; + RECT 1455.970 182.960 1456.290 183.020 ; + LAYER via ; + RECT 1152.860 243.140 1153.120 243.400 ; + RECT 1158.380 243.140 1158.640 243.400 ; + RECT 1158.380 182.960 1158.640 183.220 ; + RECT 1456.000 182.960 1456.260 183.220 ; + LAYER met2 ; + RECT 1152.810 260.000 1153.090 264.000 ; + RECT 1152.920 243.430 1153.060 260.000 ; + RECT 1152.860 243.110 1153.120 243.430 ; + RECT 1158.380 243.110 1158.640 243.430 ; + RECT 1158.440 183.250 1158.580 243.110 ; + RECT 1158.380 182.930 1158.640 183.250 ; + RECT 1456.000 182.930 1456.260 183.250 ; + RECT 1456.060 16.730 1456.200 182.930 ; + RECT 1456.060 16.590 1459.880 16.730 ; + RECT 1459.740 2.400 1459.880 16.590 ; + RECT 1459.530 -4.800 1460.090 2.400 ; +======= LAYER met2 ; RECT 1459.530 -4.800 1460.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[46] PIN la_data_out[47] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1172.610 196.760 1172.930 196.820 ; + RECT 1476.670 196.760 1476.990 196.820 ; + RECT 1172.610 196.620 1476.990 196.760 ; + RECT 1172.610 196.560 1172.930 196.620 ; + RECT 1476.670 196.560 1476.990 196.620 ; + LAYER via ; + RECT 1172.640 196.560 1172.900 196.820 ; + RECT 1476.700 196.560 1476.960 196.820 ; + LAYER met2 ; + RECT 1170.750 260.170 1171.030 264.000 ; + RECT 1170.750 260.030 1172.840 260.170 ; + RECT 1170.750 260.000 1171.030 260.030 ; + RECT 1172.700 196.850 1172.840 260.030 ; + RECT 1172.640 196.530 1172.900 196.850 ; + RECT 1476.700 196.530 1476.960 196.850 ; + RECT 1476.760 17.240 1476.900 196.530 ; + RECT 1476.760 17.100 1477.820 17.240 ; + RECT 1477.680 2.400 1477.820 17.100 ; + RECT 1477.470 -4.800 1478.030 2.400 ; +======= LAYER met2 ; RECT 1477.470 -4.800 1478.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[47] PIN la_data_out[48] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1188.710 244.020 1189.030 244.080 ; + RECT 1193.310 244.020 1193.630 244.080 ; + RECT 1188.710 243.880 1193.630 244.020 ; + RECT 1188.710 243.820 1189.030 243.880 ; + RECT 1193.310 243.820 1193.630 243.880 ; + RECT 1193.310 224.640 1193.630 224.700 ; + RECT 1490.470 224.640 1490.790 224.700 ; + RECT 1193.310 224.500 1490.790 224.640 ; + RECT 1193.310 224.440 1193.630 224.500 ; + RECT 1490.470 224.440 1490.790 224.500 ; + LAYER via ; + RECT 1188.740 243.820 1189.000 244.080 ; + RECT 1193.340 243.820 1193.600 244.080 ; + RECT 1193.340 224.440 1193.600 224.700 ; + RECT 1490.500 224.440 1490.760 224.700 ; + LAYER met2 ; + RECT 1188.690 260.000 1188.970 264.000 ; + RECT 1188.800 244.110 1188.940 260.000 ; + RECT 1188.740 243.790 1189.000 244.110 ; + RECT 1193.340 243.790 1193.600 244.110 ; + RECT 1193.400 224.730 1193.540 243.790 ; + RECT 1193.340 224.410 1193.600 224.730 ; + RECT 1490.500 224.410 1490.760 224.730 ; + RECT 1490.560 17.410 1490.700 224.410 ; + RECT 1490.560 17.270 1495.760 17.410 ; + RECT 1495.620 2.400 1495.760 17.270 ; + RECT 1495.410 -4.800 1495.970 2.400 ; +======= LAYER met2 ; RECT 1495.410 -4.800 1495.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[48] PIN la_data_out[49] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1206.650 189.620 1206.970 189.680 ; + RECT 1511.170 189.620 1511.490 189.680 ; + RECT 1206.650 189.480 1511.490 189.620 ; + RECT 1206.650 189.420 1206.970 189.480 ; + RECT 1511.170 189.420 1511.490 189.480 ; + LAYER via ; + RECT 1206.680 189.420 1206.940 189.680 ; + RECT 1511.200 189.420 1511.460 189.680 ; + LAYER met2 ; + RECT 1206.630 260.000 1206.910 264.000 ; + RECT 1206.740 189.710 1206.880 260.000 ; + RECT 1206.680 189.390 1206.940 189.710 ; + RECT 1511.200 189.390 1511.460 189.710 ; + RECT 1511.260 17.410 1511.400 189.390 ; + RECT 1511.260 17.270 1513.240 17.410 ; + RECT 1513.100 2.400 1513.240 17.270 ; + RECT 1512.890 -4.800 1513.450 2.400 ; +======= LAYER met2 ; RECT 1512.890 -4.800 1513.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[49] PIN la_data_out[4] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 402.110 244.020 402.430 244.080 ; + RECT 406.710 244.020 407.030 244.080 ; + RECT 402.110 243.880 407.030 244.020 ; + RECT 402.110 243.820 402.430 243.880 ; + RECT 406.710 243.820 407.030 243.880 ; + RECT 406.710 210.360 407.030 210.420 ; + RECT 703.870 210.360 704.190 210.420 ; + RECT 406.710 210.220 704.190 210.360 ; + RECT 406.710 210.160 407.030 210.220 ; + RECT 703.870 210.160 704.190 210.220 ; + RECT 703.870 19.280 704.190 19.340 ; + RECT 710.310 19.280 710.630 19.340 ; + RECT 703.870 19.140 710.630 19.280 ; + RECT 703.870 19.080 704.190 19.140 ; + RECT 710.310 19.080 710.630 19.140 ; + LAYER via ; + RECT 402.140 243.820 402.400 244.080 ; + RECT 406.740 243.820 407.000 244.080 ; + RECT 406.740 210.160 407.000 210.420 ; + RECT 703.900 210.160 704.160 210.420 ; + RECT 703.900 19.080 704.160 19.340 ; + RECT 710.340 19.080 710.600 19.340 ; + LAYER met2 ; + RECT 402.090 260.000 402.370 264.000 ; + RECT 402.200 244.110 402.340 260.000 ; + RECT 402.140 243.790 402.400 244.110 ; + RECT 406.740 243.790 407.000 244.110 ; + RECT 406.800 210.450 406.940 243.790 ; + RECT 406.740 210.130 407.000 210.450 ; + RECT 703.900 210.130 704.160 210.450 ; + RECT 703.960 19.370 704.100 210.130 ; + RECT 703.900 19.050 704.160 19.370 ; + RECT 710.340 19.050 710.600 19.370 ; + RECT 710.400 2.400 710.540 19.050 ; + RECT 710.190 -4.800 710.750 2.400 ; +======= LAYER met2 ; RECT 710.190 -4.800 710.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[4] PIN la_data_out[50] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1227.810 148.820 1228.130 148.880 ; + RECT 1524.970 148.820 1525.290 148.880 ; + RECT 1227.810 148.680 1525.290 148.820 ; + RECT 1227.810 148.620 1228.130 148.680 ; + RECT 1524.970 148.620 1525.290 148.680 ; + RECT 1524.970 17.920 1525.290 17.980 ; + RECT 1530.950 17.920 1531.270 17.980 ; + RECT 1524.970 17.780 1531.270 17.920 ; + RECT 1524.970 17.720 1525.290 17.780 ; + RECT 1530.950 17.720 1531.270 17.780 ; + LAYER via ; + RECT 1227.840 148.620 1228.100 148.880 ; + RECT 1525.000 148.620 1525.260 148.880 ; + RECT 1525.000 17.720 1525.260 17.980 ; + RECT 1530.980 17.720 1531.240 17.980 ; + LAYER met2 ; + RECT 1224.110 260.170 1224.390 264.000 ; + RECT 1224.110 260.030 1228.040 260.170 ; + RECT 1224.110 260.000 1224.390 260.030 ; + RECT 1227.900 148.910 1228.040 260.030 ; + RECT 1227.840 148.590 1228.100 148.910 ; + RECT 1525.000 148.590 1525.260 148.910 ; + RECT 1525.060 18.010 1525.200 148.590 ; + RECT 1525.000 17.690 1525.260 18.010 ; + RECT 1530.980 17.690 1531.240 18.010 ; + RECT 1531.040 2.400 1531.180 17.690 ; + RECT 1530.830 -4.800 1531.390 2.400 ; +======= LAYER met2 ; RECT 1530.830 -4.800 1531.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[50] PIN la_data_out[51] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1242.070 244.020 1242.390 244.080 ; + RECT 1248.050 244.020 1248.370 244.080 ; + RECT 1242.070 243.880 1248.370 244.020 ; + RECT 1242.070 243.820 1242.390 243.880 ; + RECT 1248.050 243.820 1248.370 243.880 ; + RECT 1248.050 203.900 1248.370 203.960 ; + RECT 1545.670 203.900 1545.990 203.960 ; + RECT 1248.050 203.760 1545.990 203.900 ; + RECT 1248.050 203.700 1248.370 203.760 ; + RECT 1545.670 203.700 1545.990 203.760 ; + LAYER via ; + RECT 1242.100 243.820 1242.360 244.080 ; + RECT 1248.080 243.820 1248.340 244.080 ; + RECT 1248.080 203.700 1248.340 203.960 ; + RECT 1545.700 203.700 1545.960 203.960 ; + LAYER met2 ; + RECT 1242.050 260.000 1242.330 264.000 ; + RECT 1242.160 244.110 1242.300 260.000 ; + RECT 1242.100 243.790 1242.360 244.110 ; + RECT 1248.080 243.790 1248.340 244.110 ; + RECT 1248.140 203.990 1248.280 243.790 ; + RECT 1248.080 203.670 1248.340 203.990 ; + RECT 1545.700 203.670 1545.960 203.990 ; + RECT 1545.760 16.730 1545.900 203.670 ; + RECT 1545.760 16.590 1549.120 16.730 ; + RECT 1548.980 2.400 1549.120 16.590 ; + RECT 1548.770 -4.800 1549.330 2.400 ; +======= LAYER met2 ; RECT 1548.770 -4.800 1549.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[51] PIN la_data_out[52] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1262.310 141.680 1262.630 141.740 ; + RECT 1566.830 141.680 1567.150 141.740 ; + RECT 1262.310 141.540 1567.150 141.680 ; + RECT 1262.310 141.480 1262.630 141.540 ; + RECT 1566.830 141.480 1567.150 141.540 ; + LAYER via ; + RECT 1262.340 141.480 1262.600 141.740 ; + RECT 1566.860 141.480 1567.120 141.740 ; + LAYER met2 ; + RECT 1259.990 260.170 1260.270 264.000 ; + RECT 1259.990 260.030 1262.540 260.170 ; + RECT 1259.990 260.000 1260.270 260.030 ; + RECT 1262.400 141.770 1262.540 260.030 ; + RECT 1262.340 141.450 1262.600 141.770 ; + RECT 1566.860 141.450 1567.120 141.770 ; + RECT 1566.920 2.400 1567.060 141.450 ; + RECT 1566.710 -4.800 1567.270 2.400 ; +======= LAYER met2 ; RECT 1566.710 -4.800 1567.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[52] PIN la_data_out[53] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1277.950 244.020 1278.270 244.080 ; + RECT 1283.010 244.020 1283.330 244.080 ; + RECT 1277.950 243.880 1283.330 244.020 ; + RECT 1277.950 243.820 1278.270 243.880 ; + RECT 1283.010 243.820 1283.330 243.880 ; + RECT 1283.010 211.040 1283.330 211.100 ; + RECT 1580.170 211.040 1580.490 211.100 ; + RECT 1283.010 210.900 1580.490 211.040 ; + RECT 1283.010 210.840 1283.330 210.900 ; + RECT 1580.170 210.840 1580.490 210.900 ; + LAYER via ; + RECT 1277.980 243.820 1278.240 244.080 ; + RECT 1283.040 243.820 1283.300 244.080 ; + RECT 1283.040 210.840 1283.300 211.100 ; + RECT 1580.200 210.840 1580.460 211.100 ; + LAYER met2 ; + RECT 1277.930 260.000 1278.210 264.000 ; + RECT 1278.040 244.110 1278.180 260.000 ; + RECT 1277.980 243.790 1278.240 244.110 ; + RECT 1283.040 243.790 1283.300 244.110 ; + RECT 1283.100 211.130 1283.240 243.790 ; + RECT 1283.040 210.810 1283.300 211.130 ; + RECT 1580.200 210.810 1580.460 211.130 ; + RECT 1580.260 16.730 1580.400 210.810 ; + RECT 1580.260 16.590 1585.000 16.730 ; + RECT 1584.860 2.400 1585.000 16.590 ; + RECT 1584.650 -4.800 1585.210 2.400 ; +======= LAYER met2 ; RECT 1584.650 -4.800 1585.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[53] PIN la_data_out[54] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1296.810 155.620 1297.130 155.680 ; + RECT 1600.870 155.620 1601.190 155.680 ; + RECT 1296.810 155.480 1601.190 155.620 ; + RECT 1296.810 155.420 1297.130 155.480 ; + RECT 1600.870 155.420 1601.190 155.480 ; + LAYER via ; + RECT 1296.840 155.420 1297.100 155.680 ; + RECT 1600.900 155.420 1601.160 155.680 ; + LAYER met2 ; + RECT 1295.870 260.170 1296.150 264.000 ; + RECT 1295.870 260.030 1297.040 260.170 ; + RECT 1295.870 260.000 1296.150 260.030 ; + RECT 1296.900 155.710 1297.040 260.030 ; + RECT 1296.840 155.390 1297.100 155.710 ; + RECT 1600.900 155.390 1601.160 155.710 ; + RECT 1600.960 16.730 1601.100 155.390 ; + RECT 1600.960 16.590 1602.480 16.730 ; + RECT 1602.340 2.400 1602.480 16.590 ; + RECT 1602.130 -4.800 1602.690 2.400 ; +======= LAYER met2 ; RECT 1602.130 -4.800 1602.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[54] PIN la_data_out[55] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1313.830 241.640 1314.150 241.700 ; + RECT 1317.510 241.640 1317.830 241.700 ; + RECT 1313.830 241.500 1317.830 241.640 ; + RECT 1313.830 241.440 1314.150 241.500 ; + RECT 1317.510 241.440 1317.830 241.500 ; + RECT 1317.510 217.500 1317.830 217.560 ; + RECT 1615.130 217.500 1615.450 217.560 ; + RECT 1317.510 217.360 1615.450 217.500 ; + RECT 1317.510 217.300 1317.830 217.360 ; + RECT 1615.130 217.300 1615.450 217.360 ; + RECT 1614.670 62.260 1614.990 62.520 ; + RECT 1614.760 62.120 1614.900 62.260 ; + RECT 1620.190 62.120 1620.510 62.180 ; + RECT 1614.760 61.980 1620.510 62.120 ; + RECT 1620.190 61.920 1620.510 61.980 ; + RECT 1620.190 47.980 1620.510 48.240 ; + RECT 1620.280 47.560 1620.420 47.980 ; + RECT 1620.190 47.300 1620.510 47.560 ; + LAYER via ; + RECT 1313.860 241.440 1314.120 241.700 ; + RECT 1317.540 241.440 1317.800 241.700 ; + RECT 1317.540 217.300 1317.800 217.560 ; + RECT 1615.160 217.300 1615.420 217.560 ; + RECT 1614.700 62.260 1614.960 62.520 ; + RECT 1620.220 61.920 1620.480 62.180 ; + RECT 1620.220 47.980 1620.480 48.240 ; + RECT 1620.220 47.300 1620.480 47.560 ; + LAYER met2 ; + RECT 1313.810 260.000 1314.090 264.000 ; + RECT 1313.920 241.730 1314.060 260.000 ; + RECT 1313.860 241.410 1314.120 241.730 ; + RECT 1317.540 241.410 1317.800 241.730 ; + RECT 1317.600 217.590 1317.740 241.410 ; + RECT 1317.540 217.270 1317.800 217.590 ; + RECT 1615.160 217.270 1615.420 217.590 ; + RECT 1615.220 193.530 1615.360 217.270 ; + RECT 1614.760 193.390 1615.360 193.530 ; + RECT 1614.760 62.550 1614.900 193.390 ; + RECT 1614.700 62.230 1614.960 62.550 ; + RECT 1620.220 61.890 1620.480 62.210 ; + RECT 1620.280 48.270 1620.420 61.890 ; + RECT 1620.220 47.950 1620.480 48.270 ; + RECT 1620.220 47.270 1620.480 47.590 ; + RECT 1620.280 2.400 1620.420 47.270 ; + RECT 1620.070 -4.800 1620.630 2.400 ; +======= LAYER met2 ; RECT 1620.070 -4.800 1620.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[55] PIN la_data_out[56] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1331.770 244.020 1332.090 244.080 ; + RECT 1337.750 244.020 1338.070 244.080 ; + RECT 1331.770 243.880 1338.070 244.020 ; + RECT 1331.770 243.820 1332.090 243.880 ; + RECT 1337.750 243.820 1338.070 243.880 ; + RECT 1337.750 162.420 1338.070 162.480 ; + RECT 1635.370 162.420 1635.690 162.480 ; + RECT 1337.750 162.280 1635.690 162.420 ; + RECT 1337.750 162.220 1338.070 162.280 ; + RECT 1635.370 162.220 1635.690 162.280 ; + RECT 1635.370 62.260 1635.690 62.520 ; + RECT 1635.460 61.780 1635.600 62.260 ; + RECT 1638.130 61.780 1638.450 61.840 ; + RECT 1635.460 61.640 1638.450 61.780 ; + RECT 1638.130 61.580 1638.450 61.640 ; + RECT 1638.130 47.980 1638.450 48.240 ; + RECT 1638.220 47.560 1638.360 47.980 ; + RECT 1638.130 47.300 1638.450 47.560 ; + LAYER via ; + RECT 1331.800 243.820 1332.060 244.080 ; + RECT 1337.780 243.820 1338.040 244.080 ; + RECT 1337.780 162.220 1338.040 162.480 ; + RECT 1635.400 162.220 1635.660 162.480 ; + RECT 1635.400 62.260 1635.660 62.520 ; + RECT 1638.160 61.580 1638.420 61.840 ; + RECT 1638.160 47.980 1638.420 48.240 ; + RECT 1638.160 47.300 1638.420 47.560 ; + LAYER met2 ; + RECT 1331.750 260.000 1332.030 264.000 ; + RECT 1331.860 244.110 1332.000 260.000 ; + RECT 1331.800 243.790 1332.060 244.110 ; + RECT 1337.780 243.790 1338.040 244.110 ; + RECT 1337.840 162.510 1337.980 243.790 ; + RECT 1337.780 162.190 1338.040 162.510 ; + RECT 1635.400 162.190 1635.660 162.510 ; + RECT 1635.460 62.550 1635.600 162.190 ; + RECT 1635.400 62.230 1635.660 62.550 ; + RECT 1638.160 61.550 1638.420 61.870 ; + RECT 1638.220 48.270 1638.360 61.550 ; + RECT 1638.160 47.950 1638.420 48.270 ; + RECT 1638.160 47.270 1638.420 47.590 ; + RECT 1638.220 2.400 1638.360 47.270 ; + RECT 1638.010 -4.800 1638.570 2.400 ; +======= LAYER met2 ; RECT 1638.010 -4.800 1638.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[56] PIN la_data_out[57] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1352.010 169.220 1352.330 169.280 ; + RECT 1656.070 169.220 1656.390 169.280 ; + RECT 1352.010 169.080 1656.390 169.220 ; + RECT 1352.010 169.020 1352.330 169.080 ; + RECT 1656.070 169.020 1656.390 169.080 ; + LAYER via ; + RECT 1352.040 169.020 1352.300 169.280 ; + RECT 1656.100 169.020 1656.360 169.280 ; + LAYER met2 ; + RECT 1349.230 260.170 1349.510 264.000 ; + RECT 1349.230 260.030 1352.240 260.170 ; + RECT 1349.230 260.000 1349.510 260.030 ; + RECT 1352.100 169.310 1352.240 260.030 ; + RECT 1352.040 168.990 1352.300 169.310 ; + RECT 1656.100 168.990 1656.360 169.310 ; + RECT 1656.160 2.400 1656.300 168.990 ; + RECT 1655.950 -4.800 1656.510 2.400 ; +======= LAYER met2 ; RECT 1655.950 -4.800 1656.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[57] PIN la_data_out[58] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1367.190 244.020 1367.510 244.080 ; + RECT 1372.710 244.020 1373.030 244.080 ; + RECT 1367.190 243.880 1373.030 244.020 ; + RECT 1367.190 243.820 1367.510 243.880 ; + RECT 1372.710 243.820 1373.030 243.880 ; + RECT 1372.710 176.020 1373.030 176.080 ; + RECT 1669.870 176.020 1670.190 176.080 ; + RECT 1372.710 175.880 1670.190 176.020 ; + RECT 1372.710 175.820 1373.030 175.880 ; + RECT 1669.870 175.820 1670.190 175.880 ; + LAYER via ; + RECT 1367.220 243.820 1367.480 244.080 ; + RECT 1372.740 243.820 1373.000 244.080 ; + RECT 1372.740 175.820 1373.000 176.080 ; + RECT 1669.900 175.820 1670.160 176.080 ; + LAYER met2 ; + RECT 1367.170 260.000 1367.450 264.000 ; + RECT 1367.280 244.110 1367.420 260.000 ; + RECT 1367.220 243.790 1367.480 244.110 ; + RECT 1372.740 243.790 1373.000 244.110 ; + RECT 1372.800 176.110 1372.940 243.790 ; + RECT 1372.740 175.790 1373.000 176.110 ; + RECT 1669.900 175.790 1670.160 176.110 ; + RECT 1669.960 16.730 1670.100 175.790 ; + RECT 1669.960 16.590 1673.780 16.730 ; + RECT 1673.640 2.400 1673.780 16.590 ; + RECT 1673.430 -4.800 1673.990 2.400 ; +======= LAYER met2 ; RECT 1673.430 -4.800 1673.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[58] PIN la_data_out[59] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1386.510 182.820 1386.830 182.880 ; + RECT 1690.570 182.820 1690.890 182.880 ; + RECT 1386.510 182.680 1690.890 182.820 ; + RECT 1386.510 182.620 1386.830 182.680 ; + RECT 1690.570 182.620 1690.890 182.680 ; + LAYER via ; + RECT 1386.540 182.620 1386.800 182.880 ; + RECT 1690.600 182.620 1690.860 182.880 ; + LAYER met2 ; + RECT 1385.110 260.170 1385.390 264.000 ; + RECT 1385.110 260.030 1386.740 260.170 ; + RECT 1385.110 260.000 1385.390 260.030 ; + RECT 1386.600 182.910 1386.740 260.030 ; + RECT 1386.540 182.590 1386.800 182.910 ; + RECT 1690.600 182.590 1690.860 182.910 ; + RECT 1690.660 17.410 1690.800 182.590 ; + RECT 1690.660 17.270 1691.720 17.410 ; + RECT 1691.580 2.400 1691.720 17.270 ; + RECT 1691.370 -4.800 1691.930 2.400 ; +======= LAYER met2 ; RECT 1691.370 -4.800 1691.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[59] PIN la_data_out[5] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 420.510 18.940 420.830 19.000 ; + RECT 728.250 18.940 728.570 19.000 ; + RECT 420.510 18.800 728.570 18.940 ; + RECT 420.510 18.740 420.830 18.800 ; + RECT 728.250 18.740 728.570 18.800 ; + LAYER via ; + RECT 420.540 18.740 420.800 19.000 ; + RECT 728.280 18.740 728.540 19.000 ; + LAYER met2 ; + RECT 420.030 260.170 420.310 264.000 ; + RECT 420.030 260.030 420.740 260.170 ; + RECT 420.030 260.000 420.310 260.030 ; + RECT 420.600 19.030 420.740 260.030 ; + RECT 420.540 18.710 420.800 19.030 ; + RECT 728.280 18.710 728.540 19.030 ; + RECT 728.340 2.400 728.480 18.710 ; + RECT 728.130 -4.800 728.690 2.400 ; +======= LAYER met2 ; RECT 728.130 -4.800 728.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[5] PIN la_data_out[60] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1403.070 244.020 1403.390 244.080 ; + RECT 1407.210 244.020 1407.530 244.080 ; + RECT 1403.070 243.880 1407.530 244.020 ; + RECT 1403.070 243.820 1403.390 243.880 ; + RECT 1407.210 243.820 1407.530 243.880 ; + RECT 1407.210 197.100 1407.530 197.160 ; + RECT 1704.370 197.100 1704.690 197.160 ; + RECT 1407.210 196.960 1704.690 197.100 ; + RECT 1407.210 196.900 1407.530 196.960 ; + RECT 1704.370 196.900 1704.690 196.960 ; + LAYER via ; + RECT 1403.100 243.820 1403.360 244.080 ; + RECT 1407.240 243.820 1407.500 244.080 ; + RECT 1407.240 196.900 1407.500 197.160 ; + RECT 1704.400 196.900 1704.660 197.160 ; + LAYER met2 ; + RECT 1403.050 260.000 1403.330 264.000 ; + RECT 1403.160 244.110 1403.300 260.000 ; + RECT 1403.100 243.790 1403.360 244.110 ; + RECT 1407.240 243.790 1407.500 244.110 ; + RECT 1407.300 197.190 1407.440 243.790 ; + RECT 1407.240 196.870 1407.500 197.190 ; + RECT 1704.400 196.870 1704.660 197.190 ; + RECT 1704.460 17.410 1704.600 196.870 ; + RECT 1704.460 17.270 1709.660 17.410 ; + RECT 1709.520 2.400 1709.660 17.270 ; + RECT 1709.310 -4.800 1709.870 2.400 ; +======= LAYER met2 ; RECT 1709.310 -4.800 1709.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[60] PIN la_data_out[61] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1420.550 224.300 1420.870 224.360 ; + RECT 1725.070 224.300 1725.390 224.360 ; + RECT 1420.550 224.160 1725.390 224.300 ; + RECT 1420.550 224.100 1420.870 224.160 ; + RECT 1725.070 224.100 1725.390 224.160 ; + LAYER via ; + RECT 1420.580 224.100 1420.840 224.360 ; + RECT 1725.100 224.100 1725.360 224.360 ; + LAYER met2 ; + RECT 1420.990 260.170 1421.270 264.000 ; + RECT 1420.640 260.030 1421.270 260.170 ; + RECT 1420.640 224.390 1420.780 260.030 ; + RECT 1420.990 260.000 1421.270 260.030 ; + RECT 1420.580 224.070 1420.840 224.390 ; + RECT 1725.100 224.070 1725.360 224.390 ; + RECT 1725.160 17.410 1725.300 224.070 ; + RECT 1725.160 17.270 1727.600 17.410 ; + RECT 1727.460 2.400 1727.600 17.270 ; + RECT 1727.250 -4.800 1727.810 2.400 ; +======= LAYER met2 ; RECT 1727.250 -4.800 1727.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[61] PIN la_data_out[62] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1441.710 189.960 1442.030 190.020 ; + RECT 1738.870 189.960 1739.190 190.020 ; + RECT 1441.710 189.820 1739.190 189.960 ; + RECT 1441.710 189.760 1442.030 189.820 ; + RECT 1738.870 189.760 1739.190 189.820 ; + RECT 1738.870 18.940 1739.190 19.000 ; + RECT 1745.310 18.940 1745.630 19.000 ; + RECT 1738.870 18.800 1745.630 18.940 ; + RECT 1738.870 18.740 1739.190 18.800 ; + RECT 1745.310 18.740 1745.630 18.800 ; + LAYER via ; + RECT 1441.740 189.760 1442.000 190.020 ; + RECT 1738.900 189.760 1739.160 190.020 ; + RECT 1738.900 18.740 1739.160 19.000 ; + RECT 1745.340 18.740 1745.600 19.000 ; + LAYER met2 ; + RECT 1438.930 260.170 1439.210 264.000 ; + RECT 1438.930 260.030 1441.940 260.170 ; + RECT 1438.930 260.000 1439.210 260.030 ; + RECT 1441.800 190.050 1441.940 260.030 ; + RECT 1441.740 189.730 1442.000 190.050 ; + RECT 1738.900 189.730 1739.160 190.050 ; + RECT 1738.960 19.030 1739.100 189.730 ; + RECT 1738.900 18.710 1739.160 19.030 ; + RECT 1745.340 18.710 1745.600 19.030 ; + RECT 1745.400 2.400 1745.540 18.710 ; + RECT 1745.190 -4.800 1745.750 2.400 ; +======= LAYER met2 ; RECT 1745.190 -4.800 1745.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[62] PIN la_data_out[63] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1456.890 244.020 1457.210 244.080 ; + RECT 1462.410 244.020 1462.730 244.080 ; + RECT 1456.890 243.880 1462.730 244.020 ; + RECT 1456.890 243.820 1457.210 243.880 ; + RECT 1462.410 243.820 1462.730 243.880 ; + RECT 1462.410 148.480 1462.730 148.540 ; + RECT 1759.570 148.480 1759.890 148.540 ; + RECT 1462.410 148.340 1759.890 148.480 ; + RECT 1462.410 148.280 1462.730 148.340 ; + RECT 1759.570 148.280 1759.890 148.340 ; + LAYER via ; + RECT 1456.920 243.820 1457.180 244.080 ; + RECT 1462.440 243.820 1462.700 244.080 ; + RECT 1462.440 148.280 1462.700 148.540 ; + RECT 1759.600 148.280 1759.860 148.540 ; + LAYER met2 ; + RECT 1456.870 260.000 1457.150 264.000 ; + RECT 1456.980 244.110 1457.120 260.000 ; + RECT 1456.920 243.790 1457.180 244.110 ; + RECT 1462.440 243.790 1462.700 244.110 ; + RECT 1462.500 148.570 1462.640 243.790 ; + RECT 1462.440 148.250 1462.700 148.570 ; + RECT 1759.600 148.250 1759.860 148.570 ; + RECT 1759.660 17.410 1759.800 148.250 ; + RECT 1759.660 17.270 1763.020 17.410 ; + RECT 1762.880 2.400 1763.020 17.270 ; + RECT 1762.670 -4.800 1763.230 2.400 ; +======= LAYER met2 ; RECT 1762.670 -4.800 1763.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[63] PIN la_data_out[64] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1476.210 24.040 1476.530 24.100 ; + RECT 1780.730 24.040 1781.050 24.100 ; + RECT 1476.210 23.900 1781.050 24.040 ; + RECT 1476.210 23.840 1476.530 23.900 ; + RECT 1780.730 23.840 1781.050 23.900 ; + LAYER via ; + RECT 1476.240 23.840 1476.500 24.100 ; + RECT 1780.760 23.840 1781.020 24.100 ; + LAYER met2 ; + RECT 1474.350 260.170 1474.630 264.000 ; + RECT 1474.350 260.030 1476.440 260.170 ; + RECT 1474.350 260.000 1474.630 260.030 ; + RECT 1476.300 24.130 1476.440 260.030 ; + RECT 1476.240 23.810 1476.500 24.130 ; + RECT 1780.760 23.810 1781.020 24.130 ; + RECT 1780.820 2.400 1780.960 23.810 ; + RECT 1780.610 -4.800 1781.170 2.400 ; +======= LAYER met2 ; RECT 1780.610 -4.800 1781.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[64] PIN la_data_out[65] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1492.310 244.020 1492.630 244.080 ; + RECT 1496.910 244.020 1497.230 244.080 ; + RECT 1492.310 243.880 1497.230 244.020 ; + RECT 1492.310 243.820 1492.630 243.880 ; + RECT 1496.910 243.820 1497.230 243.880 ; + RECT 1496.910 204.240 1497.230 204.300 ; + RECT 1794.070 204.240 1794.390 204.300 ; + RECT 1496.910 204.100 1794.390 204.240 ; + RECT 1496.910 204.040 1497.230 204.100 ; + RECT 1794.070 204.040 1794.390 204.100 ; + RECT 1794.070 2.960 1794.390 3.020 ; + RECT 1798.670 2.960 1798.990 3.020 ; + RECT 1794.070 2.820 1798.990 2.960 ; + RECT 1794.070 2.760 1794.390 2.820 ; + RECT 1798.670 2.760 1798.990 2.820 ; + LAYER via ; + RECT 1492.340 243.820 1492.600 244.080 ; + RECT 1496.940 243.820 1497.200 244.080 ; + RECT 1496.940 204.040 1497.200 204.300 ; + RECT 1794.100 204.040 1794.360 204.300 ; + RECT 1794.100 2.760 1794.360 3.020 ; + RECT 1798.700 2.760 1798.960 3.020 ; + LAYER met2 ; + RECT 1492.290 260.000 1492.570 264.000 ; + RECT 1492.400 244.110 1492.540 260.000 ; + RECT 1492.340 243.790 1492.600 244.110 ; + RECT 1496.940 243.790 1497.200 244.110 ; + RECT 1497.000 204.330 1497.140 243.790 ; + RECT 1496.940 204.010 1497.200 204.330 ; + RECT 1794.100 204.010 1794.360 204.330 ; + RECT 1794.160 3.050 1794.300 204.010 ; + RECT 1794.100 2.730 1794.360 3.050 ; + RECT 1798.700 2.730 1798.960 3.050 ; + RECT 1798.760 2.400 1798.900 2.730 ; + RECT 1798.550 -4.800 1799.110 2.400 ; +======= LAYER met2 ; RECT 1798.550 -4.800 1799.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[65] PIN la_data_out[66] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1510.250 141.340 1510.570 141.400 ; + RECT 1814.770 141.340 1815.090 141.400 ; + RECT 1510.250 141.200 1815.090 141.340 ; + RECT 1510.250 141.140 1510.570 141.200 ; + RECT 1814.770 141.140 1815.090 141.200 ; + LAYER via ; + RECT 1510.280 141.140 1510.540 141.400 ; + RECT 1814.800 141.140 1815.060 141.400 ; + LAYER met2 ; + RECT 1510.230 260.000 1510.510 264.000 ; + RECT 1510.340 141.430 1510.480 260.000 ; + RECT 1510.280 141.110 1510.540 141.430 ; + RECT 1814.800 141.110 1815.060 141.430 ; + RECT 1814.860 3.130 1815.000 141.110 ; + RECT 1814.860 2.990 1816.840 3.130 ; + RECT 1816.700 2.400 1816.840 2.990 ; + RECT 1816.490 -4.800 1817.050 2.400 ; +======= LAYER met2 ; RECT 1816.490 -4.800 1817.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[66] PIN la_data_out[67] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1531.410 155.960 1531.730 156.020 ; + RECT 1828.570 155.960 1828.890 156.020 ; + RECT 1531.410 155.820 1828.890 155.960 ; + RECT 1531.410 155.760 1531.730 155.820 ; + RECT 1828.570 155.760 1828.890 155.820 ; + RECT 1828.570 17.240 1828.890 17.300 ; + RECT 1834.550 17.240 1834.870 17.300 ; + RECT 1828.570 17.100 1834.870 17.240 ; + RECT 1828.570 17.040 1828.890 17.100 ; + RECT 1834.550 17.040 1834.870 17.100 ; + LAYER via ; + RECT 1531.440 155.760 1531.700 156.020 ; + RECT 1828.600 155.760 1828.860 156.020 ; + RECT 1828.600 17.040 1828.860 17.300 ; + RECT 1834.580 17.040 1834.840 17.300 ; + LAYER met2 ; + RECT 1528.170 260.170 1528.450 264.000 ; + RECT 1528.170 260.030 1531.640 260.170 ; + RECT 1528.170 260.000 1528.450 260.030 ; + RECT 1531.500 156.050 1531.640 260.030 ; + RECT 1531.440 155.730 1531.700 156.050 ; + RECT 1828.600 155.730 1828.860 156.050 ; + RECT 1828.660 17.330 1828.800 155.730 ; + RECT 1828.600 17.010 1828.860 17.330 ; + RECT 1834.580 17.010 1834.840 17.330 ; + RECT 1834.640 2.400 1834.780 17.010 ; + RECT 1834.430 -4.800 1834.990 2.400 ; +======= LAYER met2 ; RECT 1834.430 -4.800 1834.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[67] PIN la_data_out[68] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1546.130 244.020 1546.450 244.080 ; + RECT 1551.650 244.020 1551.970 244.080 ; + RECT 1546.130 243.880 1551.970 244.020 ; + RECT 1546.130 243.820 1546.450 243.880 ; + RECT 1551.650 243.820 1551.970 243.880 ; + RECT 1551.650 210.360 1551.970 210.420 ; + RECT 1849.270 210.360 1849.590 210.420 ; + RECT 1551.650 210.220 1849.590 210.360 ; + RECT 1551.650 210.160 1551.970 210.220 ; + RECT 1849.270 210.160 1849.590 210.220 ; + RECT 1849.270 193.020 1849.590 193.080 ; + RECT 1849.730 193.020 1850.050 193.080 ; + RECT 1849.270 192.880 1850.050 193.020 ; + RECT 1849.270 192.820 1849.590 192.880 ; + RECT 1849.730 192.820 1850.050 192.880 ; + RECT 1849.270 137.940 1849.590 138.000 ; + RECT 1852.490 137.940 1852.810 138.000 ; + RECT 1849.270 137.800 1852.810 137.940 ; + RECT 1849.270 137.740 1849.590 137.800 ; + RECT 1852.490 137.740 1852.810 137.800 ; + LAYER via ; + RECT 1546.160 243.820 1546.420 244.080 ; + RECT 1551.680 243.820 1551.940 244.080 ; + RECT 1551.680 210.160 1551.940 210.420 ; + RECT 1849.300 210.160 1849.560 210.420 ; + RECT 1849.300 192.820 1849.560 193.080 ; + RECT 1849.760 192.820 1850.020 193.080 ; + RECT 1849.300 137.740 1849.560 138.000 ; + RECT 1852.520 137.740 1852.780 138.000 ; + LAYER met2 ; + RECT 1546.110 260.000 1546.390 264.000 ; + RECT 1546.220 244.110 1546.360 260.000 ; + RECT 1546.160 243.790 1546.420 244.110 ; + RECT 1551.680 243.790 1551.940 244.110 ; + RECT 1551.740 210.450 1551.880 243.790 ; + RECT 1551.680 210.130 1551.940 210.450 ; + RECT 1849.300 210.130 1849.560 210.450 ; + RECT 1849.360 193.110 1849.500 210.130 ; + RECT 1849.300 192.790 1849.560 193.110 ; + RECT 1849.760 192.790 1850.020 193.110 ; + RECT 1849.820 145.250 1849.960 192.790 ; + RECT 1849.360 145.110 1849.960 145.250 ; + RECT 1849.360 138.030 1849.500 145.110 ; + RECT 1849.300 137.710 1849.560 138.030 ; + RECT 1852.520 137.710 1852.780 138.030 ; + RECT 1852.580 17.240 1852.720 137.710 ; + RECT 1852.120 17.100 1852.720 17.240 ; + RECT 1852.120 2.400 1852.260 17.100 ; + RECT 1851.910 -4.800 1852.470 2.400 ; +======= LAYER met2 ; RECT 1851.910 -4.800 1852.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[68] PIN la_data_out[69] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1565.910 217.160 1566.230 217.220 ; + RECT 1870.430 217.160 1870.750 217.220 ; + RECT 1565.910 217.020 1870.750 217.160 ; + RECT 1565.910 216.960 1566.230 217.020 ; + RECT 1870.430 216.960 1870.750 217.020 ; + RECT 1870.430 14.180 1870.750 14.240 ; + RECT 1870.060 14.040 1870.750 14.180 ; + RECT 1870.060 13.900 1870.200 14.040 ; + RECT 1870.430 13.980 1870.750 14.040 ; + RECT 1869.970 13.640 1870.290 13.900 ; + LAYER via ; + RECT 1565.940 216.960 1566.200 217.220 ; + RECT 1870.460 216.960 1870.720 217.220 ; + RECT 1870.460 13.980 1870.720 14.240 ; + RECT 1870.000 13.640 1870.260 13.900 ; + LAYER met2 ; + RECT 1564.050 260.170 1564.330 264.000 ; + RECT 1564.050 260.030 1566.140 260.170 ; + RECT 1564.050 260.000 1564.330 260.030 ; + RECT 1566.000 217.250 1566.140 260.030 ; + RECT 1565.940 216.930 1566.200 217.250 ; + RECT 1870.460 216.930 1870.720 217.250 ; + RECT 1870.520 14.270 1870.660 216.930 ; + RECT 1870.460 13.950 1870.720 14.270 ; + RECT 1870.000 13.610 1870.260 13.930 ; + RECT 1870.060 2.400 1870.200 13.610 ; + RECT 1869.850 -4.800 1870.410 2.400 ; +======= LAYER met2 ; RECT 1869.850 -4.800 1870.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[69] PIN la_data_out[6] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 441.210 17.580 441.530 17.640 ; + RECT 746.190 17.580 746.510 17.640 ; + RECT 441.210 17.440 746.510 17.580 ; + RECT 441.210 17.380 441.530 17.440 ; + RECT 746.190 17.380 746.510 17.440 ; + LAYER via ; + RECT 441.240 17.380 441.500 17.640 ; + RECT 746.220 17.380 746.480 17.640 ; + LAYER met2 ; + RECT 437.970 260.170 438.250 264.000 ; + RECT 437.970 260.030 441.440 260.170 ; + RECT 437.970 260.000 438.250 260.030 ; + RECT 441.300 17.670 441.440 260.030 ; + RECT 441.240 17.350 441.500 17.670 ; + RECT 746.220 17.350 746.480 17.670 ; + RECT 746.280 2.400 746.420 17.350 ; + RECT 746.070 -4.800 746.630 2.400 ; +======= LAYER met2 ; RECT 746.070 -4.800 746.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[6] PIN la_data_out[70] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1582.010 244.020 1582.330 244.080 ; + RECT 1586.610 244.020 1586.930 244.080 ; + RECT 1582.010 243.880 1586.930 244.020 ; + RECT 1582.010 243.820 1582.330 243.880 ; + RECT 1586.610 243.820 1586.930 243.880 ; + RECT 1586.610 162.760 1586.930 162.820 ; + RECT 1883.770 162.760 1884.090 162.820 ; + RECT 1586.610 162.620 1884.090 162.760 ; + RECT 1586.610 162.560 1586.930 162.620 ; + RECT 1883.770 162.560 1884.090 162.620 ; + RECT 1883.770 62.120 1884.090 62.180 ; + RECT 1887.910 62.120 1888.230 62.180 ; + RECT 1883.770 61.980 1888.230 62.120 ; + RECT 1883.770 61.920 1884.090 61.980 ; + RECT 1887.910 61.920 1888.230 61.980 ; + LAYER via ; + RECT 1582.040 243.820 1582.300 244.080 ; + RECT 1586.640 243.820 1586.900 244.080 ; + RECT 1586.640 162.560 1586.900 162.820 ; + RECT 1883.800 162.560 1884.060 162.820 ; + RECT 1883.800 61.920 1884.060 62.180 ; + RECT 1887.940 61.920 1888.200 62.180 ; + LAYER met2 ; + RECT 1581.990 260.000 1582.270 264.000 ; + RECT 1582.100 244.110 1582.240 260.000 ; + RECT 1582.040 243.790 1582.300 244.110 ; + RECT 1586.640 243.790 1586.900 244.110 ; + RECT 1586.700 162.850 1586.840 243.790 ; + RECT 1586.640 162.530 1586.900 162.850 ; + RECT 1883.800 162.530 1884.060 162.850 ; + RECT 1883.860 62.210 1884.000 162.530 ; + RECT 1883.800 61.890 1884.060 62.210 ; + RECT 1887.940 61.890 1888.200 62.210 ; + RECT 1888.000 2.400 1888.140 61.890 ; + RECT 1887.790 -4.800 1888.350 2.400 ; +======= LAYER met2 ; RECT 1887.790 -4.800 1888.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[70] PIN la_data_out[71] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1600.410 168.880 1600.730 168.940 ; + RECT 1904.470 168.880 1904.790 168.940 ; + RECT 1600.410 168.740 1904.790 168.880 ; + RECT 1600.410 168.680 1600.730 168.740 ; + RECT 1904.470 168.680 1904.790 168.740 ; + LAYER via ; + RECT 1600.440 168.680 1600.700 168.940 ; + RECT 1904.500 168.680 1904.760 168.940 ; + LAYER met2 ; + RECT 1599.470 260.170 1599.750 264.000 ; + RECT 1599.470 260.030 1600.640 260.170 ; + RECT 1599.470 260.000 1599.750 260.030 ; + RECT 1600.500 168.970 1600.640 260.030 ; + RECT 1600.440 168.650 1600.700 168.970 ; + RECT 1904.500 168.650 1904.760 168.970 ; + RECT 1904.560 16.730 1904.700 168.650 ; + RECT 1904.560 16.590 1906.080 16.730 ; + RECT 1905.940 2.400 1906.080 16.590 ; + RECT 1905.730 -4.800 1906.290 2.400 ; +======= LAYER met2 ; RECT 1905.730 -4.800 1906.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[71] PIN la_data_out[72] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1617.430 244.020 1617.750 244.080 ; + RECT 1621.110 244.020 1621.430 244.080 ; + RECT 1617.430 243.880 1621.430 244.020 ; + RECT 1617.430 243.820 1617.750 243.880 ; + RECT 1621.110 243.820 1621.430 243.880 ; + RECT 1621.110 176.700 1621.430 176.760 ; + RECT 1918.270 176.700 1918.590 176.760 ; + RECT 1621.110 176.560 1918.590 176.700 ; + RECT 1621.110 176.500 1621.430 176.560 ; + RECT 1918.270 176.500 1918.590 176.560 ; + RECT 1918.270 2.960 1918.590 3.020 ; + RECT 1923.330 2.960 1923.650 3.020 ; + RECT 1918.270 2.820 1923.650 2.960 ; + RECT 1918.270 2.760 1918.590 2.820 ; + RECT 1923.330 2.760 1923.650 2.820 ; + LAYER via ; + RECT 1617.460 243.820 1617.720 244.080 ; + RECT 1621.140 243.820 1621.400 244.080 ; + RECT 1621.140 176.500 1621.400 176.760 ; + RECT 1918.300 176.500 1918.560 176.760 ; + RECT 1918.300 2.760 1918.560 3.020 ; + RECT 1923.360 2.760 1923.620 3.020 ; + LAYER met2 ; + RECT 1617.410 260.000 1617.690 264.000 ; + RECT 1617.520 244.110 1617.660 260.000 ; + RECT 1617.460 243.790 1617.720 244.110 ; + RECT 1621.140 243.790 1621.400 244.110 ; + RECT 1621.200 176.790 1621.340 243.790 ; + RECT 1621.140 176.470 1621.400 176.790 ; + RECT 1918.300 176.470 1918.560 176.790 ; + RECT 1918.360 3.050 1918.500 176.470 ; + RECT 1918.300 2.730 1918.560 3.050 ; + RECT 1923.360 2.730 1923.620 3.050 ; + RECT 1923.420 2.400 1923.560 2.730 ; + RECT 1923.210 -4.800 1923.770 2.400 ; +======= LAYER met2 ; RECT 1923.210 -4.800 1923.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[72] PIN la_data_out[73] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1635.370 244.020 1635.690 244.080 ; + RECT 1641.350 244.020 1641.670 244.080 ; + RECT 1635.370 243.880 1641.670 244.020 ; + RECT 1635.370 243.820 1635.690 243.880 ; + RECT 1641.350 243.820 1641.670 243.880 ; + RECT 1641.350 183.160 1641.670 183.220 ; + RECT 1938.970 183.160 1939.290 183.220 ; + RECT 1641.350 183.020 1939.290 183.160 ; + RECT 1641.350 182.960 1641.670 183.020 ; + RECT 1938.970 182.960 1939.290 183.020 ; + RECT 1938.970 2.960 1939.290 3.020 ; + RECT 1941.270 2.960 1941.590 3.020 ; + RECT 1938.970 2.820 1941.590 2.960 ; + RECT 1938.970 2.760 1939.290 2.820 ; + RECT 1941.270 2.760 1941.590 2.820 ; + LAYER via ; + RECT 1635.400 243.820 1635.660 244.080 ; + RECT 1641.380 243.820 1641.640 244.080 ; + RECT 1641.380 182.960 1641.640 183.220 ; + RECT 1939.000 182.960 1939.260 183.220 ; + RECT 1939.000 2.760 1939.260 3.020 ; + RECT 1941.300 2.760 1941.560 3.020 ; + LAYER met2 ; + RECT 1635.350 260.000 1635.630 264.000 ; + RECT 1635.460 244.110 1635.600 260.000 ; + RECT 1635.400 243.790 1635.660 244.110 ; + RECT 1641.380 243.790 1641.640 244.110 ; + RECT 1641.440 183.250 1641.580 243.790 ; + RECT 1641.380 182.930 1641.640 183.250 ; + RECT 1939.000 182.930 1939.260 183.250 ; + RECT 1939.060 3.050 1939.200 182.930 ; + RECT 1939.000 2.730 1939.260 3.050 ; + RECT 1941.300 2.730 1941.560 3.050 ; + RECT 1941.360 2.400 1941.500 2.730 ; + RECT 1941.150 -4.800 1941.710 2.400 ; +======= LAYER met2 ; RECT 1941.150 -4.800 1941.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[73] PIN la_data_out[74] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1655.610 197.440 1655.930 197.500 ; + RECT 1952.770 197.440 1953.090 197.500 ; + RECT 1655.610 197.300 1953.090 197.440 ; + RECT 1655.610 197.240 1655.930 197.300 ; + RECT 1952.770 197.240 1953.090 197.300 ; + RECT 1952.770 37.980 1953.090 38.040 ; + RECT 1959.210 37.980 1959.530 38.040 ; + RECT 1952.770 37.840 1959.530 37.980 ; + RECT 1952.770 37.780 1953.090 37.840 ; + RECT 1959.210 37.780 1959.530 37.840 ; + LAYER via ; + RECT 1655.640 197.240 1655.900 197.500 ; + RECT 1952.800 197.240 1953.060 197.500 ; + RECT 1952.800 37.780 1953.060 38.040 ; + RECT 1959.240 37.780 1959.500 38.040 ; + LAYER met2 ; + RECT 1653.290 260.170 1653.570 264.000 ; + RECT 1653.290 260.030 1655.840 260.170 ; + RECT 1653.290 260.000 1653.570 260.030 ; + RECT 1655.700 197.530 1655.840 260.030 ; + RECT 1655.640 197.210 1655.900 197.530 ; + RECT 1952.800 197.210 1953.060 197.530 ; + RECT 1952.860 38.070 1953.000 197.210 ; + RECT 1952.800 37.750 1953.060 38.070 ; + RECT 1959.240 37.750 1959.500 38.070 ; + RECT 1959.300 2.400 1959.440 37.750 ; + RECT 1959.090 -4.800 1959.650 2.400 ; +======= LAYER met2 ; RECT 1959.090 -4.800 1959.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[74] PIN la_data_out[75] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1973.545 48.365 1973.715 96.475 ; + LAYER mcon ; + RECT 1973.545 96.305 1973.715 96.475 ; + LAYER met1 ; + RECT 1671.250 244.020 1671.570 244.080 ; + RECT 1676.310 244.020 1676.630 244.080 ; + RECT 1671.250 243.880 1676.630 244.020 ; + RECT 1671.250 243.820 1671.570 243.880 ; + RECT 1676.310 243.820 1676.630 243.880 ; + RECT 1676.310 114.140 1676.630 114.200 ; + RECT 1973.930 114.140 1974.250 114.200 ; + RECT 1676.310 114.000 1974.250 114.140 ; + RECT 1676.310 113.940 1676.630 114.000 ; + RECT 1973.930 113.940 1974.250 114.000 ; + RECT 1973.470 96.460 1973.790 96.520 ; + RECT 1973.275 96.320 1973.790 96.460 ; + RECT 1973.470 96.260 1973.790 96.320 ; + RECT 1973.485 48.520 1973.775 48.565 ; + RECT 1977.150 48.520 1977.470 48.580 ; + RECT 1973.485 48.380 1977.470 48.520 ; + RECT 1973.485 48.335 1973.775 48.380 ; + RECT 1977.150 48.320 1977.470 48.380 ; + LAYER via ; + RECT 1671.280 243.820 1671.540 244.080 ; + RECT 1676.340 243.820 1676.600 244.080 ; + RECT 1676.340 113.940 1676.600 114.200 ; + RECT 1973.960 113.940 1974.220 114.200 ; + RECT 1973.500 96.260 1973.760 96.520 ; + RECT 1977.180 48.320 1977.440 48.580 ; + LAYER met2 ; + RECT 1671.230 260.000 1671.510 264.000 ; + RECT 1671.340 244.110 1671.480 260.000 ; + RECT 1671.280 243.790 1671.540 244.110 ; + RECT 1676.340 243.790 1676.600 244.110 ; + RECT 1676.400 114.230 1676.540 243.790 ; + RECT 1676.340 113.910 1676.600 114.230 ; + RECT 1973.960 113.910 1974.220 114.230 ; + RECT 1974.020 96.970 1974.160 113.910 ; + RECT 1973.560 96.830 1974.160 96.970 ; + RECT 1973.560 96.550 1973.700 96.830 ; + RECT 1973.500 96.230 1973.760 96.550 ; + RECT 1977.180 48.290 1977.440 48.610 ; + RECT 1977.240 2.400 1977.380 48.290 ; + RECT 1977.030 -4.800 1977.590 2.400 ; +======= LAYER met2 ; RECT 1977.030 -4.800 1977.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[75] PIN la_data_out[76] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1690.110 224.640 1690.430 224.700 ; + RECT 1994.170 224.640 1994.490 224.700 ; + RECT 1690.110 224.500 1994.490 224.640 ; + RECT 1690.110 224.440 1690.430 224.500 ; + RECT 1994.170 224.440 1994.490 224.500 ; + LAYER via ; + RECT 1690.140 224.440 1690.400 224.700 ; + RECT 1994.200 224.440 1994.460 224.700 ; + LAYER met2 ; + RECT 1689.170 260.170 1689.450 264.000 ; + RECT 1689.170 260.030 1690.340 260.170 ; + RECT 1689.170 260.000 1689.450 260.030 ; + RECT 1690.200 224.730 1690.340 260.030 ; + RECT 1690.140 224.410 1690.400 224.730 ; + RECT 1994.200 224.410 1994.460 224.730 ; + RECT 1994.260 16.730 1994.400 224.410 ; + RECT 1994.260 16.590 1995.320 16.730 ; + RECT 1995.180 2.400 1995.320 16.590 ; + RECT 1994.970 -4.800 1995.530 2.400 ; +======= LAYER met2 ; RECT 1994.970 -4.800 1995.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[76] PIN la_data_out[77] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1710.810 189.620 1711.130 189.680 ; + RECT 2007.970 189.620 2008.290 189.680 ; + RECT 1710.810 189.480 2008.290 189.620 ; + RECT 1710.810 189.420 1711.130 189.480 ; + RECT 2007.970 189.420 2008.290 189.480 ; + LAYER via ; + RECT 1710.840 189.420 1711.100 189.680 ; + RECT 2008.000 189.420 2008.260 189.680 ; + LAYER met2 ; + RECT 1707.110 260.170 1707.390 264.000 ; + RECT 1707.110 260.030 1711.040 260.170 ; + RECT 1707.110 260.000 1707.390 260.030 ; + RECT 1710.900 189.710 1711.040 260.030 ; + RECT 1710.840 189.390 1711.100 189.710 ; + RECT 2008.000 189.390 2008.260 189.710 ; + RECT 2008.060 16.730 2008.200 189.390 ; + RECT 2008.060 16.590 2012.800 16.730 ; + RECT 2012.660 2.400 2012.800 16.590 ; + RECT 2012.450 -4.800 2013.010 2.400 ; +======= LAYER met2 ; RECT 2012.450 -4.800 2013.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[77] PIN la_data_out[78] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1724.610 30.840 1724.930 30.900 ; + RECT 2030.510 30.840 2030.830 30.900 ; + RECT 1724.610 30.700 2030.830 30.840 ; + RECT 1724.610 30.640 1724.930 30.700 ; + RECT 2030.510 30.640 2030.830 30.700 ; + LAYER via ; + RECT 1724.640 30.640 1724.900 30.900 ; + RECT 2030.540 30.640 2030.800 30.900 ; + LAYER met2 ; + RECT 1724.590 260.000 1724.870 264.000 ; + RECT 1724.700 30.930 1724.840 260.000 ; + RECT 1724.640 30.610 1724.900 30.930 ; + RECT 2030.540 30.610 2030.800 30.930 ; + RECT 2030.600 2.400 2030.740 30.610 ; + RECT 2030.390 -4.800 2030.950 2.400 ; +======= LAYER met2 ; RECT 2030.390 -4.800 2030.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[78] PIN la_data_out[79] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1745.310 148.140 1745.630 148.200 ; + RECT 2042.930 148.140 2043.250 148.200 ; + RECT 1745.310 148.000 2043.250 148.140 ; + RECT 1745.310 147.940 1745.630 148.000 ; + RECT 2042.930 147.940 2043.250 148.000 ; + RECT 2042.930 62.120 2043.250 62.180 ; + RECT 2048.450 62.120 2048.770 62.180 ; + RECT 2042.930 61.980 2048.770 62.120 ; + RECT 2042.930 61.920 2043.250 61.980 ; + RECT 2048.450 61.920 2048.770 61.980 ; + LAYER via ; + RECT 1745.340 147.940 1745.600 148.200 ; + RECT 2042.960 147.940 2043.220 148.200 ; + RECT 2042.960 61.920 2043.220 62.180 ; + RECT 2048.480 61.920 2048.740 62.180 ; + LAYER met2 ; + RECT 1742.530 260.170 1742.810 264.000 ; + RECT 1742.530 260.030 1745.540 260.170 ; + RECT 1742.530 260.000 1742.810 260.030 ; + RECT 1745.400 148.230 1745.540 260.030 ; + RECT 1745.340 147.910 1745.600 148.230 ; + RECT 2042.960 147.910 2043.220 148.230 ; + RECT 2043.020 62.210 2043.160 147.910 ; + RECT 2042.960 61.890 2043.220 62.210 ; + RECT 2048.480 61.890 2048.740 62.210 ; + RECT 2048.540 2.400 2048.680 61.890 ; + RECT 2048.330 -4.800 2048.890 2.400 ; +======= LAYER met2 ; RECT 2048.330 -4.800 2048.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[79] PIN la_data_out[7] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 455.470 244.020 455.790 244.080 ; + RECT 461.450 244.020 461.770 244.080 ; + RECT 455.470 243.880 461.770 244.020 ; + RECT 455.470 243.820 455.790 243.880 ; + RECT 461.450 243.820 461.770 243.880 ; + RECT 461.450 19.960 461.770 20.020 ; + RECT 763.670 19.960 763.990 20.020 ; + RECT 461.450 19.820 763.990 19.960 ; + RECT 461.450 19.760 461.770 19.820 ; + RECT 763.670 19.760 763.990 19.820 ; + LAYER via ; + RECT 455.500 243.820 455.760 244.080 ; + RECT 461.480 243.820 461.740 244.080 ; + RECT 461.480 19.760 461.740 20.020 ; + RECT 763.700 19.760 763.960 20.020 ; + LAYER met2 ; + RECT 455.450 260.000 455.730 264.000 ; + RECT 455.560 244.110 455.700 260.000 ; + RECT 455.500 243.790 455.760 244.110 ; + RECT 461.480 243.790 461.740 244.110 ; + RECT 461.540 20.050 461.680 243.790 ; + RECT 461.480 19.730 461.740 20.050 ; + RECT 763.700 19.730 763.960 20.050 ; + RECT 763.760 2.400 763.900 19.730 ; + RECT 763.550 -4.800 764.110 2.400 ; +======= LAYER met2 ; RECT 763.550 -4.800 764.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[7] PIN la_data_out[80] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1760.490 244.020 1760.810 244.080 ; + RECT 1766.010 244.020 1766.330 244.080 ; + RECT 1760.490 243.880 1766.330 244.020 ; + RECT 1760.490 243.820 1760.810 243.880 ; + RECT 1766.010 243.820 1766.330 243.880 ; + RECT 1766.010 141.680 1766.330 141.740 ; + RECT 2063.170 141.680 2063.490 141.740 ; + RECT 1766.010 141.540 2063.490 141.680 ; + RECT 1766.010 141.480 1766.330 141.540 ; + RECT 2063.170 141.480 2063.490 141.540 ; + RECT 2063.170 62.120 2063.490 62.180 ; + RECT 2066.390 62.120 2066.710 62.180 ; + RECT 2063.170 61.980 2066.710 62.120 ; + RECT 2063.170 61.920 2063.490 61.980 ; + RECT 2066.390 61.920 2066.710 61.980 ; + LAYER via ; + RECT 1760.520 243.820 1760.780 244.080 ; + RECT 1766.040 243.820 1766.300 244.080 ; + RECT 1766.040 141.480 1766.300 141.740 ; + RECT 2063.200 141.480 2063.460 141.740 ; + RECT 2063.200 61.920 2063.460 62.180 ; + RECT 2066.420 61.920 2066.680 62.180 ; + LAYER met2 ; + RECT 1760.470 260.000 1760.750 264.000 ; + RECT 1760.580 244.110 1760.720 260.000 ; + RECT 1760.520 243.790 1760.780 244.110 ; + RECT 1766.040 243.790 1766.300 244.110 ; + RECT 1766.100 141.770 1766.240 243.790 ; + RECT 1766.040 141.450 1766.300 141.770 ; + RECT 2063.200 141.450 2063.460 141.770 ; + RECT 2063.260 62.210 2063.400 141.450 ; + RECT 2063.200 61.890 2063.460 62.210 ; + RECT 2066.420 61.890 2066.680 62.210 ; + RECT 2066.480 2.400 2066.620 61.890 ; + RECT 2066.270 -4.800 2066.830 2.400 ; +======= LAYER met2 ; RECT 2066.270 -4.800 2066.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[80] PIN la_data_out[81] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1779.810 203.560 1780.130 203.620 ; + RECT 2084.330 203.560 2084.650 203.620 ; + RECT 1779.810 203.420 2084.650 203.560 ; + RECT 1779.810 203.360 1780.130 203.420 ; + RECT 2084.330 203.360 2084.650 203.420 ; + LAYER via ; + RECT 1779.840 203.360 1780.100 203.620 ; + RECT 2084.360 203.360 2084.620 203.620 ; + LAYER met2 ; + RECT 1778.410 260.170 1778.690 264.000 ; + RECT 1778.410 260.030 1780.040 260.170 ; + RECT 1778.410 260.000 1778.690 260.030 ; + RECT 1779.900 203.650 1780.040 260.030 ; + RECT 1779.840 203.330 1780.100 203.650 ; + RECT 2084.360 203.330 2084.620 203.650 ; + RECT 2084.420 2.400 2084.560 203.330 ; + RECT 2084.210 -4.800 2084.770 2.400 ; +======= LAYER met2 ; RECT 2084.210 -4.800 2084.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[81] PIN la_data_out[82] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1796.370 244.020 1796.690 244.080 ; + RECT 1800.510 244.020 1800.830 244.080 ; + RECT 1796.370 243.880 1800.830 244.020 ; + RECT 1796.370 243.820 1796.690 243.880 ; + RECT 1800.510 243.820 1800.830 243.880 ; + RECT 1800.510 120.940 1800.830 121.000 ; + RECT 2097.670 120.940 2097.990 121.000 ; + RECT 1800.510 120.800 2097.990 120.940 ; + RECT 1800.510 120.740 1800.830 120.800 ; + RECT 2097.670 120.740 2097.990 120.800 ; + LAYER via ; + RECT 1796.400 243.820 1796.660 244.080 ; + RECT 1800.540 243.820 1800.800 244.080 ; + RECT 1800.540 120.740 1800.800 121.000 ; + RECT 2097.700 120.740 2097.960 121.000 ; + LAYER met2 ; + RECT 1796.350 260.000 1796.630 264.000 ; + RECT 1796.460 244.110 1796.600 260.000 ; + RECT 1796.400 243.790 1796.660 244.110 ; + RECT 1800.540 243.790 1800.800 244.110 ; + RECT 1800.600 121.030 1800.740 243.790 ; + RECT 1800.540 120.710 1800.800 121.030 ; + RECT 2097.700 120.710 2097.960 121.030 ; + RECT 2097.760 16.730 2097.900 120.710 ; + RECT 2097.760 16.590 2102.040 16.730 ; + RECT 2101.900 2.400 2102.040 16.590 ; + RECT 2101.690 -4.800 2102.250 2.400 ; +======= LAYER met2 ; RECT 2101.690 -4.800 2102.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[82] PIN la_data_out[83] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1813.850 155.280 1814.170 155.340 ; + RECT 2118.370 155.280 2118.690 155.340 ; + RECT 1813.850 155.140 2118.690 155.280 ; + RECT 1813.850 155.080 1814.170 155.140 ; + RECT 2118.370 155.080 2118.690 155.140 ; + LAYER via ; + RECT 1813.880 155.080 1814.140 155.340 ; + RECT 2118.400 155.080 2118.660 155.340 ; + LAYER met2 ; + RECT 1814.290 260.170 1814.570 264.000 ; + RECT 1813.940 260.030 1814.570 260.170 ; + RECT 1813.940 155.370 1814.080 260.030 ; + RECT 1814.290 260.000 1814.570 260.030 ; + RECT 1813.880 155.050 1814.140 155.370 ; + RECT 2118.400 155.050 2118.660 155.370 ; + RECT 2118.460 16.730 2118.600 155.050 ; + RECT 2118.460 16.590 2119.980 16.730 ; + RECT 2119.840 2.400 2119.980 16.590 ; + RECT 2119.630 -4.800 2120.190 2.400 ; +======= LAYER met2 ; RECT 2119.630 -4.800 2120.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[83] PIN la_data_out[84] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1835.010 162.080 1835.330 162.140 ; + RECT 2132.170 162.080 2132.490 162.140 ; + RECT 1835.010 161.940 2132.490 162.080 ; + RECT 1835.010 161.880 1835.330 161.940 ; + RECT 2132.170 161.880 2132.490 161.940 ; + LAYER via ; + RECT 1835.040 161.880 1835.300 162.140 ; + RECT 2132.200 161.880 2132.460 162.140 ; + LAYER met2 ; + RECT 1832.230 260.170 1832.510 264.000 ; + RECT 1832.230 260.030 1835.240 260.170 ; + RECT 1832.230 260.000 1832.510 260.030 ; + RECT 1835.100 162.170 1835.240 260.030 ; + RECT 1835.040 161.850 1835.300 162.170 ; + RECT 2132.200 161.850 2132.460 162.170 ; + RECT 2132.260 16.730 2132.400 161.850 ; + RECT 2132.260 16.590 2137.920 16.730 ; + RECT 2137.780 2.400 2137.920 16.590 ; + RECT 2137.570 -4.800 2138.130 2.400 ; +======= LAYER met2 ; RECT 2137.570 -4.800 2138.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[84] PIN la_data_out[85] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 2155.705 2.805 2155.875 48.195 ; + LAYER mcon ; + RECT 2155.705 48.025 2155.875 48.195 ; + LAYER met1 ; + RECT 1849.730 244.020 1850.050 244.080 ; + RECT 1859.390 244.020 1859.710 244.080 ; + RECT 1849.730 243.880 1859.710 244.020 ; + RECT 1849.730 243.820 1850.050 243.880 ; + RECT 1859.390 243.820 1859.710 243.880 ; + RECT 1859.390 169.220 1859.710 169.280 ; + RECT 2152.870 169.220 2153.190 169.280 ; + RECT 1859.390 169.080 2153.190 169.220 ; + RECT 1859.390 169.020 1859.710 169.080 ; + RECT 2152.870 169.020 2153.190 169.080 ; + RECT 2152.870 48.180 2153.190 48.240 ; + RECT 2155.645 48.180 2155.935 48.225 ; + RECT 2152.870 48.040 2155.935 48.180 ; + RECT 2152.870 47.980 2153.190 48.040 ; + RECT 2155.645 47.995 2155.935 48.040 ; + RECT 2155.630 2.960 2155.950 3.020 ; + RECT 2155.435 2.820 2155.950 2.960 ; + RECT 2155.630 2.760 2155.950 2.820 ; + LAYER via ; + RECT 1849.760 243.820 1850.020 244.080 ; + RECT 1859.420 243.820 1859.680 244.080 ; + RECT 1859.420 169.020 1859.680 169.280 ; + RECT 2152.900 169.020 2153.160 169.280 ; + RECT 2152.900 47.980 2153.160 48.240 ; + RECT 2155.660 2.760 2155.920 3.020 ; + LAYER met2 ; + RECT 1849.710 260.000 1849.990 264.000 ; + RECT 1849.820 244.110 1849.960 260.000 ; + RECT 1849.760 243.790 1850.020 244.110 ; + RECT 1859.420 243.790 1859.680 244.110 ; + RECT 1859.480 169.310 1859.620 243.790 ; + RECT 1859.420 168.990 1859.680 169.310 ; + RECT 2152.900 168.990 2153.160 169.310 ; + RECT 2152.960 48.270 2153.100 168.990 ; + RECT 2152.900 47.950 2153.160 48.270 ; + RECT 2155.660 2.730 2155.920 3.050 ; + RECT 2155.720 2.400 2155.860 2.730 ; + RECT 2155.510 -4.800 2156.070 2.400 ; +======= LAYER met2 ; RECT 2155.510 -4.800 2156.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[85] PIN la_data_out[86] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1869.510 176.360 1869.830 176.420 ; + RECT 2166.670 176.360 2166.990 176.420 ; + RECT 1869.510 176.220 2166.990 176.360 ; + RECT 1869.510 176.160 1869.830 176.220 ; + RECT 2166.670 176.160 2166.990 176.220 ; + RECT 2166.670 38.320 2166.990 38.380 ; + RECT 2173.110 38.320 2173.430 38.380 ; + RECT 2166.670 38.180 2173.430 38.320 ; + RECT 2166.670 38.120 2166.990 38.180 ; + RECT 2173.110 38.120 2173.430 38.180 ; + LAYER via ; + RECT 1869.540 176.160 1869.800 176.420 ; + RECT 2166.700 176.160 2166.960 176.420 ; + RECT 2166.700 38.120 2166.960 38.380 ; + RECT 2173.140 38.120 2173.400 38.380 ; + LAYER met2 ; + RECT 1867.650 260.170 1867.930 264.000 ; + RECT 1867.650 260.030 1869.740 260.170 ; + RECT 1867.650 260.000 1867.930 260.030 ; + RECT 1869.600 176.450 1869.740 260.030 ; + RECT 1869.540 176.130 1869.800 176.450 ; + RECT 2166.700 176.130 2166.960 176.450 ; + RECT 2166.760 38.410 2166.900 176.130 ; + RECT 2166.700 38.090 2166.960 38.410 ; + RECT 2173.140 38.090 2173.400 38.410 ; + RECT 2173.200 2.400 2173.340 38.090 ; + RECT 2172.990 -4.800 2173.550 2.400 ; +======= LAYER met2 ; RECT 2172.990 -4.800 2173.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[86] PIN la_data_out[87] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1885.610 244.020 1885.930 244.080 ; + RECT 1890.210 244.020 1890.530 244.080 ; + RECT 1885.610 243.880 1890.530 244.020 ; + RECT 1885.610 243.820 1885.930 243.880 ; + RECT 1890.210 243.820 1890.530 243.880 ; + RECT 1890.210 182.820 1890.530 182.880 ; + RECT 2187.370 182.820 2187.690 182.880 ; + RECT 1890.210 182.680 2187.690 182.820 ; + RECT 1890.210 182.620 1890.530 182.680 ; + RECT 2187.370 182.620 2187.690 182.680 ; + LAYER via ; + RECT 1885.640 243.820 1885.900 244.080 ; + RECT 1890.240 243.820 1890.500 244.080 ; + RECT 1890.240 182.620 1890.500 182.880 ; + RECT 2187.400 182.620 2187.660 182.880 ; + LAYER met2 ; + RECT 1885.590 260.000 1885.870 264.000 ; + RECT 1885.700 244.110 1885.840 260.000 ; + RECT 1885.640 243.790 1885.900 244.110 ; + RECT 1890.240 243.790 1890.500 244.110 ; + RECT 1890.300 182.910 1890.440 243.790 ; + RECT 1890.240 182.590 1890.500 182.910 ; + RECT 2187.400 182.590 2187.660 182.910 ; + RECT 2187.460 16.730 2187.600 182.590 ; + RECT 2187.460 16.590 2191.280 16.730 ; + RECT 2191.140 2.400 2191.280 16.590 ; + RECT 2190.930 -4.800 2191.490 2.400 ; +======= LAYER met2 ; RECT 2190.930 -4.800 2191.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[87] PIN la_data_out[88] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1903.550 196.760 1903.870 196.820 ; + RECT 2208.070 196.760 2208.390 196.820 ; + RECT 1903.550 196.620 2208.390 196.760 ; + RECT 1903.550 196.560 1903.870 196.620 ; + RECT 2208.070 196.560 2208.390 196.620 ; + LAYER via ; + RECT 1903.580 196.560 1903.840 196.820 ; + RECT 2208.100 196.560 2208.360 196.820 ; + LAYER met2 ; + RECT 1903.530 260.000 1903.810 264.000 ; + RECT 1903.640 196.850 1903.780 260.000 ; + RECT 1903.580 196.530 1903.840 196.850 ; + RECT 2208.100 196.530 2208.360 196.850 ; + RECT 2208.160 16.730 2208.300 196.530 ; + RECT 2208.160 16.590 2209.220 16.730 ; + RECT 2209.080 2.400 2209.220 16.590 ; + RECT 2208.870 -4.800 2209.430 2.400 ; +======= LAYER met2 ; RECT 2208.870 -4.800 2209.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[88] PIN la_data_out[89] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1924.710 224.300 1925.030 224.360 ; + RECT 2221.870 224.300 2222.190 224.360 ; + RECT 1924.710 224.160 2222.190 224.300 ; + RECT 1924.710 224.100 1925.030 224.160 ; + RECT 2221.870 224.100 2222.190 224.160 ; + LAYER via ; + RECT 1924.740 224.100 1925.000 224.360 ; + RECT 2221.900 224.100 2222.160 224.360 ; + LAYER met2 ; + RECT 1921.470 260.170 1921.750 264.000 ; + RECT 1921.470 260.030 1924.940 260.170 ; + RECT 1921.470 260.000 1921.750 260.030 ; + RECT 1924.800 224.390 1924.940 260.030 ; + RECT 1924.740 224.070 1925.000 224.390 ; + RECT 2221.900 224.070 2222.160 224.390 ; + RECT 2221.960 16.730 2222.100 224.070 ; + RECT 2221.960 16.590 2227.160 16.730 ; + RECT 2227.020 2.400 2227.160 16.590 ; + RECT 2226.810 -4.800 2227.370 2.400 ; +======= LAYER met2 ; RECT 2226.810 -4.800 2227.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[89] PIN la_data_out[8] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 475.710 17.240 476.030 17.300 ; + RECT 781.610 17.240 781.930 17.300 ; + RECT 475.710 17.100 781.930 17.240 ; + RECT 475.710 17.040 476.030 17.100 ; + RECT 781.610 17.040 781.930 17.100 ; + LAYER via ; + RECT 475.740 17.040 476.000 17.300 ; + RECT 781.640 17.040 781.900 17.300 ; + LAYER met2 ; + RECT 473.390 260.170 473.670 264.000 ; + RECT 473.390 260.030 475.940 260.170 ; + RECT 473.390 260.000 473.670 260.030 ; + RECT 475.800 17.330 475.940 260.030 ; + RECT 475.740 17.010 476.000 17.330 ; + RECT 781.640 17.010 781.900 17.330 ; + RECT 781.700 2.400 781.840 17.010 ; + RECT 781.490 -4.800 782.050 2.400 ; +======= LAYER met2 ; RECT 781.490 -4.800 782.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[8] PIN la_data_out[90] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1939.430 243.340 1939.750 243.400 ; + RECT 1945.410 243.340 1945.730 243.400 ; + RECT 1939.430 243.200 1945.730 243.340 ; + RECT 1939.430 243.140 1939.750 243.200 ; + RECT 1945.410 243.140 1945.730 243.200 ; + RECT 1945.410 189.960 1945.730 190.020 ; + RECT 2242.570 189.960 2242.890 190.020 ; + RECT 1945.410 189.820 2242.890 189.960 ; + RECT 1945.410 189.760 1945.730 189.820 ; + RECT 2242.570 189.760 2242.890 189.820 ; + LAYER via ; + RECT 1939.460 243.140 1939.720 243.400 ; + RECT 1945.440 243.140 1945.700 243.400 ; + RECT 1945.440 189.760 1945.700 190.020 ; + RECT 2242.600 189.760 2242.860 190.020 ; + LAYER met2 ; + RECT 1939.410 260.000 1939.690 264.000 ; + RECT 1939.520 243.430 1939.660 260.000 ; + RECT 1939.460 243.110 1939.720 243.430 ; + RECT 1945.440 243.110 1945.700 243.430 ; + RECT 1945.500 190.050 1945.640 243.110 ; + RECT 1945.440 189.730 1945.700 190.050 ; + RECT 2242.600 189.730 2242.860 190.050 ; + RECT 2242.660 16.730 2242.800 189.730 ; + RECT 2242.660 16.590 2245.100 16.730 ; + RECT 2244.960 2.400 2245.100 16.590 ; + RECT 2244.750 -4.800 2245.310 2.400 ; +======= LAYER met2 ; RECT 2244.750 -4.800 2245.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[90] PIN la_data_out[91] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1959.210 134.880 1959.530 134.940 ; + RECT 2256.370 134.880 2256.690 134.940 ; + RECT 1959.210 134.740 2256.690 134.880 ; + RECT 1959.210 134.680 1959.530 134.740 ; + RECT 2256.370 134.680 2256.690 134.740 ; + RECT 2256.370 18.260 2256.690 18.320 ; + RECT 2262.350 18.260 2262.670 18.320 ; + RECT 2256.370 18.120 2262.670 18.260 ; + RECT 2256.370 18.060 2256.690 18.120 ; + RECT 2262.350 18.060 2262.670 18.120 ; + LAYER via ; + RECT 1959.240 134.680 1959.500 134.940 ; + RECT 2256.400 134.680 2256.660 134.940 ; + RECT 2256.400 18.060 2256.660 18.320 ; + RECT 2262.380 18.060 2262.640 18.320 ; + LAYER met2 ; + RECT 1957.350 260.170 1957.630 264.000 ; + RECT 1957.350 260.030 1959.440 260.170 ; + RECT 1957.350 260.000 1957.630 260.030 ; + RECT 1959.300 134.970 1959.440 260.030 ; + RECT 1959.240 134.650 1959.500 134.970 ; + RECT 2256.400 134.650 2256.660 134.970 ; + RECT 2256.460 18.350 2256.600 134.650 ; + RECT 2256.400 18.030 2256.660 18.350 ; + RECT 2262.380 18.030 2262.640 18.350 ; + RECT 2262.440 2.400 2262.580 18.030 ; + RECT 2262.230 -4.800 2262.790 2.400 ; +======= LAYER met2 ; RECT 2262.230 -4.800 2262.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[91] PIN la_data_out[92] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1974.850 244.020 1975.170 244.080 ; + RECT 1979.910 244.020 1980.230 244.080 ; + RECT 1974.850 243.880 1980.230 244.020 ; + RECT 1974.850 243.820 1975.170 243.880 ; + RECT 1979.910 243.820 1980.230 243.880 ; + RECT 1979.910 128.080 1980.230 128.140 ; + RECT 2277.070 128.080 2277.390 128.140 ; + RECT 1979.910 127.940 2277.390 128.080 ; + RECT 1979.910 127.880 1980.230 127.940 ; + RECT 2277.070 127.880 2277.390 127.940 ; + RECT 2277.070 2.960 2277.390 3.020 ; + RECT 2280.290 2.960 2280.610 3.020 ; + RECT 2277.070 2.820 2280.610 2.960 ; + RECT 2277.070 2.760 2277.390 2.820 ; + RECT 2280.290 2.760 2280.610 2.820 ; + LAYER via ; + RECT 1974.880 243.820 1975.140 244.080 ; + RECT 1979.940 243.820 1980.200 244.080 ; + RECT 1979.940 127.880 1980.200 128.140 ; + RECT 2277.100 127.880 2277.360 128.140 ; + RECT 2277.100 2.760 2277.360 3.020 ; + RECT 2280.320 2.760 2280.580 3.020 ; + LAYER met2 ; + RECT 1974.830 260.000 1975.110 264.000 ; + RECT 1974.940 244.110 1975.080 260.000 ; + RECT 1974.880 243.790 1975.140 244.110 ; + RECT 1979.940 243.790 1980.200 244.110 ; + RECT 1980.000 128.170 1980.140 243.790 ; + RECT 1979.940 127.850 1980.200 128.170 ; + RECT 2277.100 127.850 2277.360 128.170 ; + RECT 2277.160 3.050 2277.300 127.850 ; + RECT 2277.100 2.730 2277.360 3.050 ; + RECT 2280.320 2.730 2280.580 3.050 ; + RECT 2280.380 2.400 2280.520 2.730 ; + RECT 2280.170 -4.800 2280.730 2.400 ; +======= LAYER met2 ; RECT 2280.170 -4.800 2280.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[92] PIN la_data_out[93] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1993.710 141.340 1994.030 141.400 ; + RECT 2298.230 141.340 2298.550 141.400 ; + RECT 1993.710 141.200 2298.550 141.340 ; + RECT 1993.710 141.140 1994.030 141.200 ; + RECT 2298.230 141.140 2298.550 141.200 ; + LAYER via ; + RECT 1993.740 141.140 1994.000 141.400 ; + RECT 2298.260 141.140 2298.520 141.400 ; + LAYER met2 ; + RECT 1992.770 260.170 1993.050 264.000 ; + RECT 1992.770 260.030 1993.940 260.170 ; + RECT 1992.770 260.000 1993.050 260.030 ; + RECT 1993.800 141.430 1993.940 260.030 ; + RECT 1993.740 141.110 1994.000 141.430 ; + RECT 2298.260 141.110 2298.520 141.430 ; + RECT 2298.320 2.400 2298.460 141.110 ; + RECT 2298.110 -4.800 2298.670 2.400 ; +======= LAYER met2 ; RECT 2298.110 -4.800 2298.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[93] PIN la_data_out[94] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2014.410 148.480 2014.730 148.540 ; + RECT 2311.570 148.480 2311.890 148.540 ; + RECT 2014.410 148.340 2311.890 148.480 ; + RECT 2014.410 148.280 2014.730 148.340 ; + RECT 2311.570 148.280 2311.890 148.340 ; + LAYER via ; + RECT 2014.440 148.280 2014.700 148.540 ; + RECT 2311.600 148.280 2311.860 148.540 ; + LAYER met2 ; + RECT 2010.710 260.170 2010.990 264.000 ; + RECT 2010.710 260.030 2014.640 260.170 ; + RECT 2010.710 260.000 2010.990 260.030 ; + RECT 2014.500 148.570 2014.640 260.030 ; + RECT 2014.440 148.250 2014.700 148.570 ; + RECT 2311.600 148.250 2311.860 148.570 ; + RECT 2311.660 16.730 2311.800 148.250 ; + RECT 2311.660 16.590 2316.400 16.730 ; + RECT 2316.260 2.400 2316.400 16.590 ; + RECT 2316.050 -4.800 2316.610 2.400 ; +======= LAYER met2 ; RECT 2316.050 -4.800 2316.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[94] PIN la_data_out[95] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2028.670 244.020 2028.990 244.080 ; + RECT 2034.650 244.020 2034.970 244.080 ; + RECT 2028.670 243.880 2034.970 244.020 ; + RECT 2028.670 243.820 2028.990 243.880 ; + RECT 2034.650 243.820 2034.970 243.880 ; + RECT 2034.650 176.020 2034.970 176.080 ; + RECT 2332.270 176.020 2332.590 176.080 ; + RECT 2034.650 175.880 2332.590 176.020 ; + RECT 2034.650 175.820 2034.970 175.880 ; + RECT 2332.270 175.820 2332.590 175.880 ; + LAYER via ; + RECT 2028.700 243.820 2028.960 244.080 ; + RECT 2034.680 243.820 2034.940 244.080 ; + RECT 2034.680 175.820 2034.940 176.080 ; + RECT 2332.300 175.820 2332.560 176.080 ; + LAYER met2 ; + RECT 2028.650 260.000 2028.930 264.000 ; + RECT 2028.760 244.110 2028.900 260.000 ; + RECT 2028.700 243.790 2028.960 244.110 ; + RECT 2034.680 243.790 2034.940 244.110 ; + RECT 2034.740 176.110 2034.880 243.790 ; + RECT 2034.680 175.790 2034.940 176.110 ; + RECT 2332.300 175.790 2332.560 176.110 ; + RECT 2332.360 16.730 2332.500 175.790 ; + RECT 2332.360 16.590 2334.340 16.730 ; + RECT 2334.200 2.400 2334.340 16.590 ; + RECT 2333.990 -4.800 2334.550 2.400 ; +======= LAYER met2 ; RECT 2333.990 -4.800 2334.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[95] PIN la_data_out[96] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2048.910 183.160 2049.230 183.220 ; + RECT 2346.070 183.160 2346.390 183.220 ; + RECT 2048.910 183.020 2346.390 183.160 ; + RECT 2048.910 182.960 2049.230 183.020 ; + RECT 2346.070 182.960 2346.390 183.020 ; + LAYER via ; + RECT 2048.940 182.960 2049.200 183.220 ; + RECT 2346.100 182.960 2346.360 183.220 ; + LAYER met2 ; + RECT 2046.590 260.170 2046.870 264.000 ; + RECT 2046.590 260.030 2049.140 260.170 ; + RECT 2046.590 260.000 2046.870 260.030 ; + RECT 2049.000 183.250 2049.140 260.030 ; + RECT 2048.940 182.930 2049.200 183.250 ; + RECT 2346.100 182.930 2346.360 183.250 ; + RECT 2346.160 16.730 2346.300 182.930 ; + RECT 2346.160 16.590 2351.820 16.730 ; + RECT 2351.680 2.400 2351.820 16.590 ; + RECT 2351.470 -4.800 2352.030 2.400 ; +======= LAYER met2 ; RECT 2351.470 -4.800 2352.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[96] PIN la_data_out[97] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2064.550 244.020 2064.870 244.080 ; + RECT 2069.610 244.020 2069.930 244.080 ; + RECT 2064.550 243.880 2069.930 244.020 ; + RECT 2064.550 243.820 2064.870 243.880 ; + RECT 2069.610 243.820 2069.930 243.880 ; + RECT 2069.610 162.420 2069.930 162.480 ; + RECT 2366.770 162.420 2367.090 162.480 ; + RECT 2069.610 162.280 2367.090 162.420 ; + RECT 2069.610 162.220 2069.930 162.280 ; + RECT 2366.770 162.220 2367.090 162.280 ; + RECT 2366.770 2.960 2367.090 3.020 ; + RECT 2369.530 2.960 2369.850 3.020 ; + RECT 2366.770 2.820 2369.850 2.960 ; + RECT 2366.770 2.760 2367.090 2.820 ; + RECT 2369.530 2.760 2369.850 2.820 ; + LAYER via ; + RECT 2064.580 243.820 2064.840 244.080 ; + RECT 2069.640 243.820 2069.900 244.080 ; + RECT 2069.640 162.220 2069.900 162.480 ; + RECT 2366.800 162.220 2367.060 162.480 ; + RECT 2366.800 2.760 2367.060 3.020 ; + RECT 2369.560 2.760 2369.820 3.020 ; + LAYER met2 ; + RECT 2064.530 260.000 2064.810 264.000 ; + RECT 2064.640 244.110 2064.780 260.000 ; + RECT 2064.580 243.790 2064.840 244.110 ; + RECT 2069.640 243.790 2069.900 244.110 ; + RECT 2069.700 162.510 2069.840 243.790 ; + RECT 2069.640 162.190 2069.900 162.510 ; + RECT 2366.800 162.190 2367.060 162.510 ; + RECT 2366.860 3.050 2367.000 162.190 ; + RECT 2366.800 2.730 2367.060 3.050 ; + RECT 2369.560 2.730 2369.820 3.050 ; + RECT 2369.620 2.400 2369.760 2.730 ; + RECT 2369.410 -4.800 2369.970 2.400 ; +======= LAYER met2 ; RECT 2369.410 -4.800 2369.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[97] PIN la_data_out[98] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2083.410 51.580 2083.730 51.640 ; + RECT 2387.930 51.580 2388.250 51.640 ; + RECT 2083.410 51.440 2388.250 51.580 ; + RECT 2083.410 51.380 2083.730 51.440 ; + RECT 2387.930 51.380 2388.250 51.440 ; + LAYER via ; + RECT 2083.440 51.380 2083.700 51.640 ; + RECT 2387.960 51.380 2388.220 51.640 ; + LAYER met2 ; + RECT 2082.470 260.170 2082.750 264.000 ; + RECT 2082.470 260.030 2083.640 260.170 ; + RECT 2082.470 260.000 2082.750 260.030 ; + RECT 2083.500 51.670 2083.640 260.030 ; + RECT 2083.440 51.350 2083.700 51.670 ; + RECT 2387.960 51.350 2388.220 51.670 ; + RECT 2388.020 3.130 2388.160 51.350 ; + RECT 2387.560 2.990 2388.160 3.130 ; + RECT 2387.560 2.400 2387.700 2.990 ; + RECT 2387.350 -4.800 2387.910 2.400 ; +======= LAYER met2 ; RECT 2387.350 -4.800 2387.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[98] PIN la_data_out[99] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2100.430 244.020 2100.750 244.080 ; + RECT 2104.110 244.020 2104.430 244.080 ; + RECT 2100.430 243.880 2104.430 244.020 ; + RECT 2100.430 243.820 2100.750 243.880 ; + RECT 2104.110 243.820 2104.430 243.880 ; + RECT 2104.110 197.100 2104.430 197.160 ; + RECT 2401.270 197.100 2401.590 197.160 ; + RECT 2104.110 196.960 2401.590 197.100 ; + RECT 2104.110 196.900 2104.430 196.960 ; + RECT 2401.270 196.900 2401.590 196.960 ; + LAYER via ; + RECT 2100.460 243.820 2100.720 244.080 ; + RECT 2104.140 243.820 2104.400 244.080 ; + RECT 2104.140 196.900 2104.400 197.160 ; + RECT 2401.300 196.900 2401.560 197.160 ; + LAYER met2 ; + RECT 2100.410 260.000 2100.690 264.000 ; + RECT 2100.520 244.110 2100.660 260.000 ; + RECT 2100.460 243.790 2100.720 244.110 ; + RECT 2104.140 243.790 2104.400 244.110 ; + RECT 2104.200 197.190 2104.340 243.790 ; + RECT 2104.140 196.870 2104.400 197.190 ; + RECT 2401.300 196.870 2401.560 197.190 ; + RECT 2401.360 17.410 2401.500 196.870 ; + RECT 2401.360 17.270 2405.640 17.410 ; + RECT 2405.500 2.400 2405.640 17.270 ; + RECT 2405.290 -4.800 2405.850 2.400 ; +======= LAYER met2 ; RECT 2405.290 -4.800 2405.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[99] PIN la_data_out[9] DIRECTION OUTPUT TRISTATE ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 491.350 244.020 491.670 244.080 ; + RECT 496.410 244.020 496.730 244.080 ; + RECT 491.350 243.880 496.730 244.020 ; + RECT 491.350 243.820 491.670 243.880 ; + RECT 496.410 243.820 496.730 243.880 ; + RECT 496.410 15.540 496.730 15.600 ; + RECT 799.550 15.540 799.870 15.600 ; + RECT 496.410 15.400 799.870 15.540 ; + RECT 496.410 15.340 496.730 15.400 ; + RECT 799.550 15.340 799.870 15.400 ; + LAYER via ; + RECT 491.380 243.820 491.640 244.080 ; + RECT 496.440 243.820 496.700 244.080 ; + RECT 496.440 15.340 496.700 15.600 ; + RECT 799.580 15.340 799.840 15.600 ; + LAYER met2 ; + RECT 491.330 260.000 491.610 264.000 ; + RECT 491.440 244.110 491.580 260.000 ; + RECT 491.380 243.790 491.640 244.110 ; + RECT 496.440 243.790 496.700 244.110 ; + RECT 496.500 15.630 496.640 243.790 ; + RECT 496.440 15.310 496.700 15.630 ; + RECT 799.580 15.310 799.840 15.630 ; + RECT 799.640 2.400 799.780 15.310 ; + RECT 799.430 -4.800 799.990 2.400 ; +======= LAYER met2 ; RECT 799.430 -4.800 799.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_data_out[9] PIN la_oen[0] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 336.330 245.380 336.650 245.440 ; + RECT 642.230 245.380 642.550 245.440 ; + RECT 336.330 245.240 642.550 245.380 ; + RECT 336.330 245.180 336.650 245.240 ; + RECT 642.230 245.180 642.550 245.240 ; + LAYER via ; + RECT 336.360 245.180 336.620 245.440 ; + RECT 642.260 245.180 642.520 245.440 ; + LAYER met2 ; + RECT 336.310 260.000 336.590 264.000 ; + RECT 336.420 245.470 336.560 260.000 ; + RECT 336.360 245.150 336.620 245.470 ; + RECT 642.260 245.150 642.520 245.470 ; + RECT 642.320 17.410 642.460 245.150 ; + RECT 642.320 17.270 645.220 17.410 ; + RECT 645.080 2.400 645.220 17.270 ; + RECT 644.870 -4.800 645.430 2.400 ; +======= LAYER met2 ; RECT 644.870 -4.800 645.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[0] PIN la_oen[100] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2124.810 189.620 2125.130 189.680 ; + RECT 2428.870 189.620 2429.190 189.680 ; + RECT 2124.810 189.480 2429.190 189.620 ; + RECT 2124.810 189.420 2125.130 189.480 ; + RECT 2428.870 189.420 2429.190 189.480 ; + LAYER via ; + RECT 2124.840 189.420 2125.100 189.680 ; + RECT 2428.900 189.420 2429.160 189.680 ; + LAYER met2 ; + RECT 2123.870 260.170 2124.150 264.000 ; + RECT 2123.870 260.030 2125.040 260.170 ; + RECT 2123.870 260.000 2124.150 260.030 ; + RECT 2124.900 189.710 2125.040 260.030 ; + RECT 2124.840 189.390 2125.100 189.710 ; + RECT 2428.900 189.390 2429.160 189.710 ; + RECT 2428.960 2.400 2429.100 189.390 ; + RECT 2428.750 -4.800 2429.310 2.400 ; +======= LAYER met2 ; RECT 2428.750 -4.800 2429.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[100] PIN la_oen[101] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2141.830 244.020 2142.150 244.080 ; + RECT 2145.510 244.020 2145.830 244.080 ; + RECT 2141.830 243.880 2145.830 244.020 ; + RECT 2141.830 243.820 2142.150 243.880 ; + RECT 2145.510 243.820 2145.830 243.880 ; + RECT 2145.510 17.580 2145.830 17.640 ; + RECT 2446.810 17.580 2447.130 17.640 ; + RECT 2145.510 17.440 2447.130 17.580 ; + RECT 2145.510 17.380 2145.830 17.440 ; + RECT 2446.810 17.380 2447.130 17.440 ; + LAYER via ; + RECT 2141.860 243.820 2142.120 244.080 ; + RECT 2145.540 243.820 2145.800 244.080 ; + RECT 2145.540 17.380 2145.800 17.640 ; + RECT 2446.840 17.380 2447.100 17.640 ; + LAYER met2 ; + RECT 2141.810 260.000 2142.090 264.000 ; + RECT 2141.920 244.110 2142.060 260.000 ; + RECT 2141.860 243.790 2142.120 244.110 ; + RECT 2145.540 243.790 2145.800 244.110 ; + RECT 2145.600 17.670 2145.740 243.790 ; + RECT 2145.540 17.350 2145.800 17.670 ; + RECT 2446.840 17.350 2447.100 17.670 ; + RECT 2446.900 2.400 2447.040 17.350 ; + RECT 2446.690 -4.800 2447.250 2.400 ; +======= LAYER met2 ; RECT 2446.690 -4.800 2447.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[101] PIN la_oen[102] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2159.770 244.020 2160.090 244.080 ; + RECT 2165.750 244.020 2166.070 244.080 ; + RECT 2159.770 243.880 2166.070 244.020 ; + RECT 2159.770 243.820 2160.090 243.880 ; + RECT 2165.750 243.820 2166.070 243.880 ; + RECT 2165.750 15.540 2166.070 15.600 ; + RECT 2464.750 15.540 2465.070 15.600 ; + RECT 2165.750 15.400 2465.070 15.540 ; + RECT 2165.750 15.340 2166.070 15.400 ; + RECT 2464.750 15.340 2465.070 15.400 ; + LAYER via ; + RECT 2159.800 243.820 2160.060 244.080 ; + RECT 2165.780 243.820 2166.040 244.080 ; + RECT 2165.780 15.340 2166.040 15.600 ; + RECT 2464.780 15.340 2465.040 15.600 ; + LAYER met2 ; + RECT 2159.750 260.000 2160.030 264.000 ; + RECT 2159.860 244.110 2160.000 260.000 ; + RECT 2159.800 243.790 2160.060 244.110 ; + RECT 2165.780 243.790 2166.040 244.110 ; + RECT 2165.840 15.630 2165.980 243.790 ; + RECT 2165.780 15.310 2166.040 15.630 ; + RECT 2464.780 15.310 2465.040 15.630 ; + RECT 2464.840 2.400 2464.980 15.310 ; + RECT 2464.630 -4.800 2465.190 2.400 ; +======= LAYER met2 ; RECT 2464.630 -4.800 2465.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[102] PIN la_oen[103] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2180.010 16.900 2180.330 16.960 ; + RECT 2482.690 16.900 2483.010 16.960 ; + RECT 2180.010 16.760 2483.010 16.900 ; + RECT 2180.010 16.700 2180.330 16.760 ; + RECT 2482.690 16.700 2483.010 16.760 ; + LAYER via ; + RECT 2180.040 16.700 2180.300 16.960 ; + RECT 2482.720 16.700 2482.980 16.960 ; + LAYER met2 ; + RECT 2177.690 260.170 2177.970 264.000 ; + RECT 2177.690 260.030 2180.240 260.170 ; + RECT 2177.690 260.000 2177.970 260.030 ; + RECT 2180.100 16.990 2180.240 260.030 ; + RECT 2180.040 16.670 2180.300 16.990 ; + RECT 2482.720 16.670 2482.980 16.990 ; + RECT 2482.780 2.400 2482.920 16.670 ; + RECT 2482.570 -4.800 2483.130 2.400 ; +======= LAYER met2 ; RECT 2482.570 -4.800 2483.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[103] PIN la_oen[104] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2195.650 244.020 2195.970 244.080 ; + RECT 2200.710 244.020 2201.030 244.080 ; + RECT 2195.650 243.880 2201.030 244.020 ; + RECT 2195.650 243.820 2195.970 243.880 ; + RECT 2200.710 243.820 2201.030 243.880 ; + RECT 2200.710 17.240 2201.030 17.300 ; + RECT 2500.630 17.240 2500.950 17.300 ; + RECT 2200.710 17.100 2500.950 17.240 ; + RECT 2200.710 17.040 2201.030 17.100 ; + RECT 2500.630 17.040 2500.950 17.100 ; + LAYER via ; + RECT 2195.680 243.820 2195.940 244.080 ; + RECT 2200.740 243.820 2201.000 244.080 ; + RECT 2200.740 17.040 2201.000 17.300 ; + RECT 2500.660 17.040 2500.920 17.300 ; + LAYER met2 ; + RECT 2195.630 260.000 2195.910 264.000 ; + RECT 2195.740 244.110 2195.880 260.000 ; + RECT 2195.680 243.790 2195.940 244.110 ; + RECT 2200.740 243.790 2201.000 244.110 ; + RECT 2200.800 17.330 2200.940 243.790 ; + RECT 2200.740 17.010 2201.000 17.330 ; + RECT 2500.660 17.010 2500.920 17.330 ; + RECT 2500.720 2.400 2500.860 17.010 ; + RECT 2500.510 -4.800 2501.070 2.400 ; +======= LAYER met2 ; RECT 2500.510 -4.800 2501.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[104] PIN la_oen[105] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2214.510 15.880 2214.830 15.940 ; + RECT 2518.110 15.880 2518.430 15.940 ; + RECT 2214.510 15.740 2518.430 15.880 ; + RECT 2214.510 15.680 2214.830 15.740 ; + RECT 2518.110 15.680 2518.430 15.740 ; + LAYER via ; + RECT 2214.540 15.680 2214.800 15.940 ; + RECT 2518.140 15.680 2518.400 15.940 ; + LAYER met2 ; + RECT 2213.570 260.170 2213.850 264.000 ; + RECT 2213.570 260.030 2214.740 260.170 ; + RECT 2213.570 260.000 2213.850 260.030 ; + RECT 2214.600 15.970 2214.740 260.030 ; + RECT 2214.540 15.650 2214.800 15.970 ; + RECT 2518.140 15.650 2518.400 15.970 ; + RECT 2518.200 2.400 2518.340 15.650 ; + RECT 2517.990 -4.800 2518.550 2.400 ; +======= LAYER met2 ; RECT 2517.990 -4.800 2518.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[105] PIN la_oen[106] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2231.070 244.020 2231.390 244.080 ; + RECT 2235.210 244.020 2235.530 244.080 ; + RECT 2231.070 243.880 2235.530 244.020 ; + RECT 2231.070 243.820 2231.390 243.880 ; + RECT 2235.210 243.820 2235.530 243.880 ; + RECT 2235.210 20.640 2235.530 20.700 ; + RECT 2536.050 20.640 2536.370 20.700 ; + RECT 2235.210 20.500 2536.370 20.640 ; + RECT 2235.210 20.440 2235.530 20.500 ; + RECT 2536.050 20.440 2536.370 20.500 ; + LAYER via ; + RECT 2231.100 243.820 2231.360 244.080 ; + RECT 2235.240 243.820 2235.500 244.080 ; + RECT 2235.240 20.440 2235.500 20.700 ; + RECT 2536.080 20.440 2536.340 20.700 ; + LAYER met2 ; + RECT 2231.050 260.000 2231.330 264.000 ; + RECT 2231.160 244.110 2231.300 260.000 ; + RECT 2231.100 243.790 2231.360 244.110 ; + RECT 2235.240 243.790 2235.500 244.110 ; + RECT 2235.300 20.730 2235.440 243.790 ; + RECT 2235.240 20.410 2235.500 20.730 ; + RECT 2536.080 20.410 2536.340 20.730 ; + RECT 2536.140 2.400 2536.280 20.410 ; + RECT 2535.930 -4.800 2536.490 2.400 ; +======= LAYER met2 ; RECT 2535.930 -4.800 2536.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[106] PIN la_oen[107] @@ -3284,87 +14404,340 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 2248.990 260.000 2249.270 264.000 ; + RECT 2249.100 17.525 2249.240 260.000 ; + RECT 2249.030 17.155 2249.310 17.525 ; + RECT 2554.010 17.155 2554.290 17.525 ; + RECT 2554.080 2.400 2554.220 17.155 ; + RECT 2553.870 -4.800 2554.430 2.400 ; + LAYER via2 ; + RECT 2249.030 17.200 2249.310 17.480 ; + RECT 2554.010 17.200 2554.290 17.480 ; + LAYER met3 ; + RECT 2249.005 17.490 2249.335 17.505 ; + RECT 2553.985 17.490 2554.315 17.505 ; + RECT 2249.005 17.190 2554.315 17.490 ; + RECT 2249.005 17.175 2249.335 17.190 ; + RECT 2553.985 17.175 2554.315 17.190 ; +======= RECT 2553.870 -4.800 2554.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[107] PIN la_oen[108] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2269.710 16.560 2270.030 16.620 ; + RECT 2571.930 16.560 2572.250 16.620 ; + RECT 2269.710 16.420 2572.250 16.560 ; + RECT 2269.710 16.360 2270.030 16.420 ; + RECT 2571.930 16.360 2572.250 16.420 ; + LAYER via ; + RECT 2269.740 16.360 2270.000 16.620 ; + RECT 2571.960 16.360 2572.220 16.620 ; + LAYER met2 ; + RECT 2266.930 260.170 2267.210 264.000 ; + RECT 2266.930 260.030 2269.940 260.170 ; + RECT 2266.930 260.000 2267.210 260.030 ; + RECT 2269.800 16.650 2269.940 260.030 ; + RECT 2269.740 16.330 2270.000 16.650 ; + RECT 2571.960 16.330 2572.220 16.650 ; + RECT 2572.020 2.400 2572.160 16.330 ; + RECT 2571.810 -4.800 2572.370 2.400 ; +======= LAYER met2 ; RECT 2571.810 -4.800 2572.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[108] PIN la_oen[109] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2284.890 244.020 2285.210 244.080 ; + RECT 2290.410 244.020 2290.730 244.080 ; + RECT 2284.890 243.880 2290.730 244.020 ; + RECT 2284.890 243.820 2285.210 243.880 ; + RECT 2290.410 243.820 2290.730 243.880 ; + RECT 2290.410 16.220 2290.730 16.280 ; + RECT 2589.410 16.220 2589.730 16.280 ; + RECT 2290.410 16.080 2589.730 16.220 ; + RECT 2290.410 16.020 2290.730 16.080 ; + RECT 2589.410 16.020 2589.730 16.080 ; + LAYER via ; + RECT 2284.920 243.820 2285.180 244.080 ; + RECT 2290.440 243.820 2290.700 244.080 ; + RECT 2290.440 16.020 2290.700 16.280 ; + RECT 2589.440 16.020 2589.700 16.280 ; + LAYER met2 ; + RECT 2284.870 260.000 2285.150 264.000 ; + RECT 2284.980 244.110 2285.120 260.000 ; + RECT 2284.920 243.790 2285.180 244.110 ; + RECT 2290.440 243.790 2290.700 244.110 ; + RECT 2290.500 16.310 2290.640 243.790 ; + RECT 2290.440 15.990 2290.700 16.310 ; + RECT 2589.440 15.990 2589.700 16.310 ; + RECT 2589.500 2.400 2589.640 15.990 ; + RECT 2589.290 -4.800 2589.850 2.400 ; +======= LAYER met2 ; RECT 2589.290 -4.800 2589.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[109] PIN la_oen[10] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 515.270 246.400 515.590 246.460 ; + RECT 821.630 246.400 821.950 246.460 ; + RECT 515.270 246.260 821.950 246.400 ; + RECT 515.270 246.200 515.590 246.260 ; + RECT 821.630 246.200 821.950 246.260 ; + LAYER via ; + RECT 515.300 246.200 515.560 246.460 ; + RECT 821.660 246.200 821.920 246.460 ; + LAYER met2 ; + RECT 515.250 260.000 515.530 264.000 ; + RECT 515.360 246.490 515.500 260.000 ; + RECT 515.300 246.170 515.560 246.490 ; + RECT 821.660 246.170 821.920 246.490 ; + RECT 821.720 17.410 821.860 246.170 ; + RECT 821.720 17.270 823.700 17.410 ; + RECT 823.560 2.400 823.700 17.270 ; + RECT 823.350 -4.800 823.910 2.400 ; +======= LAYER met2 ; RECT 823.350 -4.800 823.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[10] PIN la_oen[110] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2304.210 19.960 2304.530 20.020 ; + RECT 2607.350 19.960 2607.670 20.020 ; + RECT 2304.210 19.820 2607.670 19.960 ; + RECT 2304.210 19.760 2304.530 19.820 ; + RECT 2607.350 19.760 2607.670 19.820 ; + LAYER via ; + RECT 2304.240 19.760 2304.500 20.020 ; + RECT 2607.380 19.760 2607.640 20.020 ; + LAYER met2 ; + RECT 2302.810 260.170 2303.090 264.000 ; + RECT 2302.810 260.030 2304.440 260.170 ; + RECT 2302.810 260.000 2303.090 260.030 ; + RECT 2304.300 20.050 2304.440 260.030 ; + RECT 2304.240 19.730 2304.500 20.050 ; + RECT 2607.380 19.730 2607.640 20.050 ; + RECT 2607.440 2.400 2607.580 19.730 ; + RECT 2607.230 -4.800 2607.790 2.400 ; +======= LAYER met2 ; RECT 2607.230 -4.800 2607.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[110] PIN la_oen[111] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2320.770 244.020 2321.090 244.080 ; + RECT 2324.910 244.020 2325.230 244.080 ; + RECT 2320.770 243.880 2325.230 244.020 ; + RECT 2320.770 243.820 2321.090 243.880 ; + RECT 2324.910 243.820 2325.230 243.880 ; + RECT 2324.910 19.620 2325.230 19.680 ; + RECT 2625.290 19.620 2625.610 19.680 ; + RECT 2324.910 19.480 2625.610 19.620 ; + RECT 2324.910 19.420 2325.230 19.480 ; + RECT 2625.290 19.420 2625.610 19.480 ; + LAYER via ; + RECT 2320.800 243.820 2321.060 244.080 ; + RECT 2324.940 243.820 2325.200 244.080 ; + RECT 2324.940 19.420 2325.200 19.680 ; + RECT 2625.320 19.420 2625.580 19.680 ; + LAYER met2 ; + RECT 2320.750 260.000 2321.030 264.000 ; + RECT 2320.860 244.110 2321.000 260.000 ; + RECT 2320.800 243.790 2321.060 244.110 ; + RECT 2324.940 243.790 2325.200 244.110 ; + RECT 2325.000 19.710 2325.140 243.790 ; + RECT 2324.940 19.390 2325.200 19.710 ; + RECT 2625.320 19.390 2625.580 19.710 ; + RECT 2625.380 2.400 2625.520 19.390 ; + RECT 2625.170 -4.800 2625.730 2.400 ; +======= LAYER met2 ; RECT 2625.170 -4.800 2625.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[111] PIN la_oen[112] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2338.710 245.040 2339.030 245.100 ; + RECT 2642.770 245.040 2643.090 245.100 ; + RECT 2338.710 244.900 2643.090 245.040 ; + RECT 2338.710 244.840 2339.030 244.900 ; + RECT 2642.770 244.840 2643.090 244.900 ; + LAYER via ; + RECT 2338.740 244.840 2339.000 245.100 ; + RECT 2642.800 244.840 2643.060 245.100 ; + LAYER met2 ; + RECT 2338.690 260.000 2338.970 264.000 ; + RECT 2338.800 245.130 2338.940 260.000 ; + RECT 2338.740 244.810 2339.000 245.130 ; + RECT 2642.800 244.810 2643.060 245.130 ; + RECT 2642.860 17.410 2643.000 244.810 ; + RECT 2642.860 17.270 2643.460 17.410 ; + RECT 2643.320 2.400 2643.460 17.270 ; + RECT 2643.110 -4.800 2643.670 2.400 ; +======= LAYER met2 ; RECT 2643.110 -4.800 2643.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[112] PIN la_oen[113] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 2642.845 15.725 2643.015 18.955 ; + LAYER mcon ; + RECT 2642.845 18.785 2643.015 18.955 ; + LAYER met1 ; + RECT 2359.410 18.940 2359.730 19.000 ; + RECT 2642.785 18.940 2643.075 18.985 ; + RECT 2359.410 18.800 2643.075 18.940 ; + RECT 2359.410 18.740 2359.730 18.800 ; + RECT 2642.785 18.755 2643.075 18.800 ; + RECT 2642.785 15.880 2643.075 15.925 ; + RECT 2661.170 15.880 2661.490 15.940 ; + RECT 2642.785 15.740 2661.490 15.880 ; + RECT 2642.785 15.695 2643.075 15.740 ; + RECT 2661.170 15.680 2661.490 15.740 ; + LAYER via ; + RECT 2359.440 18.740 2359.700 19.000 ; + RECT 2661.200 15.680 2661.460 15.940 ; + LAYER met2 ; + RECT 2356.630 260.170 2356.910 264.000 ; + RECT 2356.630 260.030 2359.640 260.170 ; + RECT 2356.630 260.000 2356.910 260.030 ; + RECT 2359.500 19.030 2359.640 260.030 ; + RECT 2359.440 18.710 2359.700 19.030 ; + RECT 2661.200 15.650 2661.460 15.970 ; + RECT 2661.260 2.400 2661.400 15.650 ; + RECT 2661.050 -4.800 2661.610 2.400 ; +======= LAYER met2 ; RECT 2661.050 -4.800 2661.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[113] PIN la_oen[114] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2374.130 246.060 2374.450 246.120 ; + RECT 2677.270 246.060 2677.590 246.120 ; + RECT 2374.130 245.920 2677.590 246.060 ; + RECT 2374.130 245.860 2374.450 245.920 ; + RECT 2677.270 245.860 2677.590 245.920 ; + LAYER via ; + RECT 2374.160 245.860 2374.420 246.120 ; + RECT 2677.300 245.860 2677.560 246.120 ; + LAYER met2 ; + RECT 2374.110 260.000 2374.390 264.000 ; + RECT 2374.220 246.150 2374.360 260.000 ; + RECT 2374.160 245.830 2374.420 246.150 ; + RECT 2677.300 245.830 2677.560 246.150 ; + RECT 2677.360 17.410 2677.500 245.830 ; + RECT 2677.360 17.270 2678.880 17.410 ; + RECT 2678.740 2.400 2678.880 17.270 ; + RECT 2678.530 -4.800 2679.090 2.400 ; +======= LAYER met2 ; RECT 2678.530 -4.800 2679.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[114] PIN la_oen[115] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2393.910 18.260 2394.230 18.320 ; + RECT 2696.590 18.260 2696.910 18.320 ; + RECT 2393.910 18.120 2696.910 18.260 ; + RECT 2393.910 18.060 2394.230 18.120 ; + RECT 2696.590 18.060 2696.910 18.120 ; + LAYER via ; + RECT 2393.940 18.060 2394.200 18.320 ; + RECT 2696.620 18.060 2696.880 18.320 ; + LAYER met2 ; + RECT 2392.050 260.170 2392.330 264.000 ; + RECT 2392.050 260.030 2394.140 260.170 ; + RECT 2392.050 260.000 2392.330 260.030 ; + RECT 2394.000 18.350 2394.140 260.030 ; + RECT 2393.940 18.030 2394.200 18.350 ; + RECT 2696.620 18.030 2696.880 18.350 ; + RECT 2696.680 2.400 2696.820 18.030 ; + RECT 2696.470 -4.800 2697.030 2.400 ; +======= LAYER met2 ; RECT 2696.470 -4.800 2697.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[115] PIN la_oen[116] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2410.010 245.720 2410.330 245.780 ; + RECT 2711.770 245.720 2712.090 245.780 ; + RECT 2410.010 245.580 2712.090 245.720 ; + RECT 2410.010 245.520 2410.330 245.580 ; + RECT 2711.770 245.520 2712.090 245.580 ; + LAYER via ; + RECT 2410.040 245.520 2410.300 245.780 ; + RECT 2711.800 245.520 2712.060 245.780 ; + LAYER met2 ; + RECT 2409.990 260.000 2410.270 264.000 ; + RECT 2410.100 245.810 2410.240 260.000 ; + RECT 2410.040 245.490 2410.300 245.810 ; + RECT 2711.800 245.490 2712.060 245.810 ; + RECT 2711.860 17.410 2712.000 245.490 ; + RECT 2711.860 17.270 2714.760 17.410 ; + RECT 2714.620 2.400 2714.760 17.270 ; + RECT 2714.410 -4.800 2714.970 2.400 ; +======= LAYER met2 ; RECT 2714.410 -4.800 2714.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[116] PIN la_oen[117] @@ -3372,511 +14745,2117 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 2427.930 260.170 2428.210 264.000 ; + RECT 2427.930 260.030 2428.640 260.170 ; + RECT 2427.930 260.000 2428.210 260.030 ; + RECT 2428.500 18.205 2428.640 260.030 ; + RECT 2428.430 17.835 2428.710 18.205 ; + RECT 2732.490 17.835 2732.770 18.205 ; + RECT 2732.560 2.400 2732.700 17.835 ; + RECT 2732.350 -4.800 2732.910 2.400 ; + LAYER via2 ; + RECT 2428.430 17.880 2428.710 18.160 ; + RECT 2732.490 17.880 2732.770 18.160 ; + LAYER met3 ; + RECT 2428.405 18.170 2428.735 18.185 ; + RECT 2732.465 18.170 2732.795 18.185 ; + RECT 2428.405 17.870 2732.795 18.170 ; + RECT 2428.405 17.855 2428.735 17.870 ; + RECT 2732.465 17.855 2732.795 17.870 ; +======= RECT 2732.350 -4.800 2732.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[117] PIN la_oen[118] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2445.890 245.380 2446.210 245.440 ; + RECT 2746.270 245.380 2746.590 245.440 ; + RECT 2445.890 245.240 2746.590 245.380 ; + RECT 2445.890 245.180 2446.210 245.240 ; + RECT 2746.270 245.180 2746.590 245.240 ; + LAYER via ; + RECT 2445.920 245.180 2446.180 245.440 ; + RECT 2746.300 245.180 2746.560 245.440 ; + LAYER met2 ; + RECT 2445.870 260.000 2446.150 264.000 ; + RECT 2445.980 245.470 2446.120 260.000 ; + RECT 2445.920 245.150 2446.180 245.470 ; + RECT 2746.300 245.150 2746.560 245.470 ; + RECT 2746.360 17.410 2746.500 245.150 ; + RECT 2746.360 17.270 2750.640 17.410 ; + RECT 2750.500 2.400 2750.640 17.270 ; + RECT 2750.290 -4.800 2750.850 2.400 ; +======= LAYER met2 ; RECT 2750.290 -4.800 2750.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[118] PIN la_oen[119] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2463.830 244.020 2464.150 244.080 ; + RECT 2469.810 244.020 2470.130 244.080 ; + RECT 2463.830 243.880 2470.130 244.020 ; + RECT 2463.830 243.820 2464.150 243.880 ; + RECT 2469.810 243.820 2470.130 243.880 ; + RECT 2469.810 17.580 2470.130 17.640 ; + RECT 2767.890 17.580 2768.210 17.640 ; + RECT 2469.810 17.440 2768.210 17.580 ; + RECT 2469.810 17.380 2470.130 17.440 ; + RECT 2767.890 17.380 2768.210 17.440 ; + LAYER via ; + RECT 2463.860 243.820 2464.120 244.080 ; + RECT 2469.840 243.820 2470.100 244.080 ; + RECT 2469.840 17.380 2470.100 17.640 ; + RECT 2767.920 17.380 2768.180 17.640 ; + LAYER met2 ; + RECT 2463.810 260.000 2464.090 264.000 ; + RECT 2463.920 244.110 2464.060 260.000 ; + RECT 2463.860 243.790 2464.120 244.110 ; + RECT 2469.840 243.790 2470.100 244.110 ; + RECT 2469.900 17.670 2470.040 243.790 ; + RECT 2469.840 17.350 2470.100 17.670 ; + RECT 2767.920 17.350 2768.180 17.670 ; + RECT 2767.980 2.400 2768.120 17.350 ; + RECT 2767.770 -4.800 2768.330 2.400 ; +======= LAYER met2 ; RECT 2767.770 -4.800 2768.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[119] PIN la_oen[11] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 533.210 244.020 533.530 244.080 ; + RECT 537.810 244.020 538.130 244.080 ; + RECT 533.210 243.880 538.130 244.020 ; + RECT 533.210 243.820 533.530 243.880 ; + RECT 537.810 243.820 538.130 243.880 ; + RECT 537.810 16.220 538.130 16.280 ; + RECT 840.950 16.220 841.270 16.280 ; + RECT 537.810 16.080 841.270 16.220 ; + RECT 537.810 16.020 538.130 16.080 ; + RECT 840.950 16.020 841.270 16.080 ; + LAYER via ; + RECT 533.240 243.820 533.500 244.080 ; + RECT 537.840 243.820 538.100 244.080 ; + RECT 537.840 16.020 538.100 16.280 ; + RECT 840.980 16.020 841.240 16.280 ; + LAYER met2 ; + RECT 533.190 260.000 533.470 264.000 ; + RECT 533.300 244.110 533.440 260.000 ; + RECT 533.240 243.790 533.500 244.110 ; + RECT 537.840 243.790 538.100 244.110 ; + RECT 537.900 16.310 538.040 243.790 ; + RECT 537.840 15.990 538.100 16.310 ; + RECT 840.980 15.990 841.240 16.310 ; + RECT 841.040 2.400 841.180 15.990 ; + RECT 840.830 -4.800 841.390 2.400 ; +======= LAYER met2 ; RECT 840.830 -4.800 841.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[11] PIN la_oen[120] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2483.610 17.920 2483.930 17.980 ; + RECT 2785.830 17.920 2786.150 17.980 ; + RECT 2483.610 17.780 2786.150 17.920 ; + RECT 2483.610 17.720 2483.930 17.780 ; + RECT 2785.830 17.720 2786.150 17.780 ; + LAYER via ; + RECT 2483.640 17.720 2483.900 17.980 ; + RECT 2785.860 17.720 2786.120 17.980 ; + LAYER met2 ; + RECT 2481.750 260.170 2482.030 264.000 ; + RECT 2481.750 260.030 2483.840 260.170 ; + RECT 2481.750 260.000 2482.030 260.030 ; + RECT 2483.700 18.010 2483.840 260.030 ; + RECT 2483.640 17.690 2483.900 18.010 ; + RECT 2785.860 17.690 2786.120 18.010 ; + RECT 2785.920 2.400 2786.060 17.690 ; + RECT 2785.710 -4.800 2786.270 2.400 ; +======= LAYER met2 ; RECT 2785.710 -4.800 2786.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[120] PIN la_oen[121] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2499.250 244.020 2499.570 244.080 ; + RECT 2504.310 244.020 2504.630 244.080 ; + RECT 2499.250 243.880 2504.630 244.020 ; + RECT 2499.250 243.820 2499.570 243.880 ; + RECT 2504.310 243.820 2504.630 243.880 ; + RECT 2504.310 19.280 2504.630 19.340 ; + RECT 2803.770 19.280 2804.090 19.340 ; + RECT 2504.310 19.140 2804.090 19.280 ; + RECT 2504.310 19.080 2504.630 19.140 ; + RECT 2803.770 19.080 2804.090 19.140 ; + LAYER via ; + RECT 2499.280 243.820 2499.540 244.080 ; + RECT 2504.340 243.820 2504.600 244.080 ; + RECT 2504.340 19.080 2504.600 19.340 ; + RECT 2803.800 19.080 2804.060 19.340 ; + LAYER met2 ; + RECT 2499.230 260.000 2499.510 264.000 ; + RECT 2499.340 244.110 2499.480 260.000 ; + RECT 2499.280 243.790 2499.540 244.110 ; + RECT 2504.340 243.790 2504.600 244.110 ; + RECT 2504.400 19.370 2504.540 243.790 ; + RECT 2504.340 19.050 2504.600 19.370 ; + RECT 2803.800 19.050 2804.060 19.370 ; + RECT 2803.860 2.400 2804.000 19.050 ; + RECT 2803.650 -4.800 2804.210 2.400 ; +======= LAYER met2 ; RECT 2803.650 -4.800 2804.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[121] PIN la_oen[122] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2518.110 20.300 2518.430 20.360 ; + RECT 2821.710 20.300 2822.030 20.360 ; + RECT 2518.110 20.160 2822.030 20.300 ; + RECT 2518.110 20.100 2518.430 20.160 ; + RECT 2821.710 20.100 2822.030 20.160 ; + LAYER via ; + RECT 2518.140 20.100 2518.400 20.360 ; + RECT 2821.740 20.100 2822.000 20.360 ; + LAYER met2 ; + RECT 2517.170 260.170 2517.450 264.000 ; + RECT 2517.170 260.030 2518.340 260.170 ; + RECT 2517.170 260.000 2517.450 260.030 ; + RECT 2518.200 20.390 2518.340 260.030 ; + RECT 2518.140 20.070 2518.400 20.390 ; + RECT 2821.740 20.070 2822.000 20.390 ; + RECT 2821.800 2.400 2821.940 20.070 ; + RECT 2821.590 -4.800 2822.150 2.400 ; +======= LAYER met2 ; RECT 2821.590 -4.800 2822.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[122] PIN la_oen[123] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2538.810 20.640 2539.130 20.700 ; + RECT 2839.190 20.640 2839.510 20.700 ; + RECT 2538.810 20.500 2839.510 20.640 ; + RECT 2538.810 20.440 2539.130 20.500 ; + RECT 2839.190 20.440 2839.510 20.500 ; + LAYER via ; + RECT 2538.840 20.440 2539.100 20.700 ; + RECT 2839.220 20.440 2839.480 20.700 ; + LAYER met2 ; + RECT 2535.110 260.170 2535.390 264.000 ; + RECT 2535.110 260.030 2539.040 260.170 ; + RECT 2535.110 260.000 2535.390 260.030 ; + RECT 2538.900 20.730 2539.040 260.030 ; + RECT 2538.840 20.410 2539.100 20.730 ; + RECT 2839.220 20.410 2839.480 20.730 ; + RECT 2839.280 2.400 2839.420 20.410 ; + RECT 2839.070 -4.800 2839.630 2.400 ; +======= LAYER met2 ; RECT 2839.070 -4.800 2839.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[123] PIN la_oen[124] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2553.070 242.660 2553.390 242.720 ; + RECT 2559.510 242.660 2559.830 242.720 ; + RECT 2553.070 242.520 2559.830 242.660 ; + RECT 2553.070 242.460 2553.390 242.520 ; + RECT 2559.510 242.460 2559.830 242.520 ; + RECT 2559.510 16.900 2559.830 16.960 ; + RECT 2857.130 16.900 2857.450 16.960 ; + RECT 2559.510 16.760 2857.450 16.900 ; + RECT 2559.510 16.700 2559.830 16.760 ; + RECT 2857.130 16.700 2857.450 16.760 ; + LAYER via ; + RECT 2553.100 242.460 2553.360 242.720 ; + RECT 2559.540 242.460 2559.800 242.720 ; + RECT 2559.540 16.700 2559.800 16.960 ; + RECT 2857.160 16.700 2857.420 16.960 ; + LAYER met2 ; + RECT 2553.050 260.000 2553.330 264.000 ; + RECT 2553.160 242.750 2553.300 260.000 ; + RECT 2553.100 242.430 2553.360 242.750 ; + RECT 2559.540 242.430 2559.800 242.750 ; + RECT 2559.600 16.990 2559.740 242.430 ; + RECT 2559.540 16.670 2559.800 16.990 ; + RECT 2857.160 16.670 2857.420 16.990 ; + RECT 2857.220 2.400 2857.360 16.670 ; + RECT 2857.010 -4.800 2857.570 2.400 ; +======= LAYER met2 ; RECT 2857.010 -4.800 2857.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[124] PIN la_oen[125] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2573.310 16.560 2573.630 16.620 ; + RECT 2875.070 16.560 2875.390 16.620 ; + RECT 2573.310 16.420 2875.390 16.560 ; + RECT 2573.310 16.360 2573.630 16.420 ; + RECT 2875.070 16.360 2875.390 16.420 ; + LAYER via ; + RECT 2573.340 16.360 2573.600 16.620 ; + RECT 2875.100 16.360 2875.360 16.620 ; + LAYER met2 ; + RECT 2570.990 260.170 2571.270 264.000 ; + RECT 2570.990 260.030 2573.540 260.170 ; + RECT 2570.990 260.000 2571.270 260.030 ; + RECT 2573.400 16.650 2573.540 260.030 ; + RECT 2573.340 16.330 2573.600 16.650 ; + RECT 2875.100 16.330 2875.360 16.650 ; + RECT 2875.160 2.400 2875.300 16.330 ; + RECT 2874.950 -4.800 2875.510 2.400 ; +======= LAYER met2 ; RECT 2874.950 -4.800 2875.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[125] PIN la_oen[126] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2588.950 244.020 2589.270 244.080 ; + RECT 2594.010 244.020 2594.330 244.080 ; + RECT 2588.950 243.880 2594.330 244.020 ; + RECT 2588.950 243.820 2589.270 243.880 ; + RECT 2594.010 243.820 2594.330 243.880 ; + RECT 2594.010 16.220 2594.330 16.280 ; + RECT 2893.010 16.220 2893.330 16.280 ; + RECT 2594.010 16.080 2893.330 16.220 ; + RECT 2594.010 16.020 2594.330 16.080 ; + RECT 2893.010 16.020 2893.330 16.080 ; + LAYER via ; + RECT 2588.980 243.820 2589.240 244.080 ; + RECT 2594.040 243.820 2594.300 244.080 ; + RECT 2594.040 16.020 2594.300 16.280 ; + RECT 2893.040 16.020 2893.300 16.280 ; + LAYER met2 ; + RECT 2588.930 260.000 2589.210 264.000 ; + RECT 2589.040 244.110 2589.180 260.000 ; + RECT 2588.980 243.790 2589.240 244.110 ; + RECT 2594.040 243.790 2594.300 244.110 ; + RECT 2594.100 16.310 2594.240 243.790 ; + RECT 2594.040 15.990 2594.300 16.310 ; + RECT 2893.040 15.990 2893.300 16.310 ; + RECT 2893.100 2.400 2893.240 15.990 ; + RECT 2892.890 -4.800 2893.450 2.400 ; +======= LAYER met2 ; RECT 2892.890 -4.800 2893.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[126] PIN la_oen[127] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2607.810 19.960 2608.130 20.020 ; + RECT 2910.950 19.960 2911.270 20.020 ; + RECT 2607.810 19.820 2911.270 19.960 ; + RECT 2607.810 19.760 2608.130 19.820 ; + RECT 2910.950 19.760 2911.270 19.820 ; + LAYER via ; + RECT 2607.840 19.760 2608.100 20.020 ; + RECT 2910.980 19.760 2911.240 20.020 ; + LAYER met2 ; + RECT 2606.870 260.170 2607.150 264.000 ; + RECT 2606.870 260.030 2608.040 260.170 ; + RECT 2606.870 260.000 2607.150 260.030 ; + RECT 2607.900 20.050 2608.040 260.030 ; + RECT 2607.840 19.730 2608.100 20.050 ; + RECT 2910.980 19.730 2911.240 20.050 ; + RECT 2911.040 2.400 2911.180 19.730 ; + RECT 2910.830 -4.800 2911.390 2.400 ; +======= LAYER met2 ; RECT 2910.830 -4.800 2911.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[127] PIN la_oen[12] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 551.150 247.080 551.470 247.140 ; + RECT 856.130 247.080 856.450 247.140 ; + RECT 551.150 246.940 856.450 247.080 ; + RECT 551.150 246.880 551.470 246.940 ; + RECT 856.130 246.880 856.450 246.940 ; + LAYER via ; + RECT 551.180 246.880 551.440 247.140 ; + RECT 856.160 246.880 856.420 247.140 ; + LAYER met2 ; + RECT 551.130 260.000 551.410 264.000 ; + RECT 551.240 247.170 551.380 260.000 ; + RECT 551.180 246.850 551.440 247.170 ; + RECT 856.160 246.850 856.420 247.170 ; + RECT 856.220 16.730 856.360 246.850 ; + RECT 856.220 16.590 859.120 16.730 ; + RECT 858.980 2.400 859.120 16.590 ; + RECT 858.770 -4.800 859.330 2.400 ; +======= LAYER met2 ; RECT 858.770 -4.800 859.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[12] PIN la_oen[13] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 568.630 244.020 568.950 244.080 ; + RECT 572.310 244.020 572.630 244.080 ; + RECT 568.630 243.880 572.630 244.020 ; + RECT 568.630 243.820 568.950 243.880 ; + RECT 572.310 243.820 572.630 243.880 ; + RECT 572.310 18.600 572.630 18.660 ; + RECT 876.370 18.600 876.690 18.660 ; + RECT 572.310 18.460 876.690 18.600 ; + RECT 572.310 18.400 572.630 18.460 ; + RECT 876.370 18.400 876.690 18.460 ; + LAYER via ; + RECT 568.660 243.820 568.920 244.080 ; + RECT 572.340 243.820 572.600 244.080 ; + RECT 572.340 18.400 572.600 18.660 ; + RECT 876.400 18.400 876.660 18.660 ; + LAYER met2 ; + RECT 568.610 260.000 568.890 264.000 ; + RECT 568.720 244.110 568.860 260.000 ; + RECT 568.660 243.790 568.920 244.110 ; + RECT 572.340 243.790 572.600 244.110 ; + RECT 572.400 18.690 572.540 243.790 ; + RECT 572.340 18.370 572.600 18.690 ; + RECT 876.400 18.370 876.660 18.690 ; + RECT 876.460 16.050 876.600 18.370 ; + RECT 876.460 15.910 877.060 16.050 ; + RECT 876.920 2.400 877.060 15.910 ; + RECT 876.710 -4.800 877.270 2.400 ; +======= LAYER met2 ; RECT 876.710 -4.800 877.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[13] PIN la_oen[14] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 586.570 244.020 586.890 244.080 ; + RECT 593.010 244.020 593.330 244.080 ; + RECT 586.570 243.880 593.330 244.020 ; + RECT 586.570 243.820 586.890 243.880 ; + RECT 593.010 243.820 593.330 243.880 ; + RECT 593.010 16.560 593.330 16.620 ; + RECT 593.010 16.420 865.100 16.560 ; + RECT 593.010 16.360 593.330 16.420 ; + RECT 864.960 16.220 865.100 16.420 ; + RECT 894.770 16.220 895.090 16.280 ; + RECT 864.960 16.080 895.090 16.220 ; + RECT 894.770 16.020 895.090 16.080 ; + LAYER via ; + RECT 586.600 243.820 586.860 244.080 ; + RECT 593.040 243.820 593.300 244.080 ; + RECT 593.040 16.360 593.300 16.620 ; + RECT 894.800 16.020 895.060 16.280 ; + LAYER met2 ; + RECT 586.550 260.000 586.830 264.000 ; + RECT 586.660 244.110 586.800 260.000 ; + RECT 586.600 243.790 586.860 244.110 ; + RECT 593.040 243.790 593.300 244.110 ; + RECT 593.100 16.650 593.240 243.790 ; + RECT 593.040 16.330 593.300 16.650 ; + RECT 894.800 15.990 895.060 16.310 ; + RECT 894.860 2.400 895.000 15.990 ; + RECT 894.650 -4.800 895.210 2.400 ; +======= LAYER met2 ; RECT 894.650 -4.800 895.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[14] PIN la_oen[15] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 606.810 18.260 607.130 18.320 ; + RECT 912.710 18.260 913.030 18.320 ; + RECT 606.810 18.120 913.030 18.260 ; + RECT 606.810 18.060 607.130 18.120 ; + RECT 912.710 18.060 913.030 18.120 ; + LAYER via ; + RECT 606.840 18.060 607.100 18.320 ; + RECT 912.740 18.060 913.000 18.320 ; + LAYER met2 ; + RECT 604.490 260.170 604.770 264.000 ; + RECT 604.490 260.030 607.040 260.170 ; + RECT 604.490 260.000 604.770 260.030 ; + RECT 606.900 18.350 607.040 260.030 ; + RECT 606.840 18.030 607.100 18.350 ; + RECT 912.740 18.030 913.000 18.350 ; + RECT 912.800 2.400 912.940 18.030 ; + RECT 912.590 -4.800 913.150 2.400 ; +======= LAYER met2 ; RECT 912.590 -4.800 913.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[15] PIN la_oen[16] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 622.450 244.020 622.770 244.080 ; + RECT 627.510 244.020 627.830 244.080 ; + RECT 622.450 243.880 627.830 244.020 ; + RECT 622.450 243.820 622.770 243.880 ; + RECT 627.510 243.820 627.830 243.880 ; + RECT 627.510 16.900 627.830 16.960 ; + RECT 930.190 16.900 930.510 16.960 ; + RECT 627.510 16.760 930.510 16.900 ; + RECT 627.510 16.700 627.830 16.760 ; + RECT 930.190 16.700 930.510 16.760 ; + LAYER via ; + RECT 622.480 243.820 622.740 244.080 ; + RECT 627.540 243.820 627.800 244.080 ; + RECT 627.540 16.700 627.800 16.960 ; + RECT 930.220 16.700 930.480 16.960 ; + LAYER met2 ; + RECT 622.430 260.000 622.710 264.000 ; + RECT 622.540 244.110 622.680 260.000 ; + RECT 622.480 243.790 622.740 244.110 ; + RECT 627.540 243.790 627.800 244.110 ; + RECT 627.600 16.990 627.740 243.790 ; + RECT 627.540 16.670 627.800 16.990 ; + RECT 930.220 16.670 930.480 16.990 ; + RECT 930.280 2.400 930.420 16.670 ; + RECT 930.070 -4.800 930.630 2.400 ; +======= LAYER met2 ; RECT 930.070 -4.800 930.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[16] PIN la_oen[17] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 948.130 18.260 948.450 18.320 ; + RECT 917.400 18.120 948.450 18.260 ; + RECT 641.310 17.920 641.630 17.980 ; + RECT 917.400 17.920 917.540 18.120 ; + RECT 948.130 18.060 948.450 18.120 ; + RECT 641.310 17.780 917.540 17.920 ; + RECT 641.310 17.720 641.630 17.780 ; + LAYER via ; + RECT 641.340 17.720 641.600 17.980 ; + RECT 948.160 18.060 948.420 18.320 ; + LAYER met2 ; + RECT 640.370 260.170 640.650 264.000 ; + RECT 640.370 260.030 641.540 260.170 ; + RECT 640.370 260.000 640.650 260.030 ; + RECT 641.400 18.010 641.540 260.030 ; + RECT 948.160 18.030 948.420 18.350 ; + RECT 641.340 17.690 641.600 18.010 ; + RECT 948.220 2.400 948.360 18.030 ; + RECT 948.010 -4.800 948.570 2.400 ; +======= LAYER met2 ; RECT 948.010 -4.800 948.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[17] PIN la_oen[18] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 658.330 245.380 658.650 245.440 ; + RECT 966.990 245.380 967.310 245.440 ; + RECT 658.330 245.240 967.310 245.380 ; + RECT 658.330 245.180 658.650 245.240 ; + RECT 966.990 245.180 967.310 245.240 ; + LAYER via ; + RECT 658.360 245.180 658.620 245.440 ; + RECT 967.020 245.180 967.280 245.440 ; + LAYER met2 ; + RECT 658.310 260.000 658.590 264.000 ; + RECT 658.420 245.470 658.560 260.000 ; + RECT 658.360 245.150 658.620 245.470 ; + RECT 967.020 245.150 967.280 245.470 ; + RECT 967.080 16.730 967.220 245.150 ; + RECT 966.160 16.590 967.220 16.730 ; + RECT 966.160 2.400 966.300 16.590 ; + RECT 965.950 -4.800 966.510 2.400 ; +======= LAYER met2 ; RECT 965.950 -4.800 966.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[18] PIN la_oen[19] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 676.270 242.660 676.590 242.720 ; + RECT 682.250 242.660 682.570 242.720 ; + RECT 676.270 242.520 682.570 242.660 ; + RECT 676.270 242.460 676.590 242.520 ; + RECT 682.250 242.460 682.570 242.520 ; + RECT 682.250 19.620 682.570 19.680 ; + RECT 984.010 19.620 984.330 19.680 ; + RECT 682.250 19.480 984.330 19.620 ; + RECT 682.250 19.420 682.570 19.480 ; + RECT 984.010 19.420 984.330 19.480 ; + LAYER via ; + RECT 676.300 242.460 676.560 242.720 ; + RECT 682.280 242.460 682.540 242.720 ; + RECT 682.280 19.420 682.540 19.680 ; + RECT 984.040 19.420 984.300 19.680 ; + LAYER met2 ; + RECT 676.250 260.000 676.530 264.000 ; + RECT 676.360 242.750 676.500 260.000 ; + RECT 676.300 242.430 676.560 242.750 ; + RECT 682.280 242.430 682.540 242.750 ; + RECT 682.340 19.710 682.480 242.430 ; + RECT 682.280 19.390 682.540 19.710 ; + RECT 984.040 19.390 984.300 19.710 ; + RECT 984.100 2.400 984.240 19.390 ; + RECT 983.890 -4.800 984.450 2.400 ; +======= LAYER met2 ; RECT 983.890 -4.800 984.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[19] PIN la_oen[1] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 354.270 244.020 354.590 244.080 ; + RECT 358.410 244.020 358.730 244.080 ; + RECT 354.270 243.880 358.730 244.020 ; + RECT 354.270 243.820 354.590 243.880 ; + RECT 358.410 243.820 358.730 243.880 ; + RECT 358.410 19.620 358.730 19.680 ; + RECT 662.470 19.620 662.790 19.680 ; + RECT 358.410 19.480 662.790 19.620 ; + RECT 358.410 19.420 358.730 19.480 ; + RECT 662.470 19.420 662.790 19.480 ; + LAYER via ; + RECT 354.300 243.820 354.560 244.080 ; + RECT 358.440 243.820 358.700 244.080 ; + RECT 358.440 19.420 358.700 19.680 ; + RECT 662.500 19.420 662.760 19.680 ; + LAYER met2 ; + RECT 354.250 260.000 354.530 264.000 ; + RECT 354.360 244.110 354.500 260.000 ; + RECT 354.300 243.790 354.560 244.110 ; + RECT 358.440 243.790 358.700 244.110 ; + RECT 358.500 19.710 358.640 243.790 ; + RECT 358.440 19.390 358.700 19.710 ; + RECT 662.500 19.390 662.760 19.710 ; + RECT 662.560 18.770 662.700 19.390 ; + RECT 662.560 18.630 663.160 18.770 ; + RECT 663.020 2.400 663.160 18.630 ; + RECT 662.810 -4.800 663.370 2.400 ; +======= LAYER met2 ; RECT 662.810 -4.800 663.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[1] PIN la_oen[20] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 694.210 245.720 694.530 245.780 ; + RECT 1001.030 245.720 1001.350 245.780 ; + RECT 694.210 245.580 1001.350 245.720 ; + RECT 694.210 245.520 694.530 245.580 ; + RECT 1001.030 245.520 1001.350 245.580 ; + LAYER via ; + RECT 694.240 245.520 694.500 245.780 ; + RECT 1001.060 245.520 1001.320 245.780 ; + LAYER met2 ; + RECT 694.190 260.000 694.470 264.000 ; + RECT 694.300 245.810 694.440 260.000 ; + RECT 694.240 245.490 694.500 245.810 ; + RECT 1001.060 245.490 1001.320 245.810 ; + RECT 1001.120 16.730 1001.260 245.490 ; + RECT 1001.120 16.590 1002.180 16.730 ; + RECT 1002.040 2.400 1002.180 16.590 ; + RECT 1001.830 -4.800 1002.390 2.400 ; +======= LAYER met2 ; RECT 1001.830 -4.800 1002.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[20] PIN la_oen[21] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 711.690 244.020 712.010 244.080 ; + RECT 717.210 244.020 717.530 244.080 ; + RECT 711.690 243.880 717.530 244.020 ; + RECT 711.690 243.820 712.010 243.880 ; + RECT 717.210 243.820 717.530 243.880 ; + RECT 717.210 20.640 717.530 20.700 ; + RECT 1019.430 20.640 1019.750 20.700 ; + RECT 717.210 20.500 1019.750 20.640 ; + RECT 717.210 20.440 717.530 20.500 ; + RECT 1019.430 20.440 1019.750 20.500 ; + LAYER via ; + RECT 711.720 243.820 711.980 244.080 ; + RECT 717.240 243.820 717.500 244.080 ; + RECT 717.240 20.440 717.500 20.700 ; + RECT 1019.460 20.440 1019.720 20.700 ; + LAYER met2 ; + RECT 711.670 260.000 711.950 264.000 ; + RECT 711.780 244.110 711.920 260.000 ; + RECT 711.720 243.790 711.980 244.110 ; + RECT 717.240 243.790 717.500 244.110 ; + RECT 717.300 20.730 717.440 243.790 ; + RECT 717.240 20.410 717.500 20.730 ; + RECT 1019.460 20.410 1019.720 20.730 ; + RECT 1019.520 2.400 1019.660 20.410 ; + RECT 1019.310 -4.800 1019.870 2.400 ; +======= LAYER met2 ; RECT 1019.310 -4.800 1019.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[21] PIN la_oen[22] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 729.630 246.060 729.950 246.120 ; + RECT 1035.530 246.060 1035.850 246.120 ; + RECT 729.630 245.920 1035.850 246.060 ; + RECT 729.630 245.860 729.950 245.920 ; + RECT 1035.530 245.860 1035.850 245.920 ; + LAYER via ; + RECT 729.660 245.860 729.920 246.120 ; + RECT 1035.560 245.860 1035.820 246.120 ; + LAYER met2 ; + RECT 729.610 260.000 729.890 264.000 ; + RECT 729.720 246.150 729.860 260.000 ; + RECT 729.660 245.830 729.920 246.150 ; + RECT 1035.560 245.830 1035.820 246.150 ; + RECT 1035.620 16.730 1035.760 245.830 ; + RECT 1035.620 16.590 1037.600 16.730 ; + RECT 1037.460 2.400 1037.600 16.590 ; + RECT 1037.250 -4.800 1037.810 2.400 ; +======= LAYER met2 ; RECT 1037.250 -4.800 1037.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[22] PIN la_oen[23] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 747.570 244.020 747.890 244.080 ; + RECT 751.710 244.020 752.030 244.080 ; + RECT 747.570 243.880 752.030 244.020 ; + RECT 747.570 243.820 747.890 243.880 ; + RECT 751.710 243.820 752.030 243.880 ; + RECT 751.710 20.300 752.030 20.360 ; + RECT 1055.310 20.300 1055.630 20.360 ; + RECT 751.710 20.160 1055.630 20.300 ; + RECT 751.710 20.100 752.030 20.160 ; + RECT 1055.310 20.100 1055.630 20.160 ; + LAYER via ; + RECT 747.600 243.820 747.860 244.080 ; + RECT 751.740 243.820 752.000 244.080 ; + RECT 751.740 20.100 752.000 20.360 ; + RECT 1055.340 20.100 1055.600 20.360 ; + LAYER met2 ; + RECT 747.550 260.000 747.830 264.000 ; + RECT 747.660 244.110 747.800 260.000 ; + RECT 747.600 243.790 747.860 244.110 ; + RECT 751.740 243.790 752.000 244.110 ; + RECT 751.800 20.390 751.940 243.790 ; + RECT 751.740 20.070 752.000 20.390 ; + RECT 1055.340 20.070 1055.600 20.390 ; + RECT 1055.400 2.400 1055.540 20.070 ; + RECT 1055.190 -4.800 1055.750 2.400 ; +======= LAYER met2 ; RECT 1055.190 -4.800 1055.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[23] PIN la_oen[24] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 765.510 18.940 765.830 19.000 ; + RECT 1073.250 18.940 1073.570 19.000 ; + RECT 765.510 18.800 1073.570 18.940 ; + RECT 765.510 18.740 765.830 18.800 ; + RECT 1073.250 18.740 1073.570 18.800 ; + LAYER via ; + RECT 765.540 18.740 765.800 19.000 ; + RECT 1073.280 18.740 1073.540 19.000 ; + LAYER met2 ; + RECT 765.490 260.000 765.770 264.000 ; + RECT 765.600 19.030 765.740 260.000 ; + RECT 765.540 18.710 765.800 19.030 ; + RECT 1073.280 18.710 1073.540 19.030 ; + RECT 1073.340 2.400 1073.480 18.710 ; + RECT 1073.130 -4.800 1073.690 2.400 ; +======= LAYER met2 ; RECT 1073.130 -4.800 1073.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[24] PIN la_oen[25] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 786.210 19.280 786.530 19.340 ; + RECT 1090.270 19.280 1090.590 19.340 ; + RECT 786.210 19.140 1090.590 19.280 ; + RECT 786.210 19.080 786.530 19.140 ; + RECT 1090.270 19.080 1090.590 19.140 ; + LAYER via ; + RECT 786.240 19.080 786.500 19.340 ; + RECT 1090.300 19.080 1090.560 19.340 ; + LAYER met2 ; + RECT 783.430 260.170 783.710 264.000 ; + RECT 783.430 260.030 786.440 260.170 ; + RECT 783.430 260.000 783.710 260.030 ; + RECT 786.300 19.370 786.440 260.030 ; + RECT 786.240 19.050 786.500 19.370 ; + RECT 1090.300 19.050 1090.560 19.370 ; + RECT 1090.360 17.410 1090.500 19.050 ; + RECT 1090.360 17.270 1090.960 17.410 ; + RECT 1090.820 2.400 1090.960 17.270 ; + RECT 1090.610 -4.800 1091.170 2.400 ; +======= LAYER met2 ; RECT 1090.610 -4.800 1091.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[25] PIN la_oen[26] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 801.390 244.020 801.710 244.080 ; + RECT 806.910 244.020 807.230 244.080 ; + RECT 801.390 243.880 807.230 244.020 ; + RECT 801.390 243.820 801.710 243.880 ; + RECT 806.910 243.820 807.230 243.880 ; + RECT 806.910 19.960 807.230 20.020 ; + RECT 1108.670 19.960 1108.990 20.020 ; + RECT 806.910 19.820 1108.990 19.960 ; + RECT 806.910 19.760 807.230 19.820 ; + RECT 1108.670 19.760 1108.990 19.820 ; + LAYER via ; + RECT 801.420 243.820 801.680 244.080 ; + RECT 806.940 243.820 807.200 244.080 ; + RECT 806.940 19.760 807.200 20.020 ; + RECT 1108.700 19.760 1108.960 20.020 ; + LAYER met2 ; + RECT 801.370 260.000 801.650 264.000 ; + RECT 801.480 244.110 801.620 260.000 ; + RECT 801.420 243.790 801.680 244.110 ; + RECT 806.940 243.790 807.200 244.110 ; + RECT 807.000 20.050 807.140 243.790 ; + RECT 806.940 19.730 807.200 20.050 ; + RECT 1108.700 19.730 1108.960 20.050 ; + RECT 1108.760 2.400 1108.900 19.730 ; + RECT 1108.550 -4.800 1109.110 2.400 ; +======= LAYER met2 ; RECT 1108.550 -4.800 1109.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[26] PIN la_oen[27] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 820.710 17.240 821.030 17.300 ; + RECT 1126.610 17.240 1126.930 17.300 ; + RECT 820.710 17.100 1126.930 17.240 ; + RECT 820.710 17.040 821.030 17.100 ; + RECT 1126.610 17.040 1126.930 17.100 ; + LAYER via ; + RECT 820.740 17.040 821.000 17.300 ; + RECT 1126.640 17.040 1126.900 17.300 ; + LAYER met2 ; + RECT 819.310 260.170 819.590 264.000 ; + RECT 819.310 260.030 820.940 260.170 ; + RECT 819.310 260.000 819.590 260.030 ; + RECT 820.800 17.330 820.940 260.030 ; + RECT 820.740 17.010 821.000 17.330 ; + RECT 1126.640 17.010 1126.900 17.330 ; + RECT 1126.700 2.400 1126.840 17.010 ; + RECT 1126.490 -4.800 1127.050 2.400 ; +======= LAYER met2 ; RECT 1126.490 -4.800 1127.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[27] PIN la_oen[28] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 836.810 247.420 837.130 247.480 ; + RECT 1139.490 247.420 1139.810 247.480 ; + RECT 836.810 247.280 1139.810 247.420 ; + RECT 836.810 247.220 837.130 247.280 ; + RECT 1139.490 247.220 1139.810 247.280 ; + LAYER via ; + RECT 836.840 247.220 837.100 247.480 ; + RECT 1139.520 247.220 1139.780 247.480 ; + LAYER met2 ; + RECT 836.790 260.000 837.070 264.000 ; + RECT 836.900 247.510 837.040 260.000 ; + RECT 836.840 247.190 837.100 247.510 ; + RECT 1139.520 247.190 1139.780 247.510 ; + RECT 1139.580 16.730 1139.720 247.190 ; + RECT 1139.580 16.590 1144.780 16.730 ; + RECT 1144.640 2.400 1144.780 16.590 ; + RECT 1144.430 -4.800 1144.990 2.400 ; +======= LAYER met2 ; RECT 1144.430 -4.800 1144.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[28] PIN la_oen[29] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 855.210 17.580 855.530 17.640 ; + RECT 1162.490 17.580 1162.810 17.640 ; + RECT 855.210 17.440 1162.810 17.580 ; + RECT 855.210 17.380 855.530 17.440 ; + RECT 1162.490 17.380 1162.810 17.440 ; + LAYER via ; + RECT 855.240 17.380 855.500 17.640 ; + RECT 1162.520 17.380 1162.780 17.640 ; + LAYER met2 ; + RECT 854.730 260.170 855.010 264.000 ; + RECT 854.730 260.030 855.440 260.170 ; + RECT 854.730 260.000 855.010 260.030 ; + RECT 855.300 17.670 855.440 260.030 ; + RECT 855.240 17.350 855.500 17.670 ; + RECT 1162.520 17.350 1162.780 17.670 ; + RECT 1162.580 2.400 1162.720 17.350 ; + RECT 1162.370 -4.800 1162.930 2.400 ; +======= LAYER met2 ; RECT 1162.370 -4.800 1162.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[29] PIN la_oen[2] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 372.210 245.720 372.530 245.780 ; + RECT 677.190 245.720 677.510 245.780 ; + RECT 372.210 245.580 677.510 245.720 ; + RECT 372.210 245.520 372.530 245.580 ; + RECT 677.190 245.520 677.510 245.580 ; + LAYER via ; + RECT 372.240 245.520 372.500 245.780 ; + RECT 677.220 245.520 677.480 245.780 ; + LAYER met2 ; + RECT 372.190 260.000 372.470 264.000 ; + RECT 372.300 245.810 372.440 260.000 ; + RECT 372.240 245.490 372.500 245.810 ; + RECT 677.220 245.490 677.480 245.810 ; + RECT 677.280 16.730 677.420 245.490 ; + RECT 677.280 16.590 680.640 16.730 ; + RECT 680.500 2.400 680.640 16.590 ; + RECT 680.290 -4.800 680.850 2.400 ; +======= LAYER met2 ; RECT 680.290 -4.800 680.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[2] PIN la_oen[30] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 872.690 246.400 873.010 246.460 ; + RECT 1180.890 246.400 1181.210 246.460 ; + RECT 872.690 246.260 1181.210 246.400 ; + RECT 872.690 246.200 873.010 246.260 ; + RECT 1180.890 246.200 1181.210 246.260 ; + LAYER via ; + RECT 872.720 246.200 872.980 246.460 ; + RECT 1180.920 246.200 1181.180 246.460 ; + LAYER met2 ; + RECT 872.670 260.000 872.950 264.000 ; + RECT 872.780 246.490 872.920 260.000 ; + RECT 872.720 246.170 872.980 246.490 ; + RECT 1180.920 246.170 1181.180 246.490 ; + RECT 1180.980 17.410 1181.120 246.170 ; + RECT 1180.060 17.270 1181.120 17.410 ; + RECT 1180.060 2.400 1180.200 17.270 ; + RECT 1179.850 -4.800 1180.410 2.400 ; +======= LAYER met2 ; RECT 1179.850 -4.800 1180.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[30] PIN la_oen[31] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 890.630 244.020 890.950 244.080 ; + RECT 896.610 244.020 896.930 244.080 ; + RECT 890.630 243.880 896.930 244.020 ; + RECT 890.630 243.820 890.950 243.880 ; + RECT 896.610 243.820 896.930 243.880 ; + RECT 896.610 15.540 896.930 15.600 ; + RECT 1197.910 15.540 1198.230 15.600 ; + RECT 896.610 15.400 1198.230 15.540 ; + RECT 896.610 15.340 896.930 15.400 ; + RECT 1197.910 15.340 1198.230 15.400 ; + LAYER via ; + RECT 890.660 243.820 890.920 244.080 ; + RECT 896.640 243.820 896.900 244.080 ; + RECT 896.640 15.340 896.900 15.600 ; + RECT 1197.940 15.340 1198.200 15.600 ; + LAYER met2 ; + RECT 890.610 260.000 890.890 264.000 ; + RECT 890.720 244.110 890.860 260.000 ; + RECT 890.660 243.790 890.920 244.110 ; + RECT 896.640 243.790 896.900 244.110 ; + RECT 896.700 15.630 896.840 243.790 ; + RECT 896.640 15.310 896.900 15.630 ; + RECT 1197.940 15.310 1198.200 15.630 ; + RECT 1198.000 2.400 1198.140 15.310 ; + RECT 1197.790 -4.800 1198.350 2.400 ; +======= LAYER met2 ; RECT 1197.790 -4.800 1198.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[31] PIN la_oen[32] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 908.570 245.040 908.890 245.100 ; + RECT 1214.930 245.040 1215.250 245.100 ; + RECT 908.570 244.900 1215.250 245.040 ; + RECT 908.570 244.840 908.890 244.900 ; + RECT 1214.930 244.840 1215.250 244.900 ; + LAYER via ; + RECT 908.600 244.840 908.860 245.100 ; + RECT 1214.960 244.840 1215.220 245.100 ; + LAYER met2 ; + RECT 908.550 260.000 908.830 264.000 ; + RECT 908.660 245.130 908.800 260.000 ; + RECT 908.600 244.810 908.860 245.130 ; + RECT 1214.960 244.810 1215.220 245.130 ; + RECT 1215.020 16.730 1215.160 244.810 ; + RECT 1215.020 16.590 1216.080 16.730 ; + RECT 1215.940 2.400 1216.080 16.590 ; + RECT 1215.730 -4.800 1216.290 2.400 ; +======= LAYER met2 ; RECT 1215.730 -4.800 1216.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[32] PIN la_oen[33] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 926.510 244.020 926.830 244.080 ; + RECT 931.110 244.020 931.430 244.080 ; + RECT 926.510 243.880 931.430 244.020 ; + RECT 926.510 243.820 926.830 243.880 ; + RECT 931.110 243.820 931.430 243.880 ; + RECT 931.110 15.200 931.430 15.260 ; + RECT 1233.790 15.200 1234.110 15.260 ; + RECT 931.110 15.060 1234.110 15.200 ; + RECT 931.110 15.000 931.430 15.060 ; + RECT 1233.790 15.000 1234.110 15.060 ; + LAYER via ; + RECT 926.540 243.820 926.800 244.080 ; + RECT 931.140 243.820 931.400 244.080 ; + RECT 931.140 15.000 931.400 15.260 ; + RECT 1233.820 15.000 1234.080 15.260 ; + LAYER met2 ; + RECT 926.490 260.000 926.770 264.000 ; + RECT 926.600 244.110 926.740 260.000 ; + RECT 926.540 243.790 926.800 244.110 ; + RECT 931.140 243.790 931.400 244.110 ; + RECT 931.200 15.290 931.340 243.790 ; + RECT 931.140 14.970 931.400 15.290 ; + RECT 1233.820 14.970 1234.080 15.290 ; + RECT 1233.880 2.400 1234.020 14.970 ; + RECT 1233.670 -4.800 1234.230 2.400 ; +======= LAYER met2 ; RECT 1233.670 -4.800 1234.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[33] PIN la_oen[34] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 944.450 246.740 944.770 246.800 ; + RECT 1249.430 246.740 1249.750 246.800 ; + RECT 944.450 246.600 1249.750 246.740 ; + RECT 944.450 246.540 944.770 246.600 ; + RECT 1249.430 246.540 1249.750 246.600 ; + LAYER via ; + RECT 944.480 246.540 944.740 246.800 ; + RECT 1249.460 246.540 1249.720 246.800 ; + LAYER met2 ; + RECT 944.430 260.000 944.710 264.000 ; + RECT 944.540 246.830 944.680 260.000 ; + RECT 944.480 246.510 944.740 246.830 ; + RECT 1249.460 246.510 1249.720 246.830 ; + RECT 1249.520 16.730 1249.660 246.510 ; + RECT 1249.520 16.590 1251.960 16.730 ; + RECT 1251.820 2.400 1251.960 16.590 ; + RECT 1251.610 -4.800 1252.170 2.400 ; +======= LAYER met2 ; RECT 1251.610 -4.800 1252.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[34] PIN la_oen[35] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 965.610 15.880 965.930 15.940 ; + RECT 1269.210 15.880 1269.530 15.940 ; + RECT 965.610 15.740 1269.530 15.880 ; + RECT 965.610 15.680 965.930 15.740 ; + RECT 1269.210 15.680 1269.530 15.740 ; + LAYER via ; + RECT 965.640 15.680 965.900 15.940 ; + RECT 1269.240 15.680 1269.500 15.940 ; + LAYER met2 ; + RECT 961.910 260.170 962.190 264.000 ; + RECT 961.910 260.030 965.840 260.170 ; + RECT 961.910 260.000 962.190 260.030 ; + RECT 965.700 15.970 965.840 260.030 ; + RECT 965.640 15.650 965.900 15.970 ; + RECT 1269.240 15.650 1269.500 15.970 ; + RECT 1269.300 2.400 1269.440 15.650 ; + RECT 1269.090 -4.800 1269.650 2.400 ; +======= LAYER met2 ; RECT 1269.090 -4.800 1269.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[35] PIN la_oen[36] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 979.870 243.340 980.190 243.400 ; + RECT 986.310 243.340 986.630 243.400 ; + RECT 979.870 243.200 986.630 243.340 ; + RECT 979.870 243.140 980.190 243.200 ; + RECT 986.310 243.140 986.630 243.200 ; + RECT 986.310 16.220 986.630 16.280 ; + RECT 1287.150 16.220 1287.470 16.280 ; + RECT 986.310 16.080 1287.470 16.220 ; + RECT 986.310 16.020 986.630 16.080 ; + RECT 1287.150 16.020 1287.470 16.080 ; + LAYER via ; + RECT 979.900 243.140 980.160 243.400 ; + RECT 986.340 243.140 986.600 243.400 ; + RECT 986.340 16.020 986.600 16.280 ; + RECT 1287.180 16.020 1287.440 16.280 ; + LAYER met2 ; + RECT 979.850 260.000 980.130 264.000 ; + RECT 979.960 243.430 980.100 260.000 ; + RECT 979.900 243.110 980.160 243.430 ; + RECT 986.340 243.110 986.600 243.430 ; + RECT 986.400 16.310 986.540 243.110 ; + RECT 986.340 15.990 986.600 16.310 ; + RECT 1287.180 15.990 1287.440 16.310 ; + RECT 1287.240 2.400 1287.380 15.990 ; + RECT 1287.030 -4.800 1287.590 2.400 ; +======= LAYER met2 ; RECT 1287.030 -4.800 1287.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[36] PIN la_oen[37] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1000.110 19.620 1000.430 19.680 ; + RECT 1305.090 19.620 1305.410 19.680 ; + RECT 1000.110 19.480 1305.410 19.620 ; + RECT 1000.110 19.420 1000.430 19.480 ; + RECT 1305.090 19.420 1305.410 19.480 ; + LAYER via ; + RECT 1000.140 19.420 1000.400 19.680 ; + RECT 1305.120 19.420 1305.380 19.680 ; + LAYER met2 ; + RECT 997.790 260.170 998.070 264.000 ; + RECT 997.790 260.030 1000.340 260.170 ; + RECT 997.790 260.000 998.070 260.030 ; + RECT 1000.200 19.710 1000.340 260.030 ; + RECT 1000.140 19.390 1000.400 19.710 ; + RECT 1305.120 19.390 1305.380 19.710 ; + RECT 1305.180 2.400 1305.320 19.390 ; + RECT 1304.970 -4.800 1305.530 2.400 ; +======= LAYER met2 ; RECT 1304.970 -4.800 1305.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[37] PIN la_oen[38] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1015.750 244.020 1016.070 244.080 ; + RECT 1020.810 244.020 1021.130 244.080 ; + RECT 1015.750 243.880 1021.130 244.020 ; + RECT 1015.750 243.820 1016.070 243.880 ; + RECT 1020.810 243.820 1021.130 243.880 ; + RECT 1020.810 16.560 1021.130 16.620 ; + RECT 1323.030 16.560 1323.350 16.620 ; + RECT 1020.810 16.420 1323.350 16.560 ; + RECT 1020.810 16.360 1021.130 16.420 ; + RECT 1323.030 16.360 1323.350 16.420 ; + LAYER via ; + RECT 1015.780 243.820 1016.040 244.080 ; + RECT 1020.840 243.820 1021.100 244.080 ; + RECT 1020.840 16.360 1021.100 16.620 ; + RECT 1323.060 16.360 1323.320 16.620 ; + LAYER met2 ; + RECT 1015.730 260.000 1016.010 264.000 ; + RECT 1015.840 244.110 1015.980 260.000 ; + RECT 1015.780 243.790 1016.040 244.110 ; + RECT 1020.840 243.790 1021.100 244.110 ; + RECT 1020.900 16.650 1021.040 243.790 ; + RECT 1020.840 16.330 1021.100 16.650 ; + RECT 1323.060 16.330 1323.320 16.650 ; + RECT 1323.120 2.400 1323.260 16.330 ; + RECT 1322.910 -4.800 1323.470 2.400 ; +======= LAYER met2 ; RECT 1322.910 -4.800 1323.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[38] PIN la_oen[39] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1034.610 18.600 1034.930 18.660 ; + RECT 1340.510 18.600 1340.830 18.660 ; + RECT 1034.610 18.460 1340.830 18.600 ; + RECT 1034.610 18.400 1034.930 18.460 ; + RECT 1340.510 18.400 1340.830 18.460 ; + LAYER via ; + RECT 1034.640 18.400 1034.900 18.660 ; + RECT 1340.540 18.400 1340.800 18.660 ; + LAYER met2 ; + RECT 1033.670 260.170 1033.950 264.000 ; + RECT 1033.670 260.030 1034.840 260.170 ; + RECT 1033.670 260.000 1033.950 260.030 ; + RECT 1034.700 18.690 1034.840 260.030 ; + RECT 1034.640 18.370 1034.900 18.690 ; + RECT 1340.540 18.370 1340.800 18.690 ; + RECT 1340.600 2.400 1340.740 18.370 ; + RECT 1340.390 -4.800 1340.950 2.400 ; +======= LAYER met2 ; RECT 1340.390 -4.800 1340.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[39] PIN la_oen[3] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 663.020 19.480 669.600 19.620 ; + RECT 392.910 19.280 393.230 19.340 ; + RECT 663.020 19.280 663.160 19.480 ; + RECT 392.910 19.140 663.160 19.280 ; + RECT 669.460 19.280 669.600 19.480 ; + RECT 698.350 19.280 698.670 19.340 ; + RECT 669.460 19.140 698.670 19.280 ; + RECT 392.910 19.080 393.230 19.140 ; + RECT 698.350 19.080 698.670 19.140 ; + LAYER via ; + RECT 392.940 19.080 393.200 19.340 ; + RECT 698.380 19.080 698.640 19.340 ; + LAYER met2 ; + RECT 390.130 260.170 390.410 264.000 ; + RECT 390.130 260.030 393.140 260.170 ; + RECT 390.130 260.000 390.410 260.030 ; + RECT 393.000 19.370 393.140 260.030 ; + RECT 392.940 19.050 393.200 19.370 ; + RECT 698.380 19.050 698.640 19.370 ; + RECT 698.440 2.400 698.580 19.050 ; + RECT 698.230 -4.800 698.790 2.400 ; +======= LAYER met2 ; RECT 698.230 -4.800 698.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[3] PIN la_oen[40] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1051.630 246.060 1051.950 246.120 ; + RECT 1352.470 246.060 1352.790 246.120 ; + RECT 1051.630 245.920 1352.790 246.060 ; + RECT 1051.630 245.860 1051.950 245.920 ; + RECT 1352.470 245.860 1352.790 245.920 ; + RECT 1352.470 16.900 1352.790 16.960 ; + RECT 1358.450 16.900 1358.770 16.960 ; + RECT 1352.470 16.760 1358.770 16.900 ; + RECT 1352.470 16.700 1352.790 16.760 ; + RECT 1358.450 16.700 1358.770 16.760 ; + LAYER via ; + RECT 1051.660 245.860 1051.920 246.120 ; + RECT 1352.500 245.860 1352.760 246.120 ; + RECT 1352.500 16.700 1352.760 16.960 ; + RECT 1358.480 16.700 1358.740 16.960 ; + LAYER met2 ; + RECT 1051.610 260.000 1051.890 264.000 ; + RECT 1051.720 246.150 1051.860 260.000 ; + RECT 1051.660 245.830 1051.920 246.150 ; + RECT 1352.500 245.830 1352.760 246.150 ; + RECT 1352.560 16.990 1352.700 245.830 ; + RECT 1352.500 16.670 1352.760 16.990 ; + RECT 1358.480 16.670 1358.740 16.990 ; + RECT 1358.540 2.400 1358.680 16.670 ; + RECT 1358.330 -4.800 1358.890 2.400 ; +======= LAYER met2 ; RECT 1358.330 -4.800 1358.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[40] PIN la_oen[41] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1069.570 244.020 1069.890 244.080 ; + RECT 1076.010 244.020 1076.330 244.080 ; + RECT 1069.570 243.880 1076.330 244.020 ; + RECT 1069.570 243.820 1069.890 243.880 ; + RECT 1076.010 243.820 1076.330 243.880 ; + RECT 1076.010 16.900 1076.330 16.960 ; + RECT 1076.010 16.760 1338.900 16.900 ; + RECT 1076.010 16.700 1076.330 16.760 ; + RECT 1338.760 16.220 1338.900 16.760 ; + RECT 1376.390 16.220 1376.710 16.280 ; + RECT 1338.760 16.080 1376.710 16.220 ; + RECT 1376.390 16.020 1376.710 16.080 ; + LAYER via ; + RECT 1069.600 243.820 1069.860 244.080 ; + RECT 1076.040 243.820 1076.300 244.080 ; + RECT 1076.040 16.700 1076.300 16.960 ; + RECT 1376.420 16.020 1376.680 16.280 ; + LAYER met2 ; + RECT 1069.550 260.000 1069.830 264.000 ; + RECT 1069.660 244.110 1069.800 260.000 ; + RECT 1069.600 243.790 1069.860 244.110 ; + RECT 1076.040 243.790 1076.300 244.110 ; + RECT 1076.100 16.990 1076.240 243.790 ; + RECT 1076.040 16.670 1076.300 16.990 ; + RECT 1376.420 15.990 1376.680 16.310 ; + RECT 1376.480 2.400 1376.620 15.990 ; + RECT 1376.270 -4.800 1376.830 2.400 ; +======= LAYER met2 ; RECT 1376.270 -4.800 1376.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[41] PIN la_oen[42] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1087.050 245.380 1087.370 245.440 ; + RECT 1394.790 245.380 1395.110 245.440 ; + RECT 1087.050 245.240 1395.110 245.380 ; + RECT 1087.050 245.180 1087.370 245.240 ; + RECT 1394.790 245.180 1395.110 245.240 ; + LAYER via ; + RECT 1087.080 245.180 1087.340 245.440 ; + RECT 1394.820 245.180 1395.080 245.440 ; + LAYER met2 ; + RECT 1087.030 260.000 1087.310 264.000 ; + RECT 1087.140 245.470 1087.280 260.000 ; + RECT 1087.080 245.150 1087.340 245.470 ; + RECT 1394.820 245.150 1395.080 245.470 ; + RECT 1394.880 17.410 1395.020 245.150 ; + RECT 1394.420 17.270 1395.020 17.410 ; + RECT 1394.420 2.400 1394.560 17.270 ; + RECT 1394.210 -4.800 1394.770 2.400 ; +======= LAYER met2 ; RECT 1394.210 -4.800 1394.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[42] PIN la_oen[43] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1104.990 244.020 1105.310 244.080 ; + RECT 1110.510 244.020 1110.830 244.080 ; + RECT 1104.990 243.880 1110.830 244.020 ; + RECT 1104.990 243.820 1105.310 243.880 ; + RECT 1110.510 243.820 1110.830 243.880 ; + RECT 1110.510 18.940 1110.830 19.000 ; + RECT 1412.270 18.940 1412.590 19.000 ; + RECT 1110.510 18.800 1412.590 18.940 ; + RECT 1110.510 18.740 1110.830 18.800 ; + RECT 1412.270 18.740 1412.590 18.800 ; + LAYER via ; + RECT 1105.020 243.820 1105.280 244.080 ; + RECT 1110.540 243.820 1110.800 244.080 ; + RECT 1110.540 18.740 1110.800 19.000 ; + RECT 1412.300 18.740 1412.560 19.000 ; + LAYER met2 ; + RECT 1104.970 260.000 1105.250 264.000 ; + RECT 1105.080 244.110 1105.220 260.000 ; + RECT 1105.020 243.790 1105.280 244.110 ; + RECT 1110.540 243.790 1110.800 244.110 ; + RECT 1110.600 19.030 1110.740 243.790 ; + RECT 1110.540 18.710 1110.800 19.030 ; + RECT 1412.300 18.710 1412.560 19.030 ; + RECT 1412.360 2.400 1412.500 18.710 ; + RECT 1412.150 -4.800 1412.710 2.400 ; +======= LAYER met2 ; RECT 1412.150 -4.800 1412.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[43] PIN la_oen[44] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1122.930 245.720 1123.250 245.780 ; + RECT 1428.830 245.720 1429.150 245.780 ; + RECT 1122.930 245.580 1429.150 245.720 ; + RECT 1122.930 245.520 1123.250 245.580 ; + RECT 1428.830 245.520 1429.150 245.580 ; + LAYER via ; + RECT 1122.960 245.520 1123.220 245.780 ; + RECT 1428.860 245.520 1429.120 245.780 ; + LAYER met2 ; + RECT 1122.910 260.000 1123.190 264.000 ; + RECT 1123.020 245.810 1123.160 260.000 ; + RECT 1122.960 245.490 1123.220 245.810 ; + RECT 1428.860 245.490 1429.120 245.810 ; + RECT 1428.920 16.900 1429.060 245.490 ; + RECT 1428.920 16.760 1429.980 16.900 ; + RECT 1429.840 2.400 1429.980 16.760 ; + RECT 1429.630 -4.800 1430.190 2.400 ; +======= LAYER met2 ; RECT 1429.630 -4.800 1430.190 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[44] PIN la_oen[45] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1140.870 244.020 1141.190 244.080 ; + RECT 1145.010 244.020 1145.330 244.080 ; + RECT 1140.870 243.880 1145.330 244.020 ; + RECT 1140.870 243.820 1141.190 243.880 ; + RECT 1145.010 243.820 1145.330 243.880 ; + RECT 1145.010 19.280 1145.330 19.340 ; + RECT 1447.690 19.280 1448.010 19.340 ; + RECT 1145.010 19.140 1448.010 19.280 ; + RECT 1145.010 19.080 1145.330 19.140 ; + RECT 1447.690 19.080 1448.010 19.140 ; + LAYER via ; + RECT 1140.900 243.820 1141.160 244.080 ; + RECT 1145.040 243.820 1145.300 244.080 ; + RECT 1145.040 19.080 1145.300 19.340 ; + RECT 1447.720 19.080 1447.980 19.340 ; + LAYER met2 ; + RECT 1140.850 260.000 1141.130 264.000 ; + RECT 1140.960 244.110 1141.100 260.000 ; + RECT 1140.900 243.790 1141.160 244.110 ; + RECT 1145.040 243.790 1145.300 244.110 ; + RECT 1145.100 19.370 1145.240 243.790 ; + RECT 1145.040 19.050 1145.300 19.370 ; + RECT 1447.720 19.050 1447.980 19.370 ; + RECT 1447.780 2.400 1447.920 19.050 ; + RECT 1447.570 -4.800 1448.130 2.400 ; +======= LAYER met2 ; RECT 1447.570 -4.800 1448.130 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[45] PIN la_oen[46] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1158.810 18.260 1159.130 18.320 ; + RECT 1465.630 18.260 1465.950 18.320 ; + RECT 1158.810 18.120 1465.950 18.260 ; + RECT 1158.810 18.060 1159.130 18.120 ; + RECT 1465.630 18.060 1465.950 18.120 ; + LAYER via ; + RECT 1158.840 18.060 1159.100 18.320 ; + RECT 1465.660 18.060 1465.920 18.320 ; + LAYER met2 ; + RECT 1158.790 260.000 1159.070 264.000 ; + RECT 1158.900 18.350 1159.040 260.000 ; + RECT 1158.840 18.030 1159.100 18.350 ; + RECT 1465.660 18.030 1465.920 18.350 ; + RECT 1465.720 2.400 1465.860 18.030 ; + RECT 1465.510 -4.800 1466.070 2.400 ; +======= LAYER met2 ; RECT 1465.510 -4.800 1466.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[46] PIN la_oen[47] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1179.510 17.240 1179.830 17.300 ; + RECT 1483.570 17.240 1483.890 17.300 ; + RECT 1179.510 17.100 1483.890 17.240 ; + RECT 1179.510 17.040 1179.830 17.100 ; + RECT 1483.570 17.040 1483.890 17.100 ; + LAYER via ; + RECT 1179.540 17.040 1179.800 17.300 ; + RECT 1483.600 17.040 1483.860 17.300 ; + LAYER met2 ; + RECT 1176.730 260.170 1177.010 264.000 ; + RECT 1176.730 260.030 1179.740 260.170 ; + RECT 1176.730 260.000 1177.010 260.030 ; + RECT 1179.600 17.330 1179.740 260.030 ; + RECT 1179.540 17.010 1179.800 17.330 ; + RECT 1483.600 17.010 1483.860 17.330 ; + RECT 1483.660 2.400 1483.800 17.010 ; + RECT 1483.450 -4.800 1484.010 2.400 ; +======= LAYER met2 ; RECT 1483.450 -4.800 1484.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[47] PIN la_oen[48] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1194.690 243.680 1195.010 243.740 ; + RECT 1200.210 243.680 1200.530 243.740 ; + RECT 1194.690 243.540 1200.530 243.680 ; + RECT 1194.690 243.480 1195.010 243.540 ; + RECT 1200.210 243.480 1200.530 243.540 ; + RECT 1200.210 20.640 1200.530 20.700 ; + RECT 1501.510 20.640 1501.830 20.700 ; + RECT 1200.210 20.500 1501.830 20.640 ; + RECT 1200.210 20.440 1200.530 20.500 ; + RECT 1501.510 20.440 1501.830 20.500 ; + LAYER via ; + RECT 1194.720 243.480 1194.980 243.740 ; + RECT 1200.240 243.480 1200.500 243.740 ; + RECT 1200.240 20.440 1200.500 20.700 ; + RECT 1501.540 20.440 1501.800 20.700 ; + LAYER met2 ; + RECT 1194.670 260.000 1194.950 264.000 ; + RECT 1194.780 243.770 1194.920 260.000 ; + RECT 1194.720 243.450 1194.980 243.770 ; + RECT 1200.240 243.450 1200.500 243.770 ; + RECT 1200.300 20.730 1200.440 243.450 ; + RECT 1200.240 20.410 1200.500 20.730 ; + RECT 1501.540 20.410 1501.800 20.730 ; + RECT 1501.600 2.400 1501.740 20.410 ; + RECT 1501.390 -4.800 1501.950 2.400 ; +======= LAYER met2 ; RECT 1501.390 -4.800 1501.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[48] PIN la_oen[49] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1214.010 17.920 1214.330 17.980 ; + RECT 1518.990 17.920 1519.310 17.980 ; + RECT 1214.010 17.780 1519.310 17.920 ; + RECT 1214.010 17.720 1214.330 17.780 ; + RECT 1518.990 17.720 1519.310 17.780 ; + LAYER via ; + RECT 1214.040 17.720 1214.300 17.980 ; + RECT 1519.020 17.720 1519.280 17.980 ; + LAYER met2 ; + RECT 1212.150 260.170 1212.430 264.000 ; + RECT 1212.150 260.030 1214.240 260.170 ; + RECT 1212.150 260.000 1212.430 260.030 ; + RECT 1214.100 18.010 1214.240 260.030 ; + RECT 1214.040 17.690 1214.300 18.010 ; + RECT 1519.020 17.690 1519.280 18.010 ; + RECT 1519.080 2.400 1519.220 17.690 ; + RECT 1518.870 -4.800 1519.430 2.400 ; +======= LAYER met2 ; RECT 1518.870 -4.800 1519.430 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[49] PIN la_oen[4] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 408.090 246.060 408.410 246.120 ; + RECT 711.230 246.060 711.550 246.120 ; + RECT 408.090 245.920 711.550 246.060 ; + RECT 408.090 245.860 408.410 245.920 ; + RECT 711.230 245.860 711.550 245.920 ; + LAYER via ; + RECT 408.120 245.860 408.380 246.120 ; + RECT 711.260 245.860 711.520 246.120 ; + LAYER met2 ; + RECT 408.070 260.000 408.350 264.000 ; + RECT 408.180 246.150 408.320 260.000 ; + RECT 408.120 245.830 408.380 246.150 ; + RECT 711.260 245.830 711.520 246.150 ; + RECT 711.320 16.730 711.460 245.830 ; + RECT 711.320 16.590 716.520 16.730 ; + RECT 716.380 2.400 716.520 16.590 ; + RECT 716.170 -4.800 716.730 2.400 ; +======= LAYER met2 ; RECT 716.170 -4.800 716.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[4] PIN la_oen[50] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1230.110 244.020 1230.430 244.080 ; + RECT 1234.710 244.020 1235.030 244.080 ; + RECT 1230.110 243.880 1235.030 244.020 ; + RECT 1230.110 243.820 1230.430 243.880 ; + RECT 1234.710 243.820 1235.030 243.880 ; + RECT 1234.710 19.960 1235.030 20.020 ; + RECT 1536.930 19.960 1537.250 20.020 ; + RECT 1234.710 19.820 1537.250 19.960 ; + RECT 1234.710 19.760 1235.030 19.820 ; + RECT 1536.930 19.760 1537.250 19.820 ; + LAYER via ; + RECT 1230.140 243.820 1230.400 244.080 ; + RECT 1234.740 243.820 1235.000 244.080 ; + RECT 1234.740 19.760 1235.000 20.020 ; + RECT 1536.960 19.760 1537.220 20.020 ; + LAYER met2 ; + RECT 1230.090 260.000 1230.370 264.000 ; + RECT 1230.200 244.110 1230.340 260.000 ; + RECT 1230.140 243.790 1230.400 244.110 ; + RECT 1234.740 243.790 1235.000 244.110 ; + RECT 1234.800 20.050 1234.940 243.790 ; + RECT 1234.740 19.730 1235.000 20.050 ; + RECT 1536.960 19.730 1537.220 20.050 ; + RECT 1537.020 2.400 1537.160 19.730 ; + RECT 1536.810 -4.800 1537.370 2.400 ; +======= LAYER met2 ; RECT 1536.810 -4.800 1537.370 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[50] PIN la_oen[51] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1248.510 17.580 1248.830 17.640 ; + RECT 1554.870 17.580 1555.190 17.640 ; + RECT 1248.510 17.440 1555.190 17.580 ; + RECT 1248.510 17.380 1248.830 17.440 ; + RECT 1554.870 17.380 1555.190 17.440 ; + LAYER via ; + RECT 1248.540 17.380 1248.800 17.640 ; + RECT 1554.900 17.380 1555.160 17.640 ; + LAYER met2 ; + RECT 1248.030 260.170 1248.310 264.000 ; + RECT 1248.030 260.030 1248.740 260.170 ; + RECT 1248.030 260.000 1248.310 260.030 ; + RECT 1248.600 17.670 1248.740 260.030 ; + RECT 1248.540 17.350 1248.800 17.670 ; + RECT 1554.900 17.350 1555.160 17.670 ; + RECT 1554.960 2.400 1555.100 17.350 ; + RECT 1554.750 -4.800 1555.310 2.400 ; +======= LAYER met2 ; RECT 1554.750 -4.800 1555.310 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[51] PIN la_oen[52] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1265.990 246.400 1266.310 246.460 ; + RECT 1567.290 246.400 1567.610 246.460 ; + RECT 1265.990 246.260 1567.610 246.400 ; + RECT 1265.990 246.200 1266.310 246.260 ; + RECT 1567.290 246.200 1567.610 246.260 ; + LAYER via ; + RECT 1266.020 246.200 1266.280 246.460 ; + RECT 1567.320 246.200 1567.580 246.460 ; + LAYER met2 ; + RECT 1265.970 260.000 1266.250 264.000 ; + RECT 1266.080 246.490 1266.220 260.000 ; + RECT 1266.020 246.170 1266.280 246.490 ; + RECT 1567.320 246.170 1567.580 246.490 ; + RECT 1567.380 16.730 1567.520 246.170 ; + RECT 1567.380 16.590 1573.040 16.730 ; + RECT 1572.900 2.400 1573.040 16.590 ; + RECT 1572.690 -4.800 1573.250 2.400 ; +======= LAYER met2 ; RECT 1572.690 -4.800 1573.250 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[52] PIN la_oen[53] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1283.930 244.020 1284.250 244.080 ; + RECT 1289.910 244.020 1290.230 244.080 ; + RECT 1283.930 243.880 1290.230 244.020 ; + RECT 1283.930 243.820 1284.250 243.880 ; + RECT 1289.910 243.820 1290.230 243.880 ; + RECT 1289.910 20.300 1290.230 20.360 ; + RECT 1590.290 20.300 1590.610 20.360 ; + RECT 1289.910 20.160 1590.610 20.300 ; + RECT 1289.910 20.100 1290.230 20.160 ; + RECT 1590.290 20.100 1590.610 20.160 ; + LAYER via ; + RECT 1283.960 243.820 1284.220 244.080 ; + RECT 1289.940 243.820 1290.200 244.080 ; + RECT 1289.940 20.100 1290.200 20.360 ; + RECT 1590.320 20.100 1590.580 20.360 ; + LAYER met2 ; + RECT 1283.910 260.000 1284.190 264.000 ; + RECT 1284.020 244.110 1284.160 260.000 ; + RECT 1283.960 243.790 1284.220 244.110 ; + RECT 1289.940 243.790 1290.200 244.110 ; + RECT 1290.000 20.390 1290.140 243.790 ; + RECT 1289.940 20.070 1290.200 20.390 ; + RECT 1590.320 20.070 1590.580 20.390 ; + RECT 1590.380 2.400 1590.520 20.070 ; + RECT 1590.170 -4.800 1590.730 2.400 ; +======= LAYER met2 ; RECT 1590.170 -4.800 1590.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[53] PIN la_oen[54] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1301.870 245.040 1302.190 245.100 ; + RECT 1608.690 245.040 1609.010 245.100 ; + RECT 1301.870 244.900 1609.010 245.040 ; + RECT 1301.870 244.840 1302.190 244.900 ; + RECT 1608.690 244.840 1609.010 244.900 ; + LAYER via ; + RECT 1301.900 244.840 1302.160 245.100 ; + RECT 1608.720 244.840 1608.980 245.100 ; + LAYER met2 ; + RECT 1301.850 260.000 1302.130 264.000 ; + RECT 1301.960 245.130 1302.100 260.000 ; + RECT 1301.900 244.810 1302.160 245.130 ; + RECT 1608.720 244.810 1608.980 245.130 ; + RECT 1608.780 37.810 1608.920 244.810 ; + RECT 1608.320 37.670 1608.920 37.810 ; + RECT 1608.320 2.400 1608.460 37.670 ; + RECT 1608.110 -4.800 1608.670 2.400 ; +======= LAYER met2 ; RECT 1608.110 -4.800 1608.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[54] PIN la_oen[55] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1319.810 244.020 1320.130 244.080 ; + RECT 1324.410 244.020 1324.730 244.080 ; + RECT 1319.810 243.880 1324.730 244.020 ; + RECT 1319.810 243.820 1320.130 243.880 ; + RECT 1324.410 243.820 1324.730 243.880 ; + RECT 1626.170 38.660 1626.490 38.720 ; + RECT 1607.860 38.520 1626.490 38.660 ; + RECT 1324.410 38.320 1324.730 38.380 ; + RECT 1607.860 38.320 1608.000 38.520 ; + RECT 1626.170 38.460 1626.490 38.520 ; + RECT 1324.410 38.180 1608.000 38.320 ; + RECT 1324.410 38.120 1324.730 38.180 ; + LAYER via ; + RECT 1319.840 243.820 1320.100 244.080 ; + RECT 1324.440 243.820 1324.700 244.080 ; + RECT 1324.440 38.120 1324.700 38.380 ; + RECT 1626.200 38.460 1626.460 38.720 ; + LAYER met2 ; + RECT 1319.790 260.000 1320.070 264.000 ; + RECT 1319.900 244.110 1320.040 260.000 ; + RECT 1319.840 243.790 1320.100 244.110 ; + RECT 1324.440 243.790 1324.700 244.110 ; + RECT 1324.500 38.410 1324.640 243.790 ; + RECT 1626.200 38.430 1626.460 38.750 ; + RECT 1324.440 38.090 1324.700 38.410 ; + RECT 1626.260 2.400 1626.400 38.430 ; + RECT 1626.050 -4.800 1626.610 2.400 ; +======= LAYER met2 ; RECT 1626.050 -4.800 1626.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[55] PIN la_oen[56] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1642.345 48.365 1642.515 96.475 ; + LAYER mcon ; + RECT 1642.345 96.305 1642.515 96.475 ; + LAYER met1 ; + RECT 1338.210 127.740 1338.530 127.800 ; + RECT 1642.730 127.740 1643.050 127.800 ; + RECT 1338.210 127.600 1643.050 127.740 ; + RECT 1338.210 127.540 1338.530 127.600 ; + RECT 1642.730 127.540 1643.050 127.600 ; + RECT 1642.270 96.460 1642.590 96.520 ; + RECT 1642.270 96.320 1642.785 96.460 ; + RECT 1642.270 96.260 1642.590 96.320 ; + RECT 1642.285 48.520 1642.575 48.565 ; + RECT 1644.110 48.520 1644.430 48.580 ; + RECT 1642.285 48.380 1644.430 48.520 ; + RECT 1642.285 48.335 1642.575 48.380 ; + RECT 1644.110 48.320 1644.430 48.380 ; + RECT 1644.110 2.960 1644.430 3.020 ; + RECT 1644.570 2.960 1644.890 3.020 ; + RECT 1644.110 2.820 1644.890 2.960 ; + RECT 1644.110 2.760 1644.430 2.820 ; + RECT 1644.570 2.760 1644.890 2.820 ; + LAYER via ; + RECT 1338.240 127.540 1338.500 127.800 ; + RECT 1642.760 127.540 1643.020 127.800 ; + RECT 1642.300 96.260 1642.560 96.520 ; + RECT 1644.140 48.320 1644.400 48.580 ; + RECT 1644.140 2.760 1644.400 3.020 ; + RECT 1644.600 2.760 1644.860 3.020 ; + LAYER met2 ; + RECT 1337.270 260.170 1337.550 264.000 ; + RECT 1337.270 260.030 1338.440 260.170 ; + RECT 1337.270 260.000 1337.550 260.030 ; + RECT 1338.300 127.830 1338.440 260.030 ; + RECT 1338.240 127.510 1338.500 127.830 ; + RECT 1642.760 127.510 1643.020 127.830 ; + RECT 1642.820 96.970 1642.960 127.510 ; + RECT 1642.360 96.830 1642.960 96.970 ; + RECT 1642.360 96.550 1642.500 96.830 ; + RECT 1642.300 96.230 1642.560 96.550 ; + RECT 1644.140 48.290 1644.400 48.610 ; + RECT 1644.200 48.010 1644.340 48.290 ; + RECT 1644.200 47.870 1644.800 48.010 ; + RECT 1644.660 3.050 1644.800 47.870 ; + RECT 1644.140 2.730 1644.400 3.050 ; + RECT 1644.600 2.730 1644.860 3.050 ; + RECT 1644.200 2.400 1644.340 2.730 ; + RECT 1643.990 -4.800 1644.550 2.400 ; +======= LAYER met2 ; RECT 1643.990 -4.800 1644.550 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[56] PIN la_oen[57] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1355.230 243.680 1355.550 243.740 ; + RECT 1362.590 243.680 1362.910 243.740 ; + RECT 1355.230 243.540 1362.910 243.680 ; + RECT 1355.230 243.480 1355.550 243.540 ; + RECT 1362.590 243.480 1362.910 243.540 ; + RECT 1362.590 134.880 1362.910 134.940 ; + RECT 1656.530 134.880 1656.850 134.940 ; + RECT 1362.590 134.740 1656.850 134.880 ; + RECT 1362.590 134.680 1362.910 134.740 ; + RECT 1656.530 134.680 1656.850 134.740 ; + LAYER via ; + RECT 1355.260 243.480 1355.520 243.740 ; + RECT 1362.620 243.480 1362.880 243.740 ; + RECT 1362.620 134.680 1362.880 134.940 ; + RECT 1656.560 134.680 1656.820 134.940 ; + LAYER met2 ; + RECT 1355.210 260.000 1355.490 264.000 ; + RECT 1355.320 243.770 1355.460 260.000 ; + RECT 1355.260 243.450 1355.520 243.770 ; + RECT 1362.620 243.450 1362.880 243.770 ; + RECT 1362.680 134.970 1362.820 243.450 ; + RECT 1362.620 134.650 1362.880 134.970 ; + RECT 1656.560 134.650 1656.820 134.970 ; + RECT 1656.620 16.730 1656.760 134.650 ; + RECT 1656.620 16.590 1662.280 16.730 ; + RECT 1662.140 2.400 1662.280 16.590 ; + RECT 1661.930 -4.800 1662.490 2.400 ; +======= LAYER met2 ; RECT 1661.930 -4.800 1662.490 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[57] PIN la_oen[58] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1373.170 244.020 1373.490 244.080 ; + RECT 1379.150 244.020 1379.470 244.080 ; + RECT 1373.170 243.880 1379.470 244.020 ; + RECT 1373.170 243.820 1373.490 243.880 ; + RECT 1379.150 243.820 1379.470 243.880 ; + RECT 1379.150 120.940 1379.470 121.000 ; + RECT 1676.770 120.940 1677.090 121.000 ; + RECT 1379.150 120.800 1677.090 120.940 ; + RECT 1379.150 120.740 1379.470 120.800 ; + RECT 1676.770 120.740 1677.090 120.800 ; + LAYER via ; + RECT 1373.200 243.820 1373.460 244.080 ; + RECT 1379.180 243.820 1379.440 244.080 ; + RECT 1379.180 120.740 1379.440 121.000 ; + RECT 1676.800 120.740 1677.060 121.000 ; + LAYER met2 ; + RECT 1373.150 260.000 1373.430 264.000 ; + RECT 1373.260 244.110 1373.400 260.000 ; + RECT 1373.200 243.790 1373.460 244.110 ; + RECT 1379.180 243.790 1379.440 244.110 ; + RECT 1379.240 121.030 1379.380 243.790 ; + RECT 1379.180 120.710 1379.440 121.030 ; + RECT 1676.800 120.710 1677.060 121.030 ; + RECT 1676.860 17.410 1677.000 120.710 ; + RECT 1676.860 17.270 1679.760 17.410 ; + RECT 1679.620 2.400 1679.760 17.270 ; + RECT 1679.410 -4.800 1679.970 2.400 ; +======= LAYER met2 ; RECT 1679.410 -4.800 1679.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[58] PIN la_oen[59] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1391.110 231.440 1391.430 231.500 ; + RECT 1697.470 231.440 1697.790 231.500 ; + RECT 1391.110 231.300 1697.790 231.440 ; + RECT 1391.110 231.240 1391.430 231.300 ; + RECT 1697.470 231.240 1697.790 231.300 ; + LAYER via ; + RECT 1391.140 231.240 1391.400 231.500 ; + RECT 1697.500 231.240 1697.760 231.500 ; + LAYER met2 ; + RECT 1391.090 260.000 1391.370 264.000 ; + RECT 1391.200 231.530 1391.340 260.000 ; + RECT 1391.140 231.210 1391.400 231.530 ; + RECT 1697.500 231.210 1697.760 231.530 ; + RECT 1697.560 2.400 1697.700 231.210 ; + RECT 1697.350 -4.800 1697.910 2.400 ; +======= LAYER met2 ; RECT 1697.350 -4.800 1697.910 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[59] PIN la_oen[5] @@ -3884,143 +16863,602 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 426.010 260.170 426.290 264.000 ; + RECT 426.010 260.030 427.640 260.170 ; + RECT 426.010 260.000 426.290 260.030 ; + RECT 427.500 17.525 427.640 260.030 ; + RECT 427.430 17.155 427.710 17.525 ; + RECT 734.250 17.155 734.530 17.525 ; + RECT 734.320 2.400 734.460 17.155 ; + RECT 734.110 -4.800 734.670 2.400 ; + LAYER via2 ; + RECT 427.430 17.200 427.710 17.480 ; + RECT 734.250 17.200 734.530 17.480 ; + LAYER met3 ; + RECT 427.405 17.490 427.735 17.505 ; + RECT 734.225 17.490 734.555 17.505 ; + RECT 427.405 17.190 734.555 17.490 ; + RECT 427.405 17.175 427.735 17.190 ; + RECT 734.225 17.175 734.555 17.190 ; +======= RECT 734.110 -4.800 734.670 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[5] PIN la_oen[60] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1409.050 244.020 1409.370 244.080 ; + RECT 1414.110 244.020 1414.430 244.080 ; + RECT 1409.050 243.880 1414.430 244.020 ; + RECT 1409.050 243.820 1409.370 243.880 ; + RECT 1414.110 243.820 1414.430 243.880 ; + RECT 1414.110 31.180 1414.430 31.240 ; + RECT 1715.410 31.180 1715.730 31.240 ; + RECT 1414.110 31.040 1715.730 31.180 ; + RECT 1414.110 30.980 1414.430 31.040 ; + RECT 1715.410 30.980 1715.730 31.040 ; + LAYER via ; + RECT 1409.080 243.820 1409.340 244.080 ; + RECT 1414.140 243.820 1414.400 244.080 ; + RECT 1414.140 30.980 1414.400 31.240 ; + RECT 1715.440 30.980 1715.700 31.240 ; + LAYER met2 ; + RECT 1409.030 260.000 1409.310 264.000 ; + RECT 1409.140 244.110 1409.280 260.000 ; + RECT 1409.080 243.790 1409.340 244.110 ; + RECT 1414.140 243.790 1414.400 244.110 ; + RECT 1414.200 31.270 1414.340 243.790 ; + RECT 1414.140 30.950 1414.400 31.270 ; + RECT 1715.440 30.950 1715.700 31.270 ; + RECT 1715.500 2.400 1715.640 30.950 ; + RECT 1715.290 -4.800 1715.850 2.400 ; +======= LAYER met2 ; RECT 1715.290 -4.800 1715.850 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[60] PIN la_oen[61] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1427.910 51.920 1428.230 51.980 ; + RECT 1731.970 51.920 1732.290 51.980 ; + RECT 1427.910 51.780 1732.290 51.920 ; + RECT 1427.910 51.720 1428.230 51.780 ; + RECT 1731.970 51.720 1732.290 51.780 ; + LAYER via ; + RECT 1427.940 51.720 1428.200 51.980 ; + RECT 1732.000 51.720 1732.260 51.980 ; + LAYER met2 ; + RECT 1426.970 260.170 1427.250 264.000 ; + RECT 1426.970 260.030 1428.140 260.170 ; + RECT 1426.970 260.000 1427.250 260.030 ; + RECT 1428.000 52.010 1428.140 260.030 ; + RECT 1427.940 51.690 1428.200 52.010 ; + RECT 1732.000 51.690 1732.260 52.010 ; + RECT 1732.060 17.410 1732.200 51.690 ; + RECT 1732.060 17.270 1733.580 17.410 ; + RECT 1733.440 2.400 1733.580 17.270 ; + RECT 1733.230 -4.800 1733.790 2.400 ; +======= LAYER met2 ; RECT 1733.230 -4.800 1733.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[61] PIN la_oen[62] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1751.290 19.280 1751.610 19.340 ; + RECT 1738.040 19.140 1751.610 19.280 ; + RECT 1448.610 18.940 1448.930 19.000 ; + RECT 1738.040 18.940 1738.180 19.140 ; + RECT 1751.290 19.080 1751.610 19.140 ; + RECT 1448.610 18.800 1738.180 18.940 ; + RECT 1448.610 18.740 1448.930 18.800 ; + LAYER via ; + RECT 1448.640 18.740 1448.900 19.000 ; + RECT 1751.320 19.080 1751.580 19.340 ; + LAYER met2 ; + RECT 1444.910 260.170 1445.190 264.000 ; + RECT 1444.910 260.030 1448.840 260.170 ; + RECT 1444.910 260.000 1445.190 260.030 ; + RECT 1448.700 19.030 1448.840 260.030 ; + RECT 1751.320 19.050 1751.580 19.370 ; + RECT 1448.640 18.710 1448.900 19.030 ; + RECT 1751.380 2.400 1751.520 19.050 ; + RECT 1751.170 -4.800 1751.730 2.400 ; +======= LAYER met2 ; RECT 1751.170 -4.800 1751.730 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[62] PIN la_oen[63] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1737.565 19.125 1737.735 20.655 ; + LAYER mcon ; + RECT 1737.565 20.485 1737.735 20.655 ; + LAYER met1 ; + RECT 1462.870 244.020 1463.190 244.080 ; + RECT 1469.310 244.020 1469.630 244.080 ; + RECT 1462.870 243.880 1469.630 244.020 ; + RECT 1462.870 243.820 1463.190 243.880 ; + RECT 1469.310 243.820 1469.630 243.880 ; + RECT 1737.505 20.640 1737.795 20.685 ; + RECT 1768.770 20.640 1769.090 20.700 ; + RECT 1737.505 20.500 1769.090 20.640 ; + RECT 1737.505 20.455 1737.795 20.500 ; + RECT 1768.770 20.440 1769.090 20.500 ; + RECT 1469.310 19.280 1469.630 19.340 ; + RECT 1737.505 19.280 1737.795 19.325 ; + RECT 1469.310 19.140 1737.795 19.280 ; + RECT 1469.310 19.080 1469.630 19.140 ; + RECT 1737.505 19.095 1737.795 19.140 ; + LAYER via ; + RECT 1462.900 243.820 1463.160 244.080 ; + RECT 1469.340 243.820 1469.600 244.080 ; + RECT 1768.800 20.440 1769.060 20.700 ; + RECT 1469.340 19.080 1469.600 19.340 ; + LAYER met2 ; + RECT 1462.850 260.000 1463.130 264.000 ; + RECT 1462.960 244.110 1463.100 260.000 ; + RECT 1462.900 243.790 1463.160 244.110 ; + RECT 1469.340 243.790 1469.600 244.110 ; + RECT 1469.400 19.370 1469.540 243.790 ; + RECT 1768.800 20.410 1769.060 20.730 ; + RECT 1469.340 19.050 1469.600 19.370 ; + RECT 1768.860 2.400 1769.000 20.410 ; + RECT 1768.650 -4.800 1769.210 2.400 ; +======= LAYER met2 ; RECT 1768.650 -4.800 1769.210 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[63] PIN la_oen[64] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1483.110 18.600 1483.430 18.660 ; + RECT 1786.710 18.600 1787.030 18.660 ; + RECT 1483.110 18.460 1787.030 18.600 ; + RECT 1483.110 18.400 1483.430 18.460 ; + RECT 1786.710 18.400 1787.030 18.460 ; + LAYER via ; + RECT 1483.140 18.400 1483.400 18.660 ; + RECT 1786.740 18.400 1787.000 18.660 ; + LAYER met2 ; + RECT 1480.330 260.170 1480.610 264.000 ; + RECT 1480.330 260.030 1483.340 260.170 ; + RECT 1480.330 260.000 1480.610 260.030 ; + RECT 1483.200 18.690 1483.340 260.030 ; + RECT 1483.140 18.370 1483.400 18.690 ; + RECT 1786.740 18.370 1787.000 18.690 ; + RECT 1786.800 2.400 1786.940 18.370 ; + RECT 1786.590 -4.800 1787.150 2.400 ; +======= LAYER met2 ; RECT 1786.590 -4.800 1787.150 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[64] PIN la_oen[65] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1498.290 244.020 1498.610 244.080 ; + RECT 1503.810 244.020 1504.130 244.080 ; + RECT 1498.290 243.880 1504.130 244.020 ; + RECT 1498.290 243.820 1498.610 243.880 ; + RECT 1503.810 243.820 1504.130 243.880 ; + RECT 1503.810 17.240 1504.130 17.300 ; + RECT 1804.650 17.240 1804.970 17.300 ; + RECT 1503.810 17.100 1804.970 17.240 ; + RECT 1503.810 17.040 1504.130 17.100 ; + RECT 1804.650 17.040 1804.970 17.100 ; + LAYER via ; + RECT 1498.320 243.820 1498.580 244.080 ; + RECT 1503.840 243.820 1504.100 244.080 ; + RECT 1503.840 17.040 1504.100 17.300 ; + RECT 1804.680 17.040 1804.940 17.300 ; + LAYER met2 ; + RECT 1498.270 260.000 1498.550 264.000 ; + RECT 1498.380 244.110 1498.520 260.000 ; + RECT 1498.320 243.790 1498.580 244.110 ; + RECT 1503.840 243.790 1504.100 244.110 ; + RECT 1503.900 17.330 1504.040 243.790 ; + RECT 1503.840 17.010 1504.100 17.330 ; + RECT 1804.680 17.010 1804.940 17.330 ; + RECT 1804.740 2.400 1804.880 17.010 ; + RECT 1804.530 -4.800 1805.090 2.400 ; +======= LAYER met2 ; RECT 1804.530 -4.800 1805.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[65] PIN la_oen[66] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1517.610 58.720 1517.930 58.780 ; + RECT 1821.670 58.720 1821.990 58.780 ; + RECT 1517.610 58.580 1821.990 58.720 ; + RECT 1517.610 58.520 1517.930 58.580 ; + RECT 1821.670 58.520 1821.990 58.580 ; + LAYER via ; + RECT 1517.640 58.520 1517.900 58.780 ; + RECT 1821.700 58.520 1821.960 58.780 ; + LAYER met2 ; + RECT 1516.210 260.170 1516.490 264.000 ; + RECT 1516.210 260.030 1517.840 260.170 ; + RECT 1516.210 260.000 1516.490 260.030 ; + RECT 1517.700 58.810 1517.840 260.030 ; + RECT 1517.640 58.490 1517.900 58.810 ; + RECT 1821.700 58.490 1821.960 58.810 ; + RECT 1821.760 16.730 1821.900 58.490 ; + RECT 1821.760 16.590 1822.820 16.730 ; + RECT 1822.680 2.400 1822.820 16.590 ; + RECT 1822.470 -4.800 1823.030 2.400 ; +======= LAYER met2 ; RECT 1822.470 -4.800 1823.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[66] PIN la_oen[67] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1534.170 244.020 1534.490 244.080 ; + RECT 1538.310 244.020 1538.630 244.080 ; + RECT 1534.170 243.880 1538.630 244.020 ; + RECT 1534.170 243.820 1534.490 243.880 ; + RECT 1538.310 243.820 1538.630 243.880 ; + RECT 1538.310 19.620 1538.630 19.680 ; + RECT 1840.070 19.620 1840.390 19.680 ; + RECT 1538.310 19.480 1840.390 19.620 ; + RECT 1538.310 19.420 1538.630 19.480 ; + RECT 1840.070 19.420 1840.390 19.480 ; + LAYER via ; + RECT 1534.200 243.820 1534.460 244.080 ; + RECT 1538.340 243.820 1538.600 244.080 ; + RECT 1538.340 19.420 1538.600 19.680 ; + RECT 1840.100 19.420 1840.360 19.680 ; + LAYER met2 ; + RECT 1534.150 260.000 1534.430 264.000 ; + RECT 1534.260 244.110 1534.400 260.000 ; + RECT 1534.200 243.790 1534.460 244.110 ; + RECT 1538.340 243.790 1538.600 244.110 ; + RECT 1538.400 19.710 1538.540 243.790 ; + RECT 1538.340 19.390 1538.600 19.710 ; + RECT 1840.100 19.390 1840.360 19.710 ; + RECT 1840.160 2.400 1840.300 19.390 ; + RECT 1839.950 -4.800 1840.510 2.400 ; +======= LAYER met2 ; RECT 1839.950 -4.800 1840.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[67] PIN la_oen[68] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 1631.305 17.765 1632.395 17.935 ; + LAYER mcon ; + RECT 1632.225 17.765 1632.395 17.935 ; + LAYER met1 ; + RECT 1552.110 17.920 1552.430 17.980 ; + RECT 1631.245 17.920 1631.535 17.965 ; + RECT 1552.110 17.780 1631.535 17.920 ; + RECT 1552.110 17.720 1552.430 17.780 ; + RECT 1631.245 17.735 1631.535 17.780 ; + RECT 1632.165 17.920 1632.455 17.965 ; + RECT 1858.010 17.920 1858.330 17.980 ; + RECT 1632.165 17.780 1858.330 17.920 ; + RECT 1632.165 17.735 1632.455 17.780 ; + RECT 1858.010 17.720 1858.330 17.780 ; + LAYER via ; + RECT 1552.140 17.720 1552.400 17.980 ; + RECT 1858.040 17.720 1858.300 17.980 ; + LAYER met2 ; + RECT 1552.090 260.000 1552.370 264.000 ; + RECT 1552.200 18.010 1552.340 260.000 ; + RECT 1552.140 17.690 1552.400 18.010 ; + RECT 1858.040 17.690 1858.300 18.010 ; + RECT 1858.100 2.400 1858.240 17.690 ; + RECT 1857.890 -4.800 1858.450 2.400 ; +======= LAYER met2 ; RECT 1857.890 -4.800 1858.450 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[68] PIN la_oen[69] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1572.810 19.960 1573.130 20.020 ; + RECT 1875.950 19.960 1876.270 20.020 ; + RECT 1572.810 19.820 1876.270 19.960 ; + RECT 1572.810 19.760 1573.130 19.820 ; + RECT 1875.950 19.760 1876.270 19.820 ; + LAYER via ; + RECT 1572.840 19.760 1573.100 20.020 ; + RECT 1875.980 19.760 1876.240 20.020 ; + LAYER met2 ; + RECT 1570.030 260.170 1570.310 264.000 ; + RECT 1570.030 260.030 1573.040 260.170 ; + RECT 1570.030 260.000 1570.310 260.030 ; + RECT 1572.900 20.050 1573.040 260.030 ; + RECT 1572.840 19.730 1573.100 20.050 ; + RECT 1875.980 19.730 1876.240 20.050 ; + RECT 1876.040 2.400 1876.180 19.730 ; + RECT 1875.830 -4.800 1876.390 2.400 ; +======= LAYER met2 ; RECT 1875.830 -4.800 1876.390 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[69] PIN la_oen[6] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 443.510 246.740 443.830 246.800 ; + RECT 753.090 246.740 753.410 246.800 ; + RECT 443.510 246.600 753.410 246.740 ; + RECT 443.510 246.540 443.830 246.600 ; + RECT 753.090 246.540 753.410 246.600 ; + LAYER via ; + RECT 443.540 246.540 443.800 246.800 ; + RECT 753.120 246.540 753.380 246.800 ; + LAYER met2 ; + RECT 443.490 260.000 443.770 264.000 ; + RECT 443.600 246.830 443.740 260.000 ; + RECT 443.540 246.510 443.800 246.830 ; + RECT 753.120 246.510 753.380 246.830 ; + RECT 753.180 17.410 753.320 246.510 ; + RECT 752.260 17.270 753.320 17.410 ; + RECT 752.260 2.400 752.400 17.270 ; + RECT 752.050 -4.800 752.610 2.400 ; +======= LAYER met2 ; RECT 752.050 -4.800 752.610 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[6] PIN la_oen[70] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1587.990 241.640 1588.310 241.700 ; + RECT 1593.510 241.640 1593.830 241.700 ; + RECT 1587.990 241.500 1593.830 241.640 ; + RECT 1587.990 241.440 1588.310 241.500 ; + RECT 1593.510 241.440 1593.830 241.500 ; + RECT 1593.510 16.560 1593.830 16.620 ; + RECT 1893.890 16.560 1894.210 16.620 ; + RECT 1593.510 16.420 1894.210 16.560 ; + RECT 1593.510 16.360 1593.830 16.420 ; + RECT 1893.890 16.360 1894.210 16.420 ; + LAYER via ; + RECT 1588.020 241.440 1588.280 241.700 ; + RECT 1593.540 241.440 1593.800 241.700 ; + RECT 1593.540 16.360 1593.800 16.620 ; + RECT 1893.920 16.360 1894.180 16.620 ; + LAYER met2 ; + RECT 1587.970 260.000 1588.250 264.000 ; + RECT 1588.080 241.730 1588.220 260.000 ; + RECT 1588.020 241.410 1588.280 241.730 ; + RECT 1593.540 241.410 1593.800 241.730 ; + RECT 1593.600 16.650 1593.740 241.410 ; + RECT 1593.540 16.330 1593.800 16.650 ; + RECT 1893.920 16.330 1894.180 16.650 ; + RECT 1893.980 2.400 1894.120 16.330 ; + RECT 1893.770 -4.800 1894.330 2.400 ; +======= LAYER met2 ; RECT 1893.770 -4.800 1894.330 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[70] PIN la_oen[71] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1911.370 18.260 1911.690 18.320 ; + RECT 1631.780 18.120 1911.690 18.260 ; + RECT 1607.310 17.580 1607.630 17.640 ; + RECT 1631.780 17.580 1631.920 18.120 ; + RECT 1911.370 18.060 1911.690 18.120 ; + RECT 1607.310 17.440 1631.920 17.580 ; + RECT 1607.310 17.380 1607.630 17.440 ; + LAYER via ; + RECT 1607.340 17.380 1607.600 17.640 ; + RECT 1911.400 18.060 1911.660 18.320 ; + LAYER met2 ; + RECT 1605.450 260.170 1605.730 264.000 ; + RECT 1605.450 260.030 1607.540 260.170 ; + RECT 1605.450 260.000 1605.730 260.030 ; + RECT 1607.400 17.670 1607.540 260.030 ; + RECT 1911.400 18.030 1911.660 18.350 ; + RECT 1607.340 17.350 1607.600 17.670 ; + RECT 1911.460 17.410 1911.600 18.030 ; + RECT 1911.460 17.270 1912.060 17.410 ; + RECT 1911.920 2.400 1912.060 17.270 ; + RECT 1911.710 -4.800 1912.270 2.400 ; +======= LAYER met2 ; RECT 1911.710 -4.800 1912.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[71] PIN la_oen[72] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1623.410 244.020 1623.730 244.080 ; + RECT 1628.010 244.020 1628.330 244.080 ; + RECT 1623.410 243.880 1628.330 244.020 ; + RECT 1623.410 243.820 1623.730 243.880 ; + RECT 1628.010 243.820 1628.330 243.880 ; + RECT 1628.010 16.220 1628.330 16.280 ; + RECT 1929.310 16.220 1929.630 16.280 ; + RECT 1628.010 16.080 1929.630 16.220 ; + RECT 1628.010 16.020 1628.330 16.080 ; + RECT 1929.310 16.020 1929.630 16.080 ; + LAYER via ; + RECT 1623.440 243.820 1623.700 244.080 ; + RECT 1628.040 243.820 1628.300 244.080 ; + RECT 1628.040 16.020 1628.300 16.280 ; + RECT 1929.340 16.020 1929.600 16.280 ; + LAYER met2 ; + RECT 1623.390 260.000 1623.670 264.000 ; + RECT 1623.500 244.110 1623.640 260.000 ; + RECT 1623.440 243.790 1623.700 244.110 ; + RECT 1628.040 243.790 1628.300 244.110 ; + RECT 1628.100 16.310 1628.240 243.790 ; + RECT 1628.040 15.990 1628.300 16.310 ; + RECT 1929.340 15.990 1929.600 16.310 ; + RECT 1929.400 2.400 1929.540 15.990 ; + RECT 1929.190 -4.800 1929.750 2.400 ; +======= LAYER met2 ; RECT 1929.190 -4.800 1929.750 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[72] PIN la_oen[73] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1641.810 17.580 1642.130 17.640 ; + RECT 1947.250 17.580 1947.570 17.640 ; + RECT 1641.810 17.440 1947.570 17.580 ; + RECT 1641.810 17.380 1642.130 17.440 ; + RECT 1947.250 17.380 1947.570 17.440 ; + LAYER via ; + RECT 1641.840 17.380 1642.100 17.640 ; + RECT 1947.280 17.380 1947.540 17.640 ; + LAYER met2 ; + RECT 1641.330 260.170 1641.610 264.000 ; + RECT 1641.330 260.030 1642.040 260.170 ; + RECT 1641.330 260.000 1641.610 260.030 ; + RECT 1641.900 17.670 1642.040 260.030 ; + RECT 1641.840 17.350 1642.100 17.670 ; + RECT 1947.280 17.350 1947.540 17.670 ; + RECT 1947.340 2.400 1947.480 17.350 ; + RECT 1947.130 -4.800 1947.690 2.400 ; +======= LAYER met2 ; RECT 1947.130 -4.800 1947.690 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[73] PIN la_oen[74] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1662.510 15.880 1662.830 15.940 ; + RECT 1965.190 15.880 1965.510 15.940 ; + RECT 1662.510 15.740 1965.510 15.880 ; + RECT 1662.510 15.680 1662.830 15.740 ; + RECT 1965.190 15.680 1965.510 15.740 ; + LAYER via ; + RECT 1662.540 15.680 1662.800 15.940 ; + RECT 1965.220 15.680 1965.480 15.940 ; + LAYER met2 ; + RECT 1659.270 260.170 1659.550 264.000 ; + RECT 1659.270 260.030 1662.740 260.170 ; + RECT 1659.270 260.000 1659.550 260.030 ; + RECT 1662.600 15.970 1662.740 260.030 ; + RECT 1662.540 15.650 1662.800 15.970 ; + RECT 1965.220 15.650 1965.480 15.970 ; + RECT 1965.280 2.400 1965.420 15.650 ; + RECT 1965.070 -4.800 1965.630 2.400 ; +======= LAYER met2 ; RECT 1965.070 -4.800 1965.630 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[74] PIN la_oen[75] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1677.230 244.020 1677.550 244.080 ; + RECT 1683.210 244.020 1683.530 244.080 ; + RECT 1677.230 243.880 1683.530 244.020 ; + RECT 1677.230 243.820 1677.550 243.880 ; + RECT 1683.210 243.820 1683.530 243.880 ; + RECT 1683.210 16.900 1683.530 16.960 ; + RECT 1983.130 16.900 1983.450 16.960 ; + RECT 1683.210 16.760 1983.450 16.900 ; + RECT 1683.210 16.700 1683.530 16.760 ; + RECT 1983.130 16.700 1983.450 16.760 ; + LAYER via ; + RECT 1677.260 243.820 1677.520 244.080 ; + RECT 1683.240 243.820 1683.500 244.080 ; + RECT 1683.240 16.700 1683.500 16.960 ; + RECT 1983.160 16.700 1983.420 16.960 ; + LAYER met2 ; + RECT 1677.210 260.000 1677.490 264.000 ; + RECT 1677.320 244.110 1677.460 260.000 ; + RECT 1677.260 243.790 1677.520 244.110 ; + RECT 1683.240 243.790 1683.500 244.110 ; + RECT 1683.300 16.990 1683.440 243.790 ; + RECT 1683.240 16.670 1683.500 16.990 ; + RECT 1983.160 16.670 1983.420 16.990 ; + RECT 1983.220 2.400 1983.360 16.670 ; + RECT 1983.010 -4.800 1983.570 2.400 ; +======= LAYER met2 ; RECT 1983.010 -4.800 1983.570 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[75] PIN la_oen[76] @@ -4028,31 +17466,122 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 1695.150 260.170 1695.430 264.000 ; + RECT 1695.150 260.030 1697.240 260.170 ; + RECT 1695.150 260.000 1695.430 260.030 ; + RECT 1697.100 16.845 1697.240 260.030 ; + RECT 1697.030 16.475 1697.310 16.845 ; + RECT 2001.090 16.475 2001.370 16.845 ; + RECT 2001.160 2.400 2001.300 16.475 ; + RECT 2000.950 -4.800 2001.510 2.400 ; + LAYER via2 ; + RECT 1697.030 16.520 1697.310 16.800 ; + RECT 2001.090 16.520 2001.370 16.800 ; + LAYER met3 ; + RECT 1697.005 16.810 1697.335 16.825 ; + RECT 2001.065 16.810 2001.395 16.825 ; + RECT 1697.005 16.510 2001.395 16.810 ; + RECT 1697.005 16.495 1697.335 16.510 ; + RECT 2001.065 16.495 2001.395 16.510 ; +======= RECT 2000.950 -4.800 2001.510 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[76] PIN la_oen[77] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1713.110 244.020 1713.430 244.080 ; + RECT 1717.710 244.020 1718.030 244.080 ; + RECT 1713.110 243.880 1718.030 244.020 ; + RECT 1713.110 243.820 1713.430 243.880 ; + RECT 1717.710 243.820 1718.030 243.880 ; + RECT 1717.710 15.540 1718.030 15.600 ; + RECT 2018.550 15.540 2018.870 15.600 ; + RECT 1717.710 15.400 2018.870 15.540 ; + RECT 1717.710 15.340 1718.030 15.400 ; + RECT 2018.550 15.340 2018.870 15.400 ; + LAYER via ; + RECT 1713.140 243.820 1713.400 244.080 ; + RECT 1717.740 243.820 1718.000 244.080 ; + RECT 1717.740 15.340 1718.000 15.600 ; + RECT 2018.580 15.340 2018.840 15.600 ; + LAYER met2 ; + RECT 1713.090 260.000 1713.370 264.000 ; + RECT 1713.200 244.110 1713.340 260.000 ; + RECT 1713.140 243.790 1713.400 244.110 ; + RECT 1717.740 243.790 1718.000 244.110 ; + RECT 1717.800 15.630 1717.940 243.790 ; + RECT 1717.740 15.310 1718.000 15.630 ; + RECT 2018.580 15.310 2018.840 15.630 ; + RECT 2018.640 2.400 2018.780 15.310 ; + RECT 2018.430 -4.800 2018.990 2.400 ; +======= LAYER met2 ; RECT 2018.430 -4.800 2018.990 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[77] PIN la_oen[78] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1730.590 245.380 1730.910 245.440 ; + RECT 2036.030 245.380 2036.350 245.440 ; + RECT 1730.590 245.240 2036.350 245.380 ; + RECT 1730.590 245.180 1730.910 245.240 ; + RECT 2036.030 245.180 2036.350 245.240 ; + LAYER via ; + RECT 1730.620 245.180 1730.880 245.440 ; + RECT 2036.060 245.180 2036.320 245.440 ; + LAYER met2 ; + RECT 1730.570 260.000 1730.850 264.000 ; + RECT 1730.680 245.470 1730.820 260.000 ; + RECT 1730.620 245.150 1730.880 245.470 ; + RECT 2036.060 245.150 2036.320 245.470 ; + RECT 2036.120 17.410 2036.260 245.150 ; + RECT 2036.120 17.270 2036.720 17.410 ; + RECT 2036.580 2.400 2036.720 17.270 ; + RECT 2036.370 -4.800 2036.930 2.400 ; +======= LAYER met2 ; RECT 2036.370 -4.800 2036.930 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[78] PIN la_oen[79] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1752.210 20.300 1752.530 20.360 ; + RECT 2054.430 20.300 2054.750 20.360 ; + RECT 1752.210 20.160 2054.750 20.300 ; + RECT 1752.210 20.100 1752.530 20.160 ; + RECT 2054.430 20.100 2054.750 20.160 ; + LAYER via ; + RECT 1752.240 20.100 1752.500 20.360 ; + RECT 2054.460 20.100 2054.720 20.360 ; + LAYER met2 ; + RECT 1748.510 260.170 1748.790 264.000 ; + RECT 1748.510 260.030 1752.440 260.170 ; + RECT 1748.510 260.000 1748.790 260.030 ; + RECT 1752.300 20.390 1752.440 260.030 ; + RECT 1752.240 20.070 1752.500 20.390 ; + RECT 2054.460 20.070 2054.720 20.390 ; + RECT 2054.520 2.400 2054.660 20.070 ; + RECT 2054.310 -4.800 2054.870 2.400 ; +======= LAYER met2 ; RECT 2054.310 -4.800 2054.870 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[79] PIN la_oen[7] @@ -4060,31 +17589,132 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 461.430 260.170 461.710 264.000 ; + RECT 461.430 260.030 462.140 260.170 ; + RECT 461.430 260.000 461.710 260.030 ; + RECT 462.000 16.845 462.140 260.030 ; + RECT 461.930 16.475 462.210 16.845 ; + RECT 769.670 16.475 769.950 16.845 ; + RECT 769.740 2.400 769.880 16.475 ; + RECT 769.530 -4.800 770.090 2.400 ; + LAYER via2 ; + RECT 461.930 16.520 462.210 16.800 ; + RECT 769.670 16.520 769.950 16.800 ; + LAYER met3 ; + RECT 461.905 16.810 462.235 16.825 ; + RECT 769.645 16.810 769.975 16.825 ; + RECT 461.905 16.510 769.975 16.810 ; + RECT 461.905 16.495 462.235 16.510 ; + RECT 769.645 16.495 769.975 16.510 ; +======= RECT 769.530 -4.800 770.090 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[7] PIN la_oen[80] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1766.470 244.020 1766.790 244.080 ; + RECT 1772.910 244.020 1773.230 244.080 ; + RECT 1766.470 243.880 1773.230 244.020 ; + RECT 1766.470 243.820 1766.790 243.880 ; + RECT 1772.910 243.820 1773.230 243.880 ; + RECT 1772.910 19.280 1773.230 19.340 ; + RECT 2072.370 19.280 2072.690 19.340 ; + RECT 1772.910 19.140 2072.690 19.280 ; + RECT 1772.910 19.080 1773.230 19.140 ; + RECT 2072.370 19.080 2072.690 19.140 ; + LAYER via ; + RECT 1766.500 243.820 1766.760 244.080 ; + RECT 1772.940 243.820 1773.200 244.080 ; + RECT 1772.940 19.080 1773.200 19.340 ; + RECT 2072.400 19.080 2072.660 19.340 ; + LAYER met2 ; + RECT 1766.450 260.000 1766.730 264.000 ; + RECT 1766.560 244.110 1766.700 260.000 ; + RECT 1766.500 243.790 1766.760 244.110 ; + RECT 1772.940 243.790 1773.200 244.110 ; + RECT 1773.000 19.370 1773.140 243.790 ; + RECT 1772.940 19.050 1773.200 19.370 ; + RECT 2072.400 19.050 2072.660 19.370 ; + RECT 2072.460 2.400 2072.600 19.050 ; + RECT 2072.250 -4.800 2072.810 2.400 ; +======= LAYER met2 ; RECT 2072.250 -4.800 2072.810 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[80] PIN la_oen[81] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1787.170 18.600 1787.490 18.660 ; + RECT 2089.850 18.600 2090.170 18.660 ; + RECT 1787.170 18.460 2090.170 18.600 ; + RECT 1787.170 18.400 1787.490 18.460 ; + RECT 2089.850 18.400 2090.170 18.460 ; + LAYER via ; + RECT 1787.200 18.400 1787.460 18.660 ; + RECT 2089.880 18.400 2090.140 18.660 ; + LAYER met2 ; + RECT 1784.390 260.170 1784.670 264.000 ; + RECT 1784.390 260.030 1786.940 260.170 ; + RECT 1784.390 260.000 1784.670 260.030 ; + RECT 1786.800 19.280 1786.940 260.030 ; + RECT 1786.800 19.140 1787.400 19.280 ; + RECT 1787.260 18.690 1787.400 19.140 ; + RECT 1787.200 18.370 1787.460 18.690 ; + RECT 2089.880 18.370 2090.140 18.690 ; + RECT 2089.940 2.400 2090.080 18.370 ; + RECT 2089.730 -4.800 2090.290 2.400 ; +======= LAYER met2 ; RECT 2089.730 -4.800 2090.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[81] PIN la_oen[82] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1802.350 244.020 1802.670 244.080 ; + RECT 1807.410 244.020 1807.730 244.080 ; + RECT 1802.350 243.880 1807.730 244.020 ; + RECT 1802.350 243.820 1802.670 243.880 ; + RECT 1807.410 243.820 1807.730 243.880 ; + RECT 1807.410 20.640 1807.730 20.700 ; + RECT 2107.790 20.640 2108.110 20.700 ; + RECT 1807.410 20.500 2108.110 20.640 ; + RECT 1807.410 20.440 1807.730 20.500 ; + RECT 2107.790 20.440 2108.110 20.500 ; + LAYER via ; + RECT 1802.380 243.820 1802.640 244.080 ; + RECT 1807.440 243.820 1807.700 244.080 ; + RECT 1807.440 20.440 1807.700 20.700 ; + RECT 2107.820 20.440 2108.080 20.700 ; + LAYER met2 ; + RECT 1802.330 260.000 1802.610 264.000 ; + RECT 1802.440 244.110 1802.580 260.000 ; + RECT 1802.380 243.790 1802.640 244.110 ; + RECT 1807.440 243.790 1807.700 244.110 ; + RECT 1807.500 20.730 1807.640 243.790 ; + RECT 1807.440 20.410 1807.700 20.730 ; + RECT 2107.820 20.410 2108.080 20.730 ; + RECT 2107.880 2.400 2108.020 20.410 ; + RECT 2107.670 -4.800 2108.230 2.400 ; +======= LAYER met2 ; RECT 2107.670 -4.800 2108.230 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[82] PIN la_oen[83] @@ -4092,103 +17722,488 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 1820.270 260.170 1820.550 264.000 ; + RECT 1820.270 260.030 1821.440 260.170 ; + RECT 1820.270 260.000 1820.550 260.030 ; + RECT 1821.300 17.525 1821.440 260.030 ; + RECT 1821.230 17.155 1821.510 17.525 ; + RECT 2125.750 17.155 2126.030 17.525 ; + RECT 2125.820 2.400 2125.960 17.155 ; + RECT 2125.610 -4.800 2126.170 2.400 ; + LAYER via2 ; + RECT 1821.230 17.200 1821.510 17.480 ; + RECT 2125.750 17.200 2126.030 17.480 ; + LAYER met3 ; + RECT 1821.205 17.490 1821.535 17.505 ; + RECT 2125.725 17.490 2126.055 17.505 ; + RECT 1821.205 17.190 2126.055 17.490 ; + RECT 1821.205 17.175 1821.535 17.190 ; + RECT 2125.725 17.175 2126.055 17.190 ; +======= RECT 2125.610 -4.800 2126.170 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[83] PIN la_oen[84] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 2139.605 241.485 2139.775 246.075 ; + RECT 2139.605 144.925 2139.775 193.035 ; + RECT 2139.605 48.365 2139.775 96.475 ; + LAYER mcon ; + RECT 2139.605 245.905 2139.775 246.075 ; + RECT 2139.605 192.865 2139.775 193.035 ; + RECT 2139.605 96.305 2139.775 96.475 ; + LAYER met1 ; + RECT 1838.230 246.060 1838.550 246.120 ; + RECT 2139.545 246.060 2139.835 246.105 ; + RECT 1838.230 245.920 2139.835 246.060 ; + RECT 1838.230 245.860 1838.550 245.920 ; + RECT 2139.545 245.875 2139.835 245.920 ; + RECT 2139.530 241.640 2139.850 241.700 ; + RECT 2139.335 241.500 2139.850 241.640 ; + RECT 2139.530 241.440 2139.850 241.500 ; + RECT 2139.530 193.020 2139.850 193.080 ; + RECT 2139.335 192.880 2139.850 193.020 ; + RECT 2139.530 192.820 2139.850 192.880 ; + RECT 2139.530 145.080 2139.850 145.140 ; + RECT 2139.335 144.940 2139.850 145.080 ; + RECT 2139.530 144.880 2139.850 144.940 ; + RECT 2139.530 96.460 2139.850 96.520 ; + RECT 2139.335 96.320 2139.850 96.460 ; + RECT 2139.530 96.260 2139.850 96.320 ; + RECT 2139.530 48.520 2139.850 48.580 ; + RECT 2139.335 48.380 2139.850 48.520 ; + RECT 2139.530 48.320 2139.850 48.380 ; + RECT 2139.530 14.180 2139.850 14.240 ; + RECT 2139.530 14.040 2143.900 14.180 ; + RECT 2139.530 13.980 2139.850 14.040 ; + RECT 2143.760 13.900 2143.900 14.040 ; + RECT 2143.670 13.640 2143.990 13.900 ; + LAYER via ; + RECT 1838.260 245.860 1838.520 246.120 ; + RECT 2139.560 241.440 2139.820 241.700 ; + RECT 2139.560 192.820 2139.820 193.080 ; + RECT 2139.560 144.880 2139.820 145.140 ; + RECT 2139.560 96.260 2139.820 96.520 ; + RECT 2139.560 48.320 2139.820 48.580 ; + RECT 2139.560 13.980 2139.820 14.240 ; + RECT 2143.700 13.640 2143.960 13.900 ; + LAYER met2 ; + RECT 1838.210 260.000 1838.490 264.000 ; + RECT 1838.320 246.150 1838.460 260.000 ; + RECT 1838.260 245.830 1838.520 246.150 ; + RECT 2139.560 241.410 2139.820 241.730 ; + RECT 2139.620 193.110 2139.760 241.410 ; + RECT 2139.560 192.790 2139.820 193.110 ; + RECT 2139.560 144.850 2139.820 145.170 ; + RECT 2139.620 96.550 2139.760 144.850 ; + RECT 2139.560 96.230 2139.820 96.550 ; + RECT 2139.560 48.290 2139.820 48.610 ; + RECT 2139.620 14.270 2139.760 48.290 ; + RECT 2139.560 13.950 2139.820 14.270 ; + RECT 2143.700 13.610 2143.960 13.930 ; + RECT 2143.760 2.400 2143.900 13.610 ; + RECT 2143.550 -4.800 2144.110 2.400 ; +======= LAYER met2 ; RECT 2143.550 -4.800 2144.110 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[84] PIN la_oen[85] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1855.710 17.240 1856.030 17.300 ; + RECT 2161.610 17.240 2161.930 17.300 ; + RECT 1855.710 17.100 2161.930 17.240 ; + RECT 1855.710 17.040 1856.030 17.100 ; + RECT 2161.610 17.040 2161.930 17.100 ; + LAYER via ; + RECT 1855.740 17.040 1856.000 17.300 ; + RECT 2161.640 17.040 2161.900 17.300 ; + LAYER met2 ; + RECT 1855.690 260.000 1855.970 264.000 ; + RECT 1855.800 17.330 1855.940 260.000 ; + RECT 1855.740 17.010 1856.000 17.330 ; + RECT 2161.640 17.010 2161.900 17.330 ; + RECT 2161.700 2.400 2161.840 17.010 ; + RECT 2161.490 -4.800 2162.050 2.400 ; +======= LAYER met2 ; RECT 2161.490 -4.800 2162.050 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[85] PIN la_oen[86] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 2174.105 241.485 2174.275 246.415 ; + RECT 2174.105 144.925 2174.275 193.035 ; + RECT 2174.105 48.705 2174.275 96.475 ; + RECT 2179.165 2.805 2179.335 48.195 ; + LAYER mcon ; + RECT 2174.105 246.245 2174.275 246.415 ; + RECT 2174.105 192.865 2174.275 193.035 ; + RECT 2174.105 96.305 2174.275 96.475 ; + RECT 2179.165 48.025 2179.335 48.195 ; + LAYER met1 ; + RECT 1873.650 246.400 1873.970 246.460 ; + RECT 2174.045 246.400 2174.335 246.445 ; + RECT 1873.650 246.260 2174.335 246.400 ; + RECT 1873.650 246.200 1873.970 246.260 ; + RECT 2174.045 246.215 2174.335 246.260 ; + RECT 2174.030 241.640 2174.350 241.700 ; + RECT 2173.835 241.500 2174.350 241.640 ; + RECT 2174.030 241.440 2174.350 241.500 ; + RECT 2174.030 193.020 2174.350 193.080 ; + RECT 2173.835 192.880 2174.350 193.020 ; + RECT 2174.030 192.820 2174.350 192.880 ; + RECT 2174.030 145.080 2174.350 145.140 ; + RECT 2173.835 144.940 2174.350 145.080 ; + RECT 2174.030 144.880 2174.350 144.940 ; + RECT 2174.030 96.460 2174.350 96.520 ; + RECT 2173.835 96.320 2174.350 96.460 ; + RECT 2174.030 96.260 2174.350 96.320 ; + RECT 2174.030 48.860 2174.350 48.920 ; + RECT 2173.835 48.720 2174.350 48.860 ; + RECT 2174.030 48.660 2174.350 48.720 ; + RECT 2174.030 48.180 2174.350 48.240 ; + RECT 2179.105 48.180 2179.395 48.225 ; + RECT 2174.030 48.040 2179.395 48.180 ; + RECT 2174.030 47.980 2174.350 48.040 ; + RECT 2179.105 47.995 2179.395 48.040 ; + RECT 2179.090 2.960 2179.410 3.020 ; + RECT 2178.895 2.820 2179.410 2.960 ; + RECT 2179.090 2.760 2179.410 2.820 ; + LAYER via ; + RECT 1873.680 246.200 1873.940 246.460 ; + RECT 2174.060 241.440 2174.320 241.700 ; + RECT 2174.060 192.820 2174.320 193.080 ; + RECT 2174.060 144.880 2174.320 145.140 ; + RECT 2174.060 96.260 2174.320 96.520 ; + RECT 2174.060 48.660 2174.320 48.920 ; + RECT 2174.060 47.980 2174.320 48.240 ; + RECT 2179.120 2.760 2179.380 3.020 ; + LAYER met2 ; + RECT 1873.630 260.000 1873.910 264.000 ; + RECT 1873.740 246.490 1873.880 260.000 ; + RECT 1873.680 246.170 1873.940 246.490 ; + RECT 2174.060 241.410 2174.320 241.730 ; + RECT 2174.120 193.110 2174.260 241.410 ; + RECT 2174.060 192.790 2174.320 193.110 ; + RECT 2174.060 144.850 2174.320 145.170 ; + RECT 2174.120 96.550 2174.260 144.850 ; + RECT 2174.060 96.230 2174.320 96.550 ; + RECT 2174.060 48.630 2174.320 48.950 ; + RECT 2174.120 48.270 2174.260 48.630 ; + RECT 2174.060 47.950 2174.320 48.270 ; + RECT 2179.120 2.730 2179.380 3.050 ; + RECT 2179.180 2.400 2179.320 2.730 ; + RECT 2178.970 -4.800 2179.530 2.400 ; +======= LAYER met2 ; RECT 2178.970 -4.800 2179.530 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[86] PIN la_oen[87] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1891.590 244.020 1891.910 244.080 ; + RECT 1897.110 244.020 1897.430 244.080 ; + RECT 1891.590 243.880 1897.430 244.020 ; + RECT 1891.590 243.820 1891.910 243.880 ; + RECT 1897.110 243.820 1897.430 243.880 ; + RECT 1897.110 18.940 1897.430 19.000 ; + RECT 2197.030 18.940 2197.350 19.000 ; + RECT 1897.110 18.800 2197.350 18.940 ; + RECT 1897.110 18.740 1897.430 18.800 ; + RECT 2197.030 18.740 2197.350 18.800 ; + LAYER via ; + RECT 1891.620 243.820 1891.880 244.080 ; + RECT 1897.140 243.820 1897.400 244.080 ; + RECT 1897.140 18.740 1897.400 19.000 ; + RECT 2197.060 18.740 2197.320 19.000 ; + LAYER met2 ; + RECT 1891.570 260.000 1891.850 264.000 ; + RECT 1891.680 244.110 1891.820 260.000 ; + RECT 1891.620 243.790 1891.880 244.110 ; + RECT 1897.140 243.790 1897.400 244.110 ; + RECT 1897.200 19.030 1897.340 243.790 ; + RECT 1897.140 18.710 1897.400 19.030 ; + RECT 2197.060 18.710 2197.320 19.030 ; + RECT 2197.120 2.400 2197.260 18.710 ; + RECT 2196.910 -4.800 2197.470 2.400 ; +======= LAYER met2 ; RECT 2196.910 -4.800 2197.470 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[87] PIN la_oen[88] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1909.530 245.040 1909.850 245.100 ; + RECT 2215.890 245.040 2216.210 245.100 ; + RECT 1909.530 244.900 2216.210 245.040 ; + RECT 1909.530 244.840 1909.850 244.900 ; + RECT 2215.890 244.840 2216.210 244.900 ; + LAYER via ; + RECT 1909.560 244.840 1909.820 245.100 ; + RECT 2215.920 244.840 2216.180 245.100 ; + LAYER met2 ; + RECT 1909.510 260.000 1909.790 264.000 ; + RECT 1909.620 245.130 1909.760 260.000 ; + RECT 1909.560 244.810 1909.820 245.130 ; + RECT 2215.920 244.810 2216.180 245.130 ; + RECT 2215.980 17.410 2216.120 244.810 ; + RECT 2215.060 17.270 2216.120 17.410 ; + RECT 2215.060 2.400 2215.200 17.270 ; + RECT 2214.850 -4.800 2215.410 2.400 ; +======= LAYER met2 ; RECT 2214.850 -4.800 2215.410 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[88] PIN la_oen[89] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1927.470 241.980 1927.790 242.040 ; + RECT 1931.610 241.980 1931.930 242.040 ; + RECT 1927.470 241.840 1931.930 241.980 ; + RECT 1927.470 241.780 1927.790 241.840 ; + RECT 1931.610 241.780 1931.930 241.840 ; + RECT 2232.910 18.940 2233.230 19.000 ; + RECT 2215.520 18.800 2233.230 18.940 ; + RECT 1931.610 18.260 1931.930 18.320 ; + RECT 2215.520 18.260 2215.660 18.800 ; + RECT 2232.910 18.740 2233.230 18.800 ; + RECT 1931.610 18.120 2215.660 18.260 ; + RECT 1931.610 18.060 1931.930 18.120 ; + LAYER via ; + RECT 1927.500 241.780 1927.760 242.040 ; + RECT 1931.640 241.780 1931.900 242.040 ; + RECT 1931.640 18.060 1931.900 18.320 ; + RECT 2232.940 18.740 2233.200 19.000 ; + LAYER met2 ; + RECT 1927.450 260.000 1927.730 264.000 ; + RECT 1927.560 242.070 1927.700 260.000 ; + RECT 1927.500 241.750 1927.760 242.070 ; + RECT 1931.640 241.750 1931.900 242.070 ; + RECT 1931.700 18.350 1931.840 241.750 ; + RECT 2232.940 18.710 2233.200 19.030 ; + RECT 1931.640 18.030 1931.900 18.350 ; + RECT 2233.000 2.400 2233.140 18.710 ; + RECT 2232.790 -4.800 2233.350 2.400 ; +======= LAYER met2 ; RECT 2232.790 -4.800 2233.350 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[89] PIN la_oen[8] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 479.390 245.040 479.710 245.100 ; + RECT 787.130 245.040 787.450 245.100 ; + RECT 479.390 244.900 787.450 245.040 ; + RECT 479.390 244.840 479.710 244.900 ; + RECT 787.130 244.840 787.450 244.900 ; + LAYER via ; + RECT 479.420 244.840 479.680 245.100 ; + RECT 787.160 244.840 787.420 245.100 ; + LAYER met2 ; + RECT 479.370 260.000 479.650 264.000 ; + RECT 479.480 245.130 479.620 260.000 ; + RECT 479.420 244.810 479.680 245.130 ; + RECT 787.160 244.810 787.420 245.130 ; + RECT 787.220 7.890 787.360 244.810 ; + RECT 787.220 7.750 787.820 7.890 ; + RECT 787.680 2.400 787.820 7.750 ; + RECT 787.470 -4.800 788.030 2.400 ; +======= LAYER met2 ; RECT 787.470 -4.800 788.030 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[8] PIN la_oen[90] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1945.410 245.720 1945.730 245.780 ; + RECT 2249.930 245.720 2250.250 245.780 ; + RECT 1945.410 245.580 2250.250 245.720 ; + RECT 1945.410 245.520 1945.730 245.580 ; + RECT 2249.930 245.520 2250.250 245.580 ; + LAYER via ; + RECT 1945.440 245.520 1945.700 245.780 ; + RECT 2249.960 245.520 2250.220 245.780 ; + LAYER met2 ; + RECT 1945.390 260.000 1945.670 264.000 ; + RECT 1945.500 245.810 1945.640 260.000 ; + RECT 1945.440 245.490 1945.700 245.810 ; + RECT 2249.960 245.490 2250.220 245.810 ; + RECT 2250.020 16.730 2250.160 245.490 ; + RECT 2250.020 16.590 2251.080 16.730 ; + RECT 2250.940 2.400 2251.080 16.590 ; + RECT 2250.730 -4.800 2251.290 2.400 ; +======= LAYER met2 ; RECT 2250.730 -4.800 2251.290 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[90] PIN la_oen[91] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1966.110 19.620 1966.430 19.680 ; + RECT 2268.330 19.620 2268.650 19.680 ; + RECT 1966.110 19.480 2268.650 19.620 ; + RECT 1966.110 19.420 1966.430 19.480 ; + RECT 2268.330 19.420 2268.650 19.480 ; + LAYER via ; + RECT 1966.140 19.420 1966.400 19.680 ; + RECT 2268.360 19.420 2268.620 19.680 ; + LAYER met2 ; + RECT 1963.330 260.170 1963.610 264.000 ; + RECT 1963.330 260.030 1966.340 260.170 ; + RECT 1963.330 260.000 1963.610 260.030 ; + RECT 1966.200 19.710 1966.340 260.030 ; + RECT 1966.140 19.390 1966.400 19.710 ; + RECT 2268.360 19.390 2268.620 19.710 ; + RECT 2268.420 2.400 2268.560 19.390 ; + RECT 2268.210 -4.800 2268.770 2.400 ; +======= LAYER met2 ; RECT 2268.210 -4.800 2268.770 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[91] PIN la_oen[92] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 1980.830 247.080 1981.150 247.140 ; + RECT 2284.430 247.080 2284.750 247.140 ; + RECT 1980.830 246.940 2284.750 247.080 ; + RECT 1980.830 246.880 1981.150 246.940 ; + RECT 2284.430 246.880 2284.750 246.940 ; + RECT 2284.430 2.960 2284.750 3.020 ; + RECT 2286.270 2.960 2286.590 3.020 ; + RECT 2284.430 2.820 2286.590 2.960 ; + RECT 2284.430 2.760 2284.750 2.820 ; + RECT 2286.270 2.760 2286.590 2.820 ; + LAYER via ; + RECT 1980.860 246.880 1981.120 247.140 ; + RECT 2284.460 246.880 2284.720 247.140 ; + RECT 2284.460 2.760 2284.720 3.020 ; + RECT 2286.300 2.760 2286.560 3.020 ; + LAYER met2 ; + RECT 1980.810 260.000 1981.090 264.000 ; + RECT 1980.920 247.170 1981.060 260.000 ; + RECT 1980.860 246.850 1981.120 247.170 ; + RECT 2284.460 246.850 2284.720 247.170 ; + RECT 2284.520 3.050 2284.660 246.850 ; + RECT 2284.460 2.730 2284.720 3.050 ; + RECT 2286.300 2.730 2286.560 3.050 ; + RECT 2286.360 2.400 2286.500 2.730 ; + RECT 2286.150 -4.800 2286.710 2.400 ; +======= LAYER met2 ; RECT 2286.150 -4.800 2286.710 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[92] PIN la_oen[93] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2000.610 19.960 2000.930 20.020 ; + RECT 2303.750 19.960 2304.070 20.020 ; + RECT 2000.610 19.820 2304.070 19.960 ; + RECT 2000.610 19.760 2000.930 19.820 ; + RECT 2303.750 19.760 2304.070 19.820 ; + LAYER via ; + RECT 2000.640 19.760 2000.900 20.020 ; + RECT 2303.780 19.760 2304.040 20.020 ; + LAYER met2 ; + RECT 1998.750 260.170 1999.030 264.000 ; + RECT 1998.750 260.030 2000.840 260.170 ; + RECT 1998.750 260.000 1999.030 260.030 ; + RECT 2000.700 20.050 2000.840 260.030 ; + RECT 2000.640 19.730 2000.900 20.050 ; + RECT 2303.780 19.730 2304.040 20.050 ; + RECT 2303.840 19.450 2303.980 19.730 ; + RECT 2303.840 19.310 2304.440 19.450 ; + RECT 2304.300 2.400 2304.440 19.310 ; + RECT 2304.090 -4.800 2304.650 2.400 ; +======= LAYER met2 ; RECT 2304.090 -4.800 2304.650 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[93] PIN la_oen[94] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2016.710 246.740 2017.030 246.800 ; + RECT 2318.930 246.740 2319.250 246.800 ; + RECT 2016.710 246.600 2319.250 246.740 ; + RECT 2016.710 246.540 2017.030 246.600 ; + RECT 2318.930 246.540 2319.250 246.600 ; + LAYER via ; + RECT 2016.740 246.540 2017.000 246.800 ; + RECT 2318.960 246.540 2319.220 246.800 ; + LAYER met2 ; + RECT 2016.690 260.000 2016.970 264.000 ; + RECT 2016.800 246.830 2016.940 260.000 ; + RECT 2016.740 246.510 2017.000 246.830 ; + RECT 2318.960 246.510 2319.220 246.830 ; + RECT 2319.020 16.730 2319.160 246.510 ; + RECT 2319.020 16.590 2322.380 16.730 ; + RECT 2322.240 2.400 2322.380 16.590 ; + RECT 2322.030 -4.800 2322.590 2.400 ; +======= LAYER met2 ; RECT 2322.030 -4.800 2322.590 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[94] PIN la_oen[95] @@ -4196,47 +18211,205 @@ USE SIGNAL ; PORT LAYER met2 ; +<<<<<<< HEAD + RECT 2034.630 260.170 2034.910 264.000 ; + RECT 2034.630 260.030 2035.340 260.170 ; + RECT 2034.630 260.000 2034.910 260.030 ; + RECT 2035.200 16.845 2035.340 260.030 ; + RECT 2035.130 16.475 2035.410 16.845 ; + RECT 2339.650 16.475 2339.930 16.845 ; + RECT 2339.720 2.400 2339.860 16.475 ; + RECT 2339.510 -4.800 2340.070 2.400 ; + LAYER via2 ; + RECT 2035.130 16.520 2035.410 16.800 ; + RECT 2339.650 16.520 2339.930 16.800 ; + LAYER met3 ; + RECT 2035.105 16.810 2035.435 16.825 ; + RECT 2339.625 16.810 2339.955 16.825 ; + RECT 2035.105 16.510 2339.955 16.810 ; + RECT 2035.105 16.495 2035.435 16.510 ; + RECT 2339.625 16.495 2339.955 16.510 ; +======= RECT 2339.510 -4.800 2340.070 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[95] PIN la_oen[96] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2055.810 20.300 2056.130 20.360 ; + RECT 2357.570 20.300 2357.890 20.360 ; + RECT 2055.810 20.160 2357.890 20.300 ; + RECT 2055.810 20.100 2056.130 20.160 ; + RECT 2357.570 20.100 2357.890 20.160 ; + LAYER via ; + RECT 2055.840 20.100 2056.100 20.360 ; + RECT 2357.600 20.100 2357.860 20.360 ; + LAYER met2 ; + RECT 2052.570 260.170 2052.850 264.000 ; + RECT 2052.570 260.030 2056.040 260.170 ; + RECT 2052.570 260.000 2052.850 260.030 ; + RECT 2055.900 20.390 2056.040 260.030 ; + RECT 2055.840 20.070 2056.100 20.390 ; + RECT 2357.600 20.070 2357.860 20.390 ; + RECT 2357.660 2.400 2357.800 20.070 ; + RECT 2357.450 -4.800 2358.010 2.400 ; +======= LAYER met2 ; RECT 2357.450 -4.800 2358.010 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[96] PIN la_oen[97] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2070.530 244.020 2070.850 244.080 ; + RECT 2076.510 244.020 2076.830 244.080 ; + RECT 2070.530 243.880 2076.830 244.020 ; + RECT 2070.530 243.820 2070.850 243.880 ; + RECT 2076.510 243.820 2076.830 243.880 ; + RECT 2076.510 19.280 2076.830 19.340 ; + RECT 2375.510 19.280 2375.830 19.340 ; + RECT 2076.510 19.140 2375.830 19.280 ; + RECT 2076.510 19.080 2076.830 19.140 ; + RECT 2375.510 19.080 2375.830 19.140 ; + LAYER via ; + RECT 2070.560 243.820 2070.820 244.080 ; + RECT 2076.540 243.820 2076.800 244.080 ; + RECT 2076.540 19.080 2076.800 19.340 ; + RECT 2375.540 19.080 2375.800 19.340 ; + LAYER met2 ; + RECT 2070.510 260.000 2070.790 264.000 ; + RECT 2070.620 244.110 2070.760 260.000 ; + RECT 2070.560 243.790 2070.820 244.110 ; + RECT 2076.540 243.790 2076.800 244.110 ; + RECT 2076.600 19.370 2076.740 243.790 ; + RECT 2076.540 19.050 2076.800 19.370 ; + RECT 2375.540 19.050 2375.800 19.370 ; + RECT 2375.600 2.400 2375.740 19.050 ; + RECT 2375.390 -4.800 2375.950 2.400 ; +======= LAYER met2 ; RECT 2375.390 -4.800 2375.950 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[97] PIN la_oen[98] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER li1 ; + RECT 2214.585 18.445 2216.135 18.615 ; + LAYER mcon ; + RECT 2215.965 18.445 2216.135 18.615 ; + LAYER met1 ; + RECT 2090.310 18.600 2090.630 18.660 ; + RECT 2214.525 18.600 2214.815 18.645 ; + RECT 2090.310 18.460 2214.815 18.600 ; + RECT 2090.310 18.400 2090.630 18.460 ; + RECT 2214.525 18.415 2214.815 18.460 ; + RECT 2215.905 18.600 2216.195 18.645 ; + RECT 2393.450 18.600 2393.770 18.660 ; + RECT 2215.905 18.460 2393.770 18.600 ; + RECT 2215.905 18.415 2216.195 18.460 ; + RECT 2393.450 18.400 2393.770 18.460 ; + LAYER via ; + RECT 2090.340 18.400 2090.600 18.660 ; + RECT 2393.480 18.400 2393.740 18.660 ; + LAYER met2 ; + RECT 2088.450 260.170 2088.730 264.000 ; + RECT 2088.450 260.030 2090.540 260.170 ; + RECT 2088.450 260.000 2088.730 260.030 ; + RECT 2090.400 18.690 2090.540 260.030 ; + RECT 2090.340 18.370 2090.600 18.690 ; + RECT 2393.480 18.370 2393.740 18.690 ; + RECT 2393.540 2.400 2393.680 18.370 ; + RECT 2393.330 -4.800 2393.890 2.400 ; +======= LAYER met2 ; RECT 2393.330 -4.800 2393.890 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[98] PIN la_oen[99] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2105.950 244.020 2106.270 244.080 ; + RECT 2111.010 244.020 2111.330 244.080 ; + RECT 2105.950 243.880 2111.330 244.020 ; + RECT 2105.950 243.820 2106.270 243.880 ; + RECT 2111.010 243.820 2111.330 243.880 ; + RECT 2111.010 17.920 2111.330 17.980 ; + RECT 2411.390 17.920 2411.710 17.980 ; + RECT 2111.010 17.780 2411.710 17.920 ; + RECT 2111.010 17.720 2111.330 17.780 ; + RECT 2411.390 17.720 2411.710 17.780 ; + LAYER via ; + RECT 2105.980 243.820 2106.240 244.080 ; + RECT 2111.040 243.820 2111.300 244.080 ; + RECT 2111.040 17.720 2111.300 17.980 ; + RECT 2411.420 17.720 2411.680 17.980 ; + LAYER met2 ; + RECT 2105.930 260.000 2106.210 264.000 ; + RECT 2106.040 244.110 2106.180 260.000 ; + RECT 2105.980 243.790 2106.240 244.110 ; + RECT 2111.040 243.790 2111.300 244.110 ; + RECT 2111.100 18.010 2111.240 243.790 ; + RECT 2111.040 17.690 2111.300 18.010 ; + RECT 2411.420 17.690 2411.680 18.010 ; + RECT 2411.480 2.400 2411.620 17.690 ; + RECT 2411.270 -4.800 2411.830 2.400 ; +======= LAYER met2 ; RECT 2411.270 -4.800 2411.830 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[99] PIN la_oen[9] DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 497.330 244.020 497.650 244.080 ; + RECT 503.310 244.020 503.630 244.080 ; + RECT 497.330 243.880 503.630 244.020 ; + RECT 497.330 243.820 497.650 243.880 ; + RECT 503.310 243.820 503.630 243.880 ; + RECT 503.310 15.880 503.630 15.940 ; + RECT 805.530 15.880 805.850 15.940 ; + RECT 503.310 15.740 805.850 15.880 ; + RECT 503.310 15.680 503.630 15.740 ; + RECT 805.530 15.680 805.850 15.740 ; + LAYER via ; + RECT 497.360 243.820 497.620 244.080 ; + RECT 503.340 243.820 503.600 244.080 ; + RECT 503.340 15.680 503.600 15.940 ; + RECT 805.560 15.680 805.820 15.940 ; + LAYER met2 ; + RECT 497.310 260.000 497.590 264.000 ; + RECT 497.420 244.110 497.560 260.000 ; + RECT 497.360 243.790 497.620 244.110 ; + RECT 503.340 243.790 503.600 244.110 ; + RECT 503.400 15.970 503.540 243.790 ; + RECT 503.340 15.650 503.600 15.970 ; + RECT 805.560 15.650 805.820 15.970 ; + RECT 805.620 2.400 805.760 15.650 ; + RECT 805.410 -4.800 805.970 2.400 ; +======= LAYER met2 ; RECT 805.410 -4.800 805.970 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END la_oen[9] PIN user_clock2 @@ -4251,16 +18424,58 @@ DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 2.830 17.240 3.150 17.300 ; + RECT 310.570 17.240 310.890 17.300 ; + RECT 2.830 17.100 310.890 17.240 ; + RECT 2.830 17.040 3.150 17.100 ; + RECT 310.570 17.040 310.890 17.100 ; + LAYER via ; + RECT 2.860 17.040 3.120 17.300 ; + RECT 310.600 17.040 310.860 17.300 ; + LAYER met2 ; + RECT 312.850 260.170 313.130 264.000 ; + RECT 310.660 260.030 313.130 260.170 ; + RECT 310.660 17.330 310.800 260.030 ; + RECT 312.850 260.000 313.130 260.030 ; + RECT 2.860 17.010 3.120 17.330 ; + RECT 310.600 17.010 310.860 17.330 ; + RECT 2.920 2.400 3.060 17.010 ; + RECT 2.710 -4.800 3.270 2.400 ; +======= LAYER met2 ; RECT 2.710 -4.800 3.270 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END wb_clk_i PIN wb_rst_i DIRECTION INPUT ; USE SIGNAL ; PORT +<<<<<<< HEAD + LAYER met1 ; + RECT 8.350 17.580 8.670 17.640 ; + RECT 317.470 17.580 317.790 17.640 ; + RECT 8.350 17.440 317.790 17.580 ; + RECT 8.350 17.380 8.670 17.440 ; + RECT 317.470 17.380 317.790 17.440 ; + LAYER via ; + RECT 8.380 17.380 8.640 17.640 ; + RECT 317.500 17.380 317.760 17.640 ; + LAYER met2 ; + RECT 318.370 260.170 318.650 264.000 ; + RECT 317.560 260.030 318.650 260.170 ; + RECT 317.560 17.670 317.700 260.030 ; + RECT 318.370 260.000 318.650 260.030 ; + RECT 8.380 17.350 8.640 17.670 ; + RECT 317.500 17.350 317.760 17.670 ; + RECT 8.440 2.400 8.580 17.350 ; + RECT 8.230 -4.800 8.790 2.400 ; +======= LAYER met2 ; RECT 8.230 -4.800 8.790 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END wb_rst_i PIN wbs_ack_o @@ -5100,7 +19315,71 @@ USE POWER ; PORT LAYER met4 ; + RECT -19.580 -14.220 -16.580 3533.900 ; RECT -9.980 -4.620 -6.980 3524.300 ; +<<<<<<< HEAD + RECT 4.020 -9.420 7.020 3529.100 ; + RECT 22.020 -19.020 25.020 3538.700 ; + RECT 184.020 -9.420 187.020 3529.100 ; + RECT 202.020 -19.020 205.020 3538.700 ; + RECT 364.020 3260.000 367.020 3529.100 ; + RECT 382.020 3260.000 385.020 3538.700 ; + RECT 544.020 3260.000 547.020 3529.100 ; + RECT 562.020 3260.000 565.020 3538.700 ; + RECT 724.020 3260.000 727.020 3529.100 ; + RECT 742.020 3260.000 745.020 3538.700 ; + RECT 904.020 3260.000 907.020 3529.100 ; + RECT 922.020 3260.000 925.020 3538.700 ; + RECT 1084.020 3260.000 1087.020 3529.100 ; + RECT 1102.020 3260.000 1105.020 3538.700 ; + RECT 1264.020 3260.000 1267.020 3529.100 ; + RECT 1282.020 3260.000 1285.020 3538.700 ; + RECT 1444.020 3260.000 1447.020 3529.100 ; + RECT 1462.020 3260.000 1465.020 3538.700 ; + RECT 1624.020 3260.000 1627.020 3529.100 ; + RECT 1642.020 3260.000 1645.020 3538.700 ; + RECT 1804.020 3260.000 1807.020 3529.100 ; + RECT 1822.020 3260.000 1825.020 3538.700 ; + RECT 1984.020 3260.000 1987.020 3529.100 ; + RECT 2002.020 3260.000 2005.020 3538.700 ; + RECT 2164.020 3260.000 2167.020 3529.100 ; + RECT 2182.020 3260.000 2185.020 3538.700 ; + RECT 2344.020 3260.000 2347.020 3529.100 ; + RECT 2362.020 3260.000 2365.020 3538.700 ; + RECT 2524.020 3260.000 2527.020 3529.100 ; + RECT 2542.020 3260.000 2545.020 3538.700 ; + RECT 331.040 270.640 332.640 3246.800 ; + RECT 364.020 -9.420 367.020 260.000 ; + RECT 382.020 -19.020 385.020 260.000 ; + RECT 544.020 -9.420 547.020 260.000 ; + RECT 562.020 -19.020 565.020 260.000 ; + RECT 724.020 -9.420 727.020 260.000 ; + RECT 742.020 -19.020 745.020 260.000 ; + RECT 904.020 -9.420 907.020 260.000 ; + RECT 922.020 -19.020 925.020 260.000 ; + RECT 1084.020 -9.420 1087.020 260.000 ; + RECT 1102.020 -19.020 1105.020 260.000 ; + RECT 1264.020 -9.420 1267.020 260.000 ; + RECT 1282.020 -19.020 1285.020 260.000 ; + RECT 1444.020 -9.420 1447.020 260.000 ; + RECT 1462.020 -19.020 1465.020 260.000 ; + RECT 1624.020 -9.420 1627.020 260.000 ; + RECT 1642.020 -19.020 1645.020 260.000 ; + RECT 1804.020 -9.420 1807.020 260.000 ; + RECT 1822.020 -19.020 1825.020 260.000 ; + RECT 1984.020 -9.420 1987.020 260.000 ; + RECT 2002.020 -19.020 2005.020 260.000 ; + RECT 2164.020 -9.420 2167.020 260.000 ; + RECT 2182.020 -19.020 2185.020 260.000 ; + RECT 2344.020 -9.420 2347.020 260.000 ; + RECT 2362.020 -19.020 2365.020 260.000 ; + RECT 2524.020 -9.420 2527.020 260.000 ; + RECT 2542.020 -19.020 2545.020 260.000 ; + RECT 2704.020 -9.420 2707.020 3529.100 ; + RECT 2722.020 -19.020 2725.020 3538.700 ; + RECT 2884.020 -9.420 2887.020 3529.100 ; + RECT 2902.020 -19.020 2905.020 3538.700 ; +======= RECT 4.020 3519.700 7.020 3529.000 ; RECT 184.020 3519.700 187.020 3529.000 ; RECT 364.020 3519.700 367.020 3529.000 ; @@ -5135,10 +19414,844 @@ RECT 2524.020 -9.320 2527.020 0.300 ; RECT 2704.020 -9.320 2707.020 0.300 ; RECT 2884.020 -9.320 2887.020 0.300 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d RECT 2926.600 -4.620 2929.600 3524.300 ; + RECT 2936.200 -14.220 2939.200 3533.900 ; LAYER via4 ; + RECT -18.670 3532.610 -17.490 3533.790 ; + RECT -18.670 3531.010 -17.490 3532.190 ; + RECT 22.930 3532.610 24.110 3533.790 ; + RECT 22.930 3531.010 24.110 3532.190 ; + RECT -18.670 3449.090 -17.490 3450.270 ; + RECT -18.670 3447.490 -17.490 3448.670 ; + RECT -18.670 3269.090 -17.490 3270.270 ; + RECT -18.670 3267.490 -17.490 3268.670 ; + RECT -18.670 3089.090 -17.490 3090.270 ; + RECT -18.670 3087.490 -17.490 3088.670 ; + RECT -18.670 2909.090 -17.490 2910.270 ; + RECT -18.670 2907.490 -17.490 2908.670 ; + RECT -18.670 2729.090 -17.490 2730.270 ; + RECT -18.670 2727.490 -17.490 2728.670 ; + RECT -18.670 2549.090 -17.490 2550.270 ; + RECT -18.670 2547.490 -17.490 2548.670 ; + RECT -18.670 2369.090 -17.490 2370.270 ; + RECT -18.670 2367.490 -17.490 2368.670 ; + RECT -18.670 2189.090 -17.490 2190.270 ; + RECT -18.670 2187.490 -17.490 2188.670 ; + RECT -18.670 2009.090 -17.490 2010.270 ; + RECT -18.670 2007.490 -17.490 2008.670 ; + RECT -18.670 1829.090 -17.490 1830.270 ; + RECT -18.670 1827.490 -17.490 1828.670 ; + RECT -18.670 1649.090 -17.490 1650.270 ; + RECT -18.670 1647.490 -17.490 1648.670 ; + RECT -18.670 1469.090 -17.490 1470.270 ; + RECT -18.670 1467.490 -17.490 1468.670 ; + RECT -18.670 1289.090 -17.490 1290.270 ; + RECT -18.670 1287.490 -17.490 1288.670 ; + RECT -18.670 1109.090 -17.490 1110.270 ; + RECT -18.670 1107.490 -17.490 1108.670 ; + RECT -18.670 929.090 -17.490 930.270 ; + RECT -18.670 927.490 -17.490 928.670 ; + RECT -18.670 749.090 -17.490 750.270 ; + RECT -18.670 747.490 -17.490 748.670 ; + RECT -18.670 569.090 -17.490 570.270 ; + RECT -18.670 567.490 -17.490 568.670 ; + RECT -18.670 389.090 -17.490 390.270 ; + RECT -18.670 387.490 -17.490 388.670 ; + RECT -18.670 209.090 -17.490 210.270 ; + RECT -18.670 207.490 -17.490 208.670 ; + RECT -18.670 29.090 -17.490 30.270 ; + RECT -18.670 27.490 -17.490 28.670 ; RECT -9.070 3523.010 -7.890 3524.190 ; RECT -9.070 3521.410 -7.890 3522.590 ; +<<<<<<< HEAD + RECT -9.070 3431.090 -7.890 3432.270 ; + RECT -9.070 3429.490 -7.890 3430.670 ; + RECT -9.070 3251.090 -7.890 3252.270 ; + RECT -9.070 3249.490 -7.890 3250.670 ; + RECT -9.070 3071.090 -7.890 3072.270 ; + RECT -9.070 3069.490 -7.890 3070.670 ; + RECT -9.070 2891.090 -7.890 2892.270 ; + RECT -9.070 2889.490 -7.890 2890.670 ; + RECT -9.070 2711.090 -7.890 2712.270 ; + RECT -9.070 2709.490 -7.890 2710.670 ; + RECT -9.070 2531.090 -7.890 2532.270 ; + RECT -9.070 2529.490 -7.890 2530.670 ; + RECT -9.070 2351.090 -7.890 2352.270 ; + RECT -9.070 2349.490 -7.890 2350.670 ; + RECT -9.070 2171.090 -7.890 2172.270 ; + RECT -9.070 2169.490 -7.890 2170.670 ; + RECT -9.070 1991.090 -7.890 1992.270 ; + RECT -9.070 1989.490 -7.890 1990.670 ; + RECT -9.070 1811.090 -7.890 1812.270 ; + RECT -9.070 1809.490 -7.890 1810.670 ; + RECT -9.070 1631.090 -7.890 1632.270 ; + RECT -9.070 1629.490 -7.890 1630.670 ; + RECT -9.070 1451.090 -7.890 1452.270 ; + RECT -9.070 1449.490 -7.890 1450.670 ; + RECT -9.070 1271.090 -7.890 1272.270 ; + RECT -9.070 1269.490 -7.890 1270.670 ; + RECT -9.070 1091.090 -7.890 1092.270 ; + RECT -9.070 1089.490 -7.890 1090.670 ; + RECT -9.070 911.090 -7.890 912.270 ; + RECT -9.070 909.490 -7.890 910.670 ; + RECT -9.070 731.090 -7.890 732.270 ; + RECT -9.070 729.490 -7.890 730.670 ; + RECT -9.070 551.090 -7.890 552.270 ; + RECT -9.070 549.490 -7.890 550.670 ; + RECT -9.070 371.090 -7.890 372.270 ; + RECT -9.070 369.490 -7.890 370.670 ; + RECT -9.070 191.090 -7.890 192.270 ; + RECT -9.070 189.490 -7.890 190.670 ; + RECT -9.070 11.090 -7.890 12.270 ; + RECT -9.070 9.490 -7.890 10.670 ; + RECT -9.070 -2.910 -7.890 -1.730 ; + RECT -9.070 -4.510 -7.890 -3.330 ; + RECT 4.930 3523.010 6.110 3524.190 ; + RECT 4.930 3521.410 6.110 3522.590 ; + RECT 4.930 3431.090 6.110 3432.270 ; + RECT 4.930 3429.490 6.110 3430.670 ; + RECT 4.930 3251.090 6.110 3252.270 ; + RECT 4.930 3249.490 6.110 3250.670 ; + RECT 4.930 3071.090 6.110 3072.270 ; + RECT 4.930 3069.490 6.110 3070.670 ; + RECT 4.930 2891.090 6.110 2892.270 ; + RECT 4.930 2889.490 6.110 2890.670 ; + RECT 4.930 2711.090 6.110 2712.270 ; + RECT 4.930 2709.490 6.110 2710.670 ; + RECT 4.930 2531.090 6.110 2532.270 ; + RECT 4.930 2529.490 6.110 2530.670 ; + RECT 4.930 2351.090 6.110 2352.270 ; + RECT 4.930 2349.490 6.110 2350.670 ; + RECT 4.930 2171.090 6.110 2172.270 ; + RECT 4.930 2169.490 6.110 2170.670 ; + RECT 4.930 1991.090 6.110 1992.270 ; + RECT 4.930 1989.490 6.110 1990.670 ; + RECT 4.930 1811.090 6.110 1812.270 ; + RECT 4.930 1809.490 6.110 1810.670 ; + RECT 4.930 1631.090 6.110 1632.270 ; + RECT 4.930 1629.490 6.110 1630.670 ; + RECT 4.930 1451.090 6.110 1452.270 ; + RECT 4.930 1449.490 6.110 1450.670 ; + RECT 4.930 1271.090 6.110 1272.270 ; + RECT 4.930 1269.490 6.110 1270.670 ; + RECT 4.930 1091.090 6.110 1092.270 ; + RECT 4.930 1089.490 6.110 1090.670 ; + RECT 4.930 911.090 6.110 912.270 ; + RECT 4.930 909.490 6.110 910.670 ; + RECT 4.930 731.090 6.110 732.270 ; + RECT 4.930 729.490 6.110 730.670 ; + RECT 4.930 551.090 6.110 552.270 ; + RECT 4.930 549.490 6.110 550.670 ; + RECT 4.930 371.090 6.110 372.270 ; + RECT 4.930 369.490 6.110 370.670 ; + RECT 4.930 191.090 6.110 192.270 ; + RECT 4.930 189.490 6.110 190.670 ; + RECT 4.930 11.090 6.110 12.270 ; + RECT 4.930 9.490 6.110 10.670 ; + RECT 4.930 -2.910 6.110 -1.730 ; + RECT 4.930 -4.510 6.110 -3.330 ; + RECT 202.930 3532.610 204.110 3533.790 ; + RECT 202.930 3531.010 204.110 3532.190 ; + RECT 22.930 3449.090 24.110 3450.270 ; + RECT 22.930 3447.490 24.110 3448.670 ; + RECT 22.930 3269.090 24.110 3270.270 ; + RECT 22.930 3267.490 24.110 3268.670 ; + RECT 22.930 3089.090 24.110 3090.270 ; + RECT 22.930 3087.490 24.110 3088.670 ; + RECT 22.930 2909.090 24.110 2910.270 ; + RECT 22.930 2907.490 24.110 2908.670 ; + RECT 22.930 2729.090 24.110 2730.270 ; + RECT 22.930 2727.490 24.110 2728.670 ; + RECT 22.930 2549.090 24.110 2550.270 ; + RECT 22.930 2547.490 24.110 2548.670 ; + RECT 22.930 2369.090 24.110 2370.270 ; + RECT 22.930 2367.490 24.110 2368.670 ; + RECT 22.930 2189.090 24.110 2190.270 ; + RECT 22.930 2187.490 24.110 2188.670 ; + RECT 22.930 2009.090 24.110 2010.270 ; + RECT 22.930 2007.490 24.110 2008.670 ; + RECT 22.930 1829.090 24.110 1830.270 ; + RECT 22.930 1827.490 24.110 1828.670 ; + RECT 22.930 1649.090 24.110 1650.270 ; + RECT 22.930 1647.490 24.110 1648.670 ; + RECT 22.930 1469.090 24.110 1470.270 ; + RECT 22.930 1467.490 24.110 1468.670 ; + RECT 22.930 1289.090 24.110 1290.270 ; + RECT 22.930 1287.490 24.110 1288.670 ; + RECT 22.930 1109.090 24.110 1110.270 ; + RECT 22.930 1107.490 24.110 1108.670 ; + RECT 22.930 929.090 24.110 930.270 ; + RECT 22.930 927.490 24.110 928.670 ; + RECT 22.930 749.090 24.110 750.270 ; + RECT 22.930 747.490 24.110 748.670 ; + RECT 22.930 569.090 24.110 570.270 ; + RECT 22.930 567.490 24.110 568.670 ; + RECT 22.930 389.090 24.110 390.270 ; + RECT 22.930 387.490 24.110 388.670 ; + RECT 22.930 209.090 24.110 210.270 ; + RECT 22.930 207.490 24.110 208.670 ; + RECT 22.930 29.090 24.110 30.270 ; + RECT 22.930 27.490 24.110 28.670 ; + RECT -18.670 -12.510 -17.490 -11.330 ; + RECT -18.670 -14.110 -17.490 -12.930 ; + RECT 184.930 3523.010 186.110 3524.190 ; + RECT 184.930 3521.410 186.110 3522.590 ; + RECT 184.930 3431.090 186.110 3432.270 ; + RECT 184.930 3429.490 186.110 3430.670 ; + RECT 184.930 3251.090 186.110 3252.270 ; + RECT 184.930 3249.490 186.110 3250.670 ; + RECT 184.930 3071.090 186.110 3072.270 ; + RECT 184.930 3069.490 186.110 3070.670 ; + RECT 184.930 2891.090 186.110 2892.270 ; + RECT 184.930 2889.490 186.110 2890.670 ; + RECT 184.930 2711.090 186.110 2712.270 ; + RECT 184.930 2709.490 186.110 2710.670 ; + RECT 184.930 2531.090 186.110 2532.270 ; + RECT 184.930 2529.490 186.110 2530.670 ; + RECT 184.930 2351.090 186.110 2352.270 ; + RECT 184.930 2349.490 186.110 2350.670 ; + RECT 184.930 2171.090 186.110 2172.270 ; + RECT 184.930 2169.490 186.110 2170.670 ; + RECT 184.930 1991.090 186.110 1992.270 ; + RECT 184.930 1989.490 186.110 1990.670 ; + RECT 184.930 1811.090 186.110 1812.270 ; + RECT 184.930 1809.490 186.110 1810.670 ; + RECT 184.930 1631.090 186.110 1632.270 ; + RECT 184.930 1629.490 186.110 1630.670 ; + RECT 184.930 1451.090 186.110 1452.270 ; + RECT 184.930 1449.490 186.110 1450.670 ; + RECT 184.930 1271.090 186.110 1272.270 ; + RECT 184.930 1269.490 186.110 1270.670 ; + RECT 184.930 1091.090 186.110 1092.270 ; + RECT 184.930 1089.490 186.110 1090.670 ; + RECT 184.930 911.090 186.110 912.270 ; + RECT 184.930 909.490 186.110 910.670 ; + RECT 184.930 731.090 186.110 732.270 ; + RECT 184.930 729.490 186.110 730.670 ; + RECT 184.930 551.090 186.110 552.270 ; + RECT 184.930 549.490 186.110 550.670 ; + RECT 184.930 371.090 186.110 372.270 ; + RECT 184.930 369.490 186.110 370.670 ; + RECT 184.930 191.090 186.110 192.270 ; + RECT 184.930 189.490 186.110 190.670 ; + RECT 184.930 11.090 186.110 12.270 ; + RECT 184.930 9.490 186.110 10.670 ; + RECT 184.930 -2.910 186.110 -1.730 ; + RECT 184.930 -4.510 186.110 -3.330 ; + RECT 382.930 3532.610 384.110 3533.790 ; + RECT 382.930 3531.010 384.110 3532.190 ; + RECT 202.930 3449.090 204.110 3450.270 ; + RECT 202.930 3447.490 204.110 3448.670 ; + RECT 202.930 3269.090 204.110 3270.270 ; + RECT 202.930 3267.490 204.110 3268.670 ; + RECT 364.930 3523.010 366.110 3524.190 ; + RECT 364.930 3521.410 366.110 3522.590 ; + RECT 364.930 3431.090 366.110 3432.270 ; + RECT 364.930 3429.490 366.110 3430.670 ; + RECT 562.930 3532.610 564.110 3533.790 ; + RECT 562.930 3531.010 564.110 3532.190 ; + RECT 382.930 3449.090 384.110 3450.270 ; + RECT 382.930 3447.490 384.110 3448.670 ; + RECT 382.930 3269.090 384.110 3270.270 ; + RECT 382.930 3267.490 384.110 3268.670 ; + RECT 544.930 3523.010 546.110 3524.190 ; + RECT 544.930 3521.410 546.110 3522.590 ; + RECT 544.930 3431.090 546.110 3432.270 ; + RECT 544.930 3429.490 546.110 3430.670 ; + RECT 742.930 3532.610 744.110 3533.790 ; + RECT 742.930 3531.010 744.110 3532.190 ; + RECT 562.930 3449.090 564.110 3450.270 ; + RECT 562.930 3447.490 564.110 3448.670 ; + RECT 562.930 3269.090 564.110 3270.270 ; + RECT 562.930 3267.490 564.110 3268.670 ; + RECT 724.930 3523.010 726.110 3524.190 ; + RECT 724.930 3521.410 726.110 3522.590 ; + RECT 724.930 3431.090 726.110 3432.270 ; + RECT 724.930 3429.490 726.110 3430.670 ; + RECT 922.930 3532.610 924.110 3533.790 ; + RECT 922.930 3531.010 924.110 3532.190 ; + RECT 742.930 3449.090 744.110 3450.270 ; + RECT 742.930 3447.490 744.110 3448.670 ; + RECT 742.930 3269.090 744.110 3270.270 ; + RECT 742.930 3267.490 744.110 3268.670 ; + RECT 904.930 3523.010 906.110 3524.190 ; + RECT 904.930 3521.410 906.110 3522.590 ; + RECT 904.930 3431.090 906.110 3432.270 ; + RECT 904.930 3429.490 906.110 3430.670 ; + RECT 1102.930 3532.610 1104.110 3533.790 ; + RECT 1102.930 3531.010 1104.110 3532.190 ; + RECT 922.930 3449.090 924.110 3450.270 ; + RECT 922.930 3447.490 924.110 3448.670 ; + RECT 922.930 3269.090 924.110 3270.270 ; + RECT 922.930 3267.490 924.110 3268.670 ; + RECT 1084.930 3523.010 1086.110 3524.190 ; + RECT 1084.930 3521.410 1086.110 3522.590 ; + RECT 1084.930 3431.090 1086.110 3432.270 ; + RECT 1084.930 3429.490 1086.110 3430.670 ; + RECT 1282.930 3532.610 1284.110 3533.790 ; + RECT 1282.930 3531.010 1284.110 3532.190 ; + RECT 1102.930 3449.090 1104.110 3450.270 ; + RECT 1102.930 3447.490 1104.110 3448.670 ; + RECT 1102.930 3269.090 1104.110 3270.270 ; + RECT 1102.930 3267.490 1104.110 3268.670 ; + RECT 1264.930 3523.010 1266.110 3524.190 ; + RECT 1264.930 3521.410 1266.110 3522.590 ; + RECT 1264.930 3431.090 1266.110 3432.270 ; + RECT 1264.930 3429.490 1266.110 3430.670 ; + RECT 1462.930 3532.610 1464.110 3533.790 ; + RECT 1462.930 3531.010 1464.110 3532.190 ; + RECT 1282.930 3449.090 1284.110 3450.270 ; + RECT 1282.930 3447.490 1284.110 3448.670 ; + RECT 1282.930 3269.090 1284.110 3270.270 ; + RECT 1282.930 3267.490 1284.110 3268.670 ; + RECT 1444.930 3523.010 1446.110 3524.190 ; + RECT 1444.930 3521.410 1446.110 3522.590 ; + RECT 1444.930 3431.090 1446.110 3432.270 ; + RECT 1444.930 3429.490 1446.110 3430.670 ; + RECT 1642.930 3532.610 1644.110 3533.790 ; + RECT 1642.930 3531.010 1644.110 3532.190 ; + RECT 1462.930 3449.090 1464.110 3450.270 ; + RECT 1462.930 3447.490 1464.110 3448.670 ; + RECT 1462.930 3269.090 1464.110 3270.270 ; + RECT 1462.930 3267.490 1464.110 3268.670 ; + RECT 1624.930 3523.010 1626.110 3524.190 ; + RECT 1624.930 3521.410 1626.110 3522.590 ; + RECT 1624.930 3431.090 1626.110 3432.270 ; + RECT 1624.930 3429.490 1626.110 3430.670 ; + RECT 1822.930 3532.610 1824.110 3533.790 ; + RECT 1822.930 3531.010 1824.110 3532.190 ; + RECT 1642.930 3449.090 1644.110 3450.270 ; + RECT 1642.930 3447.490 1644.110 3448.670 ; + RECT 1642.930 3269.090 1644.110 3270.270 ; + RECT 1642.930 3267.490 1644.110 3268.670 ; + RECT 1804.930 3523.010 1806.110 3524.190 ; + RECT 1804.930 3521.410 1806.110 3522.590 ; + RECT 1804.930 3431.090 1806.110 3432.270 ; + RECT 1804.930 3429.490 1806.110 3430.670 ; + RECT 2002.930 3532.610 2004.110 3533.790 ; + RECT 2002.930 3531.010 2004.110 3532.190 ; + RECT 1822.930 3449.090 1824.110 3450.270 ; + RECT 1822.930 3447.490 1824.110 3448.670 ; + RECT 1822.930 3269.090 1824.110 3270.270 ; + RECT 1822.930 3267.490 1824.110 3268.670 ; + RECT 1984.930 3523.010 1986.110 3524.190 ; + RECT 1984.930 3521.410 1986.110 3522.590 ; + RECT 1984.930 3431.090 1986.110 3432.270 ; + RECT 1984.930 3429.490 1986.110 3430.670 ; + RECT 2182.930 3532.610 2184.110 3533.790 ; + RECT 2182.930 3531.010 2184.110 3532.190 ; + RECT 2002.930 3449.090 2004.110 3450.270 ; + RECT 2002.930 3447.490 2004.110 3448.670 ; + RECT 2002.930 3269.090 2004.110 3270.270 ; + RECT 2002.930 3267.490 2004.110 3268.670 ; + RECT 2164.930 3523.010 2166.110 3524.190 ; + RECT 2164.930 3521.410 2166.110 3522.590 ; + RECT 2164.930 3431.090 2166.110 3432.270 ; + RECT 2164.930 3429.490 2166.110 3430.670 ; + RECT 2362.930 3532.610 2364.110 3533.790 ; + RECT 2362.930 3531.010 2364.110 3532.190 ; + RECT 2182.930 3449.090 2184.110 3450.270 ; + RECT 2182.930 3447.490 2184.110 3448.670 ; + RECT 2182.930 3269.090 2184.110 3270.270 ; + RECT 2182.930 3267.490 2184.110 3268.670 ; + RECT 2344.930 3523.010 2346.110 3524.190 ; + RECT 2344.930 3521.410 2346.110 3522.590 ; + RECT 2344.930 3431.090 2346.110 3432.270 ; + RECT 2344.930 3429.490 2346.110 3430.670 ; + RECT 2542.930 3532.610 2544.110 3533.790 ; + RECT 2542.930 3531.010 2544.110 3532.190 ; + RECT 2362.930 3449.090 2364.110 3450.270 ; + RECT 2362.930 3447.490 2364.110 3448.670 ; + RECT 2362.930 3269.090 2364.110 3270.270 ; + RECT 2362.930 3267.490 2364.110 3268.670 ; + RECT 2524.930 3523.010 2526.110 3524.190 ; + RECT 2524.930 3521.410 2526.110 3522.590 ; + RECT 2524.930 3431.090 2526.110 3432.270 ; + RECT 2524.930 3429.490 2526.110 3430.670 ; + RECT 2722.930 3532.610 2724.110 3533.790 ; + RECT 2722.930 3531.010 2724.110 3532.190 ; + RECT 2542.930 3449.090 2544.110 3450.270 ; + RECT 2542.930 3447.490 2544.110 3448.670 ; + RECT 2542.930 3269.090 2544.110 3270.270 ; + RECT 2542.930 3267.490 2544.110 3268.670 ; + RECT 2704.930 3523.010 2706.110 3524.190 ; + RECT 2704.930 3521.410 2706.110 3522.590 ; + RECT 2704.930 3431.090 2706.110 3432.270 ; + RECT 2704.930 3429.490 2706.110 3430.670 ; + RECT 2704.930 3251.090 2706.110 3252.270 ; + RECT 2704.930 3249.490 2706.110 3250.670 ; + RECT 202.930 3089.090 204.110 3090.270 ; + RECT 202.930 3087.490 204.110 3088.670 ; + RECT 202.930 2909.090 204.110 2910.270 ; + RECT 202.930 2907.490 204.110 2908.670 ; + RECT 202.930 2729.090 204.110 2730.270 ; + RECT 202.930 2727.490 204.110 2728.670 ; + RECT 202.930 2549.090 204.110 2550.270 ; + RECT 202.930 2547.490 204.110 2548.670 ; + RECT 202.930 2369.090 204.110 2370.270 ; + RECT 202.930 2367.490 204.110 2368.670 ; + RECT 202.930 2189.090 204.110 2190.270 ; + RECT 202.930 2187.490 204.110 2188.670 ; + RECT 202.930 2009.090 204.110 2010.270 ; + RECT 202.930 2007.490 204.110 2008.670 ; + RECT 202.930 1829.090 204.110 1830.270 ; + RECT 202.930 1827.490 204.110 1828.670 ; + RECT 202.930 1649.090 204.110 1650.270 ; + RECT 202.930 1647.490 204.110 1648.670 ; + RECT 202.930 1469.090 204.110 1470.270 ; + RECT 202.930 1467.490 204.110 1468.670 ; + RECT 202.930 1289.090 204.110 1290.270 ; + RECT 202.930 1287.490 204.110 1288.670 ; + RECT 202.930 1109.090 204.110 1110.270 ; + RECT 202.930 1107.490 204.110 1108.670 ; + RECT 202.930 929.090 204.110 930.270 ; + RECT 202.930 927.490 204.110 928.670 ; + RECT 202.930 749.090 204.110 750.270 ; + RECT 202.930 747.490 204.110 748.670 ; + RECT 202.930 569.090 204.110 570.270 ; + RECT 202.930 567.490 204.110 568.670 ; + RECT 202.930 389.090 204.110 390.270 ; + RECT 202.930 387.490 204.110 388.670 ; + RECT 331.250 3089.090 332.430 3090.270 ; + RECT 331.250 3087.490 332.430 3088.670 ; + RECT 331.250 3071.090 332.430 3072.270 ; + RECT 331.250 3069.490 332.430 3070.670 ; + RECT 331.250 2909.090 332.430 2910.270 ; + RECT 331.250 2907.490 332.430 2908.670 ; + RECT 331.250 2891.090 332.430 2892.270 ; + RECT 331.250 2889.490 332.430 2890.670 ; + RECT 331.250 2729.090 332.430 2730.270 ; + RECT 331.250 2727.490 332.430 2728.670 ; + RECT 331.250 2711.090 332.430 2712.270 ; + RECT 331.250 2709.490 332.430 2710.670 ; + RECT 331.250 2549.090 332.430 2550.270 ; + RECT 331.250 2547.490 332.430 2548.670 ; + RECT 331.250 2531.090 332.430 2532.270 ; + RECT 331.250 2529.490 332.430 2530.670 ; + RECT 331.250 2369.090 332.430 2370.270 ; + RECT 331.250 2367.490 332.430 2368.670 ; + RECT 331.250 2351.090 332.430 2352.270 ; + RECT 331.250 2349.490 332.430 2350.670 ; + RECT 331.250 2189.090 332.430 2190.270 ; + RECT 331.250 2187.490 332.430 2188.670 ; + RECT 331.250 2171.090 332.430 2172.270 ; + RECT 331.250 2169.490 332.430 2170.670 ; + RECT 331.250 2009.090 332.430 2010.270 ; + RECT 331.250 2007.490 332.430 2008.670 ; + RECT 331.250 1991.090 332.430 1992.270 ; + RECT 331.250 1989.490 332.430 1990.670 ; + RECT 331.250 1829.090 332.430 1830.270 ; + RECT 331.250 1827.490 332.430 1828.670 ; + RECT 331.250 1811.090 332.430 1812.270 ; + RECT 331.250 1809.490 332.430 1810.670 ; + RECT 331.250 1649.090 332.430 1650.270 ; + RECT 331.250 1647.490 332.430 1648.670 ; + RECT 331.250 1631.090 332.430 1632.270 ; + RECT 331.250 1629.490 332.430 1630.670 ; + RECT 331.250 1469.090 332.430 1470.270 ; + RECT 331.250 1467.490 332.430 1468.670 ; + RECT 331.250 1451.090 332.430 1452.270 ; + RECT 331.250 1449.490 332.430 1450.670 ; + RECT 331.250 1289.090 332.430 1290.270 ; + RECT 331.250 1287.490 332.430 1288.670 ; + RECT 331.250 1271.090 332.430 1272.270 ; + RECT 331.250 1269.490 332.430 1270.670 ; + RECT 331.250 1109.090 332.430 1110.270 ; + RECT 331.250 1107.490 332.430 1108.670 ; + RECT 331.250 1091.090 332.430 1092.270 ; + RECT 331.250 1089.490 332.430 1090.670 ; + RECT 331.250 929.090 332.430 930.270 ; + RECT 331.250 927.490 332.430 928.670 ; + RECT 331.250 911.090 332.430 912.270 ; + RECT 331.250 909.490 332.430 910.670 ; + RECT 331.250 749.090 332.430 750.270 ; + RECT 331.250 747.490 332.430 748.670 ; + RECT 331.250 731.090 332.430 732.270 ; + RECT 331.250 729.490 332.430 730.670 ; + RECT 331.250 569.090 332.430 570.270 ; + RECT 331.250 567.490 332.430 568.670 ; + RECT 331.250 551.090 332.430 552.270 ; + RECT 331.250 549.490 332.430 550.670 ; + RECT 331.250 389.090 332.430 390.270 ; + RECT 331.250 387.490 332.430 388.670 ; + RECT 331.250 371.090 332.430 372.270 ; + RECT 331.250 369.490 332.430 370.670 ; + RECT 2704.930 3071.090 2706.110 3072.270 ; + RECT 2704.930 3069.490 2706.110 3070.670 ; + RECT 2704.930 2891.090 2706.110 2892.270 ; + RECT 2704.930 2889.490 2706.110 2890.670 ; + RECT 2704.930 2711.090 2706.110 2712.270 ; + RECT 2704.930 2709.490 2706.110 2710.670 ; + RECT 2704.930 2531.090 2706.110 2532.270 ; + RECT 2704.930 2529.490 2706.110 2530.670 ; + RECT 2704.930 2351.090 2706.110 2352.270 ; + RECT 2704.930 2349.490 2706.110 2350.670 ; + RECT 2704.930 2171.090 2706.110 2172.270 ; + RECT 2704.930 2169.490 2706.110 2170.670 ; + RECT 2704.930 1991.090 2706.110 1992.270 ; + RECT 2704.930 1989.490 2706.110 1990.670 ; + RECT 2704.930 1811.090 2706.110 1812.270 ; + RECT 2704.930 1809.490 2706.110 1810.670 ; + RECT 2704.930 1631.090 2706.110 1632.270 ; + RECT 2704.930 1629.490 2706.110 1630.670 ; + RECT 2704.930 1451.090 2706.110 1452.270 ; + RECT 2704.930 1449.490 2706.110 1450.670 ; + RECT 2704.930 1271.090 2706.110 1272.270 ; + RECT 2704.930 1269.490 2706.110 1270.670 ; + RECT 2704.930 1091.090 2706.110 1092.270 ; + RECT 2704.930 1089.490 2706.110 1090.670 ; + RECT 2704.930 911.090 2706.110 912.270 ; + RECT 2704.930 909.490 2706.110 910.670 ; + RECT 2704.930 731.090 2706.110 732.270 ; + RECT 2704.930 729.490 2706.110 730.670 ; + RECT 2704.930 551.090 2706.110 552.270 ; + RECT 2704.930 549.490 2706.110 550.670 ; + RECT 2704.930 371.090 2706.110 372.270 ; + RECT 2704.930 369.490 2706.110 370.670 ; + RECT 202.930 209.090 204.110 210.270 ; + RECT 202.930 207.490 204.110 208.670 ; + RECT 202.930 29.090 204.110 30.270 ; + RECT 202.930 27.490 204.110 28.670 ; + RECT 22.930 -12.510 24.110 -11.330 ; + RECT 22.930 -14.110 24.110 -12.930 ; + RECT 364.930 191.090 366.110 192.270 ; + RECT 364.930 189.490 366.110 190.670 ; + RECT 364.930 11.090 366.110 12.270 ; + RECT 364.930 9.490 366.110 10.670 ; + RECT 364.930 -2.910 366.110 -1.730 ; + RECT 364.930 -4.510 366.110 -3.330 ; + RECT 382.930 209.090 384.110 210.270 ; + RECT 382.930 207.490 384.110 208.670 ; + RECT 382.930 29.090 384.110 30.270 ; + RECT 382.930 27.490 384.110 28.670 ; + RECT 202.930 -12.510 204.110 -11.330 ; + RECT 202.930 -14.110 204.110 -12.930 ; + RECT 544.930 191.090 546.110 192.270 ; + RECT 544.930 189.490 546.110 190.670 ; + RECT 544.930 11.090 546.110 12.270 ; + RECT 544.930 9.490 546.110 10.670 ; + RECT 544.930 -2.910 546.110 -1.730 ; + RECT 544.930 -4.510 546.110 -3.330 ; + RECT 562.930 209.090 564.110 210.270 ; + RECT 562.930 207.490 564.110 208.670 ; + RECT 562.930 29.090 564.110 30.270 ; + RECT 562.930 27.490 564.110 28.670 ; + RECT 382.930 -12.510 384.110 -11.330 ; + RECT 382.930 -14.110 384.110 -12.930 ; + RECT 724.930 191.090 726.110 192.270 ; + RECT 724.930 189.490 726.110 190.670 ; + RECT 724.930 11.090 726.110 12.270 ; + RECT 724.930 9.490 726.110 10.670 ; + RECT 724.930 -2.910 726.110 -1.730 ; + RECT 724.930 -4.510 726.110 -3.330 ; + RECT 742.930 209.090 744.110 210.270 ; + RECT 742.930 207.490 744.110 208.670 ; + RECT 742.930 29.090 744.110 30.270 ; + RECT 742.930 27.490 744.110 28.670 ; + RECT 562.930 -12.510 564.110 -11.330 ; + RECT 562.930 -14.110 564.110 -12.930 ; + RECT 904.930 191.090 906.110 192.270 ; + RECT 904.930 189.490 906.110 190.670 ; + RECT 904.930 11.090 906.110 12.270 ; + RECT 904.930 9.490 906.110 10.670 ; + RECT 904.930 -2.910 906.110 -1.730 ; + RECT 904.930 -4.510 906.110 -3.330 ; + RECT 922.930 209.090 924.110 210.270 ; + RECT 922.930 207.490 924.110 208.670 ; + RECT 922.930 29.090 924.110 30.270 ; + RECT 922.930 27.490 924.110 28.670 ; + RECT 742.930 -12.510 744.110 -11.330 ; + RECT 742.930 -14.110 744.110 -12.930 ; + RECT 1084.930 191.090 1086.110 192.270 ; + RECT 1084.930 189.490 1086.110 190.670 ; + RECT 1084.930 11.090 1086.110 12.270 ; + RECT 1084.930 9.490 1086.110 10.670 ; + RECT 1084.930 -2.910 1086.110 -1.730 ; + RECT 1084.930 -4.510 1086.110 -3.330 ; + RECT 1102.930 209.090 1104.110 210.270 ; + RECT 1102.930 207.490 1104.110 208.670 ; + RECT 1102.930 29.090 1104.110 30.270 ; + RECT 1102.930 27.490 1104.110 28.670 ; + RECT 922.930 -12.510 924.110 -11.330 ; + RECT 922.930 -14.110 924.110 -12.930 ; + RECT 1264.930 191.090 1266.110 192.270 ; + RECT 1264.930 189.490 1266.110 190.670 ; + RECT 1264.930 11.090 1266.110 12.270 ; + RECT 1264.930 9.490 1266.110 10.670 ; + RECT 1264.930 -2.910 1266.110 -1.730 ; + RECT 1264.930 -4.510 1266.110 -3.330 ; + RECT 1282.930 209.090 1284.110 210.270 ; + RECT 1282.930 207.490 1284.110 208.670 ; + RECT 1282.930 29.090 1284.110 30.270 ; + RECT 1282.930 27.490 1284.110 28.670 ; + RECT 1102.930 -12.510 1104.110 -11.330 ; + RECT 1102.930 -14.110 1104.110 -12.930 ; + RECT 1444.930 191.090 1446.110 192.270 ; + RECT 1444.930 189.490 1446.110 190.670 ; + RECT 1444.930 11.090 1446.110 12.270 ; + RECT 1444.930 9.490 1446.110 10.670 ; + RECT 1444.930 -2.910 1446.110 -1.730 ; + RECT 1444.930 -4.510 1446.110 -3.330 ; + RECT 1462.930 209.090 1464.110 210.270 ; + RECT 1462.930 207.490 1464.110 208.670 ; + RECT 1462.930 29.090 1464.110 30.270 ; + RECT 1462.930 27.490 1464.110 28.670 ; + RECT 1282.930 -12.510 1284.110 -11.330 ; + RECT 1282.930 -14.110 1284.110 -12.930 ; + RECT 1624.930 191.090 1626.110 192.270 ; + RECT 1624.930 189.490 1626.110 190.670 ; + RECT 1624.930 11.090 1626.110 12.270 ; + RECT 1624.930 9.490 1626.110 10.670 ; + RECT 1624.930 -2.910 1626.110 -1.730 ; + RECT 1624.930 -4.510 1626.110 -3.330 ; + RECT 1642.930 209.090 1644.110 210.270 ; + RECT 1642.930 207.490 1644.110 208.670 ; + RECT 1642.930 29.090 1644.110 30.270 ; + RECT 1642.930 27.490 1644.110 28.670 ; + RECT 1462.930 -12.510 1464.110 -11.330 ; + RECT 1462.930 -14.110 1464.110 -12.930 ; + RECT 1804.930 191.090 1806.110 192.270 ; + RECT 1804.930 189.490 1806.110 190.670 ; + RECT 1804.930 11.090 1806.110 12.270 ; + RECT 1804.930 9.490 1806.110 10.670 ; + RECT 1804.930 -2.910 1806.110 -1.730 ; + RECT 1804.930 -4.510 1806.110 -3.330 ; + RECT 1822.930 209.090 1824.110 210.270 ; + RECT 1822.930 207.490 1824.110 208.670 ; + RECT 1822.930 29.090 1824.110 30.270 ; + RECT 1822.930 27.490 1824.110 28.670 ; + RECT 1642.930 -12.510 1644.110 -11.330 ; + RECT 1642.930 -14.110 1644.110 -12.930 ; + RECT 1984.930 191.090 1986.110 192.270 ; + RECT 1984.930 189.490 1986.110 190.670 ; + RECT 1984.930 11.090 1986.110 12.270 ; + RECT 1984.930 9.490 1986.110 10.670 ; + RECT 1984.930 -2.910 1986.110 -1.730 ; + RECT 1984.930 -4.510 1986.110 -3.330 ; + RECT 2002.930 209.090 2004.110 210.270 ; + RECT 2002.930 207.490 2004.110 208.670 ; + RECT 2002.930 29.090 2004.110 30.270 ; + RECT 2002.930 27.490 2004.110 28.670 ; + RECT 1822.930 -12.510 1824.110 -11.330 ; + RECT 1822.930 -14.110 1824.110 -12.930 ; + RECT 2164.930 191.090 2166.110 192.270 ; + RECT 2164.930 189.490 2166.110 190.670 ; + RECT 2164.930 11.090 2166.110 12.270 ; + RECT 2164.930 9.490 2166.110 10.670 ; + RECT 2164.930 -2.910 2166.110 -1.730 ; + RECT 2164.930 -4.510 2166.110 -3.330 ; + RECT 2182.930 209.090 2184.110 210.270 ; + RECT 2182.930 207.490 2184.110 208.670 ; + RECT 2182.930 29.090 2184.110 30.270 ; + RECT 2182.930 27.490 2184.110 28.670 ; + RECT 2002.930 -12.510 2004.110 -11.330 ; + RECT 2002.930 -14.110 2004.110 -12.930 ; + RECT 2344.930 191.090 2346.110 192.270 ; + RECT 2344.930 189.490 2346.110 190.670 ; + RECT 2344.930 11.090 2346.110 12.270 ; + RECT 2344.930 9.490 2346.110 10.670 ; + RECT 2344.930 -2.910 2346.110 -1.730 ; + RECT 2344.930 -4.510 2346.110 -3.330 ; + RECT 2362.930 209.090 2364.110 210.270 ; + RECT 2362.930 207.490 2364.110 208.670 ; + RECT 2362.930 29.090 2364.110 30.270 ; + RECT 2362.930 27.490 2364.110 28.670 ; + RECT 2182.930 -12.510 2184.110 -11.330 ; + RECT 2182.930 -14.110 2184.110 -12.930 ; + RECT 2524.930 191.090 2526.110 192.270 ; + RECT 2524.930 189.490 2526.110 190.670 ; + RECT 2524.930 11.090 2526.110 12.270 ; + RECT 2524.930 9.490 2526.110 10.670 ; + RECT 2524.930 -2.910 2526.110 -1.730 ; + RECT 2524.930 -4.510 2526.110 -3.330 ; + RECT 2542.930 209.090 2544.110 210.270 ; + RECT 2542.930 207.490 2544.110 208.670 ; + RECT 2542.930 29.090 2544.110 30.270 ; + RECT 2542.930 27.490 2544.110 28.670 ; + RECT 2362.930 -12.510 2364.110 -11.330 ; + RECT 2362.930 -14.110 2364.110 -12.930 ; + RECT 2704.930 191.090 2706.110 192.270 ; + RECT 2704.930 189.490 2706.110 190.670 ; + RECT 2704.930 11.090 2706.110 12.270 ; + RECT 2704.930 9.490 2706.110 10.670 ; + RECT 2704.930 -2.910 2706.110 -1.730 ; + RECT 2704.930 -4.510 2706.110 -3.330 ; + RECT 2902.930 3532.610 2904.110 3533.790 ; + RECT 2902.930 3531.010 2904.110 3532.190 ; + RECT 2722.930 3449.090 2724.110 3450.270 ; + RECT 2722.930 3447.490 2724.110 3448.670 ; + RECT 2722.930 3269.090 2724.110 3270.270 ; + RECT 2722.930 3267.490 2724.110 3268.670 ; + RECT 2722.930 3089.090 2724.110 3090.270 ; + RECT 2722.930 3087.490 2724.110 3088.670 ; + RECT 2722.930 2909.090 2724.110 2910.270 ; + RECT 2722.930 2907.490 2724.110 2908.670 ; + RECT 2722.930 2729.090 2724.110 2730.270 ; + RECT 2722.930 2727.490 2724.110 2728.670 ; + RECT 2722.930 2549.090 2724.110 2550.270 ; + RECT 2722.930 2547.490 2724.110 2548.670 ; + RECT 2722.930 2369.090 2724.110 2370.270 ; + RECT 2722.930 2367.490 2724.110 2368.670 ; + RECT 2722.930 2189.090 2724.110 2190.270 ; + RECT 2722.930 2187.490 2724.110 2188.670 ; + RECT 2722.930 2009.090 2724.110 2010.270 ; + RECT 2722.930 2007.490 2724.110 2008.670 ; + RECT 2722.930 1829.090 2724.110 1830.270 ; + RECT 2722.930 1827.490 2724.110 1828.670 ; + RECT 2722.930 1649.090 2724.110 1650.270 ; + RECT 2722.930 1647.490 2724.110 1648.670 ; + RECT 2722.930 1469.090 2724.110 1470.270 ; + RECT 2722.930 1467.490 2724.110 1468.670 ; + RECT 2722.930 1289.090 2724.110 1290.270 ; + RECT 2722.930 1287.490 2724.110 1288.670 ; + RECT 2722.930 1109.090 2724.110 1110.270 ; + RECT 2722.930 1107.490 2724.110 1108.670 ; + RECT 2722.930 929.090 2724.110 930.270 ; + RECT 2722.930 927.490 2724.110 928.670 ; + RECT 2722.930 749.090 2724.110 750.270 ; + RECT 2722.930 747.490 2724.110 748.670 ; + RECT 2722.930 569.090 2724.110 570.270 ; + RECT 2722.930 567.490 2724.110 568.670 ; + RECT 2722.930 389.090 2724.110 390.270 ; + RECT 2722.930 387.490 2724.110 388.670 ; + RECT 2722.930 209.090 2724.110 210.270 ; + RECT 2722.930 207.490 2724.110 208.670 ; + RECT 2722.930 29.090 2724.110 30.270 ; + RECT 2722.930 27.490 2724.110 28.670 ; + RECT 2542.930 -12.510 2544.110 -11.330 ; + RECT 2542.930 -14.110 2544.110 -12.930 ; + RECT 2884.930 3523.010 2886.110 3524.190 ; + RECT 2884.930 3521.410 2886.110 3522.590 ; + RECT 2884.930 3431.090 2886.110 3432.270 ; + RECT 2884.930 3429.490 2886.110 3430.670 ; + RECT 2884.930 3251.090 2886.110 3252.270 ; + RECT 2884.930 3249.490 2886.110 3250.670 ; + RECT 2884.930 3071.090 2886.110 3072.270 ; + RECT 2884.930 3069.490 2886.110 3070.670 ; + RECT 2884.930 2891.090 2886.110 2892.270 ; + RECT 2884.930 2889.490 2886.110 2890.670 ; + RECT 2884.930 2711.090 2886.110 2712.270 ; + RECT 2884.930 2709.490 2886.110 2710.670 ; + RECT 2884.930 2531.090 2886.110 2532.270 ; + RECT 2884.930 2529.490 2886.110 2530.670 ; + RECT 2884.930 2351.090 2886.110 2352.270 ; + RECT 2884.930 2349.490 2886.110 2350.670 ; + RECT 2884.930 2171.090 2886.110 2172.270 ; + RECT 2884.930 2169.490 2886.110 2170.670 ; + RECT 2884.930 1991.090 2886.110 1992.270 ; + RECT 2884.930 1989.490 2886.110 1990.670 ; + RECT 2884.930 1811.090 2886.110 1812.270 ; + RECT 2884.930 1809.490 2886.110 1810.670 ; + RECT 2884.930 1631.090 2886.110 1632.270 ; + RECT 2884.930 1629.490 2886.110 1630.670 ; + RECT 2884.930 1451.090 2886.110 1452.270 ; + RECT 2884.930 1449.490 2886.110 1450.670 ; + RECT 2884.930 1271.090 2886.110 1272.270 ; + RECT 2884.930 1269.490 2886.110 1270.670 ; + RECT 2884.930 1091.090 2886.110 1092.270 ; + RECT 2884.930 1089.490 2886.110 1090.670 ; + RECT 2884.930 911.090 2886.110 912.270 ; + RECT 2884.930 909.490 2886.110 910.670 ; + RECT 2884.930 731.090 2886.110 732.270 ; + RECT 2884.930 729.490 2886.110 730.670 ; + RECT 2884.930 551.090 2886.110 552.270 ; + RECT 2884.930 549.490 2886.110 550.670 ; + RECT 2884.930 371.090 2886.110 372.270 ; + RECT 2884.930 369.490 2886.110 370.670 ; + RECT 2884.930 191.090 2886.110 192.270 ; + RECT 2884.930 189.490 2886.110 190.670 ; + RECT 2884.930 11.090 2886.110 12.270 ; + RECT 2884.930 9.490 2886.110 10.670 ; + RECT 2884.930 -2.910 2886.110 -1.730 ; + RECT 2884.930 -4.510 2886.110 -3.330 ; + RECT 2937.110 3532.610 2938.290 3533.790 ; + RECT 2937.110 3531.010 2938.290 3532.190 ; + RECT 2902.930 3449.090 2904.110 3450.270 ; + RECT 2902.930 3447.490 2904.110 3448.670 ; + RECT 2902.930 3269.090 2904.110 3270.270 ; + RECT 2902.930 3267.490 2904.110 3268.670 ; + RECT 2902.930 3089.090 2904.110 3090.270 ; + RECT 2902.930 3087.490 2904.110 3088.670 ; + RECT 2902.930 2909.090 2904.110 2910.270 ; + RECT 2902.930 2907.490 2904.110 2908.670 ; + RECT 2902.930 2729.090 2904.110 2730.270 ; + RECT 2902.930 2727.490 2904.110 2728.670 ; + RECT 2902.930 2549.090 2904.110 2550.270 ; + RECT 2902.930 2547.490 2904.110 2548.670 ; + RECT 2902.930 2369.090 2904.110 2370.270 ; + RECT 2902.930 2367.490 2904.110 2368.670 ; + RECT 2902.930 2189.090 2904.110 2190.270 ; + RECT 2902.930 2187.490 2904.110 2188.670 ; + RECT 2902.930 2009.090 2904.110 2010.270 ; + RECT 2902.930 2007.490 2904.110 2008.670 ; + RECT 2902.930 1829.090 2904.110 1830.270 ; + RECT 2902.930 1827.490 2904.110 1828.670 ; + RECT 2902.930 1649.090 2904.110 1650.270 ; + RECT 2902.930 1647.490 2904.110 1648.670 ; + RECT 2902.930 1469.090 2904.110 1470.270 ; + RECT 2902.930 1467.490 2904.110 1468.670 ; + RECT 2902.930 1289.090 2904.110 1290.270 ; + RECT 2902.930 1287.490 2904.110 1288.670 ; + RECT 2902.930 1109.090 2904.110 1110.270 ; + RECT 2902.930 1107.490 2904.110 1108.670 ; + RECT 2902.930 929.090 2904.110 930.270 ; + RECT 2902.930 927.490 2904.110 928.670 ; + RECT 2902.930 749.090 2904.110 750.270 ; + RECT 2902.930 747.490 2904.110 748.670 ; + RECT 2902.930 569.090 2904.110 570.270 ; + RECT 2902.930 567.490 2904.110 568.670 ; + RECT 2902.930 389.090 2904.110 390.270 ; + RECT 2902.930 387.490 2904.110 388.670 ; + RECT 2902.930 209.090 2904.110 210.270 ; + RECT 2902.930 207.490 2904.110 208.670 ; + RECT 2902.930 29.090 2904.110 30.270 ; + RECT 2902.930 27.490 2904.110 28.670 ; + RECT 2722.930 -12.510 2724.110 -11.330 ; + RECT 2722.930 -14.110 2724.110 -12.930 ; + RECT 2927.510 3523.010 2928.690 3524.190 ; + RECT 2927.510 3521.410 2928.690 3522.590 ; + RECT 2927.510 3431.090 2928.690 3432.270 ; + RECT 2927.510 3429.490 2928.690 3430.670 ; + RECT 2927.510 3251.090 2928.690 3252.270 ; + RECT 2927.510 3249.490 2928.690 3250.670 ; + RECT 2927.510 3071.090 2928.690 3072.270 ; + RECT 2927.510 3069.490 2928.690 3070.670 ; + RECT 2927.510 2891.090 2928.690 2892.270 ; + RECT 2927.510 2889.490 2928.690 2890.670 ; + RECT 2927.510 2711.090 2928.690 2712.270 ; + RECT 2927.510 2709.490 2928.690 2710.670 ; + RECT 2927.510 2531.090 2928.690 2532.270 ; + RECT 2927.510 2529.490 2928.690 2530.670 ; + RECT 2927.510 2351.090 2928.690 2352.270 ; + RECT 2927.510 2349.490 2928.690 2350.670 ; + RECT 2927.510 2171.090 2928.690 2172.270 ; + RECT 2927.510 2169.490 2928.690 2170.670 ; + RECT 2927.510 1991.090 2928.690 1992.270 ; + RECT 2927.510 1989.490 2928.690 1990.670 ; + RECT 2927.510 1811.090 2928.690 1812.270 ; + RECT 2927.510 1809.490 2928.690 1810.670 ; + RECT 2927.510 1631.090 2928.690 1632.270 ; + RECT 2927.510 1629.490 2928.690 1630.670 ; + RECT 2927.510 1451.090 2928.690 1452.270 ; + RECT 2927.510 1449.490 2928.690 1450.670 ; + RECT 2927.510 1271.090 2928.690 1272.270 ; + RECT 2927.510 1269.490 2928.690 1270.670 ; + RECT 2927.510 1091.090 2928.690 1092.270 ; + RECT 2927.510 1089.490 2928.690 1090.670 ; + RECT 2927.510 911.090 2928.690 912.270 ; + RECT 2927.510 909.490 2928.690 910.670 ; + RECT 2927.510 731.090 2928.690 732.270 ; + RECT 2927.510 729.490 2928.690 730.670 ; + RECT 2927.510 551.090 2928.690 552.270 ; + RECT 2927.510 549.490 2928.690 550.670 ; + RECT 2927.510 371.090 2928.690 372.270 ; + RECT 2927.510 369.490 2928.690 370.670 ; + RECT 2927.510 191.090 2928.690 192.270 ; + RECT 2927.510 189.490 2928.690 190.670 ; + RECT 2927.510 11.090 2928.690 12.270 ; + RECT 2927.510 9.490 2928.690 10.670 ; +======= RECT 4.930 3523.010 6.110 3524.190 ; RECT 4.930 3521.410 6.110 3522.590 ; RECT 184.930 3523.010 186.110 3524.190 ; @@ -5291,9 +20404,93 @@ RECT 2704.930 -4.510 2706.110 -3.330 ; RECT 2884.930 -2.910 2886.110 -1.730 ; RECT 2884.930 -4.510 2886.110 -3.330 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d RECT 2927.510 -2.910 2928.690 -1.730 ; RECT 2927.510 -4.510 2928.690 -3.330 ; + RECT 2937.110 3449.090 2938.290 3450.270 ; + RECT 2937.110 3447.490 2938.290 3448.670 ; + RECT 2937.110 3269.090 2938.290 3270.270 ; + RECT 2937.110 3267.490 2938.290 3268.670 ; + RECT 2937.110 3089.090 2938.290 3090.270 ; + RECT 2937.110 3087.490 2938.290 3088.670 ; + RECT 2937.110 2909.090 2938.290 2910.270 ; + RECT 2937.110 2907.490 2938.290 2908.670 ; + RECT 2937.110 2729.090 2938.290 2730.270 ; + RECT 2937.110 2727.490 2938.290 2728.670 ; + RECT 2937.110 2549.090 2938.290 2550.270 ; + RECT 2937.110 2547.490 2938.290 2548.670 ; + RECT 2937.110 2369.090 2938.290 2370.270 ; + RECT 2937.110 2367.490 2938.290 2368.670 ; + RECT 2937.110 2189.090 2938.290 2190.270 ; + RECT 2937.110 2187.490 2938.290 2188.670 ; + RECT 2937.110 2009.090 2938.290 2010.270 ; + RECT 2937.110 2007.490 2938.290 2008.670 ; + RECT 2937.110 1829.090 2938.290 1830.270 ; + RECT 2937.110 1827.490 2938.290 1828.670 ; + RECT 2937.110 1649.090 2938.290 1650.270 ; + RECT 2937.110 1647.490 2938.290 1648.670 ; + RECT 2937.110 1469.090 2938.290 1470.270 ; + RECT 2937.110 1467.490 2938.290 1468.670 ; + RECT 2937.110 1289.090 2938.290 1290.270 ; + RECT 2937.110 1287.490 2938.290 1288.670 ; + RECT 2937.110 1109.090 2938.290 1110.270 ; + RECT 2937.110 1107.490 2938.290 1108.670 ; + RECT 2937.110 929.090 2938.290 930.270 ; + RECT 2937.110 927.490 2938.290 928.670 ; + RECT 2937.110 749.090 2938.290 750.270 ; + RECT 2937.110 747.490 2938.290 748.670 ; + RECT 2937.110 569.090 2938.290 570.270 ; + RECT 2937.110 567.490 2938.290 568.670 ; + RECT 2937.110 389.090 2938.290 390.270 ; + RECT 2937.110 387.490 2938.290 388.670 ; + RECT 2937.110 209.090 2938.290 210.270 ; + RECT 2937.110 207.490 2938.290 208.670 ; + RECT 2937.110 29.090 2938.290 30.270 ; + RECT 2937.110 27.490 2938.290 28.670 ; + RECT 2902.930 -12.510 2904.110 -11.330 ; + RECT 2902.930 -14.110 2904.110 -12.930 ; + RECT 2937.110 -12.510 2938.290 -11.330 ; + RECT 2937.110 -14.110 2938.290 -12.930 ; LAYER met5 ; + RECT -19.580 3533.900 -16.580 3533.910 ; + RECT 22.020 3533.900 25.020 3533.910 ; + RECT 202.020 3533.900 205.020 3533.910 ; + RECT 382.020 3533.900 385.020 3533.910 ; + RECT 562.020 3533.900 565.020 3533.910 ; + RECT 742.020 3533.900 745.020 3533.910 ; + RECT 922.020 3533.900 925.020 3533.910 ; + RECT 1102.020 3533.900 1105.020 3533.910 ; + RECT 1282.020 3533.900 1285.020 3533.910 ; + RECT 1462.020 3533.900 1465.020 3533.910 ; + RECT 1642.020 3533.900 1645.020 3533.910 ; + RECT 1822.020 3533.900 1825.020 3533.910 ; + RECT 2002.020 3533.900 2005.020 3533.910 ; + RECT 2182.020 3533.900 2185.020 3533.910 ; + RECT 2362.020 3533.900 2365.020 3533.910 ; + RECT 2542.020 3533.900 2545.020 3533.910 ; + RECT 2722.020 3533.900 2725.020 3533.910 ; + RECT 2902.020 3533.900 2905.020 3533.910 ; + RECT 2936.200 3533.900 2939.200 3533.910 ; + RECT -19.580 3530.900 2939.200 3533.900 ; + RECT -19.580 3530.890 -16.580 3530.900 ; + RECT 22.020 3530.890 25.020 3530.900 ; + RECT 202.020 3530.890 205.020 3530.900 ; + RECT 382.020 3530.890 385.020 3530.900 ; + RECT 562.020 3530.890 565.020 3530.900 ; + RECT 742.020 3530.890 745.020 3530.900 ; + RECT 922.020 3530.890 925.020 3530.900 ; + RECT 1102.020 3530.890 1105.020 3530.900 ; + RECT 1282.020 3530.890 1285.020 3530.900 ; + RECT 1462.020 3530.890 1465.020 3530.900 ; + RECT 1642.020 3530.890 1645.020 3530.900 ; + RECT 1822.020 3530.890 1825.020 3530.900 ; + RECT 2002.020 3530.890 2005.020 3530.900 ; + RECT 2182.020 3530.890 2185.020 3530.900 ; + RECT 2362.020 3530.890 2365.020 3530.900 ; + RECT 2542.020 3530.890 2545.020 3530.900 ; + RECT 2722.020 3530.890 2725.020 3530.900 ; + RECT 2902.020 3530.890 2905.020 3530.900 ; + RECT 2936.200 3530.890 2939.200 3530.900 ; RECT -9.980 3524.300 -6.980 3524.310 ; RECT 4.020 3524.300 7.020 3524.310 ; RECT 184.020 3524.300 187.020 3524.310 ; @@ -5333,6 +20530,774 @@ RECT 2704.020 3521.290 2707.020 3521.300 ; RECT 2884.020 3521.290 2887.020 3521.300 ; RECT 2926.600 3521.290 2929.600 3521.300 ; +<<<<<<< HEAD + RECT -19.580 3450.380 -16.580 3450.390 ; + RECT 22.020 3450.380 25.020 3450.390 ; + RECT 202.020 3450.380 205.020 3450.390 ; + RECT 382.020 3450.380 385.020 3450.390 ; + RECT 562.020 3450.380 565.020 3450.390 ; + RECT 742.020 3450.380 745.020 3450.390 ; + RECT 922.020 3450.380 925.020 3450.390 ; + RECT 1102.020 3450.380 1105.020 3450.390 ; + RECT 1282.020 3450.380 1285.020 3450.390 ; + RECT 1462.020 3450.380 1465.020 3450.390 ; + RECT 1642.020 3450.380 1645.020 3450.390 ; + RECT 1822.020 3450.380 1825.020 3450.390 ; + RECT 2002.020 3450.380 2005.020 3450.390 ; + RECT 2182.020 3450.380 2185.020 3450.390 ; + RECT 2362.020 3450.380 2365.020 3450.390 ; + RECT 2542.020 3450.380 2545.020 3450.390 ; + RECT 2722.020 3450.380 2725.020 3450.390 ; + RECT 2902.020 3450.380 2905.020 3450.390 ; + RECT 2936.200 3450.380 2939.200 3450.390 ; + RECT -24.380 3447.380 2944.000 3450.380 ; + RECT -19.580 3447.370 -16.580 3447.380 ; + RECT 22.020 3447.370 25.020 3447.380 ; + RECT 202.020 3447.370 205.020 3447.380 ; + RECT 382.020 3447.370 385.020 3447.380 ; + RECT 562.020 3447.370 565.020 3447.380 ; + RECT 742.020 3447.370 745.020 3447.380 ; + RECT 922.020 3447.370 925.020 3447.380 ; + RECT 1102.020 3447.370 1105.020 3447.380 ; + RECT 1282.020 3447.370 1285.020 3447.380 ; + RECT 1462.020 3447.370 1465.020 3447.380 ; + RECT 1642.020 3447.370 1645.020 3447.380 ; + RECT 1822.020 3447.370 1825.020 3447.380 ; + RECT 2002.020 3447.370 2005.020 3447.380 ; + RECT 2182.020 3447.370 2185.020 3447.380 ; + RECT 2362.020 3447.370 2365.020 3447.380 ; + RECT 2542.020 3447.370 2545.020 3447.380 ; + RECT 2722.020 3447.370 2725.020 3447.380 ; + RECT 2902.020 3447.370 2905.020 3447.380 ; + RECT 2936.200 3447.370 2939.200 3447.380 ; + RECT -9.980 3432.380 -6.980 3432.390 ; + RECT 4.020 3432.380 7.020 3432.390 ; + RECT 184.020 3432.380 187.020 3432.390 ; + RECT 364.020 3432.380 367.020 3432.390 ; + RECT 544.020 3432.380 547.020 3432.390 ; + RECT 724.020 3432.380 727.020 3432.390 ; + RECT 904.020 3432.380 907.020 3432.390 ; + RECT 1084.020 3432.380 1087.020 3432.390 ; + RECT 1264.020 3432.380 1267.020 3432.390 ; + RECT 1444.020 3432.380 1447.020 3432.390 ; + RECT 1624.020 3432.380 1627.020 3432.390 ; + RECT 1804.020 3432.380 1807.020 3432.390 ; + RECT 1984.020 3432.380 1987.020 3432.390 ; + RECT 2164.020 3432.380 2167.020 3432.390 ; + RECT 2344.020 3432.380 2347.020 3432.390 ; + RECT 2524.020 3432.380 2527.020 3432.390 ; + RECT 2704.020 3432.380 2707.020 3432.390 ; + RECT 2884.020 3432.380 2887.020 3432.390 ; + RECT 2926.600 3432.380 2929.600 3432.390 ; + RECT -14.780 3429.380 2934.400 3432.380 ; + RECT -9.980 3429.370 -6.980 3429.380 ; + RECT 4.020 3429.370 7.020 3429.380 ; + RECT 184.020 3429.370 187.020 3429.380 ; + RECT 364.020 3429.370 367.020 3429.380 ; + RECT 544.020 3429.370 547.020 3429.380 ; + RECT 724.020 3429.370 727.020 3429.380 ; + RECT 904.020 3429.370 907.020 3429.380 ; + RECT 1084.020 3429.370 1087.020 3429.380 ; + RECT 1264.020 3429.370 1267.020 3429.380 ; + RECT 1444.020 3429.370 1447.020 3429.380 ; + RECT 1624.020 3429.370 1627.020 3429.380 ; + RECT 1804.020 3429.370 1807.020 3429.380 ; + RECT 1984.020 3429.370 1987.020 3429.380 ; + RECT 2164.020 3429.370 2167.020 3429.380 ; + RECT 2344.020 3429.370 2347.020 3429.380 ; + RECT 2524.020 3429.370 2527.020 3429.380 ; + RECT 2704.020 3429.370 2707.020 3429.380 ; + RECT 2884.020 3429.370 2887.020 3429.380 ; + RECT 2926.600 3429.370 2929.600 3429.380 ; + RECT -19.580 3270.380 -16.580 3270.390 ; + RECT 22.020 3270.380 25.020 3270.390 ; + RECT 202.020 3270.380 205.020 3270.390 ; + RECT 382.020 3270.380 385.020 3270.390 ; + RECT 562.020 3270.380 565.020 3270.390 ; + RECT 742.020 3270.380 745.020 3270.390 ; + RECT 922.020 3270.380 925.020 3270.390 ; + RECT 1102.020 3270.380 1105.020 3270.390 ; + RECT 1282.020 3270.380 1285.020 3270.390 ; + RECT 1462.020 3270.380 1465.020 3270.390 ; + RECT 1642.020 3270.380 1645.020 3270.390 ; + RECT 1822.020 3270.380 1825.020 3270.390 ; + RECT 2002.020 3270.380 2005.020 3270.390 ; + RECT 2182.020 3270.380 2185.020 3270.390 ; + RECT 2362.020 3270.380 2365.020 3270.390 ; + RECT 2542.020 3270.380 2545.020 3270.390 ; + RECT 2722.020 3270.380 2725.020 3270.390 ; + RECT 2902.020 3270.380 2905.020 3270.390 ; + RECT 2936.200 3270.380 2939.200 3270.390 ; + RECT -24.380 3267.380 2944.000 3270.380 ; + RECT -19.580 3267.370 -16.580 3267.380 ; + RECT 22.020 3267.370 25.020 3267.380 ; + RECT 202.020 3267.370 205.020 3267.380 ; + RECT 382.020 3267.370 385.020 3267.380 ; + RECT 562.020 3267.370 565.020 3267.380 ; + RECT 742.020 3267.370 745.020 3267.380 ; + RECT 922.020 3267.370 925.020 3267.380 ; + RECT 1102.020 3267.370 1105.020 3267.380 ; + RECT 1282.020 3267.370 1285.020 3267.380 ; + RECT 1462.020 3267.370 1465.020 3267.380 ; + RECT 1642.020 3267.370 1645.020 3267.380 ; + RECT 1822.020 3267.370 1825.020 3267.380 ; + RECT 2002.020 3267.370 2005.020 3267.380 ; + RECT 2182.020 3267.370 2185.020 3267.380 ; + RECT 2362.020 3267.370 2365.020 3267.380 ; + RECT 2542.020 3267.370 2545.020 3267.380 ; + RECT 2722.020 3267.370 2725.020 3267.380 ; + RECT 2902.020 3267.370 2905.020 3267.380 ; + RECT 2936.200 3267.370 2939.200 3267.380 ; + RECT -9.980 3252.380 -6.980 3252.390 ; + RECT 4.020 3252.380 7.020 3252.390 ; + RECT 184.020 3252.380 187.020 3252.390 ; + RECT 2704.020 3252.380 2707.020 3252.390 ; + RECT 2884.020 3252.380 2887.020 3252.390 ; + RECT 2926.600 3252.380 2929.600 3252.390 ; + RECT -14.780 3249.380 2934.400 3252.380 ; + RECT -9.980 3249.370 -6.980 3249.380 ; + RECT 4.020 3249.370 7.020 3249.380 ; + RECT 184.020 3249.370 187.020 3249.380 ; + RECT 2704.020 3249.370 2707.020 3249.380 ; + RECT 2884.020 3249.370 2887.020 3249.380 ; + RECT 2926.600 3249.370 2929.600 3249.380 ; + RECT -19.580 3090.380 -16.580 3090.390 ; + RECT 22.020 3090.380 25.020 3090.390 ; + RECT 202.020 3090.380 205.020 3090.390 ; + RECT 331.040 3090.380 332.640 3090.390 ; + RECT 2722.020 3090.380 2725.020 3090.390 ; + RECT 2902.020 3090.380 2905.020 3090.390 ; + RECT 2936.200 3090.380 2939.200 3090.390 ; + RECT -24.380 3087.380 2944.000 3090.380 ; + RECT -19.580 3087.370 -16.580 3087.380 ; + RECT 22.020 3087.370 25.020 3087.380 ; + RECT 202.020 3087.370 205.020 3087.380 ; + RECT 331.040 3087.370 332.640 3087.380 ; + RECT 2722.020 3087.370 2725.020 3087.380 ; + RECT 2902.020 3087.370 2905.020 3087.380 ; + RECT 2936.200 3087.370 2939.200 3087.380 ; + RECT -9.980 3072.380 -6.980 3072.390 ; + RECT 4.020 3072.380 7.020 3072.390 ; + RECT 184.020 3072.380 187.020 3072.390 ; + RECT 331.040 3072.380 332.640 3072.390 ; + RECT 2704.020 3072.380 2707.020 3072.390 ; + RECT 2884.020 3072.380 2887.020 3072.390 ; + RECT 2926.600 3072.380 2929.600 3072.390 ; + RECT -14.780 3069.380 2934.400 3072.380 ; + RECT -9.980 3069.370 -6.980 3069.380 ; + RECT 4.020 3069.370 7.020 3069.380 ; + RECT 184.020 3069.370 187.020 3069.380 ; + RECT 331.040 3069.370 332.640 3069.380 ; + RECT 2704.020 3069.370 2707.020 3069.380 ; + RECT 2884.020 3069.370 2887.020 3069.380 ; + RECT 2926.600 3069.370 2929.600 3069.380 ; + RECT -19.580 2910.380 -16.580 2910.390 ; + RECT 22.020 2910.380 25.020 2910.390 ; + RECT 202.020 2910.380 205.020 2910.390 ; + RECT 331.040 2910.380 332.640 2910.390 ; + RECT 2722.020 2910.380 2725.020 2910.390 ; + RECT 2902.020 2910.380 2905.020 2910.390 ; + RECT 2936.200 2910.380 2939.200 2910.390 ; + RECT -24.380 2907.380 2944.000 2910.380 ; + RECT -19.580 2907.370 -16.580 2907.380 ; + RECT 22.020 2907.370 25.020 2907.380 ; + RECT 202.020 2907.370 205.020 2907.380 ; + RECT 331.040 2907.370 332.640 2907.380 ; + RECT 2722.020 2907.370 2725.020 2907.380 ; + RECT 2902.020 2907.370 2905.020 2907.380 ; + RECT 2936.200 2907.370 2939.200 2907.380 ; + RECT -9.980 2892.380 -6.980 2892.390 ; + RECT 4.020 2892.380 7.020 2892.390 ; + RECT 184.020 2892.380 187.020 2892.390 ; + RECT 331.040 2892.380 332.640 2892.390 ; + RECT 2704.020 2892.380 2707.020 2892.390 ; + RECT 2884.020 2892.380 2887.020 2892.390 ; + RECT 2926.600 2892.380 2929.600 2892.390 ; + RECT -14.780 2889.380 2934.400 2892.380 ; + RECT -9.980 2889.370 -6.980 2889.380 ; + RECT 4.020 2889.370 7.020 2889.380 ; + RECT 184.020 2889.370 187.020 2889.380 ; + RECT 331.040 2889.370 332.640 2889.380 ; + RECT 2704.020 2889.370 2707.020 2889.380 ; + RECT 2884.020 2889.370 2887.020 2889.380 ; + RECT 2926.600 2889.370 2929.600 2889.380 ; + RECT -19.580 2730.380 -16.580 2730.390 ; + RECT 22.020 2730.380 25.020 2730.390 ; + RECT 202.020 2730.380 205.020 2730.390 ; + RECT 331.040 2730.380 332.640 2730.390 ; + RECT 2722.020 2730.380 2725.020 2730.390 ; + RECT 2902.020 2730.380 2905.020 2730.390 ; + RECT 2936.200 2730.380 2939.200 2730.390 ; + RECT -24.380 2727.380 2944.000 2730.380 ; + RECT -19.580 2727.370 -16.580 2727.380 ; + RECT 22.020 2727.370 25.020 2727.380 ; + RECT 202.020 2727.370 205.020 2727.380 ; + RECT 331.040 2727.370 332.640 2727.380 ; + RECT 2722.020 2727.370 2725.020 2727.380 ; + RECT 2902.020 2727.370 2905.020 2727.380 ; + RECT 2936.200 2727.370 2939.200 2727.380 ; + RECT -9.980 2712.380 -6.980 2712.390 ; + RECT 4.020 2712.380 7.020 2712.390 ; + RECT 184.020 2712.380 187.020 2712.390 ; + RECT 331.040 2712.380 332.640 2712.390 ; + RECT 2704.020 2712.380 2707.020 2712.390 ; + RECT 2884.020 2712.380 2887.020 2712.390 ; + RECT 2926.600 2712.380 2929.600 2712.390 ; + RECT -14.780 2709.380 2934.400 2712.380 ; + RECT -9.980 2709.370 -6.980 2709.380 ; + RECT 4.020 2709.370 7.020 2709.380 ; + RECT 184.020 2709.370 187.020 2709.380 ; + RECT 331.040 2709.370 332.640 2709.380 ; + RECT 2704.020 2709.370 2707.020 2709.380 ; + RECT 2884.020 2709.370 2887.020 2709.380 ; + RECT 2926.600 2709.370 2929.600 2709.380 ; + RECT -19.580 2550.380 -16.580 2550.390 ; + RECT 22.020 2550.380 25.020 2550.390 ; + RECT 202.020 2550.380 205.020 2550.390 ; + RECT 331.040 2550.380 332.640 2550.390 ; + RECT 2722.020 2550.380 2725.020 2550.390 ; + RECT 2902.020 2550.380 2905.020 2550.390 ; + RECT 2936.200 2550.380 2939.200 2550.390 ; + RECT -24.380 2547.380 2944.000 2550.380 ; + RECT -19.580 2547.370 -16.580 2547.380 ; + RECT 22.020 2547.370 25.020 2547.380 ; + RECT 202.020 2547.370 205.020 2547.380 ; + RECT 331.040 2547.370 332.640 2547.380 ; + RECT 2722.020 2547.370 2725.020 2547.380 ; + RECT 2902.020 2547.370 2905.020 2547.380 ; + RECT 2936.200 2547.370 2939.200 2547.380 ; + RECT -9.980 2532.380 -6.980 2532.390 ; + RECT 4.020 2532.380 7.020 2532.390 ; + RECT 184.020 2532.380 187.020 2532.390 ; + RECT 331.040 2532.380 332.640 2532.390 ; + RECT 2704.020 2532.380 2707.020 2532.390 ; + RECT 2884.020 2532.380 2887.020 2532.390 ; + RECT 2926.600 2532.380 2929.600 2532.390 ; + RECT -14.780 2529.380 2934.400 2532.380 ; + RECT -9.980 2529.370 -6.980 2529.380 ; + RECT 4.020 2529.370 7.020 2529.380 ; + RECT 184.020 2529.370 187.020 2529.380 ; + RECT 331.040 2529.370 332.640 2529.380 ; + RECT 2704.020 2529.370 2707.020 2529.380 ; + RECT 2884.020 2529.370 2887.020 2529.380 ; + RECT 2926.600 2529.370 2929.600 2529.380 ; + RECT -19.580 2370.380 -16.580 2370.390 ; + RECT 22.020 2370.380 25.020 2370.390 ; + RECT 202.020 2370.380 205.020 2370.390 ; + RECT 331.040 2370.380 332.640 2370.390 ; + RECT 2722.020 2370.380 2725.020 2370.390 ; + RECT 2902.020 2370.380 2905.020 2370.390 ; + RECT 2936.200 2370.380 2939.200 2370.390 ; + RECT -24.380 2367.380 2944.000 2370.380 ; + RECT -19.580 2367.370 -16.580 2367.380 ; + RECT 22.020 2367.370 25.020 2367.380 ; + RECT 202.020 2367.370 205.020 2367.380 ; + RECT 331.040 2367.370 332.640 2367.380 ; + RECT 2722.020 2367.370 2725.020 2367.380 ; + RECT 2902.020 2367.370 2905.020 2367.380 ; + RECT 2936.200 2367.370 2939.200 2367.380 ; + RECT -9.980 2352.380 -6.980 2352.390 ; + RECT 4.020 2352.380 7.020 2352.390 ; + RECT 184.020 2352.380 187.020 2352.390 ; + RECT 331.040 2352.380 332.640 2352.390 ; + RECT 2704.020 2352.380 2707.020 2352.390 ; + RECT 2884.020 2352.380 2887.020 2352.390 ; + RECT 2926.600 2352.380 2929.600 2352.390 ; + RECT -14.780 2349.380 2934.400 2352.380 ; + RECT -9.980 2349.370 -6.980 2349.380 ; + RECT 4.020 2349.370 7.020 2349.380 ; + RECT 184.020 2349.370 187.020 2349.380 ; + RECT 331.040 2349.370 332.640 2349.380 ; + RECT 2704.020 2349.370 2707.020 2349.380 ; + RECT 2884.020 2349.370 2887.020 2349.380 ; + RECT 2926.600 2349.370 2929.600 2349.380 ; + RECT -19.580 2190.380 -16.580 2190.390 ; + RECT 22.020 2190.380 25.020 2190.390 ; + RECT 202.020 2190.380 205.020 2190.390 ; + RECT 331.040 2190.380 332.640 2190.390 ; + RECT 2722.020 2190.380 2725.020 2190.390 ; + RECT 2902.020 2190.380 2905.020 2190.390 ; + RECT 2936.200 2190.380 2939.200 2190.390 ; + RECT -24.380 2187.380 2944.000 2190.380 ; + RECT -19.580 2187.370 -16.580 2187.380 ; + RECT 22.020 2187.370 25.020 2187.380 ; + RECT 202.020 2187.370 205.020 2187.380 ; + RECT 331.040 2187.370 332.640 2187.380 ; + RECT 2722.020 2187.370 2725.020 2187.380 ; + RECT 2902.020 2187.370 2905.020 2187.380 ; + RECT 2936.200 2187.370 2939.200 2187.380 ; + RECT -9.980 2172.380 -6.980 2172.390 ; + RECT 4.020 2172.380 7.020 2172.390 ; + RECT 184.020 2172.380 187.020 2172.390 ; + RECT 331.040 2172.380 332.640 2172.390 ; + RECT 2704.020 2172.380 2707.020 2172.390 ; + RECT 2884.020 2172.380 2887.020 2172.390 ; + RECT 2926.600 2172.380 2929.600 2172.390 ; + RECT -14.780 2169.380 2934.400 2172.380 ; + RECT -9.980 2169.370 -6.980 2169.380 ; + RECT 4.020 2169.370 7.020 2169.380 ; + RECT 184.020 2169.370 187.020 2169.380 ; + RECT 331.040 2169.370 332.640 2169.380 ; + RECT 2704.020 2169.370 2707.020 2169.380 ; + RECT 2884.020 2169.370 2887.020 2169.380 ; + RECT 2926.600 2169.370 2929.600 2169.380 ; + RECT -19.580 2010.380 -16.580 2010.390 ; + RECT 22.020 2010.380 25.020 2010.390 ; + RECT 202.020 2010.380 205.020 2010.390 ; + RECT 331.040 2010.380 332.640 2010.390 ; + RECT 2722.020 2010.380 2725.020 2010.390 ; + RECT 2902.020 2010.380 2905.020 2010.390 ; + RECT 2936.200 2010.380 2939.200 2010.390 ; + RECT -24.380 2007.380 2944.000 2010.380 ; + RECT -19.580 2007.370 -16.580 2007.380 ; + RECT 22.020 2007.370 25.020 2007.380 ; + RECT 202.020 2007.370 205.020 2007.380 ; + RECT 331.040 2007.370 332.640 2007.380 ; + RECT 2722.020 2007.370 2725.020 2007.380 ; + RECT 2902.020 2007.370 2905.020 2007.380 ; + RECT 2936.200 2007.370 2939.200 2007.380 ; + RECT -9.980 1992.380 -6.980 1992.390 ; + RECT 4.020 1992.380 7.020 1992.390 ; + RECT 184.020 1992.380 187.020 1992.390 ; + RECT 331.040 1992.380 332.640 1992.390 ; + RECT 2704.020 1992.380 2707.020 1992.390 ; + RECT 2884.020 1992.380 2887.020 1992.390 ; + RECT 2926.600 1992.380 2929.600 1992.390 ; + RECT -14.780 1989.380 2934.400 1992.380 ; + RECT -9.980 1989.370 -6.980 1989.380 ; + RECT 4.020 1989.370 7.020 1989.380 ; + RECT 184.020 1989.370 187.020 1989.380 ; + RECT 331.040 1989.370 332.640 1989.380 ; + RECT 2704.020 1989.370 2707.020 1989.380 ; + RECT 2884.020 1989.370 2887.020 1989.380 ; + RECT 2926.600 1989.370 2929.600 1989.380 ; + RECT -19.580 1830.380 -16.580 1830.390 ; + RECT 22.020 1830.380 25.020 1830.390 ; + RECT 202.020 1830.380 205.020 1830.390 ; + RECT 331.040 1830.380 332.640 1830.390 ; + RECT 2722.020 1830.380 2725.020 1830.390 ; + RECT 2902.020 1830.380 2905.020 1830.390 ; + RECT 2936.200 1830.380 2939.200 1830.390 ; + RECT -24.380 1827.380 2944.000 1830.380 ; + RECT -19.580 1827.370 -16.580 1827.380 ; + RECT 22.020 1827.370 25.020 1827.380 ; + RECT 202.020 1827.370 205.020 1827.380 ; + RECT 331.040 1827.370 332.640 1827.380 ; + RECT 2722.020 1827.370 2725.020 1827.380 ; + RECT 2902.020 1827.370 2905.020 1827.380 ; + RECT 2936.200 1827.370 2939.200 1827.380 ; + RECT -9.980 1812.380 -6.980 1812.390 ; + RECT 4.020 1812.380 7.020 1812.390 ; + RECT 184.020 1812.380 187.020 1812.390 ; + RECT 331.040 1812.380 332.640 1812.390 ; + RECT 2704.020 1812.380 2707.020 1812.390 ; + RECT 2884.020 1812.380 2887.020 1812.390 ; + RECT 2926.600 1812.380 2929.600 1812.390 ; + RECT -14.780 1809.380 2934.400 1812.380 ; + RECT -9.980 1809.370 -6.980 1809.380 ; + RECT 4.020 1809.370 7.020 1809.380 ; + RECT 184.020 1809.370 187.020 1809.380 ; + RECT 331.040 1809.370 332.640 1809.380 ; + RECT 2704.020 1809.370 2707.020 1809.380 ; + RECT 2884.020 1809.370 2887.020 1809.380 ; + RECT 2926.600 1809.370 2929.600 1809.380 ; + RECT -19.580 1650.380 -16.580 1650.390 ; + RECT 22.020 1650.380 25.020 1650.390 ; + RECT 202.020 1650.380 205.020 1650.390 ; + RECT 331.040 1650.380 332.640 1650.390 ; + RECT 2722.020 1650.380 2725.020 1650.390 ; + RECT 2902.020 1650.380 2905.020 1650.390 ; + RECT 2936.200 1650.380 2939.200 1650.390 ; + RECT -24.380 1647.380 2944.000 1650.380 ; + RECT -19.580 1647.370 -16.580 1647.380 ; + RECT 22.020 1647.370 25.020 1647.380 ; + RECT 202.020 1647.370 205.020 1647.380 ; + RECT 331.040 1647.370 332.640 1647.380 ; + RECT 2722.020 1647.370 2725.020 1647.380 ; + RECT 2902.020 1647.370 2905.020 1647.380 ; + RECT 2936.200 1647.370 2939.200 1647.380 ; + RECT -9.980 1632.380 -6.980 1632.390 ; + RECT 4.020 1632.380 7.020 1632.390 ; + RECT 184.020 1632.380 187.020 1632.390 ; + RECT 331.040 1632.380 332.640 1632.390 ; + RECT 2704.020 1632.380 2707.020 1632.390 ; + RECT 2884.020 1632.380 2887.020 1632.390 ; + RECT 2926.600 1632.380 2929.600 1632.390 ; + RECT -14.780 1629.380 2934.400 1632.380 ; + RECT -9.980 1629.370 -6.980 1629.380 ; + RECT 4.020 1629.370 7.020 1629.380 ; + RECT 184.020 1629.370 187.020 1629.380 ; + RECT 331.040 1629.370 332.640 1629.380 ; + RECT 2704.020 1629.370 2707.020 1629.380 ; + RECT 2884.020 1629.370 2887.020 1629.380 ; + RECT 2926.600 1629.370 2929.600 1629.380 ; + RECT -19.580 1470.380 -16.580 1470.390 ; + RECT 22.020 1470.380 25.020 1470.390 ; + RECT 202.020 1470.380 205.020 1470.390 ; + RECT 331.040 1470.380 332.640 1470.390 ; + RECT 2722.020 1470.380 2725.020 1470.390 ; + RECT 2902.020 1470.380 2905.020 1470.390 ; + RECT 2936.200 1470.380 2939.200 1470.390 ; + RECT -24.380 1467.380 2944.000 1470.380 ; + RECT -19.580 1467.370 -16.580 1467.380 ; + RECT 22.020 1467.370 25.020 1467.380 ; + RECT 202.020 1467.370 205.020 1467.380 ; + RECT 331.040 1467.370 332.640 1467.380 ; + RECT 2722.020 1467.370 2725.020 1467.380 ; + RECT 2902.020 1467.370 2905.020 1467.380 ; + RECT 2936.200 1467.370 2939.200 1467.380 ; + RECT -9.980 1452.380 -6.980 1452.390 ; + RECT 4.020 1452.380 7.020 1452.390 ; + RECT 184.020 1452.380 187.020 1452.390 ; + RECT 331.040 1452.380 332.640 1452.390 ; + RECT 2704.020 1452.380 2707.020 1452.390 ; + RECT 2884.020 1452.380 2887.020 1452.390 ; + RECT 2926.600 1452.380 2929.600 1452.390 ; + RECT -14.780 1449.380 2934.400 1452.380 ; + RECT -9.980 1449.370 -6.980 1449.380 ; + RECT 4.020 1449.370 7.020 1449.380 ; + RECT 184.020 1449.370 187.020 1449.380 ; + RECT 331.040 1449.370 332.640 1449.380 ; + RECT 2704.020 1449.370 2707.020 1449.380 ; + RECT 2884.020 1449.370 2887.020 1449.380 ; + RECT 2926.600 1449.370 2929.600 1449.380 ; + RECT -19.580 1290.380 -16.580 1290.390 ; + RECT 22.020 1290.380 25.020 1290.390 ; + RECT 202.020 1290.380 205.020 1290.390 ; + RECT 331.040 1290.380 332.640 1290.390 ; + RECT 2722.020 1290.380 2725.020 1290.390 ; + RECT 2902.020 1290.380 2905.020 1290.390 ; + RECT 2936.200 1290.380 2939.200 1290.390 ; + RECT -24.380 1287.380 2944.000 1290.380 ; + RECT -19.580 1287.370 -16.580 1287.380 ; + RECT 22.020 1287.370 25.020 1287.380 ; + RECT 202.020 1287.370 205.020 1287.380 ; + RECT 331.040 1287.370 332.640 1287.380 ; + RECT 2722.020 1287.370 2725.020 1287.380 ; + RECT 2902.020 1287.370 2905.020 1287.380 ; + RECT 2936.200 1287.370 2939.200 1287.380 ; + RECT -9.980 1272.380 -6.980 1272.390 ; + RECT 4.020 1272.380 7.020 1272.390 ; + RECT 184.020 1272.380 187.020 1272.390 ; + RECT 331.040 1272.380 332.640 1272.390 ; + RECT 2704.020 1272.380 2707.020 1272.390 ; + RECT 2884.020 1272.380 2887.020 1272.390 ; + RECT 2926.600 1272.380 2929.600 1272.390 ; + RECT -14.780 1269.380 2934.400 1272.380 ; + RECT -9.980 1269.370 -6.980 1269.380 ; + RECT 4.020 1269.370 7.020 1269.380 ; + RECT 184.020 1269.370 187.020 1269.380 ; + RECT 331.040 1269.370 332.640 1269.380 ; + RECT 2704.020 1269.370 2707.020 1269.380 ; + RECT 2884.020 1269.370 2887.020 1269.380 ; + RECT 2926.600 1269.370 2929.600 1269.380 ; + RECT -19.580 1110.380 -16.580 1110.390 ; + RECT 22.020 1110.380 25.020 1110.390 ; + RECT 202.020 1110.380 205.020 1110.390 ; + RECT 331.040 1110.380 332.640 1110.390 ; + RECT 2722.020 1110.380 2725.020 1110.390 ; + RECT 2902.020 1110.380 2905.020 1110.390 ; + RECT 2936.200 1110.380 2939.200 1110.390 ; + RECT -24.380 1107.380 2944.000 1110.380 ; + RECT -19.580 1107.370 -16.580 1107.380 ; + RECT 22.020 1107.370 25.020 1107.380 ; + RECT 202.020 1107.370 205.020 1107.380 ; + RECT 331.040 1107.370 332.640 1107.380 ; + RECT 2722.020 1107.370 2725.020 1107.380 ; + RECT 2902.020 1107.370 2905.020 1107.380 ; + RECT 2936.200 1107.370 2939.200 1107.380 ; + RECT -9.980 1092.380 -6.980 1092.390 ; + RECT 4.020 1092.380 7.020 1092.390 ; + RECT 184.020 1092.380 187.020 1092.390 ; + RECT 331.040 1092.380 332.640 1092.390 ; + RECT 2704.020 1092.380 2707.020 1092.390 ; + RECT 2884.020 1092.380 2887.020 1092.390 ; + RECT 2926.600 1092.380 2929.600 1092.390 ; + RECT -14.780 1089.380 2934.400 1092.380 ; + RECT -9.980 1089.370 -6.980 1089.380 ; + RECT 4.020 1089.370 7.020 1089.380 ; + RECT 184.020 1089.370 187.020 1089.380 ; + RECT 331.040 1089.370 332.640 1089.380 ; + RECT 2704.020 1089.370 2707.020 1089.380 ; + RECT 2884.020 1089.370 2887.020 1089.380 ; + RECT 2926.600 1089.370 2929.600 1089.380 ; + RECT -19.580 930.380 -16.580 930.390 ; + RECT 22.020 930.380 25.020 930.390 ; + RECT 202.020 930.380 205.020 930.390 ; + RECT 331.040 930.380 332.640 930.390 ; + RECT 2722.020 930.380 2725.020 930.390 ; + RECT 2902.020 930.380 2905.020 930.390 ; + RECT 2936.200 930.380 2939.200 930.390 ; + RECT -24.380 927.380 2944.000 930.380 ; + RECT -19.580 927.370 -16.580 927.380 ; + RECT 22.020 927.370 25.020 927.380 ; + RECT 202.020 927.370 205.020 927.380 ; + RECT 331.040 927.370 332.640 927.380 ; + RECT 2722.020 927.370 2725.020 927.380 ; + RECT 2902.020 927.370 2905.020 927.380 ; + RECT 2936.200 927.370 2939.200 927.380 ; + RECT -9.980 912.380 -6.980 912.390 ; + RECT 4.020 912.380 7.020 912.390 ; + RECT 184.020 912.380 187.020 912.390 ; + RECT 331.040 912.380 332.640 912.390 ; + RECT 2704.020 912.380 2707.020 912.390 ; + RECT 2884.020 912.380 2887.020 912.390 ; + RECT 2926.600 912.380 2929.600 912.390 ; + RECT -14.780 909.380 2934.400 912.380 ; + RECT -9.980 909.370 -6.980 909.380 ; + RECT 4.020 909.370 7.020 909.380 ; + RECT 184.020 909.370 187.020 909.380 ; + RECT 331.040 909.370 332.640 909.380 ; + RECT 2704.020 909.370 2707.020 909.380 ; + RECT 2884.020 909.370 2887.020 909.380 ; + RECT 2926.600 909.370 2929.600 909.380 ; + RECT -19.580 750.380 -16.580 750.390 ; + RECT 22.020 750.380 25.020 750.390 ; + RECT 202.020 750.380 205.020 750.390 ; + RECT 331.040 750.380 332.640 750.390 ; + RECT 2722.020 750.380 2725.020 750.390 ; + RECT 2902.020 750.380 2905.020 750.390 ; + RECT 2936.200 750.380 2939.200 750.390 ; + RECT -24.380 747.380 2944.000 750.380 ; + RECT -19.580 747.370 -16.580 747.380 ; + RECT 22.020 747.370 25.020 747.380 ; + RECT 202.020 747.370 205.020 747.380 ; + RECT 331.040 747.370 332.640 747.380 ; + RECT 2722.020 747.370 2725.020 747.380 ; + RECT 2902.020 747.370 2905.020 747.380 ; + RECT 2936.200 747.370 2939.200 747.380 ; + RECT -9.980 732.380 -6.980 732.390 ; + RECT 4.020 732.380 7.020 732.390 ; + RECT 184.020 732.380 187.020 732.390 ; + RECT 331.040 732.380 332.640 732.390 ; + RECT 2704.020 732.380 2707.020 732.390 ; + RECT 2884.020 732.380 2887.020 732.390 ; + RECT 2926.600 732.380 2929.600 732.390 ; + RECT -14.780 729.380 2934.400 732.380 ; + RECT -9.980 729.370 -6.980 729.380 ; + RECT 4.020 729.370 7.020 729.380 ; + RECT 184.020 729.370 187.020 729.380 ; + RECT 331.040 729.370 332.640 729.380 ; + RECT 2704.020 729.370 2707.020 729.380 ; + RECT 2884.020 729.370 2887.020 729.380 ; + RECT 2926.600 729.370 2929.600 729.380 ; + RECT -19.580 570.380 -16.580 570.390 ; + RECT 22.020 570.380 25.020 570.390 ; + RECT 202.020 570.380 205.020 570.390 ; + RECT 331.040 570.380 332.640 570.390 ; + RECT 2722.020 570.380 2725.020 570.390 ; + RECT 2902.020 570.380 2905.020 570.390 ; + RECT 2936.200 570.380 2939.200 570.390 ; + RECT -24.380 567.380 2944.000 570.380 ; + RECT -19.580 567.370 -16.580 567.380 ; + RECT 22.020 567.370 25.020 567.380 ; + RECT 202.020 567.370 205.020 567.380 ; + RECT 331.040 567.370 332.640 567.380 ; + RECT 2722.020 567.370 2725.020 567.380 ; + RECT 2902.020 567.370 2905.020 567.380 ; + RECT 2936.200 567.370 2939.200 567.380 ; + RECT -9.980 552.380 -6.980 552.390 ; + RECT 4.020 552.380 7.020 552.390 ; + RECT 184.020 552.380 187.020 552.390 ; + RECT 331.040 552.380 332.640 552.390 ; + RECT 2704.020 552.380 2707.020 552.390 ; + RECT 2884.020 552.380 2887.020 552.390 ; + RECT 2926.600 552.380 2929.600 552.390 ; + RECT -14.780 549.380 2934.400 552.380 ; + RECT -9.980 549.370 -6.980 549.380 ; + RECT 4.020 549.370 7.020 549.380 ; + RECT 184.020 549.370 187.020 549.380 ; + RECT 331.040 549.370 332.640 549.380 ; + RECT 2704.020 549.370 2707.020 549.380 ; + RECT 2884.020 549.370 2887.020 549.380 ; + RECT 2926.600 549.370 2929.600 549.380 ; + RECT -19.580 390.380 -16.580 390.390 ; + RECT 22.020 390.380 25.020 390.390 ; + RECT 202.020 390.380 205.020 390.390 ; + RECT 331.040 390.380 332.640 390.390 ; + RECT 2722.020 390.380 2725.020 390.390 ; + RECT 2902.020 390.380 2905.020 390.390 ; + RECT 2936.200 390.380 2939.200 390.390 ; + RECT -24.380 387.380 2944.000 390.380 ; + RECT -19.580 387.370 -16.580 387.380 ; + RECT 22.020 387.370 25.020 387.380 ; + RECT 202.020 387.370 205.020 387.380 ; + RECT 331.040 387.370 332.640 387.380 ; + RECT 2722.020 387.370 2725.020 387.380 ; + RECT 2902.020 387.370 2905.020 387.380 ; + RECT 2936.200 387.370 2939.200 387.380 ; + RECT -9.980 372.380 -6.980 372.390 ; + RECT 4.020 372.380 7.020 372.390 ; + RECT 184.020 372.380 187.020 372.390 ; + RECT 331.040 372.380 332.640 372.390 ; + RECT 2704.020 372.380 2707.020 372.390 ; + RECT 2884.020 372.380 2887.020 372.390 ; + RECT 2926.600 372.380 2929.600 372.390 ; + RECT -14.780 369.380 2934.400 372.380 ; + RECT -9.980 369.370 -6.980 369.380 ; + RECT 4.020 369.370 7.020 369.380 ; + RECT 184.020 369.370 187.020 369.380 ; + RECT 331.040 369.370 332.640 369.380 ; + RECT 2704.020 369.370 2707.020 369.380 ; + RECT 2884.020 369.370 2887.020 369.380 ; + RECT 2926.600 369.370 2929.600 369.380 ; + RECT -19.580 210.380 -16.580 210.390 ; + RECT 22.020 210.380 25.020 210.390 ; + RECT 202.020 210.380 205.020 210.390 ; + RECT 382.020 210.380 385.020 210.390 ; + RECT 562.020 210.380 565.020 210.390 ; + RECT 742.020 210.380 745.020 210.390 ; + RECT 922.020 210.380 925.020 210.390 ; + RECT 1102.020 210.380 1105.020 210.390 ; + RECT 1282.020 210.380 1285.020 210.390 ; + RECT 1462.020 210.380 1465.020 210.390 ; + RECT 1642.020 210.380 1645.020 210.390 ; + RECT 1822.020 210.380 1825.020 210.390 ; + RECT 2002.020 210.380 2005.020 210.390 ; + RECT 2182.020 210.380 2185.020 210.390 ; + RECT 2362.020 210.380 2365.020 210.390 ; + RECT 2542.020 210.380 2545.020 210.390 ; + RECT 2722.020 210.380 2725.020 210.390 ; + RECT 2902.020 210.380 2905.020 210.390 ; + RECT 2936.200 210.380 2939.200 210.390 ; + RECT -24.380 207.380 2944.000 210.380 ; + RECT -19.580 207.370 -16.580 207.380 ; + RECT 22.020 207.370 25.020 207.380 ; + RECT 202.020 207.370 205.020 207.380 ; + RECT 382.020 207.370 385.020 207.380 ; + RECT 562.020 207.370 565.020 207.380 ; + RECT 742.020 207.370 745.020 207.380 ; + RECT 922.020 207.370 925.020 207.380 ; + RECT 1102.020 207.370 1105.020 207.380 ; + RECT 1282.020 207.370 1285.020 207.380 ; + RECT 1462.020 207.370 1465.020 207.380 ; + RECT 1642.020 207.370 1645.020 207.380 ; + RECT 1822.020 207.370 1825.020 207.380 ; + RECT 2002.020 207.370 2005.020 207.380 ; + RECT 2182.020 207.370 2185.020 207.380 ; + RECT 2362.020 207.370 2365.020 207.380 ; + RECT 2542.020 207.370 2545.020 207.380 ; + RECT 2722.020 207.370 2725.020 207.380 ; + RECT 2902.020 207.370 2905.020 207.380 ; + RECT 2936.200 207.370 2939.200 207.380 ; + RECT -9.980 192.380 -6.980 192.390 ; + RECT 4.020 192.380 7.020 192.390 ; + RECT 184.020 192.380 187.020 192.390 ; + RECT 364.020 192.380 367.020 192.390 ; + RECT 544.020 192.380 547.020 192.390 ; + RECT 724.020 192.380 727.020 192.390 ; + RECT 904.020 192.380 907.020 192.390 ; + RECT 1084.020 192.380 1087.020 192.390 ; + RECT 1264.020 192.380 1267.020 192.390 ; + RECT 1444.020 192.380 1447.020 192.390 ; + RECT 1624.020 192.380 1627.020 192.390 ; + RECT 1804.020 192.380 1807.020 192.390 ; + RECT 1984.020 192.380 1987.020 192.390 ; + RECT 2164.020 192.380 2167.020 192.390 ; + RECT 2344.020 192.380 2347.020 192.390 ; + RECT 2524.020 192.380 2527.020 192.390 ; + RECT 2704.020 192.380 2707.020 192.390 ; + RECT 2884.020 192.380 2887.020 192.390 ; + RECT 2926.600 192.380 2929.600 192.390 ; + RECT -14.780 189.380 2934.400 192.380 ; + RECT -9.980 189.370 -6.980 189.380 ; + RECT 4.020 189.370 7.020 189.380 ; + RECT 184.020 189.370 187.020 189.380 ; + RECT 364.020 189.370 367.020 189.380 ; + RECT 544.020 189.370 547.020 189.380 ; + RECT 724.020 189.370 727.020 189.380 ; + RECT 904.020 189.370 907.020 189.380 ; + RECT 1084.020 189.370 1087.020 189.380 ; + RECT 1264.020 189.370 1267.020 189.380 ; + RECT 1444.020 189.370 1447.020 189.380 ; + RECT 1624.020 189.370 1627.020 189.380 ; + RECT 1804.020 189.370 1807.020 189.380 ; + RECT 1984.020 189.370 1987.020 189.380 ; + RECT 2164.020 189.370 2167.020 189.380 ; + RECT 2344.020 189.370 2347.020 189.380 ; + RECT 2524.020 189.370 2527.020 189.380 ; + RECT 2704.020 189.370 2707.020 189.380 ; + RECT 2884.020 189.370 2887.020 189.380 ; + RECT 2926.600 189.370 2929.600 189.380 ; + RECT -19.580 30.380 -16.580 30.390 ; + RECT 22.020 30.380 25.020 30.390 ; + RECT 202.020 30.380 205.020 30.390 ; + RECT 382.020 30.380 385.020 30.390 ; + RECT 562.020 30.380 565.020 30.390 ; + RECT 742.020 30.380 745.020 30.390 ; + RECT 922.020 30.380 925.020 30.390 ; + RECT 1102.020 30.380 1105.020 30.390 ; + RECT 1282.020 30.380 1285.020 30.390 ; + RECT 1462.020 30.380 1465.020 30.390 ; + RECT 1642.020 30.380 1645.020 30.390 ; + RECT 1822.020 30.380 1825.020 30.390 ; + RECT 2002.020 30.380 2005.020 30.390 ; + RECT 2182.020 30.380 2185.020 30.390 ; + RECT 2362.020 30.380 2365.020 30.390 ; + RECT 2542.020 30.380 2545.020 30.390 ; + RECT 2722.020 30.380 2725.020 30.390 ; + RECT 2902.020 30.380 2905.020 30.390 ; + RECT 2936.200 30.380 2939.200 30.390 ; + RECT -24.380 27.380 2944.000 30.380 ; + RECT -19.580 27.370 -16.580 27.380 ; + RECT 22.020 27.370 25.020 27.380 ; + RECT 202.020 27.370 205.020 27.380 ; + RECT 382.020 27.370 385.020 27.380 ; + RECT 562.020 27.370 565.020 27.380 ; + RECT 742.020 27.370 745.020 27.380 ; + RECT 922.020 27.370 925.020 27.380 ; + RECT 1102.020 27.370 1105.020 27.380 ; + RECT 1282.020 27.370 1285.020 27.380 ; + RECT 1462.020 27.370 1465.020 27.380 ; + RECT 1642.020 27.370 1645.020 27.380 ; + RECT 1822.020 27.370 1825.020 27.380 ; + RECT 2002.020 27.370 2005.020 27.380 ; + RECT 2182.020 27.370 2185.020 27.380 ; + RECT 2362.020 27.370 2365.020 27.380 ; + RECT 2542.020 27.370 2545.020 27.380 ; + RECT 2722.020 27.370 2725.020 27.380 ; + RECT 2902.020 27.370 2905.020 27.380 ; + RECT 2936.200 27.370 2939.200 27.380 ; + RECT -9.980 12.380 -6.980 12.390 ; + RECT 4.020 12.380 7.020 12.390 ; + RECT 184.020 12.380 187.020 12.390 ; + RECT 364.020 12.380 367.020 12.390 ; + RECT 544.020 12.380 547.020 12.390 ; + RECT 724.020 12.380 727.020 12.390 ; + RECT 904.020 12.380 907.020 12.390 ; + RECT 1084.020 12.380 1087.020 12.390 ; + RECT 1264.020 12.380 1267.020 12.390 ; + RECT 1444.020 12.380 1447.020 12.390 ; + RECT 1624.020 12.380 1627.020 12.390 ; + RECT 1804.020 12.380 1807.020 12.390 ; + RECT 1984.020 12.380 1987.020 12.390 ; + RECT 2164.020 12.380 2167.020 12.390 ; + RECT 2344.020 12.380 2347.020 12.390 ; + RECT 2524.020 12.380 2527.020 12.390 ; + RECT 2704.020 12.380 2707.020 12.390 ; + RECT 2884.020 12.380 2887.020 12.390 ; + RECT 2926.600 12.380 2929.600 12.390 ; + RECT -14.780 9.380 2934.400 12.380 ; + RECT -9.980 9.370 -6.980 9.380 ; + RECT 4.020 9.370 7.020 9.380 ; + RECT 184.020 9.370 187.020 9.380 ; + RECT 364.020 9.370 367.020 9.380 ; + RECT 544.020 9.370 547.020 9.380 ; + RECT 724.020 9.370 727.020 9.380 ; + RECT 904.020 9.370 907.020 9.380 ; + RECT 1084.020 9.370 1087.020 9.380 ; + RECT 1264.020 9.370 1267.020 9.380 ; + RECT 1444.020 9.370 1447.020 9.380 ; + RECT 1624.020 9.370 1627.020 9.380 ; + RECT 1804.020 9.370 1807.020 9.380 ; + RECT 1984.020 9.370 1987.020 9.380 ; + RECT 2164.020 9.370 2167.020 9.380 ; + RECT 2344.020 9.370 2347.020 9.380 ; + RECT 2524.020 9.370 2527.020 9.380 ; + RECT 2704.020 9.370 2707.020 9.380 ; + RECT 2884.020 9.370 2887.020 9.380 ; + RECT 2926.600 9.370 2929.600 9.380 ; +======= RECT -9.980 3432.140 -6.980 3432.150 ; RECT 2926.600 3432.140 2929.600 3432.150 ; RECT -14.680 3429.140 0.300 3432.140 ; @@ -5453,6 +21418,7 @@ RECT 2919.700 9.140 2934.300 12.140 ; RECT -9.980 9.130 -6.980 9.140 ; RECT 2926.600 9.130 2929.600 9.140 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d RECT -9.980 -1.620 -6.980 -1.610 ; RECT 4.020 -1.620 7.020 -1.610 ; RECT 184.020 -1.620 187.020 -1.610 ; @@ -5492,6 +21458,45 @@ RECT 2704.020 -4.630 2707.020 -4.620 ; RECT 2884.020 -4.630 2887.020 -4.620 ; RECT 2926.600 -4.630 2929.600 -4.620 ; + RECT -19.580 -11.220 -16.580 -11.210 ; + RECT 22.020 -11.220 25.020 -11.210 ; + RECT 202.020 -11.220 205.020 -11.210 ; + RECT 382.020 -11.220 385.020 -11.210 ; + RECT 562.020 -11.220 565.020 -11.210 ; + RECT 742.020 -11.220 745.020 -11.210 ; + RECT 922.020 -11.220 925.020 -11.210 ; + RECT 1102.020 -11.220 1105.020 -11.210 ; + RECT 1282.020 -11.220 1285.020 -11.210 ; + RECT 1462.020 -11.220 1465.020 -11.210 ; + RECT 1642.020 -11.220 1645.020 -11.210 ; + RECT 1822.020 -11.220 1825.020 -11.210 ; + RECT 2002.020 -11.220 2005.020 -11.210 ; + RECT 2182.020 -11.220 2185.020 -11.210 ; + RECT 2362.020 -11.220 2365.020 -11.210 ; + RECT 2542.020 -11.220 2545.020 -11.210 ; + RECT 2722.020 -11.220 2725.020 -11.210 ; + RECT 2902.020 -11.220 2905.020 -11.210 ; + RECT 2936.200 -11.220 2939.200 -11.210 ; + RECT -19.580 -14.220 2939.200 -11.220 ; + RECT -19.580 -14.230 -16.580 -14.220 ; + RECT 22.020 -14.230 25.020 -14.220 ; + RECT 202.020 -14.230 205.020 -14.220 ; + RECT 382.020 -14.230 385.020 -14.220 ; + RECT 562.020 -14.230 565.020 -14.220 ; + RECT 742.020 -14.230 745.020 -14.220 ; + RECT 922.020 -14.230 925.020 -14.220 ; + RECT 1102.020 -14.230 1105.020 -14.220 ; + RECT 1282.020 -14.230 1285.020 -14.220 ; + RECT 1462.020 -14.230 1465.020 -14.220 ; + RECT 1642.020 -14.230 1645.020 -14.220 ; + RECT 1822.020 -14.230 1825.020 -14.220 ; + RECT 2002.020 -14.230 2005.020 -14.220 ; + RECT 2182.020 -14.230 2185.020 -14.220 ; + RECT 2362.020 -14.230 2365.020 -14.220 ; + RECT 2542.020 -14.230 2545.020 -14.220 ; + RECT 2722.020 -14.230 2725.020 -14.220 ; + RECT 2902.020 -14.230 2905.020 -14.220 ; + RECT 2936.200 -14.230 2939.200 -14.220 ; END END vccd1 PIN vssd1 @@ -5499,6 +21504,2243 @@ USE GROUND ; PORT LAYER met4 ; +<<<<<<< HEAD + RECT -24.380 -19.020 -21.380 3538.700 ; + RECT -14.780 -9.420 -11.780 3529.100 ; + RECT 94.020 -9.420 97.020 3529.100 ; + RECT 112.020 -19.020 115.020 3538.700 ; + RECT 274.020 -9.420 277.020 3529.100 ; + RECT 292.020 -19.020 295.020 3538.700 ; + RECT 454.020 3260.000 457.020 3529.100 ; + RECT 472.020 3260.000 475.020 3538.700 ; + RECT 634.020 3260.000 637.020 3529.100 ; + RECT 652.020 3260.000 655.020 3538.700 ; + RECT 814.020 3260.000 817.020 3529.100 ; + RECT 832.020 3260.000 835.020 3538.700 ; + RECT 994.020 3260.000 997.020 3529.100 ; + RECT 1012.020 3260.000 1015.020 3538.700 ; + RECT 1174.020 3260.000 1177.020 3529.100 ; + RECT 1192.020 3260.000 1195.020 3538.700 ; + RECT 1354.020 3260.000 1357.020 3529.100 ; + RECT 1372.020 3260.000 1375.020 3538.700 ; + RECT 1534.020 3260.000 1537.020 3529.100 ; + RECT 1552.020 3260.000 1555.020 3538.700 ; + RECT 1714.020 3260.000 1717.020 3529.100 ; + RECT 1732.020 3260.000 1735.020 3538.700 ; + RECT 1894.020 3260.000 1897.020 3529.100 ; + RECT 1912.020 3260.000 1915.020 3538.700 ; + RECT 2074.020 3260.000 2077.020 3529.100 ; + RECT 2092.020 3260.000 2095.020 3538.700 ; + RECT 2254.020 3260.000 2257.020 3529.100 ; + RECT 2272.020 3260.000 2275.020 3538.700 ; + RECT 2434.020 3260.000 2437.020 3529.100 ; + RECT 2452.020 3260.000 2455.020 3538.700 ; + RECT 407.840 270.640 409.440 3246.800 ; + RECT 454.020 -9.420 457.020 260.000 ; + RECT 472.020 -19.020 475.020 260.000 ; + RECT 634.020 -9.420 637.020 260.000 ; + RECT 652.020 -19.020 655.020 260.000 ; + RECT 814.020 -9.420 817.020 260.000 ; + RECT 832.020 -19.020 835.020 260.000 ; + RECT 994.020 -9.420 997.020 260.000 ; + RECT 1012.020 -19.020 1015.020 260.000 ; + RECT 1174.020 -9.420 1177.020 260.000 ; + RECT 1192.020 -19.020 1195.020 260.000 ; + RECT 1354.020 -9.420 1357.020 260.000 ; + RECT 1372.020 -19.020 1375.020 260.000 ; + RECT 1534.020 -9.420 1537.020 260.000 ; + RECT 1552.020 -19.020 1555.020 260.000 ; + RECT 1714.020 -9.420 1717.020 260.000 ; + RECT 1732.020 -19.020 1735.020 260.000 ; + RECT 1894.020 -9.420 1897.020 260.000 ; + RECT 1912.020 -19.020 1915.020 260.000 ; + RECT 2074.020 -9.420 2077.020 260.000 ; + RECT 2092.020 -19.020 2095.020 260.000 ; + RECT 2254.020 -9.420 2257.020 260.000 ; + RECT 2272.020 -19.020 2275.020 260.000 ; + RECT 2434.020 -9.420 2437.020 260.000 ; + RECT 2452.020 -19.020 2455.020 260.000 ; + RECT 2614.020 -9.420 2617.020 3529.100 ; + RECT 2632.020 -19.020 2635.020 3538.700 ; + RECT 2794.020 -9.420 2797.020 3529.100 ; + RECT 2812.020 -19.020 2815.020 3538.700 ; + RECT 2931.400 -9.420 2934.400 3529.100 ; + RECT 2941.000 -19.020 2944.000 3538.700 ; + LAYER via4 ; + RECT -23.470 3537.410 -22.290 3538.590 ; + RECT -23.470 3535.810 -22.290 3536.990 ; + RECT 112.930 3537.410 114.110 3538.590 ; + RECT 112.930 3535.810 114.110 3536.990 ; + RECT -23.470 3359.090 -22.290 3360.270 ; + RECT -23.470 3357.490 -22.290 3358.670 ; + RECT -23.470 3179.090 -22.290 3180.270 ; + RECT -23.470 3177.490 -22.290 3178.670 ; + RECT -23.470 2999.090 -22.290 3000.270 ; + RECT -23.470 2997.490 -22.290 2998.670 ; + RECT -23.470 2819.090 -22.290 2820.270 ; + RECT -23.470 2817.490 -22.290 2818.670 ; + RECT -23.470 2639.090 -22.290 2640.270 ; + RECT -23.470 2637.490 -22.290 2638.670 ; + RECT -23.470 2459.090 -22.290 2460.270 ; + RECT -23.470 2457.490 -22.290 2458.670 ; + RECT -23.470 2279.090 -22.290 2280.270 ; + RECT -23.470 2277.490 -22.290 2278.670 ; + RECT -23.470 2099.090 -22.290 2100.270 ; + RECT -23.470 2097.490 -22.290 2098.670 ; + RECT -23.470 1919.090 -22.290 1920.270 ; + RECT -23.470 1917.490 -22.290 1918.670 ; + RECT -23.470 1739.090 -22.290 1740.270 ; + RECT -23.470 1737.490 -22.290 1738.670 ; + RECT -23.470 1559.090 -22.290 1560.270 ; + RECT -23.470 1557.490 -22.290 1558.670 ; + RECT -23.470 1379.090 -22.290 1380.270 ; + RECT -23.470 1377.490 -22.290 1378.670 ; + RECT -23.470 1199.090 -22.290 1200.270 ; + RECT -23.470 1197.490 -22.290 1198.670 ; + RECT -23.470 1019.090 -22.290 1020.270 ; + RECT -23.470 1017.490 -22.290 1018.670 ; + RECT -23.470 839.090 -22.290 840.270 ; + RECT -23.470 837.490 -22.290 838.670 ; + RECT -23.470 659.090 -22.290 660.270 ; + RECT -23.470 657.490 -22.290 658.670 ; + RECT -23.470 479.090 -22.290 480.270 ; + RECT -23.470 477.490 -22.290 478.670 ; + RECT -23.470 299.090 -22.290 300.270 ; + RECT -23.470 297.490 -22.290 298.670 ; + RECT -23.470 119.090 -22.290 120.270 ; + RECT -23.470 117.490 -22.290 118.670 ; + RECT -13.870 3527.810 -12.690 3528.990 ; + RECT -13.870 3526.210 -12.690 3527.390 ; + RECT -13.870 3341.090 -12.690 3342.270 ; + RECT -13.870 3339.490 -12.690 3340.670 ; + RECT -13.870 3161.090 -12.690 3162.270 ; + RECT -13.870 3159.490 -12.690 3160.670 ; + RECT -13.870 2981.090 -12.690 2982.270 ; + RECT -13.870 2979.490 -12.690 2980.670 ; + RECT -13.870 2801.090 -12.690 2802.270 ; + RECT -13.870 2799.490 -12.690 2800.670 ; + RECT -13.870 2621.090 -12.690 2622.270 ; + RECT -13.870 2619.490 -12.690 2620.670 ; + RECT -13.870 2441.090 -12.690 2442.270 ; + RECT -13.870 2439.490 -12.690 2440.670 ; + RECT -13.870 2261.090 -12.690 2262.270 ; + RECT -13.870 2259.490 -12.690 2260.670 ; + RECT -13.870 2081.090 -12.690 2082.270 ; + RECT -13.870 2079.490 -12.690 2080.670 ; + RECT -13.870 1901.090 -12.690 1902.270 ; + RECT -13.870 1899.490 -12.690 1900.670 ; + RECT -13.870 1721.090 -12.690 1722.270 ; + RECT -13.870 1719.490 -12.690 1720.670 ; + RECT -13.870 1541.090 -12.690 1542.270 ; + RECT -13.870 1539.490 -12.690 1540.670 ; + RECT -13.870 1361.090 -12.690 1362.270 ; + RECT -13.870 1359.490 -12.690 1360.670 ; + RECT -13.870 1181.090 -12.690 1182.270 ; + RECT -13.870 1179.490 -12.690 1180.670 ; + RECT -13.870 1001.090 -12.690 1002.270 ; + RECT -13.870 999.490 -12.690 1000.670 ; + RECT -13.870 821.090 -12.690 822.270 ; + RECT -13.870 819.490 -12.690 820.670 ; + RECT -13.870 641.090 -12.690 642.270 ; + RECT -13.870 639.490 -12.690 640.670 ; + RECT -13.870 461.090 -12.690 462.270 ; + RECT -13.870 459.490 -12.690 460.670 ; + RECT -13.870 281.090 -12.690 282.270 ; + RECT -13.870 279.490 -12.690 280.670 ; + RECT -13.870 101.090 -12.690 102.270 ; + RECT -13.870 99.490 -12.690 100.670 ; + RECT -13.870 -7.710 -12.690 -6.530 ; + RECT -13.870 -9.310 -12.690 -8.130 ; + RECT 94.930 3527.810 96.110 3528.990 ; + RECT 94.930 3526.210 96.110 3527.390 ; + RECT 94.930 3341.090 96.110 3342.270 ; + RECT 94.930 3339.490 96.110 3340.670 ; + RECT 94.930 3161.090 96.110 3162.270 ; + RECT 94.930 3159.490 96.110 3160.670 ; + RECT 94.930 2981.090 96.110 2982.270 ; + RECT 94.930 2979.490 96.110 2980.670 ; + RECT 94.930 2801.090 96.110 2802.270 ; + RECT 94.930 2799.490 96.110 2800.670 ; + RECT 94.930 2621.090 96.110 2622.270 ; + RECT 94.930 2619.490 96.110 2620.670 ; + RECT 94.930 2441.090 96.110 2442.270 ; + RECT 94.930 2439.490 96.110 2440.670 ; + RECT 94.930 2261.090 96.110 2262.270 ; + RECT 94.930 2259.490 96.110 2260.670 ; + RECT 94.930 2081.090 96.110 2082.270 ; + RECT 94.930 2079.490 96.110 2080.670 ; + RECT 94.930 1901.090 96.110 1902.270 ; + RECT 94.930 1899.490 96.110 1900.670 ; + RECT 94.930 1721.090 96.110 1722.270 ; + RECT 94.930 1719.490 96.110 1720.670 ; + RECT 94.930 1541.090 96.110 1542.270 ; + RECT 94.930 1539.490 96.110 1540.670 ; + RECT 94.930 1361.090 96.110 1362.270 ; + RECT 94.930 1359.490 96.110 1360.670 ; + RECT 94.930 1181.090 96.110 1182.270 ; + RECT 94.930 1179.490 96.110 1180.670 ; + RECT 94.930 1001.090 96.110 1002.270 ; + RECT 94.930 999.490 96.110 1000.670 ; + RECT 94.930 821.090 96.110 822.270 ; + RECT 94.930 819.490 96.110 820.670 ; + RECT 94.930 641.090 96.110 642.270 ; + RECT 94.930 639.490 96.110 640.670 ; + RECT 94.930 461.090 96.110 462.270 ; + RECT 94.930 459.490 96.110 460.670 ; + RECT 94.930 281.090 96.110 282.270 ; + RECT 94.930 279.490 96.110 280.670 ; + RECT 94.930 101.090 96.110 102.270 ; + RECT 94.930 99.490 96.110 100.670 ; + RECT 94.930 -7.710 96.110 -6.530 ; + RECT 94.930 -9.310 96.110 -8.130 ; + RECT 292.930 3537.410 294.110 3538.590 ; + RECT 292.930 3535.810 294.110 3536.990 ; + RECT 112.930 3359.090 114.110 3360.270 ; + RECT 112.930 3357.490 114.110 3358.670 ; + RECT 112.930 3179.090 114.110 3180.270 ; + RECT 112.930 3177.490 114.110 3178.670 ; + RECT 112.930 2999.090 114.110 3000.270 ; + RECT 112.930 2997.490 114.110 2998.670 ; + RECT 112.930 2819.090 114.110 2820.270 ; + RECT 112.930 2817.490 114.110 2818.670 ; + RECT 112.930 2639.090 114.110 2640.270 ; + RECT 112.930 2637.490 114.110 2638.670 ; + RECT 112.930 2459.090 114.110 2460.270 ; + RECT 112.930 2457.490 114.110 2458.670 ; + RECT 112.930 2279.090 114.110 2280.270 ; + RECT 112.930 2277.490 114.110 2278.670 ; + RECT 112.930 2099.090 114.110 2100.270 ; + RECT 112.930 2097.490 114.110 2098.670 ; + RECT 112.930 1919.090 114.110 1920.270 ; + RECT 112.930 1917.490 114.110 1918.670 ; + RECT 112.930 1739.090 114.110 1740.270 ; + RECT 112.930 1737.490 114.110 1738.670 ; + RECT 112.930 1559.090 114.110 1560.270 ; + RECT 112.930 1557.490 114.110 1558.670 ; + RECT 112.930 1379.090 114.110 1380.270 ; + RECT 112.930 1377.490 114.110 1378.670 ; + RECT 112.930 1199.090 114.110 1200.270 ; + RECT 112.930 1197.490 114.110 1198.670 ; + RECT 112.930 1019.090 114.110 1020.270 ; + RECT 112.930 1017.490 114.110 1018.670 ; + RECT 112.930 839.090 114.110 840.270 ; + RECT 112.930 837.490 114.110 838.670 ; + RECT 112.930 659.090 114.110 660.270 ; + RECT 112.930 657.490 114.110 658.670 ; + RECT 112.930 479.090 114.110 480.270 ; + RECT 112.930 477.490 114.110 478.670 ; + RECT 112.930 299.090 114.110 300.270 ; + RECT 112.930 297.490 114.110 298.670 ; + RECT 112.930 119.090 114.110 120.270 ; + RECT 112.930 117.490 114.110 118.670 ; + RECT -23.470 -17.310 -22.290 -16.130 ; + RECT -23.470 -18.910 -22.290 -17.730 ; + RECT 274.930 3527.810 276.110 3528.990 ; + RECT 274.930 3526.210 276.110 3527.390 ; + RECT 274.930 3341.090 276.110 3342.270 ; + RECT 274.930 3339.490 276.110 3340.670 ; + RECT 274.930 3161.090 276.110 3162.270 ; + RECT 274.930 3159.490 276.110 3160.670 ; + RECT 274.930 2981.090 276.110 2982.270 ; + RECT 274.930 2979.490 276.110 2980.670 ; + RECT 274.930 2801.090 276.110 2802.270 ; + RECT 274.930 2799.490 276.110 2800.670 ; + RECT 274.930 2621.090 276.110 2622.270 ; + RECT 274.930 2619.490 276.110 2620.670 ; + RECT 274.930 2441.090 276.110 2442.270 ; + RECT 274.930 2439.490 276.110 2440.670 ; + RECT 274.930 2261.090 276.110 2262.270 ; + RECT 274.930 2259.490 276.110 2260.670 ; + RECT 274.930 2081.090 276.110 2082.270 ; + RECT 274.930 2079.490 276.110 2080.670 ; + RECT 274.930 1901.090 276.110 1902.270 ; + RECT 274.930 1899.490 276.110 1900.670 ; + RECT 274.930 1721.090 276.110 1722.270 ; + RECT 274.930 1719.490 276.110 1720.670 ; + RECT 274.930 1541.090 276.110 1542.270 ; + RECT 274.930 1539.490 276.110 1540.670 ; + RECT 274.930 1361.090 276.110 1362.270 ; + RECT 274.930 1359.490 276.110 1360.670 ; + RECT 274.930 1181.090 276.110 1182.270 ; + RECT 274.930 1179.490 276.110 1180.670 ; + RECT 274.930 1001.090 276.110 1002.270 ; + RECT 274.930 999.490 276.110 1000.670 ; + RECT 274.930 821.090 276.110 822.270 ; + RECT 274.930 819.490 276.110 820.670 ; + RECT 274.930 641.090 276.110 642.270 ; + RECT 274.930 639.490 276.110 640.670 ; + RECT 274.930 461.090 276.110 462.270 ; + RECT 274.930 459.490 276.110 460.670 ; + RECT 274.930 281.090 276.110 282.270 ; + RECT 274.930 279.490 276.110 280.670 ; + RECT 274.930 101.090 276.110 102.270 ; + RECT 274.930 99.490 276.110 100.670 ; + RECT 274.930 -7.710 276.110 -6.530 ; + RECT 274.930 -9.310 276.110 -8.130 ; + RECT 472.930 3537.410 474.110 3538.590 ; + RECT 472.930 3535.810 474.110 3536.990 ; + RECT 292.930 3359.090 294.110 3360.270 ; + RECT 292.930 3357.490 294.110 3358.670 ; + RECT 454.930 3527.810 456.110 3528.990 ; + RECT 454.930 3526.210 456.110 3527.390 ; + RECT 454.930 3341.090 456.110 3342.270 ; + RECT 454.930 3339.490 456.110 3340.670 ; + RECT 652.930 3537.410 654.110 3538.590 ; + RECT 652.930 3535.810 654.110 3536.990 ; + RECT 472.930 3359.090 474.110 3360.270 ; + RECT 472.930 3357.490 474.110 3358.670 ; + RECT 634.930 3527.810 636.110 3528.990 ; + RECT 634.930 3526.210 636.110 3527.390 ; + RECT 634.930 3341.090 636.110 3342.270 ; + RECT 634.930 3339.490 636.110 3340.670 ; + RECT 832.930 3537.410 834.110 3538.590 ; + RECT 832.930 3535.810 834.110 3536.990 ; + RECT 652.930 3359.090 654.110 3360.270 ; + RECT 652.930 3357.490 654.110 3358.670 ; + RECT 814.930 3527.810 816.110 3528.990 ; + RECT 814.930 3526.210 816.110 3527.390 ; + RECT 814.930 3341.090 816.110 3342.270 ; + RECT 814.930 3339.490 816.110 3340.670 ; + RECT 1012.930 3537.410 1014.110 3538.590 ; + RECT 1012.930 3535.810 1014.110 3536.990 ; + RECT 832.930 3359.090 834.110 3360.270 ; + RECT 832.930 3357.490 834.110 3358.670 ; + RECT 994.930 3527.810 996.110 3528.990 ; + RECT 994.930 3526.210 996.110 3527.390 ; + RECT 994.930 3341.090 996.110 3342.270 ; + RECT 994.930 3339.490 996.110 3340.670 ; + RECT 1192.930 3537.410 1194.110 3538.590 ; + RECT 1192.930 3535.810 1194.110 3536.990 ; + RECT 1012.930 3359.090 1014.110 3360.270 ; + RECT 1012.930 3357.490 1014.110 3358.670 ; + RECT 1174.930 3527.810 1176.110 3528.990 ; + RECT 1174.930 3526.210 1176.110 3527.390 ; + RECT 1174.930 3341.090 1176.110 3342.270 ; + RECT 1174.930 3339.490 1176.110 3340.670 ; + RECT 1372.930 3537.410 1374.110 3538.590 ; + RECT 1372.930 3535.810 1374.110 3536.990 ; + RECT 1192.930 3359.090 1194.110 3360.270 ; + RECT 1192.930 3357.490 1194.110 3358.670 ; + RECT 1354.930 3527.810 1356.110 3528.990 ; + RECT 1354.930 3526.210 1356.110 3527.390 ; + RECT 1354.930 3341.090 1356.110 3342.270 ; + RECT 1354.930 3339.490 1356.110 3340.670 ; + RECT 1552.930 3537.410 1554.110 3538.590 ; + RECT 1552.930 3535.810 1554.110 3536.990 ; + RECT 1372.930 3359.090 1374.110 3360.270 ; + RECT 1372.930 3357.490 1374.110 3358.670 ; + RECT 1534.930 3527.810 1536.110 3528.990 ; + RECT 1534.930 3526.210 1536.110 3527.390 ; + RECT 1534.930 3341.090 1536.110 3342.270 ; + RECT 1534.930 3339.490 1536.110 3340.670 ; + RECT 1732.930 3537.410 1734.110 3538.590 ; + RECT 1732.930 3535.810 1734.110 3536.990 ; + RECT 1552.930 3359.090 1554.110 3360.270 ; + RECT 1552.930 3357.490 1554.110 3358.670 ; + RECT 1714.930 3527.810 1716.110 3528.990 ; + RECT 1714.930 3526.210 1716.110 3527.390 ; + RECT 1714.930 3341.090 1716.110 3342.270 ; + RECT 1714.930 3339.490 1716.110 3340.670 ; + RECT 1912.930 3537.410 1914.110 3538.590 ; + RECT 1912.930 3535.810 1914.110 3536.990 ; + RECT 1732.930 3359.090 1734.110 3360.270 ; + RECT 1732.930 3357.490 1734.110 3358.670 ; + RECT 1894.930 3527.810 1896.110 3528.990 ; + RECT 1894.930 3526.210 1896.110 3527.390 ; + RECT 1894.930 3341.090 1896.110 3342.270 ; + RECT 1894.930 3339.490 1896.110 3340.670 ; + RECT 2092.930 3537.410 2094.110 3538.590 ; + RECT 2092.930 3535.810 2094.110 3536.990 ; + RECT 1912.930 3359.090 1914.110 3360.270 ; + RECT 1912.930 3357.490 1914.110 3358.670 ; + RECT 2074.930 3527.810 2076.110 3528.990 ; + RECT 2074.930 3526.210 2076.110 3527.390 ; + RECT 2074.930 3341.090 2076.110 3342.270 ; + RECT 2074.930 3339.490 2076.110 3340.670 ; + RECT 2272.930 3537.410 2274.110 3538.590 ; + RECT 2272.930 3535.810 2274.110 3536.990 ; + RECT 2092.930 3359.090 2094.110 3360.270 ; + RECT 2092.930 3357.490 2094.110 3358.670 ; + RECT 2254.930 3527.810 2256.110 3528.990 ; + RECT 2254.930 3526.210 2256.110 3527.390 ; + RECT 2254.930 3341.090 2256.110 3342.270 ; + RECT 2254.930 3339.490 2256.110 3340.670 ; + RECT 2452.930 3537.410 2454.110 3538.590 ; + RECT 2452.930 3535.810 2454.110 3536.990 ; + RECT 2272.930 3359.090 2274.110 3360.270 ; + RECT 2272.930 3357.490 2274.110 3358.670 ; + RECT 2434.930 3527.810 2436.110 3528.990 ; + RECT 2434.930 3526.210 2436.110 3527.390 ; + RECT 2434.930 3341.090 2436.110 3342.270 ; + RECT 2434.930 3339.490 2436.110 3340.670 ; + RECT 2632.930 3537.410 2634.110 3538.590 ; + RECT 2632.930 3535.810 2634.110 3536.990 ; + RECT 2452.930 3359.090 2454.110 3360.270 ; + RECT 2452.930 3357.490 2454.110 3358.670 ; + RECT 2614.930 3527.810 2616.110 3528.990 ; + RECT 2614.930 3526.210 2616.110 3527.390 ; + RECT 2614.930 3341.090 2616.110 3342.270 ; + RECT 2614.930 3339.490 2616.110 3340.670 ; + RECT 292.930 3179.090 294.110 3180.270 ; + RECT 292.930 3177.490 294.110 3178.670 ; + RECT 292.930 2999.090 294.110 3000.270 ; + RECT 292.930 2997.490 294.110 2998.670 ; + RECT 292.930 2819.090 294.110 2820.270 ; + RECT 292.930 2817.490 294.110 2818.670 ; + RECT 292.930 2639.090 294.110 2640.270 ; + RECT 292.930 2637.490 294.110 2638.670 ; + RECT 292.930 2459.090 294.110 2460.270 ; + RECT 292.930 2457.490 294.110 2458.670 ; + RECT 292.930 2279.090 294.110 2280.270 ; + RECT 292.930 2277.490 294.110 2278.670 ; + RECT 292.930 2099.090 294.110 2100.270 ; + RECT 292.930 2097.490 294.110 2098.670 ; + RECT 292.930 1919.090 294.110 1920.270 ; + RECT 292.930 1917.490 294.110 1918.670 ; + RECT 292.930 1739.090 294.110 1740.270 ; + RECT 292.930 1737.490 294.110 1738.670 ; + RECT 292.930 1559.090 294.110 1560.270 ; + RECT 292.930 1557.490 294.110 1558.670 ; + RECT 292.930 1379.090 294.110 1380.270 ; + RECT 292.930 1377.490 294.110 1378.670 ; + RECT 292.930 1199.090 294.110 1200.270 ; + RECT 292.930 1197.490 294.110 1198.670 ; + RECT 292.930 1019.090 294.110 1020.270 ; + RECT 292.930 1017.490 294.110 1018.670 ; + RECT 292.930 839.090 294.110 840.270 ; + RECT 292.930 837.490 294.110 838.670 ; + RECT 292.930 659.090 294.110 660.270 ; + RECT 292.930 657.490 294.110 658.670 ; + RECT 292.930 479.090 294.110 480.270 ; + RECT 292.930 477.490 294.110 478.670 ; + RECT 292.930 299.090 294.110 300.270 ; + RECT 292.930 297.490 294.110 298.670 ; + RECT 408.050 3179.090 409.230 3180.270 ; + RECT 408.050 3177.490 409.230 3178.670 ; + RECT 408.050 3161.090 409.230 3162.270 ; + RECT 408.050 3159.490 409.230 3160.670 ; + RECT 408.050 2999.090 409.230 3000.270 ; + RECT 408.050 2997.490 409.230 2998.670 ; + RECT 408.050 2981.090 409.230 2982.270 ; + RECT 408.050 2979.490 409.230 2980.670 ; + RECT 408.050 2819.090 409.230 2820.270 ; + RECT 408.050 2817.490 409.230 2818.670 ; + RECT 408.050 2801.090 409.230 2802.270 ; + RECT 408.050 2799.490 409.230 2800.670 ; + RECT 408.050 2639.090 409.230 2640.270 ; + RECT 408.050 2637.490 409.230 2638.670 ; + RECT 408.050 2621.090 409.230 2622.270 ; + RECT 408.050 2619.490 409.230 2620.670 ; + RECT 408.050 2459.090 409.230 2460.270 ; + RECT 408.050 2457.490 409.230 2458.670 ; + RECT 408.050 2441.090 409.230 2442.270 ; + RECT 408.050 2439.490 409.230 2440.670 ; + RECT 408.050 2279.090 409.230 2280.270 ; + RECT 408.050 2277.490 409.230 2278.670 ; + RECT 408.050 2261.090 409.230 2262.270 ; + RECT 408.050 2259.490 409.230 2260.670 ; + RECT 408.050 2099.090 409.230 2100.270 ; + RECT 408.050 2097.490 409.230 2098.670 ; + RECT 408.050 2081.090 409.230 2082.270 ; + RECT 408.050 2079.490 409.230 2080.670 ; + RECT 408.050 1919.090 409.230 1920.270 ; + RECT 408.050 1917.490 409.230 1918.670 ; + RECT 408.050 1901.090 409.230 1902.270 ; + RECT 408.050 1899.490 409.230 1900.670 ; + RECT 408.050 1739.090 409.230 1740.270 ; + RECT 408.050 1737.490 409.230 1738.670 ; + RECT 408.050 1721.090 409.230 1722.270 ; + RECT 408.050 1719.490 409.230 1720.670 ; + RECT 408.050 1559.090 409.230 1560.270 ; + RECT 408.050 1557.490 409.230 1558.670 ; + RECT 408.050 1541.090 409.230 1542.270 ; + RECT 408.050 1539.490 409.230 1540.670 ; + RECT 408.050 1379.090 409.230 1380.270 ; + RECT 408.050 1377.490 409.230 1378.670 ; + RECT 408.050 1361.090 409.230 1362.270 ; + RECT 408.050 1359.490 409.230 1360.670 ; + RECT 408.050 1199.090 409.230 1200.270 ; + RECT 408.050 1197.490 409.230 1198.670 ; + RECT 408.050 1181.090 409.230 1182.270 ; + RECT 408.050 1179.490 409.230 1180.670 ; + RECT 408.050 1019.090 409.230 1020.270 ; + RECT 408.050 1017.490 409.230 1018.670 ; + RECT 408.050 1001.090 409.230 1002.270 ; + RECT 408.050 999.490 409.230 1000.670 ; + RECT 408.050 839.090 409.230 840.270 ; + RECT 408.050 837.490 409.230 838.670 ; + RECT 408.050 821.090 409.230 822.270 ; + RECT 408.050 819.490 409.230 820.670 ; + RECT 408.050 659.090 409.230 660.270 ; + RECT 408.050 657.490 409.230 658.670 ; + RECT 408.050 641.090 409.230 642.270 ; + RECT 408.050 639.490 409.230 640.670 ; + RECT 408.050 479.090 409.230 480.270 ; + RECT 408.050 477.490 409.230 478.670 ; + RECT 408.050 461.090 409.230 462.270 ; + RECT 408.050 459.490 409.230 460.670 ; + RECT 408.050 299.090 409.230 300.270 ; + RECT 408.050 297.490 409.230 298.670 ; + RECT 408.050 281.090 409.230 282.270 ; + RECT 408.050 279.490 409.230 280.670 ; + RECT 2614.930 3161.090 2616.110 3162.270 ; + RECT 2614.930 3159.490 2616.110 3160.670 ; + RECT 2614.930 2981.090 2616.110 2982.270 ; + RECT 2614.930 2979.490 2616.110 2980.670 ; + RECT 2614.930 2801.090 2616.110 2802.270 ; + RECT 2614.930 2799.490 2616.110 2800.670 ; + RECT 2614.930 2621.090 2616.110 2622.270 ; + RECT 2614.930 2619.490 2616.110 2620.670 ; + RECT 2614.930 2441.090 2616.110 2442.270 ; + RECT 2614.930 2439.490 2616.110 2440.670 ; + RECT 2614.930 2261.090 2616.110 2262.270 ; + RECT 2614.930 2259.490 2616.110 2260.670 ; + RECT 2614.930 2081.090 2616.110 2082.270 ; + RECT 2614.930 2079.490 2616.110 2080.670 ; + RECT 2614.930 1901.090 2616.110 1902.270 ; + RECT 2614.930 1899.490 2616.110 1900.670 ; + RECT 2614.930 1721.090 2616.110 1722.270 ; + RECT 2614.930 1719.490 2616.110 1720.670 ; + RECT 2614.930 1541.090 2616.110 1542.270 ; + RECT 2614.930 1539.490 2616.110 1540.670 ; + RECT 2614.930 1361.090 2616.110 1362.270 ; + RECT 2614.930 1359.490 2616.110 1360.670 ; + RECT 2614.930 1181.090 2616.110 1182.270 ; + RECT 2614.930 1179.490 2616.110 1180.670 ; + RECT 2614.930 1001.090 2616.110 1002.270 ; + RECT 2614.930 999.490 2616.110 1000.670 ; + RECT 2614.930 821.090 2616.110 822.270 ; + RECT 2614.930 819.490 2616.110 820.670 ; + RECT 2614.930 641.090 2616.110 642.270 ; + RECT 2614.930 639.490 2616.110 640.670 ; + RECT 2614.930 461.090 2616.110 462.270 ; + RECT 2614.930 459.490 2616.110 460.670 ; + RECT 2614.930 281.090 2616.110 282.270 ; + RECT 2614.930 279.490 2616.110 280.670 ; + RECT 292.930 119.090 294.110 120.270 ; + RECT 292.930 117.490 294.110 118.670 ; + RECT 112.930 -17.310 114.110 -16.130 ; + RECT 112.930 -18.910 114.110 -17.730 ; + RECT 454.930 101.090 456.110 102.270 ; + RECT 454.930 99.490 456.110 100.670 ; + RECT 454.930 -7.710 456.110 -6.530 ; + RECT 454.930 -9.310 456.110 -8.130 ; + RECT 472.930 119.090 474.110 120.270 ; + RECT 472.930 117.490 474.110 118.670 ; + RECT 292.930 -17.310 294.110 -16.130 ; + RECT 292.930 -18.910 294.110 -17.730 ; + RECT 634.930 101.090 636.110 102.270 ; + RECT 634.930 99.490 636.110 100.670 ; + RECT 634.930 -7.710 636.110 -6.530 ; + RECT 634.930 -9.310 636.110 -8.130 ; + RECT 652.930 119.090 654.110 120.270 ; + RECT 652.930 117.490 654.110 118.670 ; + RECT 472.930 -17.310 474.110 -16.130 ; + RECT 472.930 -18.910 474.110 -17.730 ; + RECT 814.930 101.090 816.110 102.270 ; + RECT 814.930 99.490 816.110 100.670 ; + RECT 814.930 -7.710 816.110 -6.530 ; + RECT 814.930 -9.310 816.110 -8.130 ; + RECT 832.930 119.090 834.110 120.270 ; + RECT 832.930 117.490 834.110 118.670 ; + RECT 652.930 -17.310 654.110 -16.130 ; + RECT 652.930 -18.910 654.110 -17.730 ; + RECT 994.930 101.090 996.110 102.270 ; + RECT 994.930 99.490 996.110 100.670 ; + RECT 994.930 -7.710 996.110 -6.530 ; + RECT 994.930 -9.310 996.110 -8.130 ; + RECT 1012.930 119.090 1014.110 120.270 ; + RECT 1012.930 117.490 1014.110 118.670 ; + RECT 832.930 -17.310 834.110 -16.130 ; + RECT 832.930 -18.910 834.110 -17.730 ; + RECT 1174.930 101.090 1176.110 102.270 ; + RECT 1174.930 99.490 1176.110 100.670 ; + RECT 1174.930 -7.710 1176.110 -6.530 ; + RECT 1174.930 -9.310 1176.110 -8.130 ; + RECT 1192.930 119.090 1194.110 120.270 ; + RECT 1192.930 117.490 1194.110 118.670 ; + RECT 1012.930 -17.310 1014.110 -16.130 ; + RECT 1012.930 -18.910 1014.110 -17.730 ; + RECT 1354.930 101.090 1356.110 102.270 ; + RECT 1354.930 99.490 1356.110 100.670 ; + RECT 1354.930 -7.710 1356.110 -6.530 ; + RECT 1354.930 -9.310 1356.110 -8.130 ; + RECT 1372.930 119.090 1374.110 120.270 ; + RECT 1372.930 117.490 1374.110 118.670 ; + RECT 1192.930 -17.310 1194.110 -16.130 ; + RECT 1192.930 -18.910 1194.110 -17.730 ; + RECT 1534.930 101.090 1536.110 102.270 ; + RECT 1534.930 99.490 1536.110 100.670 ; + RECT 1534.930 -7.710 1536.110 -6.530 ; + RECT 1534.930 -9.310 1536.110 -8.130 ; + RECT 1552.930 119.090 1554.110 120.270 ; + RECT 1552.930 117.490 1554.110 118.670 ; + RECT 1372.930 -17.310 1374.110 -16.130 ; + RECT 1372.930 -18.910 1374.110 -17.730 ; + RECT 1714.930 101.090 1716.110 102.270 ; + RECT 1714.930 99.490 1716.110 100.670 ; + RECT 1714.930 -7.710 1716.110 -6.530 ; + RECT 1714.930 -9.310 1716.110 -8.130 ; + RECT 1732.930 119.090 1734.110 120.270 ; + RECT 1732.930 117.490 1734.110 118.670 ; + RECT 1552.930 -17.310 1554.110 -16.130 ; + RECT 1552.930 -18.910 1554.110 -17.730 ; + RECT 1894.930 101.090 1896.110 102.270 ; + RECT 1894.930 99.490 1896.110 100.670 ; + RECT 1894.930 -7.710 1896.110 -6.530 ; + RECT 1894.930 -9.310 1896.110 -8.130 ; + RECT 1912.930 119.090 1914.110 120.270 ; + RECT 1912.930 117.490 1914.110 118.670 ; + RECT 1732.930 -17.310 1734.110 -16.130 ; + RECT 1732.930 -18.910 1734.110 -17.730 ; + RECT 2074.930 101.090 2076.110 102.270 ; + RECT 2074.930 99.490 2076.110 100.670 ; + RECT 2074.930 -7.710 2076.110 -6.530 ; + RECT 2074.930 -9.310 2076.110 -8.130 ; + RECT 2092.930 119.090 2094.110 120.270 ; + RECT 2092.930 117.490 2094.110 118.670 ; + RECT 1912.930 -17.310 1914.110 -16.130 ; + RECT 1912.930 -18.910 1914.110 -17.730 ; + RECT 2254.930 101.090 2256.110 102.270 ; + RECT 2254.930 99.490 2256.110 100.670 ; + RECT 2254.930 -7.710 2256.110 -6.530 ; + RECT 2254.930 -9.310 2256.110 -8.130 ; + RECT 2272.930 119.090 2274.110 120.270 ; + RECT 2272.930 117.490 2274.110 118.670 ; + RECT 2092.930 -17.310 2094.110 -16.130 ; + RECT 2092.930 -18.910 2094.110 -17.730 ; + RECT 2434.930 101.090 2436.110 102.270 ; + RECT 2434.930 99.490 2436.110 100.670 ; + RECT 2434.930 -7.710 2436.110 -6.530 ; + RECT 2434.930 -9.310 2436.110 -8.130 ; + RECT 2452.930 119.090 2454.110 120.270 ; + RECT 2452.930 117.490 2454.110 118.670 ; + RECT 2272.930 -17.310 2274.110 -16.130 ; + RECT 2272.930 -18.910 2274.110 -17.730 ; + RECT 2614.930 101.090 2616.110 102.270 ; + RECT 2614.930 99.490 2616.110 100.670 ; + RECT 2614.930 -7.710 2616.110 -6.530 ; + RECT 2614.930 -9.310 2616.110 -8.130 ; + RECT 2812.930 3537.410 2814.110 3538.590 ; + RECT 2812.930 3535.810 2814.110 3536.990 ; + RECT 2632.930 3359.090 2634.110 3360.270 ; + RECT 2632.930 3357.490 2634.110 3358.670 ; + RECT 2632.930 3179.090 2634.110 3180.270 ; + RECT 2632.930 3177.490 2634.110 3178.670 ; + RECT 2632.930 2999.090 2634.110 3000.270 ; + RECT 2632.930 2997.490 2634.110 2998.670 ; + RECT 2632.930 2819.090 2634.110 2820.270 ; + RECT 2632.930 2817.490 2634.110 2818.670 ; + RECT 2632.930 2639.090 2634.110 2640.270 ; + RECT 2632.930 2637.490 2634.110 2638.670 ; + RECT 2632.930 2459.090 2634.110 2460.270 ; + RECT 2632.930 2457.490 2634.110 2458.670 ; + RECT 2632.930 2279.090 2634.110 2280.270 ; + RECT 2632.930 2277.490 2634.110 2278.670 ; + RECT 2632.930 2099.090 2634.110 2100.270 ; + RECT 2632.930 2097.490 2634.110 2098.670 ; + RECT 2632.930 1919.090 2634.110 1920.270 ; + RECT 2632.930 1917.490 2634.110 1918.670 ; + RECT 2632.930 1739.090 2634.110 1740.270 ; + RECT 2632.930 1737.490 2634.110 1738.670 ; + RECT 2632.930 1559.090 2634.110 1560.270 ; + RECT 2632.930 1557.490 2634.110 1558.670 ; + RECT 2632.930 1379.090 2634.110 1380.270 ; + RECT 2632.930 1377.490 2634.110 1378.670 ; + RECT 2632.930 1199.090 2634.110 1200.270 ; + RECT 2632.930 1197.490 2634.110 1198.670 ; + RECT 2632.930 1019.090 2634.110 1020.270 ; + RECT 2632.930 1017.490 2634.110 1018.670 ; + RECT 2632.930 839.090 2634.110 840.270 ; + RECT 2632.930 837.490 2634.110 838.670 ; + RECT 2632.930 659.090 2634.110 660.270 ; + RECT 2632.930 657.490 2634.110 658.670 ; + RECT 2632.930 479.090 2634.110 480.270 ; + RECT 2632.930 477.490 2634.110 478.670 ; + RECT 2632.930 299.090 2634.110 300.270 ; + RECT 2632.930 297.490 2634.110 298.670 ; + RECT 2632.930 119.090 2634.110 120.270 ; + RECT 2632.930 117.490 2634.110 118.670 ; + RECT 2452.930 -17.310 2454.110 -16.130 ; + RECT 2452.930 -18.910 2454.110 -17.730 ; + RECT 2794.930 3527.810 2796.110 3528.990 ; + RECT 2794.930 3526.210 2796.110 3527.390 ; + RECT 2794.930 3341.090 2796.110 3342.270 ; + RECT 2794.930 3339.490 2796.110 3340.670 ; + RECT 2794.930 3161.090 2796.110 3162.270 ; + RECT 2794.930 3159.490 2796.110 3160.670 ; + RECT 2794.930 2981.090 2796.110 2982.270 ; + RECT 2794.930 2979.490 2796.110 2980.670 ; + RECT 2794.930 2801.090 2796.110 2802.270 ; + RECT 2794.930 2799.490 2796.110 2800.670 ; + RECT 2794.930 2621.090 2796.110 2622.270 ; + RECT 2794.930 2619.490 2796.110 2620.670 ; + RECT 2794.930 2441.090 2796.110 2442.270 ; + RECT 2794.930 2439.490 2796.110 2440.670 ; + RECT 2794.930 2261.090 2796.110 2262.270 ; + RECT 2794.930 2259.490 2796.110 2260.670 ; + RECT 2794.930 2081.090 2796.110 2082.270 ; + RECT 2794.930 2079.490 2796.110 2080.670 ; + RECT 2794.930 1901.090 2796.110 1902.270 ; + RECT 2794.930 1899.490 2796.110 1900.670 ; + RECT 2794.930 1721.090 2796.110 1722.270 ; + RECT 2794.930 1719.490 2796.110 1720.670 ; + RECT 2794.930 1541.090 2796.110 1542.270 ; + RECT 2794.930 1539.490 2796.110 1540.670 ; + RECT 2794.930 1361.090 2796.110 1362.270 ; + RECT 2794.930 1359.490 2796.110 1360.670 ; + RECT 2794.930 1181.090 2796.110 1182.270 ; + RECT 2794.930 1179.490 2796.110 1180.670 ; + RECT 2794.930 1001.090 2796.110 1002.270 ; + RECT 2794.930 999.490 2796.110 1000.670 ; + RECT 2794.930 821.090 2796.110 822.270 ; + RECT 2794.930 819.490 2796.110 820.670 ; + RECT 2794.930 641.090 2796.110 642.270 ; + RECT 2794.930 639.490 2796.110 640.670 ; + RECT 2794.930 461.090 2796.110 462.270 ; + RECT 2794.930 459.490 2796.110 460.670 ; + RECT 2794.930 281.090 2796.110 282.270 ; + RECT 2794.930 279.490 2796.110 280.670 ; + RECT 2794.930 101.090 2796.110 102.270 ; + RECT 2794.930 99.490 2796.110 100.670 ; + RECT 2794.930 -7.710 2796.110 -6.530 ; + RECT 2794.930 -9.310 2796.110 -8.130 ; + RECT 2941.910 3537.410 2943.090 3538.590 ; + RECT 2941.910 3535.810 2943.090 3536.990 ; + RECT 2812.930 3359.090 2814.110 3360.270 ; + RECT 2812.930 3357.490 2814.110 3358.670 ; + RECT 2812.930 3179.090 2814.110 3180.270 ; + RECT 2812.930 3177.490 2814.110 3178.670 ; + RECT 2812.930 2999.090 2814.110 3000.270 ; + RECT 2812.930 2997.490 2814.110 2998.670 ; + RECT 2812.930 2819.090 2814.110 2820.270 ; + RECT 2812.930 2817.490 2814.110 2818.670 ; + RECT 2812.930 2639.090 2814.110 2640.270 ; + RECT 2812.930 2637.490 2814.110 2638.670 ; + RECT 2812.930 2459.090 2814.110 2460.270 ; + RECT 2812.930 2457.490 2814.110 2458.670 ; + RECT 2812.930 2279.090 2814.110 2280.270 ; + RECT 2812.930 2277.490 2814.110 2278.670 ; + RECT 2812.930 2099.090 2814.110 2100.270 ; + RECT 2812.930 2097.490 2814.110 2098.670 ; + RECT 2812.930 1919.090 2814.110 1920.270 ; + RECT 2812.930 1917.490 2814.110 1918.670 ; + RECT 2812.930 1739.090 2814.110 1740.270 ; + RECT 2812.930 1737.490 2814.110 1738.670 ; + RECT 2812.930 1559.090 2814.110 1560.270 ; + RECT 2812.930 1557.490 2814.110 1558.670 ; + RECT 2812.930 1379.090 2814.110 1380.270 ; + RECT 2812.930 1377.490 2814.110 1378.670 ; + RECT 2812.930 1199.090 2814.110 1200.270 ; + RECT 2812.930 1197.490 2814.110 1198.670 ; + RECT 2812.930 1019.090 2814.110 1020.270 ; + RECT 2812.930 1017.490 2814.110 1018.670 ; + RECT 2812.930 839.090 2814.110 840.270 ; + RECT 2812.930 837.490 2814.110 838.670 ; + RECT 2812.930 659.090 2814.110 660.270 ; + RECT 2812.930 657.490 2814.110 658.670 ; + RECT 2812.930 479.090 2814.110 480.270 ; + RECT 2812.930 477.490 2814.110 478.670 ; + RECT 2812.930 299.090 2814.110 300.270 ; + RECT 2812.930 297.490 2814.110 298.670 ; + RECT 2812.930 119.090 2814.110 120.270 ; + RECT 2812.930 117.490 2814.110 118.670 ; + RECT 2632.930 -17.310 2634.110 -16.130 ; + RECT 2632.930 -18.910 2634.110 -17.730 ; + RECT 2932.310 3527.810 2933.490 3528.990 ; + RECT 2932.310 3526.210 2933.490 3527.390 ; + RECT 2932.310 3341.090 2933.490 3342.270 ; + RECT 2932.310 3339.490 2933.490 3340.670 ; + RECT 2932.310 3161.090 2933.490 3162.270 ; + RECT 2932.310 3159.490 2933.490 3160.670 ; + RECT 2932.310 2981.090 2933.490 2982.270 ; + RECT 2932.310 2979.490 2933.490 2980.670 ; + RECT 2932.310 2801.090 2933.490 2802.270 ; + RECT 2932.310 2799.490 2933.490 2800.670 ; + RECT 2932.310 2621.090 2933.490 2622.270 ; + RECT 2932.310 2619.490 2933.490 2620.670 ; + RECT 2932.310 2441.090 2933.490 2442.270 ; + RECT 2932.310 2439.490 2933.490 2440.670 ; + RECT 2932.310 2261.090 2933.490 2262.270 ; + RECT 2932.310 2259.490 2933.490 2260.670 ; + RECT 2932.310 2081.090 2933.490 2082.270 ; + RECT 2932.310 2079.490 2933.490 2080.670 ; + RECT 2932.310 1901.090 2933.490 1902.270 ; + RECT 2932.310 1899.490 2933.490 1900.670 ; + RECT 2932.310 1721.090 2933.490 1722.270 ; + RECT 2932.310 1719.490 2933.490 1720.670 ; + RECT 2932.310 1541.090 2933.490 1542.270 ; + RECT 2932.310 1539.490 2933.490 1540.670 ; + RECT 2932.310 1361.090 2933.490 1362.270 ; + RECT 2932.310 1359.490 2933.490 1360.670 ; + RECT 2932.310 1181.090 2933.490 1182.270 ; + RECT 2932.310 1179.490 2933.490 1180.670 ; + RECT 2932.310 1001.090 2933.490 1002.270 ; + RECT 2932.310 999.490 2933.490 1000.670 ; + RECT 2932.310 821.090 2933.490 822.270 ; + RECT 2932.310 819.490 2933.490 820.670 ; + RECT 2932.310 641.090 2933.490 642.270 ; + RECT 2932.310 639.490 2933.490 640.670 ; + RECT 2932.310 461.090 2933.490 462.270 ; + RECT 2932.310 459.490 2933.490 460.670 ; + RECT 2932.310 281.090 2933.490 282.270 ; + RECT 2932.310 279.490 2933.490 280.670 ; + RECT 2932.310 101.090 2933.490 102.270 ; + RECT 2932.310 99.490 2933.490 100.670 ; + RECT 2932.310 -7.710 2933.490 -6.530 ; + RECT 2932.310 -9.310 2933.490 -8.130 ; + RECT 2941.910 3359.090 2943.090 3360.270 ; + RECT 2941.910 3357.490 2943.090 3358.670 ; + RECT 2941.910 3179.090 2943.090 3180.270 ; + RECT 2941.910 3177.490 2943.090 3178.670 ; + RECT 2941.910 2999.090 2943.090 3000.270 ; + RECT 2941.910 2997.490 2943.090 2998.670 ; + RECT 2941.910 2819.090 2943.090 2820.270 ; + RECT 2941.910 2817.490 2943.090 2818.670 ; + RECT 2941.910 2639.090 2943.090 2640.270 ; + RECT 2941.910 2637.490 2943.090 2638.670 ; + RECT 2941.910 2459.090 2943.090 2460.270 ; + RECT 2941.910 2457.490 2943.090 2458.670 ; + RECT 2941.910 2279.090 2943.090 2280.270 ; + RECT 2941.910 2277.490 2943.090 2278.670 ; + RECT 2941.910 2099.090 2943.090 2100.270 ; + RECT 2941.910 2097.490 2943.090 2098.670 ; + RECT 2941.910 1919.090 2943.090 1920.270 ; + RECT 2941.910 1917.490 2943.090 1918.670 ; + RECT 2941.910 1739.090 2943.090 1740.270 ; + RECT 2941.910 1737.490 2943.090 1738.670 ; + RECT 2941.910 1559.090 2943.090 1560.270 ; + RECT 2941.910 1557.490 2943.090 1558.670 ; + RECT 2941.910 1379.090 2943.090 1380.270 ; + RECT 2941.910 1377.490 2943.090 1378.670 ; + RECT 2941.910 1199.090 2943.090 1200.270 ; + RECT 2941.910 1197.490 2943.090 1198.670 ; + RECT 2941.910 1019.090 2943.090 1020.270 ; + RECT 2941.910 1017.490 2943.090 1018.670 ; + RECT 2941.910 839.090 2943.090 840.270 ; + RECT 2941.910 837.490 2943.090 838.670 ; + RECT 2941.910 659.090 2943.090 660.270 ; + RECT 2941.910 657.490 2943.090 658.670 ; + RECT 2941.910 479.090 2943.090 480.270 ; + RECT 2941.910 477.490 2943.090 478.670 ; + RECT 2941.910 299.090 2943.090 300.270 ; + RECT 2941.910 297.490 2943.090 298.670 ; + RECT 2941.910 119.090 2943.090 120.270 ; + RECT 2941.910 117.490 2943.090 118.670 ; + RECT 2812.930 -17.310 2814.110 -16.130 ; + RECT 2812.930 -18.910 2814.110 -17.730 ; + RECT 2941.910 -17.310 2943.090 -16.130 ; + RECT 2941.910 -18.910 2943.090 -17.730 ; + LAYER met5 ; + RECT -24.380 3538.700 -21.380 3538.710 ; + RECT 112.020 3538.700 115.020 3538.710 ; + RECT 292.020 3538.700 295.020 3538.710 ; + RECT 472.020 3538.700 475.020 3538.710 ; + RECT 652.020 3538.700 655.020 3538.710 ; + RECT 832.020 3538.700 835.020 3538.710 ; + RECT 1012.020 3538.700 1015.020 3538.710 ; + RECT 1192.020 3538.700 1195.020 3538.710 ; + RECT 1372.020 3538.700 1375.020 3538.710 ; + RECT 1552.020 3538.700 1555.020 3538.710 ; + RECT 1732.020 3538.700 1735.020 3538.710 ; + RECT 1912.020 3538.700 1915.020 3538.710 ; + RECT 2092.020 3538.700 2095.020 3538.710 ; + RECT 2272.020 3538.700 2275.020 3538.710 ; + RECT 2452.020 3538.700 2455.020 3538.710 ; + RECT 2632.020 3538.700 2635.020 3538.710 ; + RECT 2812.020 3538.700 2815.020 3538.710 ; + RECT 2941.000 3538.700 2944.000 3538.710 ; + RECT -24.380 3535.700 2944.000 3538.700 ; + RECT -24.380 3535.690 -21.380 3535.700 ; + RECT 112.020 3535.690 115.020 3535.700 ; + RECT 292.020 3535.690 295.020 3535.700 ; + RECT 472.020 3535.690 475.020 3535.700 ; + RECT 652.020 3535.690 655.020 3535.700 ; + RECT 832.020 3535.690 835.020 3535.700 ; + RECT 1012.020 3535.690 1015.020 3535.700 ; + RECT 1192.020 3535.690 1195.020 3535.700 ; + RECT 1372.020 3535.690 1375.020 3535.700 ; + RECT 1552.020 3535.690 1555.020 3535.700 ; + RECT 1732.020 3535.690 1735.020 3535.700 ; + RECT 1912.020 3535.690 1915.020 3535.700 ; + RECT 2092.020 3535.690 2095.020 3535.700 ; + RECT 2272.020 3535.690 2275.020 3535.700 ; + RECT 2452.020 3535.690 2455.020 3535.700 ; + RECT 2632.020 3535.690 2635.020 3535.700 ; + RECT 2812.020 3535.690 2815.020 3535.700 ; + RECT 2941.000 3535.690 2944.000 3535.700 ; + RECT -14.780 3529.100 -11.780 3529.110 ; + RECT 94.020 3529.100 97.020 3529.110 ; + RECT 274.020 3529.100 277.020 3529.110 ; + RECT 454.020 3529.100 457.020 3529.110 ; + RECT 634.020 3529.100 637.020 3529.110 ; + RECT 814.020 3529.100 817.020 3529.110 ; + RECT 994.020 3529.100 997.020 3529.110 ; + RECT 1174.020 3529.100 1177.020 3529.110 ; + RECT 1354.020 3529.100 1357.020 3529.110 ; + RECT 1534.020 3529.100 1537.020 3529.110 ; + RECT 1714.020 3529.100 1717.020 3529.110 ; + RECT 1894.020 3529.100 1897.020 3529.110 ; + RECT 2074.020 3529.100 2077.020 3529.110 ; + RECT 2254.020 3529.100 2257.020 3529.110 ; + RECT 2434.020 3529.100 2437.020 3529.110 ; + RECT 2614.020 3529.100 2617.020 3529.110 ; + RECT 2794.020 3529.100 2797.020 3529.110 ; + RECT 2931.400 3529.100 2934.400 3529.110 ; + RECT -14.780 3526.100 2934.400 3529.100 ; + RECT -14.780 3526.090 -11.780 3526.100 ; + RECT 94.020 3526.090 97.020 3526.100 ; + RECT 274.020 3526.090 277.020 3526.100 ; + RECT 454.020 3526.090 457.020 3526.100 ; + RECT 634.020 3526.090 637.020 3526.100 ; + RECT 814.020 3526.090 817.020 3526.100 ; + RECT 994.020 3526.090 997.020 3526.100 ; + RECT 1174.020 3526.090 1177.020 3526.100 ; + RECT 1354.020 3526.090 1357.020 3526.100 ; + RECT 1534.020 3526.090 1537.020 3526.100 ; + RECT 1714.020 3526.090 1717.020 3526.100 ; + RECT 1894.020 3526.090 1897.020 3526.100 ; + RECT 2074.020 3526.090 2077.020 3526.100 ; + RECT 2254.020 3526.090 2257.020 3526.100 ; + RECT 2434.020 3526.090 2437.020 3526.100 ; + RECT 2614.020 3526.090 2617.020 3526.100 ; + RECT 2794.020 3526.090 2797.020 3526.100 ; + RECT 2931.400 3526.090 2934.400 3526.100 ; + RECT -24.380 3360.380 -21.380 3360.390 ; + RECT 112.020 3360.380 115.020 3360.390 ; + RECT 292.020 3360.380 295.020 3360.390 ; + RECT 472.020 3360.380 475.020 3360.390 ; + RECT 652.020 3360.380 655.020 3360.390 ; + RECT 832.020 3360.380 835.020 3360.390 ; + RECT 1012.020 3360.380 1015.020 3360.390 ; + RECT 1192.020 3360.380 1195.020 3360.390 ; + RECT 1372.020 3360.380 1375.020 3360.390 ; + RECT 1552.020 3360.380 1555.020 3360.390 ; + RECT 1732.020 3360.380 1735.020 3360.390 ; + RECT 1912.020 3360.380 1915.020 3360.390 ; + RECT 2092.020 3360.380 2095.020 3360.390 ; + RECT 2272.020 3360.380 2275.020 3360.390 ; + RECT 2452.020 3360.380 2455.020 3360.390 ; + RECT 2632.020 3360.380 2635.020 3360.390 ; + RECT 2812.020 3360.380 2815.020 3360.390 ; + RECT 2941.000 3360.380 2944.000 3360.390 ; + RECT -24.380 3357.380 2944.000 3360.380 ; + RECT -24.380 3357.370 -21.380 3357.380 ; + RECT 112.020 3357.370 115.020 3357.380 ; + RECT 292.020 3357.370 295.020 3357.380 ; + RECT 472.020 3357.370 475.020 3357.380 ; + RECT 652.020 3357.370 655.020 3357.380 ; + RECT 832.020 3357.370 835.020 3357.380 ; + RECT 1012.020 3357.370 1015.020 3357.380 ; + RECT 1192.020 3357.370 1195.020 3357.380 ; + RECT 1372.020 3357.370 1375.020 3357.380 ; + RECT 1552.020 3357.370 1555.020 3357.380 ; + RECT 1732.020 3357.370 1735.020 3357.380 ; + RECT 1912.020 3357.370 1915.020 3357.380 ; + RECT 2092.020 3357.370 2095.020 3357.380 ; + RECT 2272.020 3357.370 2275.020 3357.380 ; + RECT 2452.020 3357.370 2455.020 3357.380 ; + RECT 2632.020 3357.370 2635.020 3357.380 ; + RECT 2812.020 3357.370 2815.020 3357.380 ; + RECT 2941.000 3357.370 2944.000 3357.380 ; + RECT -14.780 3342.380 -11.780 3342.390 ; + RECT 94.020 3342.380 97.020 3342.390 ; + RECT 274.020 3342.380 277.020 3342.390 ; + RECT 454.020 3342.380 457.020 3342.390 ; + RECT 634.020 3342.380 637.020 3342.390 ; + RECT 814.020 3342.380 817.020 3342.390 ; + RECT 994.020 3342.380 997.020 3342.390 ; + RECT 1174.020 3342.380 1177.020 3342.390 ; + RECT 1354.020 3342.380 1357.020 3342.390 ; + RECT 1534.020 3342.380 1537.020 3342.390 ; + RECT 1714.020 3342.380 1717.020 3342.390 ; + RECT 1894.020 3342.380 1897.020 3342.390 ; + RECT 2074.020 3342.380 2077.020 3342.390 ; + RECT 2254.020 3342.380 2257.020 3342.390 ; + RECT 2434.020 3342.380 2437.020 3342.390 ; + RECT 2614.020 3342.380 2617.020 3342.390 ; + RECT 2794.020 3342.380 2797.020 3342.390 ; + RECT 2931.400 3342.380 2934.400 3342.390 ; + RECT -14.780 3339.380 2934.400 3342.380 ; + RECT -14.780 3339.370 -11.780 3339.380 ; + RECT 94.020 3339.370 97.020 3339.380 ; + RECT 274.020 3339.370 277.020 3339.380 ; + RECT 454.020 3339.370 457.020 3339.380 ; + RECT 634.020 3339.370 637.020 3339.380 ; + RECT 814.020 3339.370 817.020 3339.380 ; + RECT 994.020 3339.370 997.020 3339.380 ; + RECT 1174.020 3339.370 1177.020 3339.380 ; + RECT 1354.020 3339.370 1357.020 3339.380 ; + RECT 1534.020 3339.370 1537.020 3339.380 ; + RECT 1714.020 3339.370 1717.020 3339.380 ; + RECT 1894.020 3339.370 1897.020 3339.380 ; + RECT 2074.020 3339.370 2077.020 3339.380 ; + RECT 2254.020 3339.370 2257.020 3339.380 ; + RECT 2434.020 3339.370 2437.020 3339.380 ; + RECT 2614.020 3339.370 2617.020 3339.380 ; + RECT 2794.020 3339.370 2797.020 3339.380 ; + RECT 2931.400 3339.370 2934.400 3339.380 ; + RECT -24.380 3180.380 -21.380 3180.390 ; + RECT 112.020 3180.380 115.020 3180.390 ; + RECT 292.020 3180.380 295.020 3180.390 ; + RECT 407.840 3180.380 409.440 3180.390 ; + RECT 2632.020 3180.380 2635.020 3180.390 ; + RECT 2812.020 3180.380 2815.020 3180.390 ; + RECT 2941.000 3180.380 2944.000 3180.390 ; + RECT -24.380 3177.380 2944.000 3180.380 ; + RECT -24.380 3177.370 -21.380 3177.380 ; + RECT 112.020 3177.370 115.020 3177.380 ; + RECT 292.020 3177.370 295.020 3177.380 ; + RECT 407.840 3177.370 409.440 3177.380 ; + RECT 2632.020 3177.370 2635.020 3177.380 ; + RECT 2812.020 3177.370 2815.020 3177.380 ; + RECT 2941.000 3177.370 2944.000 3177.380 ; + RECT -14.780 3162.380 -11.780 3162.390 ; + RECT 94.020 3162.380 97.020 3162.390 ; + RECT 274.020 3162.380 277.020 3162.390 ; + RECT 407.840 3162.380 409.440 3162.390 ; + RECT 2614.020 3162.380 2617.020 3162.390 ; + RECT 2794.020 3162.380 2797.020 3162.390 ; + RECT 2931.400 3162.380 2934.400 3162.390 ; + RECT -14.780 3159.380 2934.400 3162.380 ; + RECT -14.780 3159.370 -11.780 3159.380 ; + RECT 94.020 3159.370 97.020 3159.380 ; + RECT 274.020 3159.370 277.020 3159.380 ; + RECT 407.840 3159.370 409.440 3159.380 ; + RECT 2614.020 3159.370 2617.020 3159.380 ; + RECT 2794.020 3159.370 2797.020 3159.380 ; + RECT 2931.400 3159.370 2934.400 3159.380 ; + RECT -24.380 3000.380 -21.380 3000.390 ; + RECT 112.020 3000.380 115.020 3000.390 ; + RECT 292.020 3000.380 295.020 3000.390 ; + RECT 407.840 3000.380 409.440 3000.390 ; + RECT 2632.020 3000.380 2635.020 3000.390 ; + RECT 2812.020 3000.380 2815.020 3000.390 ; + RECT 2941.000 3000.380 2944.000 3000.390 ; + RECT -24.380 2997.380 2944.000 3000.380 ; + RECT -24.380 2997.370 -21.380 2997.380 ; + RECT 112.020 2997.370 115.020 2997.380 ; + RECT 292.020 2997.370 295.020 2997.380 ; + RECT 407.840 2997.370 409.440 2997.380 ; + RECT 2632.020 2997.370 2635.020 2997.380 ; + RECT 2812.020 2997.370 2815.020 2997.380 ; + RECT 2941.000 2997.370 2944.000 2997.380 ; + RECT -14.780 2982.380 -11.780 2982.390 ; + RECT 94.020 2982.380 97.020 2982.390 ; + RECT 274.020 2982.380 277.020 2982.390 ; + RECT 407.840 2982.380 409.440 2982.390 ; + RECT 2614.020 2982.380 2617.020 2982.390 ; + RECT 2794.020 2982.380 2797.020 2982.390 ; + RECT 2931.400 2982.380 2934.400 2982.390 ; + RECT -14.780 2979.380 2934.400 2982.380 ; + RECT -14.780 2979.370 -11.780 2979.380 ; + RECT 94.020 2979.370 97.020 2979.380 ; + RECT 274.020 2979.370 277.020 2979.380 ; + RECT 407.840 2979.370 409.440 2979.380 ; + RECT 2614.020 2979.370 2617.020 2979.380 ; + RECT 2794.020 2979.370 2797.020 2979.380 ; + RECT 2931.400 2979.370 2934.400 2979.380 ; + RECT -24.380 2820.380 -21.380 2820.390 ; + RECT 112.020 2820.380 115.020 2820.390 ; + RECT 292.020 2820.380 295.020 2820.390 ; + RECT 407.840 2820.380 409.440 2820.390 ; + RECT 2632.020 2820.380 2635.020 2820.390 ; + RECT 2812.020 2820.380 2815.020 2820.390 ; + RECT 2941.000 2820.380 2944.000 2820.390 ; + RECT -24.380 2817.380 2944.000 2820.380 ; + RECT -24.380 2817.370 -21.380 2817.380 ; + RECT 112.020 2817.370 115.020 2817.380 ; + RECT 292.020 2817.370 295.020 2817.380 ; + RECT 407.840 2817.370 409.440 2817.380 ; + RECT 2632.020 2817.370 2635.020 2817.380 ; + RECT 2812.020 2817.370 2815.020 2817.380 ; + RECT 2941.000 2817.370 2944.000 2817.380 ; + RECT -14.780 2802.380 -11.780 2802.390 ; + RECT 94.020 2802.380 97.020 2802.390 ; + RECT 274.020 2802.380 277.020 2802.390 ; + RECT 407.840 2802.380 409.440 2802.390 ; + RECT 2614.020 2802.380 2617.020 2802.390 ; + RECT 2794.020 2802.380 2797.020 2802.390 ; + RECT 2931.400 2802.380 2934.400 2802.390 ; + RECT -14.780 2799.380 2934.400 2802.380 ; + RECT -14.780 2799.370 -11.780 2799.380 ; + RECT 94.020 2799.370 97.020 2799.380 ; + RECT 274.020 2799.370 277.020 2799.380 ; + RECT 407.840 2799.370 409.440 2799.380 ; + RECT 2614.020 2799.370 2617.020 2799.380 ; + RECT 2794.020 2799.370 2797.020 2799.380 ; + RECT 2931.400 2799.370 2934.400 2799.380 ; + RECT -24.380 2640.380 -21.380 2640.390 ; + RECT 112.020 2640.380 115.020 2640.390 ; + RECT 292.020 2640.380 295.020 2640.390 ; + RECT 407.840 2640.380 409.440 2640.390 ; + RECT 2632.020 2640.380 2635.020 2640.390 ; + RECT 2812.020 2640.380 2815.020 2640.390 ; + RECT 2941.000 2640.380 2944.000 2640.390 ; + RECT -24.380 2637.380 2944.000 2640.380 ; + RECT -24.380 2637.370 -21.380 2637.380 ; + RECT 112.020 2637.370 115.020 2637.380 ; + RECT 292.020 2637.370 295.020 2637.380 ; + RECT 407.840 2637.370 409.440 2637.380 ; + RECT 2632.020 2637.370 2635.020 2637.380 ; + RECT 2812.020 2637.370 2815.020 2637.380 ; + RECT 2941.000 2637.370 2944.000 2637.380 ; + RECT -14.780 2622.380 -11.780 2622.390 ; + RECT 94.020 2622.380 97.020 2622.390 ; + RECT 274.020 2622.380 277.020 2622.390 ; + RECT 407.840 2622.380 409.440 2622.390 ; + RECT 2614.020 2622.380 2617.020 2622.390 ; + RECT 2794.020 2622.380 2797.020 2622.390 ; + RECT 2931.400 2622.380 2934.400 2622.390 ; + RECT -14.780 2619.380 2934.400 2622.380 ; + RECT -14.780 2619.370 -11.780 2619.380 ; + RECT 94.020 2619.370 97.020 2619.380 ; + RECT 274.020 2619.370 277.020 2619.380 ; + RECT 407.840 2619.370 409.440 2619.380 ; + RECT 2614.020 2619.370 2617.020 2619.380 ; + RECT 2794.020 2619.370 2797.020 2619.380 ; + RECT 2931.400 2619.370 2934.400 2619.380 ; + RECT -24.380 2460.380 -21.380 2460.390 ; + RECT 112.020 2460.380 115.020 2460.390 ; + RECT 292.020 2460.380 295.020 2460.390 ; + RECT 407.840 2460.380 409.440 2460.390 ; + RECT 2632.020 2460.380 2635.020 2460.390 ; + RECT 2812.020 2460.380 2815.020 2460.390 ; + RECT 2941.000 2460.380 2944.000 2460.390 ; + RECT -24.380 2457.380 2944.000 2460.380 ; + RECT -24.380 2457.370 -21.380 2457.380 ; + RECT 112.020 2457.370 115.020 2457.380 ; + RECT 292.020 2457.370 295.020 2457.380 ; + RECT 407.840 2457.370 409.440 2457.380 ; + RECT 2632.020 2457.370 2635.020 2457.380 ; + RECT 2812.020 2457.370 2815.020 2457.380 ; + RECT 2941.000 2457.370 2944.000 2457.380 ; + RECT -14.780 2442.380 -11.780 2442.390 ; + RECT 94.020 2442.380 97.020 2442.390 ; + RECT 274.020 2442.380 277.020 2442.390 ; + RECT 407.840 2442.380 409.440 2442.390 ; + RECT 2614.020 2442.380 2617.020 2442.390 ; + RECT 2794.020 2442.380 2797.020 2442.390 ; + RECT 2931.400 2442.380 2934.400 2442.390 ; + RECT -14.780 2439.380 2934.400 2442.380 ; + RECT -14.780 2439.370 -11.780 2439.380 ; + RECT 94.020 2439.370 97.020 2439.380 ; + RECT 274.020 2439.370 277.020 2439.380 ; + RECT 407.840 2439.370 409.440 2439.380 ; + RECT 2614.020 2439.370 2617.020 2439.380 ; + RECT 2794.020 2439.370 2797.020 2439.380 ; + RECT 2931.400 2439.370 2934.400 2439.380 ; + RECT -24.380 2280.380 -21.380 2280.390 ; + RECT 112.020 2280.380 115.020 2280.390 ; + RECT 292.020 2280.380 295.020 2280.390 ; + RECT 407.840 2280.380 409.440 2280.390 ; + RECT 2632.020 2280.380 2635.020 2280.390 ; + RECT 2812.020 2280.380 2815.020 2280.390 ; + RECT 2941.000 2280.380 2944.000 2280.390 ; + RECT -24.380 2277.380 2944.000 2280.380 ; + RECT -24.380 2277.370 -21.380 2277.380 ; + RECT 112.020 2277.370 115.020 2277.380 ; + RECT 292.020 2277.370 295.020 2277.380 ; + RECT 407.840 2277.370 409.440 2277.380 ; + RECT 2632.020 2277.370 2635.020 2277.380 ; + RECT 2812.020 2277.370 2815.020 2277.380 ; + RECT 2941.000 2277.370 2944.000 2277.380 ; + RECT -14.780 2262.380 -11.780 2262.390 ; + RECT 94.020 2262.380 97.020 2262.390 ; + RECT 274.020 2262.380 277.020 2262.390 ; + RECT 407.840 2262.380 409.440 2262.390 ; + RECT 2614.020 2262.380 2617.020 2262.390 ; + RECT 2794.020 2262.380 2797.020 2262.390 ; + RECT 2931.400 2262.380 2934.400 2262.390 ; + RECT -14.780 2259.380 2934.400 2262.380 ; + RECT -14.780 2259.370 -11.780 2259.380 ; + RECT 94.020 2259.370 97.020 2259.380 ; + RECT 274.020 2259.370 277.020 2259.380 ; + RECT 407.840 2259.370 409.440 2259.380 ; + RECT 2614.020 2259.370 2617.020 2259.380 ; + RECT 2794.020 2259.370 2797.020 2259.380 ; + RECT 2931.400 2259.370 2934.400 2259.380 ; + RECT -24.380 2100.380 -21.380 2100.390 ; + RECT 112.020 2100.380 115.020 2100.390 ; + RECT 292.020 2100.380 295.020 2100.390 ; + RECT 407.840 2100.380 409.440 2100.390 ; + RECT 2632.020 2100.380 2635.020 2100.390 ; + RECT 2812.020 2100.380 2815.020 2100.390 ; + RECT 2941.000 2100.380 2944.000 2100.390 ; + RECT -24.380 2097.380 2944.000 2100.380 ; + RECT -24.380 2097.370 -21.380 2097.380 ; + RECT 112.020 2097.370 115.020 2097.380 ; + RECT 292.020 2097.370 295.020 2097.380 ; + RECT 407.840 2097.370 409.440 2097.380 ; + RECT 2632.020 2097.370 2635.020 2097.380 ; + RECT 2812.020 2097.370 2815.020 2097.380 ; + RECT 2941.000 2097.370 2944.000 2097.380 ; + RECT -14.780 2082.380 -11.780 2082.390 ; + RECT 94.020 2082.380 97.020 2082.390 ; + RECT 274.020 2082.380 277.020 2082.390 ; + RECT 407.840 2082.380 409.440 2082.390 ; + RECT 2614.020 2082.380 2617.020 2082.390 ; + RECT 2794.020 2082.380 2797.020 2082.390 ; + RECT 2931.400 2082.380 2934.400 2082.390 ; + RECT -14.780 2079.380 2934.400 2082.380 ; + RECT -14.780 2079.370 -11.780 2079.380 ; + RECT 94.020 2079.370 97.020 2079.380 ; + RECT 274.020 2079.370 277.020 2079.380 ; + RECT 407.840 2079.370 409.440 2079.380 ; + RECT 2614.020 2079.370 2617.020 2079.380 ; + RECT 2794.020 2079.370 2797.020 2079.380 ; + RECT 2931.400 2079.370 2934.400 2079.380 ; + RECT -24.380 1920.380 -21.380 1920.390 ; + RECT 112.020 1920.380 115.020 1920.390 ; + RECT 292.020 1920.380 295.020 1920.390 ; + RECT 407.840 1920.380 409.440 1920.390 ; + RECT 2632.020 1920.380 2635.020 1920.390 ; + RECT 2812.020 1920.380 2815.020 1920.390 ; + RECT 2941.000 1920.380 2944.000 1920.390 ; + RECT -24.380 1917.380 2944.000 1920.380 ; + RECT -24.380 1917.370 -21.380 1917.380 ; + RECT 112.020 1917.370 115.020 1917.380 ; + RECT 292.020 1917.370 295.020 1917.380 ; + RECT 407.840 1917.370 409.440 1917.380 ; + RECT 2632.020 1917.370 2635.020 1917.380 ; + RECT 2812.020 1917.370 2815.020 1917.380 ; + RECT 2941.000 1917.370 2944.000 1917.380 ; + RECT -14.780 1902.380 -11.780 1902.390 ; + RECT 94.020 1902.380 97.020 1902.390 ; + RECT 274.020 1902.380 277.020 1902.390 ; + RECT 407.840 1902.380 409.440 1902.390 ; + RECT 2614.020 1902.380 2617.020 1902.390 ; + RECT 2794.020 1902.380 2797.020 1902.390 ; + RECT 2931.400 1902.380 2934.400 1902.390 ; + RECT -14.780 1899.380 2934.400 1902.380 ; + RECT -14.780 1899.370 -11.780 1899.380 ; + RECT 94.020 1899.370 97.020 1899.380 ; + RECT 274.020 1899.370 277.020 1899.380 ; + RECT 407.840 1899.370 409.440 1899.380 ; + RECT 2614.020 1899.370 2617.020 1899.380 ; + RECT 2794.020 1899.370 2797.020 1899.380 ; + RECT 2931.400 1899.370 2934.400 1899.380 ; + RECT -24.380 1740.380 -21.380 1740.390 ; + RECT 112.020 1740.380 115.020 1740.390 ; + RECT 292.020 1740.380 295.020 1740.390 ; + RECT 407.840 1740.380 409.440 1740.390 ; + RECT 2632.020 1740.380 2635.020 1740.390 ; + RECT 2812.020 1740.380 2815.020 1740.390 ; + RECT 2941.000 1740.380 2944.000 1740.390 ; + RECT -24.380 1737.380 2944.000 1740.380 ; + RECT -24.380 1737.370 -21.380 1737.380 ; + RECT 112.020 1737.370 115.020 1737.380 ; + RECT 292.020 1737.370 295.020 1737.380 ; + RECT 407.840 1737.370 409.440 1737.380 ; + RECT 2632.020 1737.370 2635.020 1737.380 ; + RECT 2812.020 1737.370 2815.020 1737.380 ; + RECT 2941.000 1737.370 2944.000 1737.380 ; + RECT -14.780 1722.380 -11.780 1722.390 ; + RECT 94.020 1722.380 97.020 1722.390 ; + RECT 274.020 1722.380 277.020 1722.390 ; + RECT 407.840 1722.380 409.440 1722.390 ; + RECT 2614.020 1722.380 2617.020 1722.390 ; + RECT 2794.020 1722.380 2797.020 1722.390 ; + RECT 2931.400 1722.380 2934.400 1722.390 ; + RECT -14.780 1719.380 2934.400 1722.380 ; + RECT -14.780 1719.370 -11.780 1719.380 ; + RECT 94.020 1719.370 97.020 1719.380 ; + RECT 274.020 1719.370 277.020 1719.380 ; + RECT 407.840 1719.370 409.440 1719.380 ; + RECT 2614.020 1719.370 2617.020 1719.380 ; + RECT 2794.020 1719.370 2797.020 1719.380 ; + RECT 2931.400 1719.370 2934.400 1719.380 ; + RECT -24.380 1560.380 -21.380 1560.390 ; + RECT 112.020 1560.380 115.020 1560.390 ; + RECT 292.020 1560.380 295.020 1560.390 ; + RECT 407.840 1560.380 409.440 1560.390 ; + RECT 2632.020 1560.380 2635.020 1560.390 ; + RECT 2812.020 1560.380 2815.020 1560.390 ; + RECT 2941.000 1560.380 2944.000 1560.390 ; + RECT -24.380 1557.380 2944.000 1560.380 ; + RECT -24.380 1557.370 -21.380 1557.380 ; + RECT 112.020 1557.370 115.020 1557.380 ; + RECT 292.020 1557.370 295.020 1557.380 ; + RECT 407.840 1557.370 409.440 1557.380 ; + RECT 2632.020 1557.370 2635.020 1557.380 ; + RECT 2812.020 1557.370 2815.020 1557.380 ; + RECT 2941.000 1557.370 2944.000 1557.380 ; + RECT -14.780 1542.380 -11.780 1542.390 ; + RECT 94.020 1542.380 97.020 1542.390 ; + RECT 274.020 1542.380 277.020 1542.390 ; + RECT 407.840 1542.380 409.440 1542.390 ; + RECT 2614.020 1542.380 2617.020 1542.390 ; + RECT 2794.020 1542.380 2797.020 1542.390 ; + RECT 2931.400 1542.380 2934.400 1542.390 ; + RECT -14.780 1539.380 2934.400 1542.380 ; + RECT -14.780 1539.370 -11.780 1539.380 ; + RECT 94.020 1539.370 97.020 1539.380 ; + RECT 274.020 1539.370 277.020 1539.380 ; + RECT 407.840 1539.370 409.440 1539.380 ; + RECT 2614.020 1539.370 2617.020 1539.380 ; + RECT 2794.020 1539.370 2797.020 1539.380 ; + RECT 2931.400 1539.370 2934.400 1539.380 ; + RECT -24.380 1380.380 -21.380 1380.390 ; + RECT 112.020 1380.380 115.020 1380.390 ; + RECT 292.020 1380.380 295.020 1380.390 ; + RECT 407.840 1380.380 409.440 1380.390 ; + RECT 2632.020 1380.380 2635.020 1380.390 ; + RECT 2812.020 1380.380 2815.020 1380.390 ; + RECT 2941.000 1380.380 2944.000 1380.390 ; + RECT -24.380 1377.380 2944.000 1380.380 ; + RECT -24.380 1377.370 -21.380 1377.380 ; + RECT 112.020 1377.370 115.020 1377.380 ; + RECT 292.020 1377.370 295.020 1377.380 ; + RECT 407.840 1377.370 409.440 1377.380 ; + RECT 2632.020 1377.370 2635.020 1377.380 ; + RECT 2812.020 1377.370 2815.020 1377.380 ; + RECT 2941.000 1377.370 2944.000 1377.380 ; + RECT -14.780 1362.380 -11.780 1362.390 ; + RECT 94.020 1362.380 97.020 1362.390 ; + RECT 274.020 1362.380 277.020 1362.390 ; + RECT 407.840 1362.380 409.440 1362.390 ; + RECT 2614.020 1362.380 2617.020 1362.390 ; + RECT 2794.020 1362.380 2797.020 1362.390 ; + RECT 2931.400 1362.380 2934.400 1362.390 ; + RECT -14.780 1359.380 2934.400 1362.380 ; + RECT -14.780 1359.370 -11.780 1359.380 ; + RECT 94.020 1359.370 97.020 1359.380 ; + RECT 274.020 1359.370 277.020 1359.380 ; + RECT 407.840 1359.370 409.440 1359.380 ; + RECT 2614.020 1359.370 2617.020 1359.380 ; + RECT 2794.020 1359.370 2797.020 1359.380 ; + RECT 2931.400 1359.370 2934.400 1359.380 ; + RECT -24.380 1200.380 -21.380 1200.390 ; + RECT 112.020 1200.380 115.020 1200.390 ; + RECT 292.020 1200.380 295.020 1200.390 ; + RECT 407.840 1200.380 409.440 1200.390 ; + RECT 2632.020 1200.380 2635.020 1200.390 ; + RECT 2812.020 1200.380 2815.020 1200.390 ; + RECT 2941.000 1200.380 2944.000 1200.390 ; + RECT -24.380 1197.380 2944.000 1200.380 ; + RECT -24.380 1197.370 -21.380 1197.380 ; + RECT 112.020 1197.370 115.020 1197.380 ; + RECT 292.020 1197.370 295.020 1197.380 ; + RECT 407.840 1197.370 409.440 1197.380 ; + RECT 2632.020 1197.370 2635.020 1197.380 ; + RECT 2812.020 1197.370 2815.020 1197.380 ; + RECT 2941.000 1197.370 2944.000 1197.380 ; + RECT -14.780 1182.380 -11.780 1182.390 ; + RECT 94.020 1182.380 97.020 1182.390 ; + RECT 274.020 1182.380 277.020 1182.390 ; + RECT 407.840 1182.380 409.440 1182.390 ; + RECT 2614.020 1182.380 2617.020 1182.390 ; + RECT 2794.020 1182.380 2797.020 1182.390 ; + RECT 2931.400 1182.380 2934.400 1182.390 ; + RECT -14.780 1179.380 2934.400 1182.380 ; + RECT -14.780 1179.370 -11.780 1179.380 ; + RECT 94.020 1179.370 97.020 1179.380 ; + RECT 274.020 1179.370 277.020 1179.380 ; + RECT 407.840 1179.370 409.440 1179.380 ; + RECT 2614.020 1179.370 2617.020 1179.380 ; + RECT 2794.020 1179.370 2797.020 1179.380 ; + RECT 2931.400 1179.370 2934.400 1179.380 ; + RECT -24.380 1020.380 -21.380 1020.390 ; + RECT 112.020 1020.380 115.020 1020.390 ; + RECT 292.020 1020.380 295.020 1020.390 ; + RECT 407.840 1020.380 409.440 1020.390 ; + RECT 2632.020 1020.380 2635.020 1020.390 ; + RECT 2812.020 1020.380 2815.020 1020.390 ; + RECT 2941.000 1020.380 2944.000 1020.390 ; + RECT -24.380 1017.380 2944.000 1020.380 ; + RECT -24.380 1017.370 -21.380 1017.380 ; + RECT 112.020 1017.370 115.020 1017.380 ; + RECT 292.020 1017.370 295.020 1017.380 ; + RECT 407.840 1017.370 409.440 1017.380 ; + RECT 2632.020 1017.370 2635.020 1017.380 ; + RECT 2812.020 1017.370 2815.020 1017.380 ; + RECT 2941.000 1017.370 2944.000 1017.380 ; + RECT -14.780 1002.380 -11.780 1002.390 ; + RECT 94.020 1002.380 97.020 1002.390 ; + RECT 274.020 1002.380 277.020 1002.390 ; + RECT 407.840 1002.380 409.440 1002.390 ; + RECT 2614.020 1002.380 2617.020 1002.390 ; + RECT 2794.020 1002.380 2797.020 1002.390 ; + RECT 2931.400 1002.380 2934.400 1002.390 ; + RECT -14.780 999.380 2934.400 1002.380 ; + RECT -14.780 999.370 -11.780 999.380 ; + RECT 94.020 999.370 97.020 999.380 ; + RECT 274.020 999.370 277.020 999.380 ; + RECT 407.840 999.370 409.440 999.380 ; + RECT 2614.020 999.370 2617.020 999.380 ; + RECT 2794.020 999.370 2797.020 999.380 ; + RECT 2931.400 999.370 2934.400 999.380 ; + RECT -24.380 840.380 -21.380 840.390 ; + RECT 112.020 840.380 115.020 840.390 ; + RECT 292.020 840.380 295.020 840.390 ; + RECT 407.840 840.380 409.440 840.390 ; + RECT 2632.020 840.380 2635.020 840.390 ; + RECT 2812.020 840.380 2815.020 840.390 ; + RECT 2941.000 840.380 2944.000 840.390 ; + RECT -24.380 837.380 2944.000 840.380 ; + RECT -24.380 837.370 -21.380 837.380 ; + RECT 112.020 837.370 115.020 837.380 ; + RECT 292.020 837.370 295.020 837.380 ; + RECT 407.840 837.370 409.440 837.380 ; + RECT 2632.020 837.370 2635.020 837.380 ; + RECT 2812.020 837.370 2815.020 837.380 ; + RECT 2941.000 837.370 2944.000 837.380 ; + RECT -14.780 822.380 -11.780 822.390 ; + RECT 94.020 822.380 97.020 822.390 ; + RECT 274.020 822.380 277.020 822.390 ; + RECT 407.840 822.380 409.440 822.390 ; + RECT 2614.020 822.380 2617.020 822.390 ; + RECT 2794.020 822.380 2797.020 822.390 ; + RECT 2931.400 822.380 2934.400 822.390 ; + RECT -14.780 819.380 2934.400 822.380 ; + RECT -14.780 819.370 -11.780 819.380 ; + RECT 94.020 819.370 97.020 819.380 ; + RECT 274.020 819.370 277.020 819.380 ; + RECT 407.840 819.370 409.440 819.380 ; + RECT 2614.020 819.370 2617.020 819.380 ; + RECT 2794.020 819.370 2797.020 819.380 ; + RECT 2931.400 819.370 2934.400 819.380 ; + RECT -24.380 660.380 -21.380 660.390 ; + RECT 112.020 660.380 115.020 660.390 ; + RECT 292.020 660.380 295.020 660.390 ; + RECT 407.840 660.380 409.440 660.390 ; + RECT 2632.020 660.380 2635.020 660.390 ; + RECT 2812.020 660.380 2815.020 660.390 ; + RECT 2941.000 660.380 2944.000 660.390 ; + RECT -24.380 657.380 2944.000 660.380 ; + RECT -24.380 657.370 -21.380 657.380 ; + RECT 112.020 657.370 115.020 657.380 ; + RECT 292.020 657.370 295.020 657.380 ; + RECT 407.840 657.370 409.440 657.380 ; + RECT 2632.020 657.370 2635.020 657.380 ; + RECT 2812.020 657.370 2815.020 657.380 ; + RECT 2941.000 657.370 2944.000 657.380 ; + RECT -14.780 642.380 -11.780 642.390 ; + RECT 94.020 642.380 97.020 642.390 ; + RECT 274.020 642.380 277.020 642.390 ; + RECT 407.840 642.380 409.440 642.390 ; + RECT 2614.020 642.380 2617.020 642.390 ; + RECT 2794.020 642.380 2797.020 642.390 ; + RECT 2931.400 642.380 2934.400 642.390 ; + RECT -14.780 639.380 2934.400 642.380 ; + RECT -14.780 639.370 -11.780 639.380 ; + RECT 94.020 639.370 97.020 639.380 ; + RECT 274.020 639.370 277.020 639.380 ; + RECT 407.840 639.370 409.440 639.380 ; + RECT 2614.020 639.370 2617.020 639.380 ; + RECT 2794.020 639.370 2797.020 639.380 ; + RECT 2931.400 639.370 2934.400 639.380 ; + RECT -24.380 480.380 -21.380 480.390 ; + RECT 112.020 480.380 115.020 480.390 ; + RECT 292.020 480.380 295.020 480.390 ; + RECT 407.840 480.380 409.440 480.390 ; + RECT 2632.020 480.380 2635.020 480.390 ; + RECT 2812.020 480.380 2815.020 480.390 ; + RECT 2941.000 480.380 2944.000 480.390 ; + RECT -24.380 477.380 2944.000 480.380 ; + RECT -24.380 477.370 -21.380 477.380 ; + RECT 112.020 477.370 115.020 477.380 ; + RECT 292.020 477.370 295.020 477.380 ; + RECT 407.840 477.370 409.440 477.380 ; + RECT 2632.020 477.370 2635.020 477.380 ; + RECT 2812.020 477.370 2815.020 477.380 ; + RECT 2941.000 477.370 2944.000 477.380 ; + RECT -14.780 462.380 -11.780 462.390 ; + RECT 94.020 462.380 97.020 462.390 ; + RECT 274.020 462.380 277.020 462.390 ; + RECT 407.840 462.380 409.440 462.390 ; + RECT 2614.020 462.380 2617.020 462.390 ; + RECT 2794.020 462.380 2797.020 462.390 ; + RECT 2931.400 462.380 2934.400 462.390 ; + RECT -14.780 459.380 2934.400 462.380 ; + RECT -14.780 459.370 -11.780 459.380 ; + RECT 94.020 459.370 97.020 459.380 ; + RECT 274.020 459.370 277.020 459.380 ; + RECT 407.840 459.370 409.440 459.380 ; + RECT 2614.020 459.370 2617.020 459.380 ; + RECT 2794.020 459.370 2797.020 459.380 ; + RECT 2931.400 459.370 2934.400 459.380 ; + RECT -24.380 300.380 -21.380 300.390 ; + RECT 112.020 300.380 115.020 300.390 ; + RECT 292.020 300.380 295.020 300.390 ; + RECT 407.840 300.380 409.440 300.390 ; + RECT 2632.020 300.380 2635.020 300.390 ; + RECT 2812.020 300.380 2815.020 300.390 ; + RECT 2941.000 300.380 2944.000 300.390 ; + RECT -24.380 297.380 2944.000 300.380 ; + RECT -24.380 297.370 -21.380 297.380 ; + RECT 112.020 297.370 115.020 297.380 ; + RECT 292.020 297.370 295.020 297.380 ; + RECT 407.840 297.370 409.440 297.380 ; + RECT 2632.020 297.370 2635.020 297.380 ; + RECT 2812.020 297.370 2815.020 297.380 ; + RECT 2941.000 297.370 2944.000 297.380 ; + RECT -14.780 282.380 -11.780 282.390 ; + RECT 94.020 282.380 97.020 282.390 ; + RECT 274.020 282.380 277.020 282.390 ; + RECT 407.840 282.380 409.440 282.390 ; + RECT 2614.020 282.380 2617.020 282.390 ; + RECT 2794.020 282.380 2797.020 282.390 ; + RECT 2931.400 282.380 2934.400 282.390 ; + RECT -14.780 279.380 2934.400 282.380 ; + RECT -14.780 279.370 -11.780 279.380 ; + RECT 94.020 279.370 97.020 279.380 ; + RECT 274.020 279.370 277.020 279.380 ; + RECT 407.840 279.370 409.440 279.380 ; + RECT 2614.020 279.370 2617.020 279.380 ; + RECT 2794.020 279.370 2797.020 279.380 ; + RECT 2931.400 279.370 2934.400 279.380 ; + RECT -24.380 120.380 -21.380 120.390 ; + RECT 112.020 120.380 115.020 120.390 ; + RECT 292.020 120.380 295.020 120.390 ; + RECT 472.020 120.380 475.020 120.390 ; + RECT 652.020 120.380 655.020 120.390 ; + RECT 832.020 120.380 835.020 120.390 ; + RECT 1012.020 120.380 1015.020 120.390 ; + RECT 1192.020 120.380 1195.020 120.390 ; + RECT 1372.020 120.380 1375.020 120.390 ; + RECT 1552.020 120.380 1555.020 120.390 ; + RECT 1732.020 120.380 1735.020 120.390 ; + RECT 1912.020 120.380 1915.020 120.390 ; + RECT 2092.020 120.380 2095.020 120.390 ; + RECT 2272.020 120.380 2275.020 120.390 ; + RECT 2452.020 120.380 2455.020 120.390 ; + RECT 2632.020 120.380 2635.020 120.390 ; + RECT 2812.020 120.380 2815.020 120.390 ; + RECT 2941.000 120.380 2944.000 120.390 ; + RECT -24.380 117.380 2944.000 120.380 ; + RECT -24.380 117.370 -21.380 117.380 ; + RECT 112.020 117.370 115.020 117.380 ; + RECT 292.020 117.370 295.020 117.380 ; + RECT 472.020 117.370 475.020 117.380 ; + RECT 652.020 117.370 655.020 117.380 ; + RECT 832.020 117.370 835.020 117.380 ; + RECT 1012.020 117.370 1015.020 117.380 ; + RECT 1192.020 117.370 1195.020 117.380 ; + RECT 1372.020 117.370 1375.020 117.380 ; + RECT 1552.020 117.370 1555.020 117.380 ; + RECT 1732.020 117.370 1735.020 117.380 ; + RECT 1912.020 117.370 1915.020 117.380 ; + RECT 2092.020 117.370 2095.020 117.380 ; + RECT 2272.020 117.370 2275.020 117.380 ; + RECT 2452.020 117.370 2455.020 117.380 ; + RECT 2632.020 117.370 2635.020 117.380 ; + RECT 2812.020 117.370 2815.020 117.380 ; + RECT 2941.000 117.370 2944.000 117.380 ; + RECT -14.780 102.380 -11.780 102.390 ; + RECT 94.020 102.380 97.020 102.390 ; + RECT 274.020 102.380 277.020 102.390 ; + RECT 454.020 102.380 457.020 102.390 ; + RECT 634.020 102.380 637.020 102.390 ; + RECT 814.020 102.380 817.020 102.390 ; + RECT 994.020 102.380 997.020 102.390 ; + RECT 1174.020 102.380 1177.020 102.390 ; + RECT 1354.020 102.380 1357.020 102.390 ; + RECT 1534.020 102.380 1537.020 102.390 ; + RECT 1714.020 102.380 1717.020 102.390 ; + RECT 1894.020 102.380 1897.020 102.390 ; + RECT 2074.020 102.380 2077.020 102.390 ; + RECT 2254.020 102.380 2257.020 102.390 ; + RECT 2434.020 102.380 2437.020 102.390 ; + RECT 2614.020 102.380 2617.020 102.390 ; + RECT 2794.020 102.380 2797.020 102.390 ; + RECT 2931.400 102.380 2934.400 102.390 ; + RECT -14.780 99.380 2934.400 102.380 ; + RECT -14.780 99.370 -11.780 99.380 ; + RECT 94.020 99.370 97.020 99.380 ; + RECT 274.020 99.370 277.020 99.380 ; + RECT 454.020 99.370 457.020 99.380 ; + RECT 634.020 99.370 637.020 99.380 ; + RECT 814.020 99.370 817.020 99.380 ; + RECT 994.020 99.370 997.020 99.380 ; + RECT 1174.020 99.370 1177.020 99.380 ; + RECT 1354.020 99.370 1357.020 99.380 ; + RECT 1534.020 99.370 1537.020 99.380 ; + RECT 1714.020 99.370 1717.020 99.380 ; + RECT 1894.020 99.370 1897.020 99.380 ; + RECT 2074.020 99.370 2077.020 99.380 ; + RECT 2254.020 99.370 2257.020 99.380 ; + RECT 2434.020 99.370 2437.020 99.380 ; + RECT 2614.020 99.370 2617.020 99.380 ; + RECT 2794.020 99.370 2797.020 99.380 ; + RECT 2931.400 99.370 2934.400 99.380 ; + RECT -14.780 -6.420 -11.780 -6.410 ; + RECT 94.020 -6.420 97.020 -6.410 ; + RECT 274.020 -6.420 277.020 -6.410 ; + RECT 454.020 -6.420 457.020 -6.410 ; + RECT 634.020 -6.420 637.020 -6.410 ; + RECT 814.020 -6.420 817.020 -6.410 ; + RECT 994.020 -6.420 997.020 -6.410 ; + RECT 1174.020 -6.420 1177.020 -6.410 ; + RECT 1354.020 -6.420 1357.020 -6.410 ; + RECT 1534.020 -6.420 1537.020 -6.410 ; + RECT 1714.020 -6.420 1717.020 -6.410 ; + RECT 1894.020 -6.420 1897.020 -6.410 ; + RECT 2074.020 -6.420 2077.020 -6.410 ; + RECT 2254.020 -6.420 2257.020 -6.410 ; + RECT 2434.020 -6.420 2437.020 -6.410 ; + RECT 2614.020 -6.420 2617.020 -6.410 ; + RECT 2794.020 -6.420 2797.020 -6.410 ; + RECT 2931.400 -6.420 2934.400 -6.410 ; + RECT -14.780 -9.420 2934.400 -6.420 ; + RECT -14.780 -9.430 -11.780 -9.420 ; + RECT 94.020 -9.430 97.020 -9.420 ; + RECT 274.020 -9.430 277.020 -9.420 ; + RECT 454.020 -9.430 457.020 -9.420 ; + RECT 634.020 -9.430 637.020 -9.420 ; + RECT 814.020 -9.430 817.020 -9.420 ; + RECT 994.020 -9.430 997.020 -9.420 ; + RECT 1174.020 -9.430 1177.020 -9.420 ; + RECT 1354.020 -9.430 1357.020 -9.420 ; + RECT 1534.020 -9.430 1537.020 -9.420 ; + RECT 1714.020 -9.430 1717.020 -9.420 ; + RECT 1894.020 -9.430 1897.020 -9.420 ; + RECT 2074.020 -9.430 2077.020 -9.420 ; + RECT 2254.020 -9.430 2257.020 -9.420 ; + RECT 2434.020 -9.430 2437.020 -9.420 ; + RECT 2614.020 -9.430 2617.020 -9.420 ; + RECT 2794.020 -9.430 2797.020 -9.420 ; + RECT 2931.400 -9.430 2934.400 -9.420 ; + RECT -24.380 -16.020 -21.380 -16.010 ; + RECT 112.020 -16.020 115.020 -16.010 ; + RECT 292.020 -16.020 295.020 -16.010 ; + RECT 472.020 -16.020 475.020 -16.010 ; + RECT 652.020 -16.020 655.020 -16.010 ; + RECT 832.020 -16.020 835.020 -16.010 ; + RECT 1012.020 -16.020 1015.020 -16.010 ; + RECT 1192.020 -16.020 1195.020 -16.010 ; + RECT 1372.020 -16.020 1375.020 -16.010 ; + RECT 1552.020 -16.020 1555.020 -16.010 ; + RECT 1732.020 -16.020 1735.020 -16.010 ; + RECT 1912.020 -16.020 1915.020 -16.010 ; + RECT 2092.020 -16.020 2095.020 -16.010 ; + RECT 2272.020 -16.020 2275.020 -16.010 ; + RECT 2452.020 -16.020 2455.020 -16.010 ; + RECT 2632.020 -16.020 2635.020 -16.010 ; + RECT 2812.020 -16.020 2815.020 -16.010 ; + RECT 2941.000 -16.020 2944.000 -16.010 ; + RECT -24.380 -19.020 2944.000 -16.020 ; + RECT -24.380 -19.030 -21.380 -19.020 ; + RECT 112.020 -19.030 115.020 -19.020 ; + RECT 292.020 -19.030 295.020 -19.020 ; + RECT 472.020 -19.030 475.020 -19.020 ; + RECT 652.020 -19.030 655.020 -19.020 ; + RECT 832.020 -19.030 835.020 -19.020 ; + RECT 1012.020 -19.030 1015.020 -19.020 ; + RECT 1192.020 -19.030 1195.020 -19.020 ; + RECT 1372.020 -19.030 1375.020 -19.020 ; + RECT 1552.020 -19.030 1555.020 -19.020 ; + RECT 1732.020 -19.030 1735.020 -19.020 ; + RECT 1912.020 -19.030 1915.020 -19.020 ; + RECT 2092.020 -19.030 2095.020 -19.020 ; + RECT 2272.020 -19.030 2275.020 -19.020 ; + RECT 2452.020 -19.030 2455.020 -19.020 ; + RECT 2632.020 -19.030 2635.020 -19.020 ; + RECT 2812.020 -19.030 2815.020 -19.020 ; + RECT 2941.000 -19.030 2944.000 -19.020 ; + END + END vssd1 + OBS + LAYER li1 ; + RECT 315.520 270.795 2604.480 3246.645 ; + LAYER met1 ; + RECT 315.520 268.540 2604.480 3246.800 ; + LAYER met2 ; + RECT 312.850 3255.720 352.130 3256.000 ; + RECT 352.970 3255.720 437.230 3256.000 ; + RECT 438.070 3255.720 522.330 3256.000 ; + RECT 523.170 3255.720 607.430 3256.000 ; + RECT 608.270 3255.720 692.530 3256.000 ; + RECT 693.370 3255.720 777.630 3256.000 ; + RECT 778.470 3255.720 863.190 3256.000 ; + RECT 864.030 3255.720 948.290 3256.000 ; + RECT 949.130 3255.720 1033.390 3256.000 ; + RECT 1034.230 3255.720 1118.490 3256.000 ; + RECT 1119.330 3255.720 1203.590 3256.000 ; + RECT 1204.430 3255.720 1289.150 3256.000 ; + RECT 1289.990 3255.720 1374.250 3256.000 ; + RECT 1375.090 3255.720 1459.350 3256.000 ; + RECT 1460.190 3255.720 1544.450 3256.000 ; + RECT 1545.290 3255.720 1629.550 3256.000 ; + RECT 1630.390 3255.720 1714.650 3256.000 ; + RECT 1715.490 3255.720 1800.210 3256.000 ; + RECT 1801.050 3255.720 1885.310 3256.000 ; + RECT 1886.150 3255.720 1970.410 3256.000 ; + RECT 1971.250 3255.720 2055.510 3256.000 ; + RECT 2056.350 3255.720 2140.610 3256.000 ; + RECT 2141.450 3255.720 2226.170 3256.000 ; + RECT 2227.010 3255.720 2311.270 3256.000 ; + RECT 2312.110 3255.720 2396.370 3256.000 ; + RECT 2397.210 3255.720 2481.470 3256.000 ; + RECT 2482.310 3255.720 2566.570 3256.000 ; + RECT 2567.410 3255.720 2602.540 3256.000 ; + RECT 312.850 264.280 2602.540 3255.720 ; + RECT 313.410 264.000 318.090 264.280 ; + RECT 318.930 264.000 324.070 264.280 ; + RECT 324.910 264.000 330.050 264.280 ; + RECT 330.890 264.000 336.030 264.280 ; + RECT 336.870 264.000 342.010 264.280 ; + RECT 342.850 264.000 347.990 264.280 ; + RECT 348.830 264.000 353.970 264.280 ; + RECT 354.810 264.000 359.950 264.280 ; + RECT 360.790 264.000 365.930 264.280 ; + RECT 366.770 264.000 371.910 264.280 ; + RECT 372.750 264.000 377.890 264.280 ; + RECT 378.730 264.000 383.870 264.280 ; + RECT 384.710 264.000 389.850 264.280 ; + RECT 390.690 264.000 395.830 264.280 ; + RECT 396.670 264.000 401.810 264.280 ; + RECT 402.650 264.000 407.790 264.280 ; + RECT 408.630 264.000 413.770 264.280 ; + RECT 414.610 264.000 419.750 264.280 ; + RECT 420.590 264.000 425.730 264.280 ; + RECT 426.570 264.000 431.710 264.280 ; + RECT 432.550 264.000 437.690 264.280 ; + RECT 438.530 264.000 443.210 264.280 ; + RECT 444.050 264.000 449.190 264.280 ; + RECT 450.030 264.000 455.170 264.280 ; + RECT 456.010 264.000 461.150 264.280 ; + RECT 461.990 264.000 467.130 264.280 ; + RECT 467.970 264.000 473.110 264.280 ; + RECT 473.950 264.000 479.090 264.280 ; + RECT 479.930 264.000 485.070 264.280 ; + RECT 485.910 264.000 491.050 264.280 ; + RECT 491.890 264.000 497.030 264.280 ; + RECT 497.870 264.000 503.010 264.280 ; + RECT 503.850 264.000 508.990 264.280 ; + RECT 509.830 264.000 514.970 264.280 ; + RECT 515.810 264.000 520.950 264.280 ; + RECT 521.790 264.000 526.930 264.280 ; + RECT 527.770 264.000 532.910 264.280 ; + RECT 533.750 264.000 538.890 264.280 ; + RECT 539.730 264.000 544.870 264.280 ; + RECT 545.710 264.000 550.850 264.280 ; + RECT 551.690 264.000 556.830 264.280 ; + RECT 557.670 264.000 562.810 264.280 ; + RECT 563.650 264.000 568.330 264.280 ; + RECT 569.170 264.000 574.310 264.280 ; + RECT 575.150 264.000 580.290 264.280 ; + RECT 581.130 264.000 586.270 264.280 ; + RECT 587.110 264.000 592.250 264.280 ; + RECT 593.090 264.000 598.230 264.280 ; + RECT 599.070 264.000 604.210 264.280 ; + RECT 605.050 264.000 610.190 264.280 ; + RECT 611.030 264.000 616.170 264.280 ; + RECT 617.010 264.000 622.150 264.280 ; + RECT 622.990 264.000 628.130 264.280 ; + RECT 628.970 264.000 634.110 264.280 ; + RECT 634.950 264.000 640.090 264.280 ; + RECT 640.930 264.000 646.070 264.280 ; + RECT 646.910 264.000 652.050 264.280 ; + RECT 652.890 264.000 658.030 264.280 ; + RECT 658.870 264.000 664.010 264.280 ; + RECT 664.850 264.000 669.990 264.280 ; + RECT 670.830 264.000 675.970 264.280 ; + RECT 676.810 264.000 681.950 264.280 ; + RECT 682.790 264.000 687.930 264.280 ; + RECT 688.770 264.000 693.910 264.280 ; + RECT 694.750 264.000 699.430 264.280 ; + RECT 700.270 264.000 705.410 264.280 ; + RECT 706.250 264.000 711.390 264.280 ; + RECT 712.230 264.000 717.370 264.280 ; + RECT 718.210 264.000 723.350 264.280 ; + RECT 724.190 264.000 729.330 264.280 ; + RECT 730.170 264.000 735.310 264.280 ; + RECT 736.150 264.000 741.290 264.280 ; + RECT 742.130 264.000 747.270 264.280 ; + RECT 748.110 264.000 753.250 264.280 ; + RECT 754.090 264.000 759.230 264.280 ; + RECT 760.070 264.000 765.210 264.280 ; + RECT 766.050 264.000 771.190 264.280 ; + RECT 772.030 264.000 777.170 264.280 ; + RECT 778.010 264.000 783.150 264.280 ; + RECT 783.990 264.000 789.130 264.280 ; + RECT 789.970 264.000 795.110 264.280 ; + RECT 795.950 264.000 801.090 264.280 ; + RECT 801.930 264.000 807.070 264.280 ; + RECT 807.910 264.000 813.050 264.280 ; + RECT 813.890 264.000 819.030 264.280 ; + RECT 819.870 264.000 824.550 264.280 ; + RECT 825.390 264.000 830.530 264.280 ; + RECT 831.370 264.000 836.510 264.280 ; + RECT 837.350 264.000 842.490 264.280 ; + RECT 843.330 264.000 848.470 264.280 ; + RECT 849.310 264.000 854.450 264.280 ; + RECT 855.290 264.000 860.430 264.280 ; + RECT 861.270 264.000 866.410 264.280 ; + RECT 867.250 264.000 872.390 264.280 ; + RECT 873.230 264.000 878.370 264.280 ; + RECT 879.210 264.000 884.350 264.280 ; + RECT 885.190 264.000 890.330 264.280 ; + RECT 891.170 264.000 896.310 264.280 ; + RECT 897.150 264.000 902.290 264.280 ; + RECT 903.130 264.000 908.270 264.280 ; + RECT 909.110 264.000 914.250 264.280 ; + RECT 915.090 264.000 920.230 264.280 ; + RECT 921.070 264.000 926.210 264.280 ; + RECT 927.050 264.000 932.190 264.280 ; + RECT 933.030 264.000 938.170 264.280 ; + RECT 939.010 264.000 944.150 264.280 ; + RECT 944.990 264.000 950.130 264.280 ; + RECT 950.970 264.000 955.650 264.280 ; + RECT 956.490 264.000 961.630 264.280 ; + RECT 962.470 264.000 967.610 264.280 ; + RECT 968.450 264.000 973.590 264.280 ; + RECT 974.430 264.000 979.570 264.280 ; + RECT 980.410 264.000 985.550 264.280 ; + RECT 986.390 264.000 991.530 264.280 ; + RECT 992.370 264.000 997.510 264.280 ; + RECT 998.350 264.000 1003.490 264.280 ; + RECT 1004.330 264.000 1009.470 264.280 ; + RECT 1010.310 264.000 1015.450 264.280 ; + RECT 1016.290 264.000 1021.430 264.280 ; + RECT 1022.270 264.000 1027.410 264.280 ; + RECT 1028.250 264.000 1033.390 264.280 ; + RECT 1034.230 264.000 1039.370 264.280 ; + RECT 1040.210 264.000 1045.350 264.280 ; + RECT 1046.190 264.000 1051.330 264.280 ; + RECT 1052.170 264.000 1057.310 264.280 ; + RECT 1058.150 264.000 1063.290 264.280 ; + RECT 1064.130 264.000 1069.270 264.280 ; + RECT 1070.110 264.000 1075.250 264.280 ; + RECT 1076.090 264.000 1080.770 264.280 ; + RECT 1081.610 264.000 1086.750 264.280 ; + RECT 1087.590 264.000 1092.730 264.280 ; + RECT 1093.570 264.000 1098.710 264.280 ; + RECT 1099.550 264.000 1104.690 264.280 ; + RECT 1105.530 264.000 1110.670 264.280 ; + RECT 1111.510 264.000 1116.650 264.280 ; + RECT 1117.490 264.000 1122.630 264.280 ; + RECT 1123.470 264.000 1128.610 264.280 ; + RECT 1129.450 264.000 1134.590 264.280 ; + RECT 1135.430 264.000 1140.570 264.280 ; + RECT 1141.410 264.000 1146.550 264.280 ; + RECT 1147.390 264.000 1152.530 264.280 ; + RECT 1153.370 264.000 1158.510 264.280 ; + RECT 1159.350 264.000 1164.490 264.280 ; + RECT 1165.330 264.000 1170.470 264.280 ; + RECT 1171.310 264.000 1176.450 264.280 ; + RECT 1177.290 264.000 1182.430 264.280 ; + RECT 1183.270 264.000 1188.410 264.280 ; + RECT 1189.250 264.000 1194.390 264.280 ; + RECT 1195.230 264.000 1200.370 264.280 ; + RECT 1201.210 264.000 1206.350 264.280 ; + RECT 1207.190 264.000 1211.870 264.280 ; + RECT 1212.710 264.000 1217.850 264.280 ; + RECT 1218.690 264.000 1223.830 264.280 ; + RECT 1224.670 264.000 1229.810 264.280 ; + RECT 1230.650 264.000 1235.790 264.280 ; + RECT 1236.630 264.000 1241.770 264.280 ; + RECT 1242.610 264.000 1247.750 264.280 ; + RECT 1248.590 264.000 1253.730 264.280 ; + RECT 1254.570 264.000 1259.710 264.280 ; + RECT 1260.550 264.000 1265.690 264.280 ; + RECT 1266.530 264.000 1271.670 264.280 ; + RECT 1272.510 264.000 1277.650 264.280 ; + RECT 1278.490 264.000 1283.630 264.280 ; + RECT 1284.470 264.000 1289.610 264.280 ; + RECT 1290.450 264.000 1295.590 264.280 ; + RECT 1296.430 264.000 1301.570 264.280 ; + RECT 1302.410 264.000 1307.550 264.280 ; + RECT 1308.390 264.000 1313.530 264.280 ; + RECT 1314.370 264.000 1319.510 264.280 ; + RECT 1320.350 264.000 1325.490 264.280 ; + RECT 1326.330 264.000 1331.470 264.280 ; + RECT 1332.310 264.000 1336.990 264.280 ; + RECT 1337.830 264.000 1342.970 264.280 ; + RECT 1343.810 264.000 1348.950 264.280 ; + RECT 1349.790 264.000 1354.930 264.280 ; + RECT 1355.770 264.000 1360.910 264.280 ; + RECT 1361.750 264.000 1366.890 264.280 ; + RECT 1367.730 264.000 1372.870 264.280 ; + RECT 1373.710 264.000 1378.850 264.280 ; + RECT 1379.690 264.000 1384.830 264.280 ; + RECT 1385.670 264.000 1390.810 264.280 ; + RECT 1391.650 264.000 1396.790 264.280 ; + RECT 1397.630 264.000 1402.770 264.280 ; + RECT 1403.610 264.000 1408.750 264.280 ; + RECT 1409.590 264.000 1414.730 264.280 ; + RECT 1415.570 264.000 1420.710 264.280 ; + RECT 1421.550 264.000 1426.690 264.280 ; + RECT 1427.530 264.000 1432.670 264.280 ; + RECT 1433.510 264.000 1438.650 264.280 ; + RECT 1439.490 264.000 1444.630 264.280 ; + RECT 1445.470 264.000 1450.610 264.280 ; + RECT 1451.450 264.000 1456.590 264.280 ; + RECT 1457.430 264.000 1462.570 264.280 ; + RECT 1463.410 264.000 1468.090 264.280 ; + RECT 1468.930 264.000 1474.070 264.280 ; + RECT 1474.910 264.000 1480.050 264.280 ; + RECT 1480.890 264.000 1486.030 264.280 ; + RECT 1486.870 264.000 1492.010 264.280 ; + RECT 1492.850 264.000 1497.990 264.280 ; + RECT 1498.830 264.000 1503.970 264.280 ; + RECT 1504.810 264.000 1509.950 264.280 ; + RECT 1510.790 264.000 1515.930 264.280 ; + RECT 1516.770 264.000 1521.910 264.280 ; + RECT 1522.750 264.000 1527.890 264.280 ; + RECT 1528.730 264.000 1533.870 264.280 ; + RECT 1534.710 264.000 1539.850 264.280 ; + RECT 1540.690 264.000 1545.830 264.280 ; + RECT 1546.670 264.000 1551.810 264.280 ; + RECT 1552.650 264.000 1557.790 264.280 ; + RECT 1558.630 264.000 1563.770 264.280 ; + RECT 1564.610 264.000 1569.750 264.280 ; + RECT 1570.590 264.000 1575.730 264.280 ; + RECT 1576.570 264.000 1581.710 264.280 ; + RECT 1582.550 264.000 1587.690 264.280 ; + RECT 1588.530 264.000 1593.210 264.280 ; + RECT 1594.050 264.000 1599.190 264.280 ; + RECT 1600.030 264.000 1605.170 264.280 ; + RECT 1606.010 264.000 1611.150 264.280 ; + RECT 1611.990 264.000 1617.130 264.280 ; + RECT 1617.970 264.000 1623.110 264.280 ; + RECT 1623.950 264.000 1629.090 264.280 ; + RECT 1629.930 264.000 1635.070 264.280 ; + RECT 1635.910 264.000 1641.050 264.280 ; + RECT 1641.890 264.000 1647.030 264.280 ; + RECT 1647.870 264.000 1653.010 264.280 ; + RECT 1653.850 264.000 1658.990 264.280 ; + RECT 1659.830 264.000 1664.970 264.280 ; + RECT 1665.810 264.000 1670.950 264.280 ; + RECT 1671.790 264.000 1676.930 264.280 ; + RECT 1677.770 264.000 1682.910 264.280 ; + RECT 1683.750 264.000 1688.890 264.280 ; + RECT 1689.730 264.000 1694.870 264.280 ; + RECT 1695.710 264.000 1700.850 264.280 ; + RECT 1701.690 264.000 1706.830 264.280 ; + RECT 1707.670 264.000 1712.810 264.280 ; + RECT 1713.650 264.000 1718.330 264.280 ; + RECT 1719.170 264.000 1724.310 264.280 ; + RECT 1725.150 264.000 1730.290 264.280 ; + RECT 1731.130 264.000 1736.270 264.280 ; + RECT 1737.110 264.000 1742.250 264.280 ; + RECT 1743.090 264.000 1748.230 264.280 ; + RECT 1749.070 264.000 1754.210 264.280 ; + RECT 1755.050 264.000 1760.190 264.280 ; + RECT 1761.030 264.000 1766.170 264.280 ; + RECT 1767.010 264.000 1772.150 264.280 ; + RECT 1772.990 264.000 1778.130 264.280 ; + RECT 1778.970 264.000 1784.110 264.280 ; + RECT 1784.950 264.000 1790.090 264.280 ; + RECT 1790.930 264.000 1796.070 264.280 ; + RECT 1796.910 264.000 1802.050 264.280 ; + RECT 1802.890 264.000 1808.030 264.280 ; + RECT 1808.870 264.000 1814.010 264.280 ; + RECT 1814.850 264.000 1819.990 264.280 ; + RECT 1820.830 264.000 1825.970 264.280 ; + RECT 1826.810 264.000 1831.950 264.280 ; + RECT 1832.790 264.000 1837.930 264.280 ; + RECT 1838.770 264.000 1843.910 264.280 ; + RECT 1844.750 264.000 1849.430 264.280 ; + RECT 1850.270 264.000 1855.410 264.280 ; + RECT 1856.250 264.000 1861.390 264.280 ; + RECT 1862.230 264.000 1867.370 264.280 ; + RECT 1868.210 264.000 1873.350 264.280 ; + RECT 1874.190 264.000 1879.330 264.280 ; + RECT 1880.170 264.000 1885.310 264.280 ; + RECT 1886.150 264.000 1891.290 264.280 ; + RECT 1892.130 264.000 1897.270 264.280 ; + RECT 1898.110 264.000 1903.250 264.280 ; + RECT 1904.090 264.000 1909.230 264.280 ; + RECT 1910.070 264.000 1915.210 264.280 ; + RECT 1916.050 264.000 1921.190 264.280 ; + RECT 1922.030 264.000 1927.170 264.280 ; + RECT 1928.010 264.000 1933.150 264.280 ; + RECT 1933.990 264.000 1939.130 264.280 ; + RECT 1939.970 264.000 1945.110 264.280 ; + RECT 1945.950 264.000 1951.090 264.280 ; + RECT 1951.930 264.000 1957.070 264.280 ; + RECT 1957.910 264.000 1963.050 264.280 ; + RECT 1963.890 264.000 1969.030 264.280 ; + RECT 1969.870 264.000 1974.550 264.280 ; + RECT 1975.390 264.000 1980.530 264.280 ; + RECT 1981.370 264.000 1986.510 264.280 ; + RECT 1987.350 264.000 1992.490 264.280 ; + RECT 1993.330 264.000 1998.470 264.280 ; + RECT 1999.310 264.000 2004.450 264.280 ; + RECT 2005.290 264.000 2010.430 264.280 ; + RECT 2011.270 264.000 2016.410 264.280 ; + RECT 2017.250 264.000 2022.390 264.280 ; + RECT 2023.230 264.000 2028.370 264.280 ; + RECT 2029.210 264.000 2034.350 264.280 ; + RECT 2035.190 264.000 2040.330 264.280 ; + RECT 2041.170 264.000 2046.310 264.280 ; + RECT 2047.150 264.000 2052.290 264.280 ; + RECT 2053.130 264.000 2058.270 264.280 ; + RECT 2059.110 264.000 2064.250 264.280 ; + RECT 2065.090 264.000 2070.230 264.280 ; + RECT 2071.070 264.000 2076.210 264.280 ; + RECT 2077.050 264.000 2082.190 264.280 ; + RECT 2083.030 264.000 2088.170 264.280 ; + RECT 2089.010 264.000 2094.150 264.280 ; + RECT 2094.990 264.000 2100.130 264.280 ; + RECT 2100.970 264.000 2105.650 264.280 ; + RECT 2106.490 264.000 2111.630 264.280 ; + RECT 2112.470 264.000 2117.610 264.280 ; + RECT 2118.450 264.000 2123.590 264.280 ; + RECT 2124.430 264.000 2129.570 264.280 ; + RECT 2130.410 264.000 2135.550 264.280 ; + RECT 2136.390 264.000 2141.530 264.280 ; + RECT 2142.370 264.000 2147.510 264.280 ; + RECT 2148.350 264.000 2153.490 264.280 ; + RECT 2154.330 264.000 2159.470 264.280 ; + RECT 2160.310 264.000 2165.450 264.280 ; + RECT 2166.290 264.000 2171.430 264.280 ; + RECT 2172.270 264.000 2177.410 264.280 ; + RECT 2178.250 264.000 2183.390 264.280 ; + RECT 2184.230 264.000 2189.370 264.280 ; + RECT 2190.210 264.000 2195.350 264.280 ; + RECT 2196.190 264.000 2201.330 264.280 ; + RECT 2202.170 264.000 2207.310 264.280 ; + RECT 2208.150 264.000 2213.290 264.280 ; + RECT 2214.130 264.000 2219.270 264.280 ; + RECT 2220.110 264.000 2225.250 264.280 ; + RECT 2226.090 264.000 2230.770 264.280 ; + RECT 2231.610 264.000 2236.750 264.280 ; + RECT 2237.590 264.000 2242.730 264.280 ; + RECT 2243.570 264.000 2248.710 264.280 ; + RECT 2249.550 264.000 2254.690 264.280 ; + RECT 2255.530 264.000 2260.670 264.280 ; + RECT 2261.510 264.000 2266.650 264.280 ; + RECT 2267.490 264.000 2272.630 264.280 ; + RECT 2273.470 264.000 2278.610 264.280 ; + RECT 2279.450 264.000 2284.590 264.280 ; + RECT 2285.430 264.000 2290.570 264.280 ; + RECT 2291.410 264.000 2296.550 264.280 ; + RECT 2297.390 264.000 2302.530 264.280 ; + RECT 2303.370 264.000 2308.510 264.280 ; + RECT 2309.350 264.000 2314.490 264.280 ; + RECT 2315.330 264.000 2320.470 264.280 ; + RECT 2321.310 264.000 2326.450 264.280 ; + RECT 2327.290 264.000 2332.430 264.280 ; + RECT 2333.270 264.000 2338.410 264.280 ; + RECT 2339.250 264.000 2344.390 264.280 ; + RECT 2345.230 264.000 2350.370 264.280 ; + RECT 2351.210 264.000 2356.350 264.280 ; + RECT 2357.190 264.000 2361.870 264.280 ; + RECT 2362.710 264.000 2367.850 264.280 ; + RECT 2368.690 264.000 2373.830 264.280 ; + RECT 2374.670 264.000 2379.810 264.280 ; + RECT 2380.650 264.000 2385.790 264.280 ; + RECT 2386.630 264.000 2391.770 264.280 ; + RECT 2392.610 264.000 2397.750 264.280 ; + RECT 2398.590 264.000 2403.730 264.280 ; + RECT 2404.570 264.000 2409.710 264.280 ; + RECT 2410.550 264.000 2415.690 264.280 ; + RECT 2416.530 264.000 2421.670 264.280 ; + RECT 2422.510 264.000 2427.650 264.280 ; + RECT 2428.490 264.000 2433.630 264.280 ; + RECT 2434.470 264.000 2439.610 264.280 ; + RECT 2440.450 264.000 2445.590 264.280 ; + RECT 2446.430 264.000 2451.570 264.280 ; + RECT 2452.410 264.000 2457.550 264.280 ; + RECT 2458.390 264.000 2463.530 264.280 ; + RECT 2464.370 264.000 2469.510 264.280 ; + RECT 2470.350 264.000 2475.490 264.280 ; + RECT 2476.330 264.000 2481.470 264.280 ; + RECT 2482.310 264.000 2486.990 264.280 ; + RECT 2487.830 264.000 2492.970 264.280 ; + RECT 2493.810 264.000 2498.950 264.280 ; + RECT 2499.790 264.000 2504.930 264.280 ; + RECT 2505.770 264.000 2510.910 264.280 ; + RECT 2511.750 264.000 2516.890 264.280 ; + RECT 2517.730 264.000 2522.870 264.280 ; + RECT 2523.710 264.000 2528.850 264.280 ; + RECT 2529.690 264.000 2534.830 264.280 ; + RECT 2535.670 264.000 2540.810 264.280 ; + RECT 2541.650 264.000 2546.790 264.280 ; + RECT 2547.630 264.000 2552.770 264.280 ; + RECT 2553.610 264.000 2558.750 264.280 ; + RECT 2559.590 264.000 2564.730 264.280 ; + RECT 2565.570 264.000 2570.710 264.280 ; + RECT 2571.550 264.000 2576.690 264.280 ; + RECT 2577.530 264.000 2582.670 264.280 ; + RECT 2583.510 264.000 2588.650 264.280 ; + RECT 2589.490 264.000 2594.630 264.280 ; + RECT 2595.470 264.000 2600.610 264.280 ; + RECT 2601.450 264.000 2602.540 264.280 ; + LAYER met3 ; + RECT 312.825 3227.200 2606.010 3246.725 ; + RECT 312.825 3225.800 2605.600 3227.200 ; + RECT 312.825 3224.480 2606.010 3225.800 ; + RECT 314.400 3223.080 2606.010 3224.480 ; + RECT 312.825 3160.560 2606.010 3223.080 ; + RECT 312.825 3159.160 2605.600 3160.560 ; + RECT 312.825 3153.080 2606.010 3159.160 ; + RECT 314.400 3151.680 2606.010 3153.080 ; + RECT 312.825 3093.920 2606.010 3151.680 ; + RECT 312.825 3092.520 2605.600 3093.920 ; + RECT 312.825 3081.680 2606.010 3092.520 ; + RECT 314.400 3080.280 2606.010 3081.680 ; + RECT 312.825 3027.280 2606.010 3080.280 ; + RECT 312.825 3025.880 2605.600 3027.280 ; + RECT 312.825 3010.280 2606.010 3025.880 ; + RECT 314.400 3008.880 2606.010 3010.280 ; + RECT 312.825 2960.640 2606.010 3008.880 ; + RECT 312.825 2959.240 2605.600 2960.640 ; + RECT 312.825 2938.880 2606.010 2959.240 ; + RECT 314.400 2937.480 2606.010 2938.880 ; + RECT 312.825 2894.000 2606.010 2937.480 ; + RECT 312.825 2892.600 2605.600 2894.000 ; + RECT 312.825 2867.480 2606.010 2892.600 ; + RECT 314.400 2866.080 2606.010 2867.480 ; + RECT 312.825 2827.360 2606.010 2866.080 ; + RECT 312.825 2825.960 2605.600 2827.360 ; + RECT 312.825 2796.080 2606.010 2825.960 ; + RECT 314.400 2794.680 2606.010 2796.080 ; + RECT 312.825 2760.720 2606.010 2794.680 ; + RECT 312.825 2759.320 2605.600 2760.720 ; + RECT 312.825 2724.680 2606.010 2759.320 ; + RECT 314.400 2723.280 2606.010 2724.680 ; + RECT 312.825 2694.080 2606.010 2723.280 ; + RECT 312.825 2692.680 2605.600 2694.080 ; + RECT 312.825 2653.280 2606.010 2692.680 ; + RECT 314.400 2651.880 2606.010 2653.280 ; + RECT 312.825 2627.440 2606.010 2651.880 ; + RECT 312.825 2626.040 2605.600 2627.440 ; + RECT 312.825 2581.880 2606.010 2626.040 ; + RECT 314.400 2580.480 2606.010 2581.880 ; + RECT 312.825 2560.800 2606.010 2580.480 ; + RECT 312.825 2559.400 2605.600 2560.800 ; + RECT 312.825 2510.480 2606.010 2559.400 ; + RECT 314.400 2509.080 2606.010 2510.480 ; + RECT 312.825 2494.160 2606.010 2509.080 ; + RECT 312.825 2492.760 2605.600 2494.160 ; + RECT 312.825 2439.080 2606.010 2492.760 ; + RECT 314.400 2437.680 2606.010 2439.080 ; + RECT 312.825 2427.520 2606.010 2437.680 ; + RECT 312.825 2426.120 2605.600 2427.520 ; + RECT 312.825 2367.680 2606.010 2426.120 ; + RECT 314.400 2366.280 2606.010 2367.680 ; + RECT 312.825 2360.880 2606.010 2366.280 ; + RECT 312.825 2359.480 2605.600 2360.880 ; + RECT 312.825 2296.280 2606.010 2359.480 ; + RECT 314.400 2294.880 2606.010 2296.280 ; + RECT 312.825 2294.240 2606.010 2294.880 ; + RECT 312.825 2292.840 2605.600 2294.240 ; + RECT 312.825 2227.600 2606.010 2292.840 ; + RECT 312.825 2226.200 2605.600 2227.600 ; + RECT 312.825 2224.880 2606.010 2226.200 ; + RECT 314.400 2223.480 2606.010 2224.880 ; + RECT 312.825 2160.960 2606.010 2223.480 ; + RECT 312.825 2159.560 2605.600 2160.960 ; + RECT 312.825 2153.480 2606.010 2159.560 ; + RECT 314.400 2152.080 2606.010 2153.480 ; + RECT 312.825 2094.320 2606.010 2152.080 ; + RECT 312.825 2092.920 2605.600 2094.320 ; + RECT 312.825 2082.080 2606.010 2092.920 ; + RECT 314.400 2080.680 2606.010 2082.080 ; + RECT 312.825 2027.680 2606.010 2080.680 ; + RECT 312.825 2026.280 2605.600 2027.680 ; + RECT 312.825 2010.680 2606.010 2026.280 ; + RECT 314.400 2009.280 2606.010 2010.680 ; + RECT 312.825 1961.040 2606.010 2009.280 ; + RECT 312.825 1959.640 2605.600 1961.040 ; + RECT 312.825 1939.280 2606.010 1959.640 ; + RECT 314.400 1937.880 2606.010 1939.280 ; + RECT 312.825 1894.400 2606.010 1937.880 ; + RECT 312.825 1893.000 2605.600 1894.400 ; + RECT 312.825 1867.880 2606.010 1893.000 ; + RECT 314.400 1866.480 2606.010 1867.880 ; + RECT 312.825 1827.760 2606.010 1866.480 ; + RECT 312.825 1826.360 2605.600 1827.760 ; + RECT 312.825 1796.480 2606.010 1826.360 ; + RECT 314.400 1795.080 2606.010 1796.480 ; + RECT 312.825 1760.440 2606.010 1795.080 ; + RECT 312.825 1759.040 2605.600 1760.440 ; + RECT 312.825 1724.400 2606.010 1759.040 ; + RECT 314.400 1723.000 2606.010 1724.400 ; + RECT 312.825 1693.800 2606.010 1723.000 ; + RECT 312.825 1692.400 2605.600 1693.800 ; + RECT 312.825 1653.000 2606.010 1692.400 ; + RECT 314.400 1651.600 2606.010 1653.000 ; + RECT 312.825 1627.160 2606.010 1651.600 ; + RECT 312.825 1625.760 2605.600 1627.160 ; + RECT 312.825 1581.600 2606.010 1625.760 ; + RECT 314.400 1580.200 2606.010 1581.600 ; + RECT 312.825 1560.520 2606.010 1580.200 ; + RECT 312.825 1559.120 2605.600 1560.520 ; + RECT 312.825 1510.200 2606.010 1559.120 ; + RECT 314.400 1508.800 2606.010 1510.200 ; + RECT 312.825 1493.880 2606.010 1508.800 ; + RECT 312.825 1492.480 2605.600 1493.880 ; + RECT 312.825 1438.800 2606.010 1492.480 ; + RECT 314.400 1437.400 2606.010 1438.800 ; + RECT 312.825 1427.240 2606.010 1437.400 ; + RECT 312.825 1425.840 2605.600 1427.240 ; + RECT 312.825 1367.400 2606.010 1425.840 ; + RECT 314.400 1366.000 2606.010 1367.400 ; + RECT 312.825 1360.600 2606.010 1366.000 ; + RECT 312.825 1359.200 2605.600 1360.600 ; + RECT 312.825 1296.000 2606.010 1359.200 ; + RECT 314.400 1294.600 2606.010 1296.000 ; + RECT 312.825 1293.960 2606.010 1294.600 ; + RECT 312.825 1292.560 2605.600 1293.960 ; + RECT 312.825 1227.320 2606.010 1292.560 ; + RECT 312.825 1225.920 2605.600 1227.320 ; + RECT 312.825 1224.600 2606.010 1225.920 ; + RECT 314.400 1223.200 2606.010 1224.600 ; + RECT 312.825 1160.680 2606.010 1223.200 ; + RECT 312.825 1159.280 2605.600 1160.680 ; + RECT 312.825 1153.200 2606.010 1159.280 ; + RECT 314.400 1151.800 2606.010 1153.200 ; + RECT 312.825 1094.040 2606.010 1151.800 ; + RECT 312.825 1092.640 2605.600 1094.040 ; + RECT 312.825 1081.800 2606.010 1092.640 ; + RECT 314.400 1080.400 2606.010 1081.800 ; + RECT 312.825 1027.400 2606.010 1080.400 ; + RECT 312.825 1026.000 2605.600 1027.400 ; + RECT 312.825 1010.400 2606.010 1026.000 ; + RECT 314.400 1009.000 2606.010 1010.400 ; + RECT 312.825 960.760 2606.010 1009.000 ; + RECT 312.825 959.360 2605.600 960.760 ; + RECT 312.825 939.000 2606.010 959.360 ; + RECT 314.400 937.600 2606.010 939.000 ; + RECT 312.825 894.120 2606.010 937.600 ; + RECT 312.825 892.720 2605.600 894.120 ; + RECT 312.825 867.600 2606.010 892.720 ; + RECT 314.400 866.200 2606.010 867.600 ; + RECT 312.825 827.480 2606.010 866.200 ; + RECT 312.825 826.080 2605.600 827.480 ; + RECT 312.825 796.200 2606.010 826.080 ; + RECT 314.400 794.800 2606.010 796.200 ; + RECT 312.825 760.840 2606.010 794.800 ; + RECT 312.825 759.440 2605.600 760.840 ; + RECT 312.825 724.800 2606.010 759.440 ; + RECT 314.400 723.400 2606.010 724.800 ; + RECT 312.825 694.200 2606.010 723.400 ; + RECT 312.825 692.800 2605.600 694.200 ; + RECT 312.825 653.400 2606.010 692.800 ; + RECT 314.400 652.000 2606.010 653.400 ; + RECT 312.825 627.560 2606.010 652.000 ; + RECT 312.825 626.160 2605.600 627.560 ; + RECT 312.825 582.000 2606.010 626.160 ; + RECT 314.400 580.600 2606.010 582.000 ; + RECT 312.825 560.920 2606.010 580.600 ; + RECT 312.825 559.520 2605.600 560.920 ; + RECT 312.825 510.600 2606.010 559.520 ; + RECT 314.400 509.200 2606.010 510.600 ; + RECT 312.825 494.280 2606.010 509.200 ; + RECT 312.825 492.880 2605.600 494.280 ; + RECT 312.825 439.200 2606.010 492.880 ; + RECT 314.400 437.800 2606.010 439.200 ; + RECT 312.825 427.640 2606.010 437.800 ; + RECT 312.825 426.240 2605.600 427.640 ; + RECT 312.825 367.800 2606.010 426.240 ; + RECT 314.400 366.400 2606.010 367.800 ; + RECT 312.825 361.000 2606.010 366.400 ; + RECT 312.825 359.600 2605.600 361.000 ; + RECT 312.825 296.400 2606.010 359.600 ; + RECT 314.400 295.000 2606.010 296.400 ; + RECT 312.825 294.360 2606.010 295.000 ; + RECT 312.825 292.960 2605.600 294.360 ; + RECT 312.825 270.715 2606.010 292.960 ; + LAYER met4 ; + RECT 326.855 270.640 330.640 3246.800 ; + RECT 333.040 270.640 407.440 3246.800 ; + RECT 409.840 270.640 2592.225 3246.800 ; +======= RECT -14.680 -9.320 -11.680 3529.000 ; RECT 94.020 3519.700 97.020 3529.000 ; RECT 274.020 3519.700 277.020 3529.000 ; @@ -8200,6 +26442,7 @@ RECT 4.020 0.300 2905.020 3519.700 ; LAYER met5 ; RECT 0.300 9.130 2919.700 3486.390 ; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d END END user_project_wrapper END LIBRARY
diff --git a/mag/caravel.mag b/mag/caravel.mag index 7c815a3..0023f26 100644 --- a/mag/caravel.mag +++ b/mag/caravel.mag
@@ -1,7 +1,13 @@ magic tech sky130A magscale 1 2 +<<<<<<< HEAD +timestamp 1608019001 +<< checkpaint >> +rect -1260 -1260 718860 1038860 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d << metal1 >> rect 93904 1010925 93910 1010977 rect 93962 1010965 93968 1010977 @@ -80687,6 +80693,49 @@ rect 455018 40175 455254 40298 rect 459242 40175 459478 40411 << metal5 >> +<<<<<<< HEAD +rect 399104 236881 411520 236923 +rect 399104 236645 399146 236881 +rect 399382 236645 411242 236881 +rect 411478 236645 411520 236881 +rect 399104 236603 411520 236645 +rect 427520 223561 448000 223603 +rect 427520 223325 427562 223561 +rect 427798 223325 447722 223561 +rect 447958 223325 448000 223561 +rect 427520 223283 448000 223325 +rect 380288 222895 400384 222937 +rect 380288 222659 380330 222895 +rect 380566 222659 400106 222895 +rect 400342 222659 400384 222895 +rect 380288 222617 400384 222659 +use user_id_programming user_id_value ../mag +timestamp 1608019001 +transform 1 0 656625 0 1 80926 +box 0 0 7109 7077 +use storage storage ../mag +timestamp 1608019001 +transform 1 0 52031 0 1 61392 +box 0 0 88934 189234 +use mgmt_core soc ../mag +timestamp 1608019001 +transform 1 0 204550 0 1 53700 +box 0 0 430000 170000 +use sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped rstb_level ../mag +timestamp 1608019001 +transform 1 0 154753 0 1 51403 +box 0 1 5124 5084 +use simple_por por ../mag +timestamp 1608019001 +transform 1 0 654176 0 1 104197 +box 25 11 11344 8338 +use mgmt_protect mgmt_buffers ../mag +timestamp 1608019001 +transform 1 0 288100 0 1 239747 +box 0 0 169594 13025 +use gpio_control_block gpio_control_bidir\[1\] ../mag +timestamp 1608019001 +======= rect 324032 270847 331264 270889 rect 324032 270611 324074 270847 rect 324310 270611 330986 270847 @@ -80769,9 +80818,53 @@ box 25 11 11344 8291 use gpio_control_block gpio_control_bidir\[1\] timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 166200 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_bidir\[0\] +<<<<<<< HEAD +timestamp 1608019001 +transform -1 0 708537 0 1 121000 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[37\] +timestamp 1608019001 +transform 1 0 8567 0 1 202600 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[36\] +timestamp 1608019001 +transform 1 0 8567 0 1 245800 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[3\] +timestamp 1608019001 +transform -1 0 708537 0 1 256400 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[2\] +timestamp 1608019001 +transform -1 0 708537 0 1 211200 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[35\] +timestamp 1608019001 +transform 1 0 8567 0 1 289000 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[34\] +timestamp 1608019001 +transform 1 0 8567 0 1 332200 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[33\] +timestamp 1608019001 +transform 1 0 8567 0 1 375400 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[5\] +timestamp 1608019001 +transform -1 0 708537 0 1 346400 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[4\] +timestamp 1608019001 +transform -1 0 708537 0 1 301400 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[7\] +timestamp 1608019001 +======= timestamp 1607961244 transform -1 0 708537 0 1 121000 box 38 0 33934 18344 @@ -80817,109 +80910,223 @@ box 38 0 33934 18344 use gpio_control_block gpio_control_in\[7\] timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 479800 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[6\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 391600 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[32\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 418600 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[31\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 546200 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[30\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 589400 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[29\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 632600 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[9\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 568800 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[8\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 523800 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[10\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 614000 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[28\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 675800 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[27\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 719000 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[26\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 762200 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[13\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 749200 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[12\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 704200 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[11\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform -1 0 708537 0 1 659000 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[25\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 1 0 8567 0 1 805400 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[24\] +<<<<<<< HEAD +timestamp 1608019001 +transform 1 0 8567 0 1 889800 +box 0 0 33934 18344 +use gpio_control_block gpio_control_in\[23\] +timestamp 1608019001 +======= timestamp 1607961244 transform 1 0 8567 0 1 931224 box 38 0 33934 18344 use gpio_control_block gpio_control_in\[23\] timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 97200 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[22\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 148600 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[21\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 200000 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[20\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 251400 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[19\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 303000 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[18\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 353400 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[17\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 420800 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[16\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 497800 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[15\] +<<<<<<< HEAD +timestamp 1608019001 +======= timestamp 1607961244 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d transform 0 1 549200 -1 0 1029747 -box 38 0 33934 18344 +box 0 0 33934 18344 use gpio_control_block gpio_control_in\[14\] +<<<<<<< HEAD +timestamp 1608019001 +transform -1 0 708537 0 1 927600 +box 0 0 33934 18344 +use chip_io padframe ../mag +timestamp 1608019001 +transform 1 0 0 0 1 0 +box 0 0 717600 1037600 +use user_project_wrapper mprj ../mag +timestamp 1608019001 +transform 1 0 65277 0 1 276402 +box -4876 -3806 588800 707742 +======= timestamp 1607961244 transform -1 0 708537 0 1 927600 box 38 0 33934 18344 @@ -80931,6 +81138,7 @@ timestamp 1607961244 transform 1 0 0 0 1 0 box 0 0 717600 1037600 +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d << properties >> string FIXED_BBOX 0 0 717600 1037600 << end >>
diff --git a/mag/ghazi_top_dffram_csv.mag.xz b/mag/ghazi_top_dffram_csv.mag.xz new file mode 100644 index 0000000..498e688 --- /dev/null +++ b/mag/ghazi_top_dffram_csv.mag.xz Binary files differ
diff --git a/mag/mgmt_core.mag.gz b/mag/mgmt_core.mag.gz deleted file mode 100644 index 92f56a4..0000000 --- a/mag/mgmt_core.mag.gz +++ /dev/null Binary files differ
diff --git a/mag/mgmt_core.mag.xz b/mag/mgmt_core.mag.xz new file mode 100644 index 0000000..3b6ca09 --- /dev/null +++ b/mag/mgmt_core.mag.xz Binary files differ
diff --git a/mag/user_project_wrapper.mag b/mag/user_project_wrapper.mag index 7617c75..e26891d 100644 --- a/mag/user_project_wrapper.mag +++ b/mag/user_project_wrapper.mag Binary files differ
diff --git a/openlane/ghazi_top_dffram_csv/config.tcl b/openlane/ghazi_top_dffram_csv/config.tcl new file mode 100755 index 0000000..0377151 --- /dev/null +++ b/openlane/ghazi_top_dffram_csv/config.tcl
@@ -0,0 +1,22 @@ + +set script_dir [file dirname [file normalize [info script]]] +set ::env(DESIGN_NAME) ghazi_top_dffram_csv + +# Change if needed +set ::env(VERILOG_FILES) [glob $script_dir/../../verilog/rtl/defines.v $script_dir/../../verilog/rtl/ghazi/*.v] +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(FP_SIZING) relative +set ::env(DIE_AREA) "0 0 2300 3000" +set ::env(PL_TARGET_DENSITY) 0.3 +set ::env(GENERATE_FINAL_SUMMARY_REPORT) 1 +set ::env(SYNTH_STRATEGY) 0 +set ::env(SYNTH_MAX_FANOUT) 4 +set ::env(FP_PIN_ORDER_CFG) /$script_dir/pin_order.cfg +set ::env(PDN_CFG) $script_dir/pdn.tcl +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_ALLOW_CONGESTION) 1 +#defaults +set ::env(BASE_SDC_FILE) $script_dir/ghazi_top_dffram_csv.sdc +# Fill this +set ::env(CLOCK_PERIOD) "80" +set ::env(CLOCK_PORT) "wb_clk_i"
diff --git a/openlane/ghazi_top_dffram_csv/ghazi_top_dffram_csv.sdc b/openlane/ghazi_top_dffram_csv/ghazi_top_dffram_csv.sdc new file mode 100755 index 0000000..1bdf971 --- /dev/null +++ b/openlane/ghazi_top_dffram_csv/ghazi_top_dffram_csv.sdc
@@ -0,0 +1,36 @@ +create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period $::env(CLOCK_PERIOD) +set SCL /home/merlproj/backend-tools/openlane_rc4/designs/aireen_dffram/syn/sky130_fd_sc_hd__tt_025C_1v80.lib + +set IO_PCT 0.2 +set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] +set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT] +puts "\[INFO\]: Setting output delay to: $output_delay_value" +puts "\[INFO\]: Setting input delay to: $input_delay_value" + + + +set_false_path -through wb_rst_i +set_false_path -through RESET_n +#set_input_delay $input_delay_value -clock wbs_clk_i [all_inputs] +#set_output_delay $output_delay_value -clock wbs_clk_i [all_outputs] + + + + +set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]] +##set rst_indx [lsearch [all_inputs] [get_port resetn]] +set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx] +##set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx] +set all_inputs_wo_clk_rst $all_inputs_wo_clk + + +# correct resetn +set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk_rst +##set_input_delay 0.0 -clock [get_clocks $::env(CLOCK_PORT)] {resetn} +set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs] + +# TODO set this as parameter +set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] +set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs]
diff --git a/openlane/ghazi_top_dffram_csv/pdn.tcl b/openlane/ghazi_top_dffram_csv/pdn.tcl new file mode 100644 index 0000000..bbe9ce6 --- /dev/null +++ b/openlane/ghazi_top_dffram_csv/pdn.tcl
@@ -0,0 +1,37 @@ +# Power nets +set ::power_nets $::env(VDD_PIN) +set ::ground_nets $::env(GND_PIN) + +set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" + +pdngen::specify_grid stdcell { + name grid + rails { + met1 {width $::env(FP_PDN_RAIL_WIDTH) pitch $::env(PLACE_SITE_HEIGHT) offset $::env(FP_PDN_RAIL_OFFSET)} + } + straps { + met4 {width $::env(FP_PDN_VWIDTH) pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} + } + connect {{met1 met4} } +} + +pdngen::specify_grid macro { + orient {R0 R180 MX MY R90 R270 MXR90 MYR90} + power_pins "VDDE" + ground_pins "VSSE" + blockages "li1 met1 met2 met3 met4 met5" + straps { + } + connect { } +} + +set ::halo 0 + +# Metal layer for rails on every row +set ::rails_mlayer "met1" ; + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/openlane/ghazi_top_dffram_csv/pin_order.cfg b/openlane/ghazi_top_dffram_csv/pin_order.cfg new file mode 100755 index 0000000..8b7d8f5 --- /dev/null +++ b/openlane/ghazi_top_dffram_csv/pin_order.cfg
@@ -0,0 +1,125 @@ +#BUS_SORT +#NR +io_in\[15\] +io_out\[15\] +io_oeb\[15\] +io_in\[16\] +io_out\[16\] +io_oeb\[16\] +io_in\[17\] +io_out\[17\] +io_oeb\[17\] +io_in\[18\] +io_out\[18\] +io_oeb\[18\] +io_in\[19\] +io_out\[19\] +io_oeb\[19\] +io_in\[20\] +io_out\[20\] +io_oeb\[20\] +io_in\[21\] +io_out\[21\] +io_oeb\[21\] +io_in\[22\] +io_out\[22\] +io_oeb\[22\] +io_in\[23\] +io_out\[23\] +io_oeb\[23\] + +#S +wb_.* +la_.* +user_clock2 + +#E +io_in\[0\] +io_out\[0\] +io_oeb\[0\] +io_in\[1\] +io_out\[1\] +io_oeb\[1\] +io_in\[2\] +io_out\[2\] +io_oeb\[2\] +io_in\[3\] +io_out\[3\] +io_oeb\[3\] +io_in\[4\] +io_out\[4\] +io_oeb\[4\] +io_in\[5\] +io_out\[5\] +io_oeb\[5\] +io_in\[6\] +io_out\[6\] +io_oeb\[6\] +io_in\[7\] +io_out\[7\] +io_oeb\[7\] +io_in\[8\] +io_out\[8\] +io_oeb\[8\] +io_in\[9\] +io_out\[9\] +io_oeb\[9\] +io_in\[10\] +io_out\[10\] +io_oeb\[10\] +io_in\[11\] +io_out\[11\] +io_oeb\[11\] +io_in\[12\] +io_out\[12\] +io_oeb\[12\] +io_in\[13\] +io_out\[13\] +io_oeb\[13\] +io_in\[14\] +io_out\[14\] +io_oeb\[14\] + +#WR +io_in\[24\] +io_out\[24\] +io_oeb\[24\] +io_in\[25\] +io_out\[25\] +io_oeb\[25\] +io_in\[26\] +io_out\[26\] +io_oeb\[26\] +io_in\[27\] +io_out\[27\] +io_oeb\[27\] +io_in\[28\] +io_out\[28\] +io_oeb\[28\] +io_in\[29\] +io_out\[29\] +io_oeb\[29\] +io_in\[30\] +io_out\[30\] +io_oeb\[30\] +io_in\[31\] +io_out\[31\] +io_oeb\[31\] +io_in\[32\] +io_out\[32\] +io_oeb\[32\] +io_in\[33\] +io_out\[33\] +io_oeb\[33\] +io_in\[34\] +io_out\[34\] +io_oeb\[34\] +io_in\[35\] +io_out\[35\] +io_oeb\[35\] +io_in\[36\] +io_out\[36\] +io_oeb\[36\] +io_in\[37\] +io_out\[37\] +io_oeb\[37\]
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl new file mode 100644 index 0000000..6de8e8a --- /dev/null +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,63 @@ +package require openlane +set script_dir [file dirname [file normalize [info script]]] + +prep -design $script_dir -tag user_project_wrapper -overwrite +set save_path $script_dir/../.. + +verilog_elaborate + +init_floorplan + +place_io_ol + +set ::env(FP_DEF_TEMPATE) $script_dir/../../def/user_project_wrapper_empty.def + +apply_def_template + +add_macro_placement mprj 310 260 N + +manual_macro_placement f + +set ::env(_SPACING) 1.8 +set ::env(_WIDTH) 3 + +set power_domains [list {vccd1 vssd1} {vccd2 vssd2}] + +set ::env(_VDD_NET_NAME) vccd1 +set ::env(_GND_NET_NAME) vssd1 +set ::env(_V_OFFSET) 14 +set ::env(_H_OFFSET) $::env(_V_OFFSET) +set ::env(_V_PITCH) 180 +set ::env(_H_PITCH) 180 +set ::env(_V_PDN_OFFSET) 0 +set ::env(_H_PDN_OFFSET) 0 + +foreach domain $power_domains { + set ::env(_VDD_NET_NAME) [lindex $domain 0] + set ::env(_GND_NET_NAME) [lindex $domain 1] + gen_pdn + set ::env(_V_OFFSET) \ + [expr $::env(_V_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))] + set ::env(_H_OFFSET) \ + [expr $::env(_H_OFFSET) + 2*($::env(_WIDTH)+$::env(_SPACING))] + set ::env(_V_PDN_OFFSET) [expr $::env(_V_PDN_OFFSET)+6*$::env(_WIDTH)] + set ::env(_H_PDN_OFFSET) [expr $::env(_H_PDN_OFFSET)+6*$::env(_WIDTH)] +} + +global_routing_or +detailed_routing +run_magic +run_magic_spice_export + +save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(tritonRoute_result_file_tag).def \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -save_path $save_path \ + -tag $::env(RUN_TAG) + +run_magic_drc + +run_lvs; # requires run_magic_spice_export + +run_antenna_check
diff --git a/openlane/user_project_wrapper/pdn.tcl b/openlane/user_project_wrapper/pdn.tcl new file mode 100644 index 0000000..5838b0c --- /dev/null +++ b/openlane/user_project_wrapper/pdn.tcl
@@ -0,0 +1,47 @@ +# Power nets +set ::power_nets $::env(_VDD_NET_NAME) +set ::ground_nets $::env(_GND_NET_NAME) + +pdngen::specify_grid stdcell { + name grid + core_ring { + met5 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_H_OFFSET)} + met4 {width $::env(_WIDTH) spacing $::env(_SPACING) core_offset $::env(_V_OFFSET)} + } + rails { + } + straps { + met4 {width $::env(_WIDTH) pitch $::env(_V_PITCH) offset $::env(_V_PDN_OFFSET)} + met5 {width $::env(_WIDTH) pitch $::env(_H_PITCH) offset $::env(_H_PDN_OFFSET)} + } + connect {{met4 met5}} +} + +pdngen::specify_grid macro { + instance "mprj" + power_pins "VPWR" + ground_pins "VGND" + blockages "li1 met1 met2 met3 met4" + straps { + } + connect {{met4_PIN_ver met5}} +} + + +pdngen::specify_grid macro { + power_pins $::env(_VDD_NET_NAME) + ground_pins $::env(_GND_NET_NAME) + blockages "" + straps { + } + connect {} +} + +set ::halo 0 + +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; + +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ; +
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/Makefile b/verilog/dv/caravel/ghazi_top_dffram_csv/Makefile new file mode 100644 index 0000000..350b2f9 --- /dev/null +++ b/verilog/dv/caravel/ghazi_top_dffram_csv/Makefile
@@ -0,0 +1,18 @@ +# ---- Test patterns for project striVe ---- + +.SUFFIXES: +.SILENT: clean all + +PATTERNS = test_1 + +all: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \ + done + +clean: ${PATTERNS} + for i in ${PATTERNS}; do \ + ( cd $$i && make clean ) ; \ + done + +.PHONY: clean all
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/hex/test_1.hex b/verilog/dv/caravel/ghazi_top_dffram_csv/hex/test_1.hex new file mode 100644 index 0000000..b22dac8 --- /dev/null +++ b/verilog/dv/caravel/ghazi_top_dffram_csv/hex/test_1.hex
@@ -0,0 +1,11 @@ +40010437 +00040413 +0FF00293 +00542E23 +0FF00513 +00000593 +00B42823 +00158593 +FEB51CE3 +00000013 +00000FFF \ No newline at end of file
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/Makefile b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/Makefile new file mode 100644 index 0000000..6cb9bc4 --- /dev/null +++ b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/Makefile
@@ -0,0 +1,42 @@ +FIRMWARE_PATH = ../.. +RTL_PATH = ../../../../rtl +IP_PATH = ../../../../ip +BEHAVIOURAL_MODELS = ../../ + +GCC_PATH?=/ef/apps/bin +GCC_PREFIX?=riscv32-unknown-elf +PDK_PATH?=/ef/tech/SW/sky130A + +.SUFFIXES: + +PATTERN = test_1 + +all: ${PATTERN:=.vcd} + +hex: ${PATTERN:=.hex} + +%.vvp: %_tb.v %.hex + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \ + -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \ + -o $@ $< + +%.vcd: %.vvp + vvp $< + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1.c b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1.c new file mode 100644 index 0000000..7429a92 --- /dev/null +++ b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1.c
@@ -0,0 +1,34 @@ +#include "../../defs.h" + +void main() +{ + // reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; + // reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; + // reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; + // reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL; + // reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + // reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + + reg_mprj_xfer = 1; + while(reg_mprj_xfer == 1); + + reg_la1_ena = 0x00000000; + reg_la1_data = 0x0000015C; + + reg_la0_ena = 0x00000000; + reg_la0_data = 0x00000001; + reg_la0_data = 0x00000000; + reg_mprj_datah = 0x20; + +}
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1_tb.v b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1_tb.v new file mode 100644 index 0000000..ea18d61 --- /dev/null +++ b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1_tb.v
@@ -0,0 +1,151 @@ +`default_nettype none + +`timescale 1 ns / 1 ps + +`include "caravel.v" +`include "spiflash.v" +`include "tbprog.v" + +module test_1_tb; + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + wire [6:0] mprj_io_0; + wire mprj_ready; + + assign mprj_io_0 = mprj_io[12:6]; + assign mprj_ready = mprj_io[37]; + + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + $dumpfile("test_1.vcd"); + $dumpvars(0, test_1_tb); + + // Repeat cycles of 1000 clock edges as needed to complete testbench + repeat (300) begin + repeat (1000) @(posedge clock); + // $display("+1000 cycles"); + end + $display("%c[1;31m",27); + $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed"); + $display("%c[0m",27); + $finish; + end + + initial begin + // Observe Output pins [12:6] + wait(mprj_ready == 1'b1); + wait(mprj_io_0 == 7'h01); + wait(mprj_io_0 == 7'h03); + wait(mprj_io_0 == 7'h05); + wait(mprj_io_0 == 7'h07); + wait(mprj_io_0 == 7'h13); + wait(mprj_io_0 == 7'h55); + wait(mprj_io_0 == 7'h7F); + + $display("Monitor: Test 1 Mega-Project IO (RTL) Passed"); + $finish; + end + + initial begin + RSTB <= 1'b0; + #2000; + RSTB <= 1'b1; // Release reset + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #200; + power1 <= 1'b1; + #200; + power2 <= 1'b1; + #200; + power3 <= 1'b1; + #200; + power4 <= 1'b1; + end + + always @(mprj_io) begin + #1 $display("MPRJ-IO state = 0x%0h ", mprj_io_0); + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + wire r_Rx_Serial; + assign mprj_io[5] = r_Rx_Serial; + + + + wire VDD1V8; + wire VDD3V3; + wire VSS; + + assign VDD3V3 = power1; + assign VDD1V8 = power2; + assign VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (VDD3V3), + .vdda2 (VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (VDD1V8), + .vccd2 (VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("test_1.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + + tbprog #( + .FILENAME("../hex/test_1.hex") + ) prog_uut ( + .mprj_ready (mprj_ready), + .r_Rx_Serial (r_Rx_Serial) + ); + +endmodule +`default_nettype wire
diff --git a/verilog/dv/caravel/tbprog.v b/verilog/dv/caravel/tbprog.v new file mode 100644 index 0000000..f6c6612 --- /dev/null +++ b/verilog/dv/caravel/tbprog.v
@@ -0,0 +1,90 @@ +`timescale 1ns / 1ps + +module tbprog #( + parameter FILENAME="program.hex" +)( + input mprj_ready, + output reg r_Rx_Serial // used by task UART_WRITE_BYTE +); + +reg r_Clock = 0; +parameter c_BIT_PERIOD = 8681; // used by task UART_WRITE_BYTE +parameter c_CLOCK_PERIOD_NS = 100; + +reg [31:0] INSTR[(256*64)-1 : 0]; +integer instr_count = 0; +reg ready; +reg test; + +always @ ( posedge r_Clock ) begin + if (mprj_ready) begin + ready <= 1'b1; + end else begin + ready <= 1'b0; + end +end + +initial begin + $readmemh(FILENAME,INSTR); +end + +task UART_WRITE_BYTE; + input [7:0] i_Data; + integer ii; + begin + // Send Start Bit + r_Rx_Serial <= 1'b0; + #(c_BIT_PERIOD); + #1000; + + // Send Data Byte + for (ii=0; ii<8; ii=ii+1) begin + r_Rx_Serial <= i_Data[ii]; + #(c_BIT_PERIOD); + end + + // Send Stop Bit + r_Rx_Serial <= 1'b1; + #(c_BIT_PERIOD); + end +endtask // UART_WRITE_BYTE + +initial begin + test = 1'b0; + #1000 test = 1'b1; +end + +always + #(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock; + +initial begin + r_Rx_Serial <= 1'b1; + #2000; + while (!ready && test) begin + @(posedge r_Clock) + r_Rx_Serial <= 1'b1; + end + while (instr_count<255 && INSTR[instr_count]!=32'h00000FFF) begin + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][31:24]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][23:16]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][15:8]); + @(posedge r_Clock); + UART_WRITE_BYTE(INSTR[instr_count][7:0]); + @(posedge r_Clock); + instr_count = instr_count + 1'b1; + end + @(posedge r_Clock); + UART_WRITE_BYTE(8'h00); + @(posedge r_Clock); + UART_WRITE_BYTE(8'h00); + @(posedge r_Clock); + UART_WRITE_BYTE(8'h0F); + @(posedge r_Clock); + UART_WRITE_BYTE(8'hFF); + @(posedge r_Clock); +end + +endmodule
diff --git a/verilog/gl/ghazi_top_dffram_csv.v b/verilog/gl/ghazi_top_dffram_csv.v new file mode 100644 index 0000000..b793de5 --- /dev/null +++ b/verilog/gl/ghazi_top_dffram_csv.v Binary files differ
diff --git a/verilog/gl/user_project_wrapper.v b/verilog/gl/user_project_wrapper.v index ff068f0..25b5dd6 100644 --- a/verilog/gl/user_project_wrapper.v +++ b/verilog/gl/user_project_wrapper.v
@@ -1,6 +1,10 @@ /* Generated by Yosys 0.9+3621 (git sha1 84e9fa7, gcc 8.3.1 -fPIC -Os) */ +<<<<<<< HEAD +module user_project_wrapper(wb_clk_i, wb_rst_i, wbs_stb_i, wbs_cyc_i, wbs_we_i, wbs_sel_i, wbs_dat_i, wbs_adr_i, wbs_ack_o, wbs_dat_o, la_data_in, la_data_out, la_oen, io_in, io_out, io_oeb, analog_io, user_clock2); +======= module user_project_wrapper(user_clock2, wb_clk_i, wb_rst_i, wbs_ack_o, wbs_cyc_i, wbs_stb_i, wbs_we_i, vccd1, vssd1, vccd2, vssd2, vdda1, vssa1, vdda2, vssa2, analog_io, io_in, io_oeb, io_out, la_data_in, la_data_out, la_oen, wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i); +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d inout [30:0] analog_io; input [37:0] io_in; output [37:0] io_oeb; @@ -9,6 +13,8 @@ output [127:0] la_data_out; input [127:0] la_oen; input user_clock2; +<<<<<<< HEAD +======= input vccd1; input vccd2; input vdda1; @@ -17,6 +23,7 @@ input vssa2; input vssd1; input vssd2; +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d input wb_clk_i; input wb_rst_i; output wbs_ack_o; @@ -27,13 +34,21 @@ input [3:0] wbs_sel_i; input wbs_stb_i; input wbs_we_i; +<<<<<<< HEAD + ghazi_top_dffram_csv mprj ( +======= user_proj_example mprj ( +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d .io_in(io_in), .io_oeb(io_oeb), .io_out(io_out), .la_data_in(la_data_in), .la_data_out(la_data_out), .la_oen(la_oen), +<<<<<<< HEAD + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i) +======= .vccd1(vccd1), .vccd2(vccd2), .vdda1(vdda1), @@ -52,5 +67,6 @@ .wbs_sel_i(wbs_sel_i), .wbs_stb_i(wbs_stb_i), .wbs_we_i(wbs_we_i) +>>>>>>> f48448d4736bd6d56fed4dbf7f9cc50552d8745d ); endmodule
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index fa85ee2..714432f 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v
@@ -83,7 +83,10 @@ /*------------------------------*/ /* Include user project here */ /*------------------------------*/ -`include "user_proj_example.v" +`include "ghazi/ghazi_top_dffram_csv.v" +`include "ghazi/ghazi_top.v" +`include "ghazi/iccm_controller.v" +`include "ghazi/uart_rx_prog.v" // `ifdef USE_OPENRAM // `include "sram_1rw1r_32_256_8_sky130.v"
diff --git a/verilog/rtl/ghazi/ghazi_top.v b/verilog/rtl/ghazi/ghazi_top.v new file mode 100644 index 0000000..557f335 --- /dev/null +++ b/verilog/rtl/ghazi/ghazi_top.v
@@ -0,0 +1,22423 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ghazi_top ( + clk_i, + rst_lc_ni, + rst_ni, + ram_main_instr_req, + ram_main_instr_we, + ram_main_instr_addr, + ram_main_instr_wdata, + ram_main_instr_wmask, + ram_main_instr_rdata, + ram_main_instr_rvalid, + ram_main_instr_rerror, + ram_main_data_req, + ram_main_data_we, + ram_main_data_addr, + ram_main_data_wdata, + ram_main_data_wmask, + ram_main_data_rdata, + ram_main_data_rvalid, + ram_main_data_rerror, + jtag_tck_i, + jtag_tms_i, + jtag_trst_ni, + jtag_tdi_i, + jtag_tdo_o, + cio_gpio_gpio_p2d, + cio_gpio_gpio_d2p, + cio_gpio_gpio_en_d2p, + cio_uart_rx_p2d, + cio_uart_tx_d2p, + cio_uart_tx_en_d2p, + cio_spi_device_sck_p2d, + cio_spi_device_csb_p2d, + cio_spi_device_sdi_p2d, + cio_spi_device_sdo_d2p, + cio_spi_device_sdo_en_d2p, + ndmreset_req_o +); + localparam integer brqrv_pkg_RegFileFF = 0; + parameter integer BuraqRegFile = brqrv_pkg_RegFileFF; + localparam integer brqrv_pkg_RV32MSingleCycle = 3; + parameter integer BuraqM = brqrv_pkg_RV32MSingleCycle; + parameter [0:0] BuraqPipeLine = 0; + input clk_i; + input rst_lc_ni; + input rst_ni; + output wire ram_main_instr_req; + output wire ram_main_instr_we; + output wire [13:0] ram_main_instr_addr; + output wire [31:0] ram_main_instr_wdata; + output wire [31:0] ram_main_instr_wmask; + input wire [31:0] ram_main_instr_rdata; + input wire ram_main_instr_rvalid; + input wire [1:0] ram_main_instr_rerror; + output wire ram_main_data_req; + output wire ram_main_data_we; + output wire [13:0] ram_main_data_addr; + output wire [31:0] ram_main_data_wdata; + output wire [31:0] ram_main_data_wmask; + input wire [31:0] ram_main_data_rdata; + input wire ram_main_data_rvalid; + input wire [1:0] ram_main_data_rerror; + input jtag_tck_i; + input jtag_tms_i; + input jtag_trst_ni; + input jtag_tdi_i; + output wire jtag_tdo_o; + input [31:0] cio_gpio_gpio_p2d; + output wire [31:0] cio_gpio_gpio_d2p; + output wire [31:0] cio_gpio_gpio_en_d2p; + input cio_uart_rx_p2d; + output wire cio_uart_tx_d2p; + output wire cio_uart_tx_en_d2p; + input cio_spi_device_sck_p2d; + input cio_spi_device_csb_p2d; + input cio_spi_device_sdi_p2d; + output wire cio_spi_device_sdo_d2p; + output wire cio_spi_device_sdo_en_d2p; + output wire ndmreset_req_o; + localparam [31:0] JTAG_IDCODE = {4'h0, 16'h4f54, 11'h426, 1'b1}; + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + localparam signed [31:0] top_pkg_TL_DIW = 1; + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + localparam signed [31:0] top_pkg_TL_DUW = 16; + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + wire [2:0] unused_spi_device; + wire core_sleep_o; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] main_tl_srami_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] main_tl_srami_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] main_tl_sramd_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] main_tl_sramd_rsp; + wire [40:0] intr_vector; + wire intr_rv_timer_timer_expired_0_0; + wire intr_uart_tx_watermark; + wire intr_uart_rx_watermark; + wire intr_uart_tx_empty; + wire intr_uart_rx_overflow; + wire intr_uart_rx_frame_err; + wire intr_uart_rx_break_err; + wire intr_uart_rx_timeout; + wire intr_uart_rx_parity_err; + wire [31:0] intr_gpio_gpio; + wire irq_plic; + wire msip; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] gpio_tl_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] gpio_tl_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] uart_tl_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] uart_tl_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] rv_plic_tl_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] rv_plic_tl_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] rv_timer_tl_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] rv_timer_tl_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] main_tl_corei_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] main_tl_corei_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] main_tl_cored_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] main_tl_cored_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] main_tl_dm_sba_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] main_tl_dm_sba_rsp; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] main_tl_debug_mem_req; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] main_tl_debug_mem_rsp; + wire debug_req; + localparam integer brqrv_pkg_RV32BNone = 0; + buraq_core_top #( + .PMPEnable(1), + .PMPGranularity(0), + .PMPNumRegions(16), + .MHPMCounterNum(10), + .MHPMCounterWidth(32), + .RV32E(0), + .RV32M(BuraqM), + .RV32B(brqrv_pkg_RV32BNone), + .RegFile(BuraqRegFile), + .BranchTargetALU(1), + .WritebackStage(1), + .ICache(0), + .ICacheECC(0), + .BranchPredictor(0), + .DbgTriggerEn(1), + .SecureBuraq(0), + .PipeLine(BuraqPipeLine) + ) u_rv_buraq_core( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(1'b0), + .hart_id_i(32'b00000000000000000000000000000000), + .boot_addr_i(32'h00080000), + .tl_i_o(main_tl_corei_req), + .tl_i_i(main_tl_corei_rsp), + .tl_d_o(main_tl_cored_req), + .tl_d_i(main_tl_cored_rsp), + .irq_software_i(msip), + .irq_timer_i(intr_rv_timer_timer_expired_0_0), + .irq_external_i(irq_plic), + .esc_tx_i(), + .esc_rx_o(), + .debug_req_i(debug_req), + .fetch_enable_i(1'b1), + .core_sleep_o(core_sleep_o) + ); + tlul_adapter_sram #( + .SramAw(14), + .SramDw(32), + .Outstanding(2) + ) imem( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(main_tl_srami_req), + .tl_o(main_tl_srami_rsp), + .req_o(ram_main_instr_req), + .gnt_i(1'b1), + .we_o(ram_main_instr_we), + .addr_o(ram_main_instr_addr), + .wdata_o(ram_main_instr_wdata), + .wmask_o(ram_main_instr_wmask), + .rdata_i(ram_main_instr_rdata), + .rvalid_i(ram_main_instr_rvalid), + .rerror_i(ram_main_instr_rerror) + ); + tlul_adapter_sram #( + .SramAw(14), + .SramDw(32), + .Outstanding(2) + ) lmem( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(main_tl_sramd_req), + .tl_o(main_tl_sramd_rsp), + .req_o(ram_main_data_req), + .gnt_i(1'b1), + .we_o(ram_main_data_we), + .addr_o(ram_main_data_addr), + .wdata_o(ram_main_data_wdata), + .wmask_o(ram_main_data_wmask), + .rdata_i(ram_main_data_rdata), + .rvalid_i(ram_main_data_rvalid), + .rerror_i(ram_main_data_rerror) + ); + rv_dm #( + .NrHarts(1), + .IdcodeValue(JTAG_IDCODE) + ) u_dm_top( + .clk_i(clk_i), + .rst_ni(rst_lc_ni), + .testmode_i(1'b0), + .ndmreset_o(ndmreset_req_o), + .dmactive_o(), + .debug_req_o(debug_req), + .unavailable_i(1'b0), + .tl_d_i(main_tl_debug_mem_req), + .tl_d_o(main_tl_debug_mem_rsp), + .tl_h_o(main_tl_dm_sba_req), + .tl_h_i(main_tl_dm_sba_rsp), + .tck_i(jtag_tck_i), + .tms_i(jtag_tms_i), + .trst_ni(jtag_trst_ni), + .td_i(jtag_tdi_i), + .td_o(jtag_tdo_o), + .tdo_oe_o() + ); + tlul_gpio u_gpio( + .cio_gpio_i(cio_gpio_gpio_p2d), + .cio_gpio_o(cio_gpio_gpio_d2p), + .cio_gpio_en_o(cio_gpio_gpio_en_d2p), + .intr_gpio_o(intr_gpio_gpio), + .tl_i(gpio_tl_req), + .tl_o(gpio_tl_rsp), + .clk_i(clk_i), + .rst_ni(rst_ni) + ); + uart u_uart( + .cio_rx_i(cio_uart_rx_p2d), + .cio_tx_o(cio_uart_tx_d2p), + .cio_tx_en_o(cio_uart_tx_en_d2p), + .intr_tx_watermark_o(intr_uart_tx_watermark), + .intr_rx_watermark_o(intr_uart_rx_watermark), + .intr_tx_empty_o(intr_uart_tx_empty), + .intr_rx_overflow_o(intr_uart_rx_overflow), + .intr_rx_frame_err_o(intr_uart_rx_frame_err), + .intr_rx_break_err_o(intr_uart_rx_break_err), + .intr_rx_timeout_o(intr_uart_rx_timeout), + .intr_rx_parity_err_o(intr_uart_rx_parity_err), + .tl_i(uart_tl_req), + .tl_o(uart_tl_rsp), + .clk_i(clk_i), + .rst_ni(rst_ni) + ); + rv_plic u_rv_plic( + .tl_i(rv_plic_tl_req), + .tl_o(rv_plic_tl_rsp), + .intr_src_i(intr_vector), + .irq_o(irq_plic), + .irq_id_o(), + .msip_o(msip), + .clk_i(clk_i), + .rst_ni(rst_ni) + ); + rv_timer u_rv_timer( + .intr_timer_expired_0_0_o(intr_rv_timer_timer_expired_0_0), + .tl_i(rv_timer_tl_req), + .tl_o(rv_timer_tl_rsp), + .clk_i(clk_i), + .rst_ni(rst_ni) + ); + xbar ghazi_xbar( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_corei_i(main_tl_corei_req), + .tl_corei_o(main_tl_corei_rsp), + .tl_cored_i(main_tl_cored_req), + .tl_cored_o(main_tl_cored_rsp), + .tl_dm_sba_i(main_tl_dm_sba_req), + .tl_dm_sba_o(main_tl_dm_sba_rsp), + .tl_srami_o(main_tl_srami_req), + .tl_srami_i(main_tl_srami_rsp), + .tl_sramd_o(main_tl_sramd_req), + .tl_sramd_i(main_tl_sramd_rsp), + .tl_gpio_o(gpio_tl_req), + .tl_gpio_i(gpio_tl_rsp), + .tl_uart_o(uart_tl_req), + .tl_uart_i(uart_tl_rsp), + .tl_debug_mem_o(main_tl_debug_mem_req), + .tl_debug_mem_i(main_tl_debug_mem_rsp), + .tl_rv_plic_o(rv_plic_tl_req), + .tl_rv_plic_i(rv_plic_tl_rsp), + .tl_spi_device_o(), + .tl_spi_device_i(), + .tl_rv_timer_o(rv_timer_tl_req), + .tl_rv_timer_i(rv_timer_tl_rsp) + ); + assign unused_spi_device = {cio_spi_device_sck_p2d, cio_spi_device_csb_p2d, cio_spi_device_sdi_p2d}; + assign cio_spi_device_sdo_d2p = 1'b0; + assign cio_spi_device_sdo_en_d2p = 1'b0; + assign intr_vector = {intr_uart_rx_parity_err, intr_uart_rx_timeout, intr_uart_rx_break_err, intr_uart_rx_frame_err, intr_uart_rx_overflow, intr_uart_tx_empty, intr_uart_rx_watermark, intr_uart_tx_watermark, intr_gpio_gpio, 1'b0}; +endmodule // ghazi_top +module xbar ( + clk_i, + rst_ni, + tl_corei_i, + tl_corei_o, + tl_cored_i, + tl_cored_o, + tl_dm_sba_i, + tl_dm_sba_o, + tl_srami_o, + tl_srami_i, + tl_sramd_o, + tl_sramd_i, + tl_gpio_o, + tl_gpio_i, + tl_uart_o, + tl_uart_i, + tl_debug_mem_o, + tl_debug_mem_i, + tl_rv_plic_o, + tl_rv_plic_i, + tl_spi_device_o, + tl_spi_device_i, + tl_rv_timer_o, + tl_rv_timer_i +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_corei_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_corei_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_cored_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_cored_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_dm_sba_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_dm_sba_o; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_srami_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_srami_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sramd_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sramd_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_gpio_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_gpio_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_uart_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_uart_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_debug_mem_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_debug_mem_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_rv_plic_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_rv_plic_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_spi_device_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_spi_device_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_rv_timer_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_rv_timer_i; + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_s1n_12_us_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_s1n_12_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (7 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (7 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_s1n_12_ds_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (7 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (7 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_s1n_12_ds_d2h; + reg [2:0] dev_sel_s1n_12; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_s1n_18_us_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_s1n_18_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_s1n_18_ds_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_s1n_18_ds_d2h; + reg [1:0] dev_sel_s1n_18; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_19_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_19_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_19_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_19_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_20_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_20_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_20_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_20_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_21_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_21_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_21_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_21_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_25_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_25_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_25_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_25_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_26_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_26_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_26_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_26_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_29_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_29_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_29_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_29_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_30_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_30_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_30_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_30_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_sm1_31_us_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (2 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (2 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_sm1_31_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_sm1_31_ds_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_sm1_31_ds_d2h; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_s1n_35_us_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_s1n_35_us_d2h; + wire [(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (7 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (7 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15)):(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] tl_s1n_35_ds_h2d; + wire [(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (7 * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (7 * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW)):(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)] tl_s1n_35_ds_d2h; + reg [2:0] dev_sel_s1n_35; + wire [31:0] addr_test; + assign addr_test = tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)]; + assign tl_sm1_21_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (6 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (6 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_21_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_25_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (5 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (5 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_25_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_26_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (4 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (4 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_26_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_20_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (3 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (3 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_20_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_29_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (2 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (2 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_29_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_30_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_30_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_31_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_12_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_12_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_31_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_19_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_18_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_18_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_19_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_20_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_18_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_18_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_20_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_19_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (6 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (6 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_19_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_21_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (5 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (5 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_21_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_25_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (4 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (4 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_25_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_26_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (3 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (3 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_26_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_29_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (2 * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (2 * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_29_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_30_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_30_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_sm1_31_us_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] = tl_s1n_35_ds_h2d[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]; + assign tl_s1n_35_ds_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] = tl_sm1_31_us_d2h[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]; + assign tl_s1n_12_us_h2d = tl_cored_i; + assign tl_cored_o = tl_s1n_12_us_d2h; + assign tl_s1n_18_us_h2d = tl_corei_i; + assign tl_corei_o = tl_s1n_18_us_d2h; + assign tl_srami_o = tl_sm1_19_ds_h2d; + assign tl_sm1_19_ds_d2h = tl_srami_i; + assign tl_sramd_o = tl_sm1_21_ds_h2d; + assign tl_sm1_21_ds_d2h = tl_sramd_i; + assign tl_gpio_o = tl_sm1_25_ds_h2d; + assign tl_sm1_25_ds_d2h = tl_gpio_i; + assign tl_uart_o = tl_sm1_26_ds_h2d; + assign tl_sm1_26_ds_d2h = tl_uart_i; + assign tl_rv_plic_o = tl_sm1_29_ds_h2d; + assign tl_sm1_29_ds_d2h = tl_rv_plic_i; + assign tl_debug_mem_o = tl_sm1_20_ds_h2d; + assign tl_sm1_20_ds_d2h = tl_debug_mem_i; + assign tl_spi_device_o = tl_sm1_30_ds_h2d; + assign tl_sm1_30_ds_d2h = tl_spi_device_i; + assign tl_rv_timer_o = tl_sm1_31_ds_h2d; + assign tl_sm1_31_ds_d2h = tl_rv_timer_i; + assign tl_s1n_35_us_h2d = tl_dm_sba_i; + assign tl_dm_sba_o = tl_s1n_35_us_d2h; + always @(*) + if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_SRAMD) == ADDR_SPACE_SRAMD) + dev_sel_s1n_12 = 3'b000; + else if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_GPIO) == ADDR_SPACE_GPIO) + dev_sel_s1n_12 = 3'b001; + else if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_UART) == ADDR_SPACE_UART) + dev_sel_s1n_12 = 3'b010; + else if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_DEBUG_MEM) == ADDR_SPACE_DEBUG_MEM) + dev_sel_s1n_12 = 3'b011; + else if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_RV_PLIC) == ADDR_SPACE_RV_PLIC) + dev_sel_s1n_12 = 3'b100; + else if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_SPI_DEVICE) == ADDR_SPACE_SPI_DEVICE) + dev_sel_s1n_12 = 3'b101; + else if ((tl_s1n_12_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_RV_TIMER) == ADDR_SPACE_RV_TIMER) + dev_sel_s1n_12 = 3'b110; + else + dev_sel_s1n_12 = 3'b111; + always @(*) + if ((tl_s1n_18_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_SRAMI) == ADDR_SPACE_SRAMI) + dev_sel_s1n_18 = 2'b00; + else if ((tl_s1n_18_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_DEBUG_MEM) == ADDR_SPACE_DEBUG_MEM) + dev_sel_s1n_18 = 2'b01; + else + dev_sel_s1n_18 = 2'b10; + always @(*) + if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_SRAMI) == ADDR_SPACE_SRAMI) + dev_sel_s1n_35 = 3'b000; + else if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_SRAMD) == ADDR_SPACE_SRAMD) + dev_sel_s1n_35 = 3'b001; + else if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_GPIO) == ADDR_SPACE_GPIO) + dev_sel_s1n_35 = 3'b010; + else if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_UART) == ADDR_SPACE_UART) + dev_sel_s1n_35 = 3'b011; + else if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_RV_PLIC) == ADDR_SPACE_RV_PLIC) + dev_sel_s1n_35 = 3'b100; + else if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_SPI_DEVICE) == ADDR_SPACE_SPI_DEVICE) + dev_sel_s1n_35 = 3'b101; + else if ((tl_s1n_35_us_h2d[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] & ~ADDR_MASK_RV_TIMER) == ADDR_SPACE_RV_TIMER) + dev_sel_s1n_35 = 3'b110; + else + dev_sel_s1n_35 = 3'b111; + tlul_socket_1n #( + .HReqDepth(4'h0), + .HRspDepth(4'h0), + .DReqDepth(16'h0000), + .DRspDepth(16'h0000), + .N(7) + ) u_s1n_12( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_s1n_12_us_h2d), + .tl_h_o(tl_s1n_12_us_d2h), + .tl_d_o(tl_s1n_12_ds_h2d), + .tl_d_i(tl_s1n_12_ds_d2h), + .dev_select_i(dev_sel_s1n_12) + ); + tlul_socket_1n #( + .HReqDepth(4'h0), + .HRspDepth(4'h0), + .DReqDepth(8'h00), + .DRspDepth(8'h00), + .N(2) + ) u_s1n_18( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_s1n_18_us_h2d), + .tl_h_o(tl_s1n_18_us_d2h), + .tl_d_o(tl_s1n_18_ds_h2d), + .tl_d_i(tl_s1n_18_ds_d2h), + .dev_select_i(dev_sel_s1n_18) + ); + tlul_socket_m1 #( + .HReqDepth(12'h000), + .HRspDepth(12'h000), + .DReqDepth(4'h0), + .DRspDepth(4'h0), + .M(2) + ) u_sm1_19( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_19_us_h2d), + .tl_h_o(tl_sm1_19_us_d2h), + .tl_d_o(tl_sm1_19_ds_h2d), + .tl_d_i(tl_sm1_19_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(8'h00), + .HRspDepth(8'h00), + .DReqPass(1'b0), + .DRspPass(1'b0), + .M(2) + ) u_sm1_20( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_20_us_h2d), + .tl_h_o(tl_sm1_20_us_d2h), + .tl_d_o(tl_sm1_20_ds_h2d), + .tl_d_i(tl_sm1_20_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(12'h000), + .HRspDepth(12'h000), + .DReqDepth(4'h0), + .DRspDepth(4'h0), + .M(2) + ) u_sm1_21( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_21_us_h2d), + .tl_h_o(tl_sm1_21_us_d2h), + .tl_d_o(tl_sm1_21_ds_h2d), + .tl_d_i(tl_sm1_21_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(8'h00), + .HRspDepth(8'h00), + .DReqDepth(4'h0), + .DRspDepth(4'h0), + .M(2) + ) u_sm1_25( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_25_us_h2d), + .tl_h_o(tl_sm1_25_us_d2h), + .tl_d_o(tl_sm1_25_ds_h2d), + .tl_d_i(tl_sm1_25_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(8'h00), + .HRspDepth(8'h00), + .DReqDepth(4'h0), + .DRspDepth(4'h0), + .M(2) + ) u_sm1_26( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_26_us_h2d), + .tl_h_o(tl_sm1_26_us_d2h), + .tl_d_o(tl_sm1_26_ds_h2d), + .tl_d_i(tl_sm1_26_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(8'h00), + .HRspDepth(8'h00), + .DReqPass(1'b0), + .DRspPass(1'b0), + .M(2) + ) u_sm1_29( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_29_us_h2d), + .tl_h_o(tl_sm1_29_us_d2h), + .tl_d_o(tl_sm1_29_ds_h2d), + .tl_d_i(tl_sm1_29_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(8'h00), + .HRspDepth(8'h00), + .DReqDepth(4'h0), + .DRspDepth(4'h0), + .M(2) + ) u_sm1_30( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_30_us_h2d), + .tl_h_o(tl_sm1_30_us_d2h), + .tl_d_o(tl_sm1_30_ds_h2d), + .tl_d_i(tl_sm1_30_ds_d2h) + ); + tlul_socket_m1 #( + .HReqDepth(8'h00), + .HRspDepth(8'h00), + .DReqDepth(4'h0), + .DRspDepth(4'h0), + .M(2) + ) u_sm1_31( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_sm1_31_us_h2d), + .tl_h_o(tl_sm1_31_us_d2h), + .tl_d_o(tl_sm1_31_ds_h2d), + .tl_d_i(tl_sm1_31_ds_d2h) + ); + tlul_socket_1n #( + .HReqDepth(4'h0), + .HRspDepth(4'h0), + .DReqDepth(16'h0000), + .DRspDepth(16'h0000), + .N(7) + ) u_s1n_35( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_s1n_35_us_h2d), + .tl_h_o(tl_s1n_35_us_d2h), + .tl_d_o(tl_s1n_35_ds_h2d), + .tl_d_i(tl_s1n_35_ds_d2h), + .dev_select_i(dev_sel_s1n_12) + ); +endmodule +module buraq_core_top ( + clk_i, + rst_ni, + test_en_i, + hart_id_i, + boot_addr_i, + tl_i_o, + tl_i_i, + tl_d_o, + tl_d_i, + irq_software_i, + irq_timer_i, + irq_external_i, + esc_tx_i, + esc_rx_o, + debug_req_i, + fetch_enable_i, + core_sleep_o +); + parameter [0:0] PMPEnable = 1'b0; + parameter [31:0] PMPGranularity = 0; + parameter [31:0] PMPNumRegions = 4; + parameter [31:0] MHPMCounterNum = 10; + parameter [31:0] MHPMCounterWidth = 32; + parameter [0:0] RV32E = 0; + localparam integer brqrv_pkg_RV32MSingleCycle = 3; + parameter integer RV32M = brqrv_pkg_RV32MSingleCycle; + localparam integer brqrv_pkg_RV32BNone = 0; + parameter integer RV32B = brqrv_pkg_RV32BNone; + localparam integer brqrv_pkg_RegFileFF = 0; + parameter integer RegFile = brqrv_pkg_RegFileFF; + parameter [0:0] BranchTargetALU = 1'b1; + parameter [0:0] WritebackStage = 1'b1; + parameter [0:0] ICache = 1'b0; + parameter [0:0] ICacheECC = 1'b0; + parameter [0:0] BranchPredictor = 1'b0; + parameter [0:0] DbgTriggerEn = 1'b1; + parameter [0:0] SecureBuraq = 1'b0; + parameter [31:0] DmHaltAddr = 32'h1a110800; + parameter [31:0] DmExceptionAddr = 32'h1a110808; + parameter [0:0] PipeLine = 1'b0; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire [31:0] hart_id_i; + input wire [31:0] boot_addr_i; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i_o; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_i_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_d_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_d_i; + input wire irq_software_i; + input wire irq_timer_i; + input wire irq_external_i; + input wire [1:0] esc_tx_i; + output wire [1:0] esc_rx_o; + input wire debug_req_i; + input wire fetch_enable_i; + output wire core_sleep_o; + localparam signed [31:0] TL_AW = 32; + localparam signed [31:0] TL_DW = 32; + localparam signed [31:0] TL_AIW = 8; + localparam signed [31:0] TL_DIW = 1; + localparam signed [31:0] TL_DUW = 16; + localparam signed [31:0] TL_DBW = TL_DW >> 3; + localparam signed [31:0] TL_SZW = $clog2($clog2(TL_DBW) + 1); + localparam signed [31:0] FLASH_BANKS = 2; + localparam signed [31:0] FLASH_PAGES_PER_BANK = 256; + localparam signed [31:0] FLASH_WORDS_PER_PAGE = 128; + localparam signed [31:0] FLASH_INFO_TYPES = 2; + localparam signed [(FLASH_INFO_TYPES * 32) - 1:0] FLASH_INFO_PER_BANK = {32'sd4, 32'sd4}; + localparam signed [31:0] FLASH_DATA_WIDTH = 64; + localparam signed [31:0] FLASH_METADATA_WIDTH = 12; + localparam signed [31:0] NUM_AST_ALERTS = 7; + localparam signed [31:0] NUM_IO_RAILS = 2; + localparam signed [31:0] ENTROPY_STREAM = 4; + localparam signed [31:0] ADC_CHANNELS = 2; + localparam signed [31:0] ADC_DATAW = 10; + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + localparam signed [31:0] FifoPass = (PipeLine ? 1'b0 : 1'b1); + localparam signed [31:0] FifoDepth = (PipeLine ? 4'h2 : 4'h0); + wire instr_req; + wire instr_gnt; + wire instr_rvalid; + wire [31:0] instr_addr; + wire [31:0] instr_rdata; + wire instr_err; + wire data_req; + wire data_gnt; + wire data_rvalid; + wire data_we; + wire [3:0] data_be; + wire [31:0] data_addr; + wire [31:0] data_wdata; + wire [31:0] data_rdata; + wire data_err; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i_brqrv2fifo; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_i_fifo2brqrv; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_d_brqrv2fifo; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_d_fifo2brqrv; + wire irq_nm; + prim_esc_receiver i_prim_esc_receiver( + .clk_i(clk_i), + .rst_ni(rst_ni), + .esc_en_o(irq_nm), + .esc_rx_o(esc_rx_o), + .esc_tx_i(esc_tx_i) + ); + wire alert_minor; + wire alert_major; + wire unused_alert_minor; + wire unused_alert_major; + assign unused_alert_minor = alert_minor; + assign unused_alert_major = alert_major; + brqrv_core #( + .PMPEnable(PMPEnable), + .PMPGranularity(PMPGranularity), + .PMPNumRegions(PMPNumRegions), + .MHPMCounterNum(MHPMCounterNum), + .MHPMCounterWidth(MHPMCounterWidth), + .RV32E(RV32E), + .RV32M(RV32M), + .RV32B(RV32B), + .RegFile(RegFile), + .BranchTargetALU(BranchTargetALU), + .WritebackStage(WritebackStage), + .ICache(ICache), + .ICacheECC(ICacheECC), + .BranchPredictor(BranchPredictor), + .DbgTriggerEn(DbgTriggerEn), + .SecureBuraq(SecureBuraq), + .DmHaltAddr(DmHaltAddr), + .DmExceptionAddr(DmExceptionAddr) + ) u_core( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .hart_id_i(hart_id_i), + .boot_addr_i(boot_addr_i), + .instr_req_o(instr_req), + .instr_gnt_i(instr_gnt), + .instr_rvalid_i(instr_rvalid), + .instr_addr_o(instr_addr), + .instr_rdata_i(instr_rdata), + .instr_err_i(instr_err), + .data_req_o(data_req), + .data_gnt_i(data_gnt), + .data_rvalid_i(data_rvalid), + .data_we_o(data_we), + .data_be_o(data_be), + .data_addr_o(data_addr), + .data_wdata_o(data_wdata), + .data_rdata_i(data_rdata), + .data_err_i(data_err), + .irq_software_i(irq_software_i), + .irq_timer_i(irq_timer_i), + .irq_external_i(irq_external_i), + .irq_fast_i({15 {1'sb0}}), + .irq_nm_i(irq_nm), + .debug_req_i(debug_req_i), + .fetch_enable_i(fetch_enable_i), + .alert_minor_o(alert_minor), + .alert_major_o(alert_major), + .core_sleep_o(core_sleep_o) + ); + tlul_adapter_host #(.MAX_REQS(2)) tl_adapter_host_i_brqrv( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_i(instr_req), + .gnt_o(instr_gnt), + .addr_i(instr_addr), + .we_i(1'b0), + .wdata_i(32'b00000000000000000000000000000000), + .be_i(4'hf), + .valid_o(instr_rvalid), + .rdata_o(instr_rdata), + .err_o(instr_err), + .tl_o(tl_i_brqrv2fifo), + .tl_i(tl_i_fifo2brqrv) + ); + tlul_fifo_sync #( + .ReqPass(FifoPass), + .RspPass(FifoPass), + .ReqDepth(FifoDepth), + .RspDepth(FifoDepth) + ) fifo_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_i_brqrv2fifo), + .tl_h_o(tl_i_fifo2brqrv), + .tl_d_o(tl_i_o), + .tl_d_i(tl_i_i), + .spare_req_i(1'b0), + .spare_req_o(), + .spare_rsp_i(1'b0), + .spare_rsp_o() + ); + tlul_adapter_host #(.MAX_REQS(2)) tl_adapter_host_d_brqrv( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_i(data_req), + .gnt_o(data_gnt), + .addr_i(data_addr), + .we_i(data_we), + .wdata_i(data_wdata), + .be_i(data_be), + .valid_o(data_rvalid), + .rdata_o(data_rdata), + .err_o(data_err), + .tl_o(tl_d_brqrv2fifo), + .tl_i(tl_d_fifo2brqrv) + ); + tlul_fifo_sync #( + .ReqPass(FifoPass), + .RspPass(FifoPass), + .ReqDepth(FifoDepth), + .RspDepth(FifoDepth) + ) fifo_d( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_d_brqrv2fifo), + .tl_h_o(tl_d_fifo2brqrv), + .tl_d_o(tl_d_o), + .tl_d_i(tl_d_i), + .spare_req_i(1'b0), + .spare_req_o(), + .spare_rsp_i(1'b0), + .spare_rsp_o() + ); +endmodule +module brqrv_core ( + clk_i, + rst_ni, + test_en_i, + hart_id_i, + boot_addr_i, + instr_req_o, + instr_gnt_i, + instr_rvalid_i, + instr_addr_o, + instr_rdata_i, + instr_err_i, + data_req_o, + data_gnt_i, + data_rvalid_i, + data_we_o, + data_be_o, + data_addr_o, + data_wdata_o, + data_rdata_i, + data_err_i, + irq_software_i, + irq_timer_i, + irq_external_i, + irq_fast_i, + irq_nm_i, + debug_req_i, + fetch_enable_i, + alert_minor_o, + alert_major_o, + core_sleep_o +); + parameter [0:0] PMPEnable = 1'b0; + parameter [31:0] PMPGranularity = 0; + parameter [31:0] PMPNumRegions = 4; + parameter [31:0] MHPMCounterNum = 0; + parameter [31:0] MHPMCounterWidth = 40; + parameter [0:0] RV32E = 1'b0; + localparam integer brqrv_pkg_RV32MFast = 2; + parameter integer RV32M = brqrv_pkg_RV32MFast; + localparam integer brqrv_pkg_RV32BNone = 0; + parameter integer RV32B = brqrv_pkg_RV32BNone; + localparam integer brqrv_pkg_RegFileFF = 0; + parameter integer RegFile = brqrv_pkg_RegFileFF; + parameter [0:0] BranchTargetALU = 1'b0; + parameter [0:0] WritebackStage = 1'b0; + parameter [0:0] ICache = 1'b0; + parameter [0:0] ICacheECC = 1'b0; + parameter [0:0] BranchPredictor = 1'b0; + parameter [0:0] DbgTriggerEn = 1'b0; + parameter [0:0] SecureBuraq = 1'b0; + parameter [31:0] DmHaltAddr = 32'h1a110800; + parameter [31:0] DmExceptionAddr = 32'h1a110808; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire [31:0] hart_id_i; + input wire [31:0] boot_addr_i; + output wire instr_req_o; + input wire instr_gnt_i; + input wire instr_rvalid_i; + output wire [31:0] instr_addr_o; + input wire [31:0] instr_rdata_i; + input wire instr_err_i; + output wire data_req_o; + input wire data_gnt_i; + input wire data_rvalid_i; + output wire data_we_o; + output wire [3:0] data_be_o; + output wire [31:0] data_addr_o; + output wire [31:0] data_wdata_o; + input wire [31:0] data_rdata_i; + input wire data_err_i; + input wire irq_software_i; + input wire irq_timer_i; + input wire irq_external_i; + input wire [14:0] irq_fast_i; + input wire irq_nm_i; + input wire debug_req_i; + input wire fetch_enable_i; + output wire alert_minor_o; + output wire alert_major_o; + output wire core_sleep_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + localparam [31:0] PMP_NUM_CHAN = 2; + localparam [0:0] DataIndTiming = SecureBuraq; + localparam [0:0] DummyInstructions = SecureBuraq; + localparam [0:0] SpecBranch = PMPEnable & (PMPNumRegions == 16); + localparam [0:0] RegFileECC = SecureBuraq; + localparam [31:0] RegFileDataWidth = (RegFileECC ? 39 : 32); + wire dummy_instr_id; + wire instr_valid_id; + wire instr_new_id; + wire [31:0] instr_rdata_id; + wire [31:0] instr_rdata_alu_id; + wire [15:0] instr_rdata_c_id; + wire instr_is_compressed_id; + wire instr_bp_taken_id; + wire instr_fetch_err; + wire instr_fetch_err_plus2; + wire illegal_c_insn_id; + wire [31:0] pc_if; + wire [31:0] pc_id; + wire [31:0] pc_wb; + wire [67:0] imd_val_d_ex; + wire [67:0] imd_val_q_ex; + wire [1:0] imd_val_we_ex; + wire data_ind_timing; + wire dummy_instr_en; + wire [2:0] dummy_instr_mask; + wire dummy_instr_seed_en; + wire [31:0] dummy_instr_seed; + wire icache_enable; + wire icache_inval; + wire pc_mismatch_alert; + wire instr_first_cycle_id; + wire instr_valid_clear; + wire pc_set; + wire pc_set_spec; + wire nt_branch_mispredict; + wire [2:0] pc_mux_id; + wire [1:0] exc_pc_mux_id; + wire [5:0] exc_cause; + wire lsu_load_err; + wire lsu_store_err; + wire lsu_addr_incr_req; + wire [31:0] lsu_addr_last; + wire [31:0] branch_target_ex; + wire branch_decision; + wire ctrl_busy; + wire if_busy; + wire lsu_busy; + wire core_busy_d; + reg core_busy_q; + wire [4:0] rf_raddr_a; + wire [31:0] rf_rdata_a; + wire [4:0] rf_raddr_b; + wire [31:0] rf_rdata_b; + wire rf_ren_a; + wire rf_ren_b; + wire [4:0] rf_waddr_wb; + wire [31:0] rf_wdata_wb; + wire [31:0] rf_wdata_fwd_wb; + wire [31:0] rf_wdata_lsu; + wire rf_we_wb; + wire rf_we_lsu; + wire [4:0] rf_waddr_id; + wire [31:0] rf_wdata_id; + wire rf_we_id; + wire rf_rd_a_wb_match; + wire rf_rd_b_wb_match; + wire [5:0] alu_operator_ex; + wire [31:0] alu_operand_a_ex; + wire [31:0] alu_operand_b_ex; + wire [31:0] bt_a_operand; + wire [31:0] bt_b_operand; + wire [31:0] alu_adder_result_ex; + wire [31:0] result_ex; + wire mult_en_ex; + wire div_en_ex; + wire mult_sel_ex; + wire div_sel_ex; + wire [1:0] multdiv_operator_ex; + wire [1:0] multdiv_signed_mode_ex; + wire [31:0] multdiv_operand_a_ex; + wire [31:0] multdiv_operand_b_ex; + wire multdiv_ready_id; + wire csr_access; + wire [1:0] csr_op; + wire csr_op_en; + wire [11:0] csr_addr; + wire [31:0] csr_rdata; + wire [31:0] csr_wdata; + wire illegal_csr_insn_id; + wire lsu_we; + wire [1:0] lsu_type; + wire lsu_sign_ext; + wire lsu_req; + wire [31:0] lsu_wdata; + wire lsu_req_done; + wire id_in_ready; + wire ex_valid; + wire lsu_resp_valid; + wire instr_req_int; + wire en_wb; + wire [1:0] instr_type_wb; + wire ready_wb; + wire rf_write_wb; + wire outstanding_load_wb; + wire outstanding_store_wb; + wire irq_pending; + wire nmi_mode; + wire [17:0] irqs; + wire csr_mstatus_mie; + wire [31:0] csr_mepc; + wire [31:0] csr_depc; + wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr; + wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg; + wire [PMP_NUM_CHAN - 1:0] pmp_req_err; + wire instr_req_out; + wire data_req_out; + wire csr_save_if; + wire csr_save_id; + wire csr_save_wb; + wire csr_restore_mret_id; + wire csr_restore_dret_id; + wire csr_save_cause; + wire csr_mtvec_init; + wire [31:0] csr_mtvec; + wire [31:0] csr_mtval; + wire csr_mstatus_tw; + wire [1:0] priv_mode_id; + wire [1:0] priv_mode_if; + wire [1:0] priv_mode_lsu; + wire debug_mode; + wire [2:0] debug_cause; + wire debug_csr_save; + wire debug_single_step; + wire debug_ebreakm; + wire debug_ebreaku; + wire trigger_match; + wire instr_id_done; + wire instr_id_done_compressed; + wire instr_done_wb; + wire perf_iside_wait; + wire perf_dside_wait; + wire perf_mul_wait; + wire perf_div_wait; + wire perf_jump; + wire perf_branch; + wire perf_tbranch; + wire perf_load; + wire perf_store; + wire illegal_insn_id; + wire unused_illegal_insn_id; + wire clk; + wire clock_en; + assign core_busy_d = (ctrl_busy | if_busy) | lsu_busy; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + core_busy_q <= 1'b0; + else + core_busy_q <= core_busy_d; + reg fetch_enable_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + fetch_enable_q <= 1'b0; + else if (fetch_enable_i) + fetch_enable_q <= 1'b1; + assign clock_en = fetch_enable_q & (((core_busy_q | debug_req_i) | irq_pending) | irq_nm_i); + assign core_sleep_o = ~clock_en; + prim_clock_gating core_clock_gate_i( + .clk_i(clk_i), + .en_i(clock_en), + .test_en_i(test_en_i), + .clk_o(clk) + ); + brqrv_ifu #( + .DmHaltAddr(DmHaltAddr), + .DmExceptionAddr(DmExceptionAddr), + .DummyInstructions(DummyInstructions), + .ICache(ICache), + .ICacheECC(ICacheECC), + .SecureBuraq(SecureBuraq), + .BranchPredictor(BranchPredictor) + ) if_stage_i( + .clk_i(clk), + .rst_ni(rst_ni), + .boot_addr_i(boot_addr_i), + .req_i(instr_req_int), + .instr_req_o(instr_req_out), + .instr_addr_o(instr_addr_o), + .instr_gnt_i(instr_gnt_i), + .instr_rvalid_i(instr_rvalid_i), + .instr_rdata_i(instr_rdata_i), + .instr_err_i(instr_err_i), + .instr_pmp_err_i(pmp_req_err[PMP_I]), + .instr_valid_id_o(instr_valid_id), + .instr_new_id_o(instr_new_id), + .instr_rdata_id_o(instr_rdata_id), + .instr_rdata_alu_id_o(instr_rdata_alu_id), + .instr_rdata_c_id_o(instr_rdata_c_id), + .instr_is_compressed_id_o(instr_is_compressed_id), + .instr_bp_taken_o(instr_bp_taken_id), + .instr_fetch_err_o(instr_fetch_err), + .instr_fetch_err_plus2_o(instr_fetch_err_plus2), + .illegal_c_insn_id_o(illegal_c_insn_id), + .dummy_instr_id_o(dummy_instr_id), + .pc_if_o(pc_if), + .pc_id_o(pc_id), + .instr_valid_clear_i(instr_valid_clear), + .pc_set_i(pc_set), + .pc_set_spec_i(pc_set_spec), + .pc_mux_i(pc_mux_id), + .nt_branch_mispredict_i(nt_branch_mispredict), + .exc_pc_mux_i(exc_pc_mux_id), + .exc_cause(exc_cause), + .dummy_instr_en_i(dummy_instr_en), + .dummy_instr_mask_i(dummy_instr_mask), + .dummy_instr_seed_en_i(dummy_instr_seed_en), + .dummy_instr_seed_i(dummy_instr_seed), + .icache_enable_i(icache_enable), + .icache_inval_i(icache_inval), + .branch_target_ex_i(branch_target_ex), + .csr_mepc_i(csr_mepc), + .csr_depc_i(csr_depc), + .csr_mtvec_i(csr_mtvec), + .csr_mtvec_init_o(csr_mtvec_init), + .id_in_ready_i(id_in_ready), + .pc_mismatch_alert_o(pc_mismatch_alert), + .if_busy_o(if_busy) + ); + assign perf_iside_wait = id_in_ready & ~instr_valid_id; + assign instr_req_o = instr_req_out & ~pmp_req_err[PMP_I]; + brqrv_idu #( + .RV32E(RV32E), + .RV32M(RV32M), + .RV32B(RV32B), + .BranchTargetALU(BranchTargetALU), + .DataIndTiming(DataIndTiming), + .SpecBranch(SpecBranch), + .WritebackStage(WritebackStage), + .BranchPredictor(BranchPredictor) + ) id_stage_i( + .clk_i(clk), + .rst_ni(rst_ni), + .ctrl_busy_o(ctrl_busy), + .illegal_insn_o(illegal_insn_id), + .instr_valid_i(instr_valid_id), + .instr_rdata_i(instr_rdata_id), + .instr_rdata_alu_i(instr_rdata_alu_id), + .instr_rdata_c_i(instr_rdata_c_id), + .instr_is_compressed_i(instr_is_compressed_id), + .instr_bp_taken_i(instr_bp_taken_id), + .branch_decision_i(branch_decision), + .instr_first_cycle_id_o(instr_first_cycle_id), + .instr_valid_clear_o(instr_valid_clear), + .id_in_ready_o(id_in_ready), + .instr_req_o(instr_req_int), + .pc_set_o(pc_set), + .pc_set_spec_o(pc_set_spec), + .pc_mux_o(pc_mux_id), + .nt_branch_mispredict_o(nt_branch_mispredict), + .exc_pc_mux_o(exc_pc_mux_id), + .exc_cause_o(exc_cause), + .icache_inval_o(icache_inval), + .instr_fetch_err_i(instr_fetch_err), + .instr_fetch_err_plus2_i(instr_fetch_err_plus2), + .illegal_c_insn_i(illegal_c_insn_id), + .pc_id_i(pc_id), + .ex_valid_i(ex_valid), + .lsu_resp_valid_i(lsu_resp_valid), + .alu_operator_ex_o(alu_operator_ex), + .alu_operand_a_ex_o(alu_operand_a_ex), + .alu_operand_b_ex_o(alu_operand_b_ex), + .imd_val_q_ex_o(imd_val_q_ex), + .imd_val_d_ex_i(imd_val_d_ex), + .imd_val_we_ex_i(imd_val_we_ex), + .bt_a_operand_o(bt_a_operand), + .bt_b_operand_o(bt_b_operand), + .mult_en_ex_o(mult_en_ex), + .div_en_ex_o(div_en_ex), + .mult_sel_ex_o(mult_sel_ex), + .div_sel_ex_o(div_sel_ex), + .multdiv_operator_ex_o(multdiv_operator_ex), + .multdiv_signed_mode_ex_o(multdiv_signed_mode_ex), + .multdiv_operand_a_ex_o(multdiv_operand_a_ex), + .multdiv_operand_b_ex_o(multdiv_operand_b_ex), + .multdiv_ready_id_o(multdiv_ready_id), + .csr_access_o(csr_access), + .csr_op_o(csr_op), + .csr_op_en_o(csr_op_en), + .csr_save_if_o(csr_save_if), + .csr_save_id_o(csr_save_id), + .csr_save_wb_o(csr_save_wb), + .csr_restore_mret_id_o(csr_restore_mret_id), + .csr_restore_dret_id_o(csr_restore_dret_id), + .csr_save_cause_o(csr_save_cause), + .csr_mtval_o(csr_mtval), + .priv_mode_i(priv_mode_id), + .csr_mstatus_tw_i(csr_mstatus_tw), + .illegal_csr_insn_i(illegal_csr_insn_id), + .data_ind_timing_i(data_ind_timing), + .lsu_req_o(lsu_req), + .lsu_we_o(lsu_we), + .lsu_type_o(lsu_type), + .lsu_sign_ext_o(lsu_sign_ext), + .lsu_wdata_o(lsu_wdata), + .lsu_req_done_i(lsu_req_done), + .lsu_addr_incr_req_i(lsu_addr_incr_req), + .lsu_addr_last_i(lsu_addr_last), + .lsu_load_err_i(lsu_load_err), + .lsu_store_err_i(lsu_store_err), + .csr_mstatus_mie_i(csr_mstatus_mie), + .irq_pending_i(irq_pending), + .irqs_i(irqs), + .irq_nm_i(irq_nm_i), + .nmi_mode_o(nmi_mode), + .debug_mode_o(debug_mode), + .debug_cause_o(debug_cause), + .debug_csr_save_o(debug_csr_save), + .debug_req_i(debug_req_i), + .debug_single_step_i(debug_single_step), + .debug_ebreakm_i(debug_ebreakm), + .debug_ebreaku_i(debug_ebreaku), + .trigger_match_i(trigger_match), + .result_ex_i(result_ex), + .csr_rdata_i(csr_rdata), + .rf_raddr_a_o(rf_raddr_a), + .rf_rdata_a_i(rf_rdata_a), + .rf_raddr_b_o(rf_raddr_b), + .rf_rdata_b_i(rf_rdata_b), + .rf_ren_a_o(rf_ren_a), + .rf_ren_b_o(rf_ren_b), + .rf_waddr_id_o(rf_waddr_id), + .rf_wdata_id_o(rf_wdata_id), + .rf_we_id_o(rf_we_id), + .rf_rd_a_wb_match_o(rf_rd_a_wb_match), + .rf_rd_b_wb_match_o(rf_rd_b_wb_match), + .rf_waddr_wb_i(rf_waddr_wb), + .rf_wdata_fwd_wb_i(rf_wdata_fwd_wb), + .rf_write_wb_i(rf_write_wb), + .en_wb_o(en_wb), + .instr_type_wb_o(instr_type_wb), + .ready_wb_i(ready_wb), + .outstanding_load_wb_i(outstanding_load_wb), + .outstanding_store_wb_i(outstanding_store_wb), + .perf_jump_o(perf_jump), + .perf_branch_o(perf_branch), + .perf_tbranch_o(perf_tbranch), + .perf_dside_wait_o(perf_dside_wait), + .perf_mul_wait_o(perf_mul_wait), + .perf_div_wait_o(perf_div_wait), + .instr_id_done_o(instr_id_done), + .instr_id_done_compressed_o(instr_id_done_compressed) + ); + assign unused_illegal_insn_id = illegal_insn_id; + brqrv_exu #( + .RV32M(RV32M), + .RV32B(RV32B), + .BranchTargetALU(BranchTargetALU) + ) ex_block_i( + .clk_i(clk), + .rst_ni(rst_ni), + .alu_operator_i(alu_operator_ex), + .alu_operand_a_i(alu_operand_a_ex), + .alu_operand_b_i(alu_operand_b_ex), + .alu_instr_first_cycle_i(instr_first_cycle_id), + .bt_a_operand_i(bt_a_operand), + .bt_b_operand_i(bt_b_operand), + .multdiv_operator_i(multdiv_operator_ex), + .mult_en_i(mult_en_ex), + .div_en_i(div_en_ex), + .mult_sel_i(mult_sel_ex), + .div_sel_i(div_sel_ex), + .multdiv_signed_mode_i(multdiv_signed_mode_ex), + .multdiv_operand_a_i(multdiv_operand_a_ex), + .multdiv_operand_b_i(multdiv_operand_b_ex), + .multdiv_ready_id_i(multdiv_ready_id), + .data_ind_timing_i(data_ind_timing), + .imd_val_we_o(imd_val_we_ex), + .imd_val_d_o(imd_val_d_ex), + .imd_val_q_i(imd_val_q_ex), + .alu_adder_result_ex_o(alu_adder_result_ex), + .result_ex_o(result_ex), + .branch_target_o(branch_target_ex), + .branch_decision_o(branch_decision), + .ex_valid_o(ex_valid) + ); + assign data_req_o = data_req_out & ~pmp_req_err[PMP_D]; + brqrv_lsu load_store_unit_i( + .clk_i(clk), + .rst_ni(rst_ni), + .data_req_o(data_req_out), + .data_gnt_i(data_gnt_i), + .data_rvalid_i(data_rvalid_i), + .data_err_i(data_err_i), + .data_pmp_err_i(pmp_req_err[PMP_D]), + .data_addr_o(data_addr_o), + .data_we_o(data_we_o), + .data_be_o(data_be_o), + .data_wdata_o(data_wdata_o), + .data_rdata_i(data_rdata_i), + .lsu_we_i(lsu_we), + .lsu_type_i(lsu_type), + .lsu_wdata_i(lsu_wdata), + .lsu_sign_ext_i(lsu_sign_ext), + .lsu_rdata_o(rf_wdata_lsu), + .lsu_rdata_valid_o(rf_we_lsu), + .lsu_req_i(lsu_req), + .lsu_req_done_o(lsu_req_done), + .adder_result_ex_i(alu_adder_result_ex), + .addr_incr_req_o(lsu_addr_incr_req), + .addr_last_o(lsu_addr_last), + .lsu_resp_valid_o(lsu_resp_valid), + .load_err_o(lsu_load_err), + .store_err_o(lsu_store_err), + .busy_o(lsu_busy), + .perf_load_o(perf_load), + .perf_store_o(perf_store) + ); + brqrv_wbu #(.WritebackStage(WritebackStage)) wb_stage_i( + .clk_i(clk), + .rst_ni(rst_ni), + .en_wb_i(en_wb), + .instr_type_wb_i(instr_type_wb), + .pc_id_i(pc_id), + .ready_wb_o(ready_wb), + .rf_write_wb_o(rf_write_wb), + .outstanding_load_wb_o(outstanding_load_wb), + .outstanding_store_wb_o(outstanding_store_wb), + .pc_wb_o(pc_wb), + .rf_waddr_id_i(rf_waddr_id), + .rf_wdata_id_i(rf_wdata_id), + .rf_we_id_i(rf_we_id), + .rf_wdata_lsu_i(rf_wdata_lsu), + .rf_we_lsu_i(rf_we_lsu), + .rf_wdata_fwd_wb_o(rf_wdata_fwd_wb), + .rf_waddr_wb_o(rf_waddr_wb), + .rf_wdata_wb_o(rf_wdata_wb), + .rf_we_wb_o(rf_we_wb), + .lsu_resp_valid_i(lsu_resp_valid), + .instr_done_wb_o(instr_done_wb) + ); + wire [RegFileDataWidth - 1:0] rf_wdata_wb_ecc; + wire [RegFileDataWidth - 1:0] rf_rdata_a_ecc; + wire [RegFileDataWidth - 1:0] rf_rdata_b_ecc; + wire rf_ecc_err_comb; + generate + if (RegFileECC) begin : gen_regfile_ecc + wire [1:0] rf_ecc_err_a; + wire [1:0] rf_ecc_err_b; + wire rf_ecc_err_a_id; + wire rf_ecc_err_b_id; + prim_secded_39_32_enc regfile_ecc_enc( + .in(rf_wdata_wb), + .out(rf_wdata_wb_ecc) + ); + prim_secded_39_32_dec regfile_ecc_dec_a( + .in(rf_rdata_a_ecc), + .d_o(), + .syndrome_o(), + .err_o(rf_ecc_err_a) + ); + prim_secded_39_32_dec regfile_ecc_dec_b( + .in(rf_rdata_b_ecc), + .d_o(), + .syndrome_o(), + .err_o(rf_ecc_err_b) + ); + assign rf_rdata_a = rf_rdata_a_ecc[31:0]; + assign rf_rdata_b = rf_rdata_b_ecc[31:0]; + assign rf_ecc_err_a_id = (|rf_ecc_err_a & rf_ren_a) & ~rf_rd_a_wb_match; + assign rf_ecc_err_b_id = (|rf_ecc_err_b & rf_ren_b) & ~rf_rd_b_wb_match; + assign rf_ecc_err_comb = instr_valid_id & (rf_ecc_err_a_id | rf_ecc_err_b_id); + end + else begin : gen_no_regfile_ecc + wire unused_rf_ren_a; + wire unused_rf_ren_b; + wire unused_rf_rd_a_wb_match; + wire unused_rf_rd_b_wb_match; + assign unused_rf_ren_a = rf_ren_a; + assign unused_rf_ren_b = rf_ren_b; + assign unused_rf_rd_a_wb_match = rf_rd_a_wb_match; + assign unused_rf_rd_b_wb_match = rf_rd_b_wb_match; + assign rf_wdata_wb_ecc = rf_wdata_wb; + assign rf_rdata_a = rf_rdata_a_ecc; + assign rf_rdata_b = rf_rdata_b_ecc; + assign rf_ecc_err_comb = 1'b0; + end + endgenerate + generate + if (RegFile == RegFileFF) begin : gen_regfile_ff + brqrv_register_file_ff #( + .RV32E(RV32E), + .DataWidth(RegFileDataWidth), + .DummyInstructions(DummyInstructions) + ) register_file_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .dummy_instr_id_i(dummy_instr_id), + .raddr_a_i(rf_raddr_a), + .rdata_a_o(rf_rdata_a_ecc), + .raddr_b_i(rf_raddr_b), + .rdata_b_o(rf_rdata_b_ecc), + .waddr_a_i(rf_waddr_wb), + .wdata_a_i(rf_wdata_wb_ecc), + .we_a_i(rf_we_wb) + ); + end + else if (RegFile == RegFileFPGA) begin : gen_regfile_fpga + brqrv_register_file_fpga #( + .RV32E(RV32E), + .DataWidth(RegFileDataWidth), + .DummyInstructions(DummyInstructions) + ) register_file_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .test_en_i(test_en_i), + .dummy_instr_id_i(dummy_instr_id), + .raddr_a_i(rf_raddr_a), + .rdata_a_o(rf_rdata_a_ecc), + .raddr_b_i(rf_raddr_b), + .rdata_b_o(rf_rdata_b_ecc), + .waddr_a_i(rf_waddr_wb), + .wdata_a_i(rf_wdata_wb_ecc), + .we_a_i(rf_we_wb) + ); + end + endgenerate + assign alert_minor_o = 1'b0; + assign alert_major_o = rf_ecc_err_comb | pc_mismatch_alert; + assign csr_wdata = alu_operand_a_ex; + function automatic [11:0] sv2v_cast_12; + input reg [11:0] inp; + sv2v_cast_12 = inp; + endfunction + assign csr_addr = sv2v_cast_12((csr_access ? alu_operand_b_ex[11:0] : 12'b000000000000)); + brqrv_csr #( + .DbgTriggerEn(DbgTriggerEn), + .DataIndTiming(DataIndTiming), + .DummyInstructions(DummyInstructions), + .ICache(ICache), + .MHPMCounterNum(MHPMCounterNum), + .MHPMCounterWidth(MHPMCounterWidth), + .PMPEnable(PMPEnable), + .PMPGranularity(PMPGranularity), + .PMPNumRegions(PMPNumRegions), + .RV32E(RV32E), + .RV32M(RV32M) + ) cs_registers_i( + .clk_i(clk), + .rst_ni(rst_ni), + .hart_id_i(hart_id_i), + .priv_mode_id_o(priv_mode_id), + .priv_mode_if_o(priv_mode_if), + .priv_mode_lsu_o(priv_mode_lsu), + .csr_mtvec_o(csr_mtvec), + .csr_mtvec_init_i(csr_mtvec_init), + .boot_addr_i(boot_addr_i), + .csr_access_i(csr_access), + .csr_addr_i(csr_addr), + .csr_wdata_i(csr_wdata), + .csr_op_i(csr_op), + .csr_op_en_i(csr_op_en), + .csr_rdata_o(csr_rdata), + .irq_software_i(irq_software_i), + .irq_timer_i(irq_timer_i), + .irq_external_i(irq_external_i), + .irq_fast_i(irq_fast_i), + .nmi_mode_i(nmi_mode), + .irq_pending_o(irq_pending), + .irqs_o(irqs), + .csr_mstatus_mie_o(csr_mstatus_mie), + .csr_mstatus_tw_o(csr_mstatus_tw), + .csr_mepc_o(csr_mepc), + .csr_pmp_cfg_o(csr_pmp_cfg), + .csr_pmp_addr_o(csr_pmp_addr), + .csr_depc_o(csr_depc), + .debug_mode_i(debug_mode), + .debug_cause_i(debug_cause), + .debug_csr_save_i(debug_csr_save), + .debug_single_step_o(debug_single_step), + .debug_ebreakm_o(debug_ebreakm), + .debug_ebreaku_o(debug_ebreaku), + .trigger_match_o(trigger_match), + .pc_if_i(pc_if), + .pc_id_i(pc_id), + .pc_wb_i(pc_wb), + .data_ind_timing_o(data_ind_timing), + .dummy_instr_en_o(dummy_instr_en), + .dummy_instr_mask_o(dummy_instr_mask), + .dummy_instr_seed_en_o(dummy_instr_seed_en), + .dummy_instr_seed_o(dummy_instr_seed), + .icache_enable_o(icache_enable), + .csr_save_if_i(csr_save_if), + .csr_save_id_i(csr_save_id), + .csr_save_wb_i(csr_save_wb), + .csr_restore_mret_i(csr_restore_mret_id), + .csr_restore_dret_i(csr_restore_dret_id), + .csr_save_cause_i(csr_save_cause), + .csr_mcause_i(exc_cause), + .csr_mtval_i(csr_mtval), + .illegal_csr_insn_o(illegal_csr_insn_id), + .instr_ret_i(instr_id_done), + .instr_ret_compressed_i(instr_id_done_compressed), + .iside_wait_i(perf_iside_wait), + .jump_i(perf_jump), + .branch_i(perf_branch), + .branch_taken_i(perf_tbranch), + .mem_load_i(perf_load), + .mem_store_i(perf_store), + .dside_wait_i(perf_dside_wait), + .mul_wait_i(perf_mul_wait), + .div_wait_i(perf_div_wait) + ); + generate + if (PMPEnable) begin : g_pmp + wire [(PMP_NUM_CHAN * 34) - 1:0] pmp_req_addr; + wire [(PMP_NUM_CHAN * 2) - 1:0] pmp_req_type; + wire [(PMP_NUM_CHAN * 2) - 1:0] pmp_priv_lvl; + assign pmp_req_addr[((PMP_NUM_CHAN - 1) - PMP_I) * 34+:34] = {2'b00, instr_addr_o[31:0]}; + assign pmp_req_type[((PMP_NUM_CHAN - 1) - PMP_I) * 2+:2] = PMP_ACC_EXEC; + assign pmp_priv_lvl[((PMP_NUM_CHAN - 1) - PMP_I) * 2+:2] = priv_mode_if; + assign pmp_req_addr[((PMP_NUM_CHAN - 1) - PMP_D) * 34+:34] = {2'b00, data_addr_o[31:0]}; + assign pmp_req_type[((PMP_NUM_CHAN - 1) - PMP_D) * 2+:2] = (data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ); + assign pmp_priv_lvl[((PMP_NUM_CHAN - 1) - PMP_D) * 2+:2] = priv_mode_lsu; + brqrv_pmp #( + .PMPGranularity(PMPGranularity), + .PMPNumChan(PMP_NUM_CHAN), + .PMPNumRegions(PMPNumRegions) + ) pmp_i( + .clk_i(clk), + .rst_ni(rst_ni), + .csr_pmp_cfg_i(csr_pmp_cfg), + .csr_pmp_addr_i(csr_pmp_addr), + .priv_mode_i(pmp_priv_lvl), + .pmp_req_addr_i(pmp_req_addr), + .pmp_req_type_i(pmp_req_type), + .pmp_req_err_o(pmp_req_err) + ); + end + else begin : g_no_pmp + wire [1:0] unused_priv_lvl_if; + wire [1:0] unused_priv_lvl_ls; + wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] unused_csr_pmp_addr; + wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] unused_csr_pmp_cfg; + assign unused_priv_lvl_if = priv_mode_if; + assign unused_priv_lvl_ls = priv_mode_lsu; + assign unused_csr_pmp_addr = csr_pmp_addr; + assign unused_csr_pmp_cfg = csr_pmp_cfg; + assign pmp_req_err[PMP_I] = 1'b0; + assign pmp_req_err[PMP_D] = 1'b0; + end + endgenerate +endmodule +module brqrv_csr ( + clk_i, + rst_ni, + hart_id_i, + priv_mode_id_o, + priv_mode_if_o, + priv_mode_lsu_o, + csr_mstatus_tw_o, + csr_mtvec_o, + csr_mtvec_init_i, + boot_addr_i, + csr_access_i, + csr_addr_i, + csr_wdata_i, + csr_op_i, + csr_op_en_i, + csr_rdata_o, + irq_software_i, + irq_timer_i, + irq_external_i, + irq_fast_i, + nmi_mode_i, + irq_pending_o, + irqs_o, + csr_mstatus_mie_o, + csr_mepc_o, + csr_pmp_cfg_o, + csr_pmp_addr_o, + debug_mode_i, + debug_cause_i, + debug_csr_save_i, + csr_depc_o, + debug_single_step_o, + debug_ebreakm_o, + debug_ebreaku_o, + trigger_match_o, + pc_if_i, + pc_id_i, + pc_wb_i, + data_ind_timing_o, + dummy_instr_en_o, + dummy_instr_mask_o, + dummy_instr_seed_en_o, + dummy_instr_seed_o, + icache_enable_o, + csr_save_if_i, + csr_save_id_i, + csr_save_wb_i, + csr_restore_mret_i, + csr_restore_dret_i, + csr_save_cause_i, + csr_mcause_i, + csr_mtval_i, + illegal_csr_insn_o, + instr_ret_i, + instr_ret_compressed_i, + iside_wait_i, + jump_i, + branch_i, + branch_taken_i, + mem_load_i, + mem_store_i, + dside_wait_i, + mul_wait_i, + div_wait_i +); + parameter [0:0] DbgTriggerEn = 0; + parameter [0:0] DataIndTiming = 1'b0; + parameter [0:0] DummyInstructions = 1'b0; + parameter [0:0] ICache = 1'b0; + parameter [31:0] MHPMCounterNum = 10; + parameter [31:0] MHPMCounterWidth = 40; + parameter [0:0] PMPEnable = 0; + parameter [31:0] PMPGranularity = 0; + parameter [31:0] PMPNumRegions = 4; + parameter [0:0] RV32E = 0; + localparam integer brqrv_pkg_RV32MFast = 2; + parameter integer RV32M = brqrv_pkg_RV32MFast; + input wire clk_i; + input wire rst_ni; + input wire [31:0] hart_id_i; + output wire [1:0] priv_mode_id_o; + output wire [1:0] priv_mode_if_o; + output wire [1:0] priv_mode_lsu_o; + output wire csr_mstatus_tw_o; + output wire [31:0] csr_mtvec_o; + input wire csr_mtvec_init_i; + input wire [31:0] boot_addr_i; + input wire csr_access_i; + input wire [11:0] csr_addr_i; + input wire [31:0] csr_wdata_i; + input wire [1:0] csr_op_i; + input csr_op_en_i; + output wire [31:0] csr_rdata_o; + input wire irq_software_i; + input wire irq_timer_i; + input wire irq_external_i; + input wire [14:0] irq_fast_i; + input wire nmi_mode_i; + output wire irq_pending_o; + output wire [17:0] irqs_o; + output wire csr_mstatus_mie_o; + output wire [31:0] csr_mepc_o; + output wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_o; + output wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_o; + input wire debug_mode_i; + input wire [2:0] debug_cause_i; + input wire debug_csr_save_i; + output wire [31:0] csr_depc_o; + output wire debug_single_step_o; + output wire debug_ebreakm_o; + output wire debug_ebreaku_o; + output wire trigger_match_o; + input wire [31:0] pc_if_i; + input wire [31:0] pc_id_i; + input wire [31:0] pc_wb_i; + output wire data_ind_timing_o; + output wire dummy_instr_en_o; + output wire [2:0] dummy_instr_mask_o; + output wire dummy_instr_seed_en_o; + output wire [31:0] dummy_instr_seed_o; + output wire icache_enable_o; + input wire csr_save_if_i; + input wire csr_save_id_i; + input wire csr_save_wb_i; + input wire csr_restore_mret_i; + input wire csr_restore_dret_i; + input wire csr_save_cause_i; + input wire [5:0] csr_mcause_i; + input wire [31:0] csr_mtval_i; + output wire illegal_csr_insn_o; + input wire instr_ret_i; + input wire instr_ret_compressed_i; + input wire iside_wait_i; + input wire jump_i; + input wire branch_i; + input wire branch_taken_i; + input wire mem_load_i; + input wire mem_store_i; + input wire dside_wait_i; + input wire mul_wait_i; + input wire div_wait_i; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + localparam [31:0] RV32MEnabled = (RV32M == RV32MNone ? 0 : 1); + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + localparam [31:0] MISA_VALUE = ((((((((((0 | 4) | 0) | (sv2v_cast_32(RV32E) << 4)) | 0) | (sv2v_cast_32(!RV32E) << 8)) | (RV32MEnabled << 12)) | 0) | 0) | 1048576) | 0) | (sv2v_cast_32(CSR_MISA_MXL) << 30); + reg [31:0] exception_pc; + reg [1:0] priv_lvl_q; + reg [1:0] priv_lvl_d; + reg [5:0] mstatus_q; + reg [5:0] mstatus_d; + reg [17:0] mie_q; + reg [17:0] mie_d; + reg [31:0] mscratch_q; + reg [31:0] mscratch_d; + reg [31:0] mepc_q; + reg [31:0] mepc_d; + reg [5:0] mcause_q; + reg [5:0] mcause_d; + reg [31:0] mtval_q; + reg [31:0] mtval_d; + reg [31:0] mtvec_q; + reg [31:0] mtvec_d; + wire [17:0] mip; + reg [31:0] dcsr_q; + reg [31:0] dcsr_d; + reg [31:0] depc_q; + reg [31:0] depc_d; + reg [31:0] dscratch0_q; + reg [31:0] dscratch0_d; + reg [31:0] dscratch1_q; + reg [31:0] dscratch1_d; + reg [2:0] mstack_q; + reg [2:0] mstack_d; + reg [31:0] mstack_epc_q; + reg [31:0] mstack_epc_d; + reg [5:0] mstack_cause_q; + reg [5:0] mstack_cause_d; + reg [31:0] pmp_addr_rdata [0:PMP_MAX_REGIONS - 1]; + wire [PMP_CFG_W - 1:0] pmp_cfg_rdata [0:PMP_MAX_REGIONS - 1]; + wire [31:0] mcountinhibit; + reg [MHPMCounterNum + 2:0] mcountinhibit_d; + reg [MHPMCounterNum + 2:0] mcountinhibit_q; + reg mcountinhibit_we; + wire [63:0] mhpmcounter [0:31]; + reg [31:0] mhpmcounter_we; + reg [31:0] mhpmcounterh_we; + reg [31:0] mhpmcounter_incr; + reg [31:0] mhpmevent [0:31]; + wire [4:0] mhpmcounter_idx; + wire [31:0] tselect_rdata; + wire [31:0] tmatch_control_rdata; + wire [31:0] tmatch_value_rdata; + wire [31:0] cpuctrl_rdata; + wire [31:0] cpuctrl_wdata; + reg [31:0] csr_wdata_int; + reg [31:0] csr_rdata_int; + wire csr_we_int; + wire csr_wreq; + reg illegal_csr; + wire illegal_csr_priv; + wire illegal_csr_write; + wire [7:0] unused_boot_addr; + wire [2:0] unused_csr_addr; + assign unused_boot_addr = boot_addr_i[7:0]; + wire [11:0] csr_addr; + assign csr_addr = csr_addr_i; + assign unused_csr_addr = csr_addr[7:5]; + assign mhpmcounter_idx = csr_addr[4:0]; + assign illegal_csr_priv = csr_addr[9:8] > priv_lvl_q; + assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wreq; + assign illegal_csr_insn_o = csr_access_i & ((illegal_csr | illegal_csr_write) | illegal_csr_priv); + assign mip[17] = irq_software_i; + assign mip[16] = irq_timer_i; + assign mip[15] = irq_external_i; + assign mip[14-:15] = irq_fast_i; + always @(*) begin + csr_rdata_int = {32 {1'sb0}}; + illegal_csr = 1'b0; + case (csr_addr_i) + CSR_MHARTID: csr_rdata_int = hart_id_i; + CSR_MSTATUS: begin + csr_rdata_int = {32 {1'sb0}}; + csr_rdata_int[CSR_MSTATUS_MIE_BIT] = mstatus_q[5]; + csr_rdata_int[CSR_MSTATUS_MPIE_BIT] = mstatus_q[4]; + csr_rdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q[3-:2]; + csr_rdata_int[CSR_MSTATUS_MPRV_BIT] = mstatus_q[1]; + csr_rdata_int[CSR_MSTATUS_TW_BIT] = mstatus_q[0]; + end + CSR_MISA: csr_rdata_int = MISA_VALUE; + CSR_MIE: begin + csr_rdata_int = {32 {1'sb0}}; + csr_rdata_int[CSR_MSIX_BIT] = mie_q[17]; + csr_rdata_int[CSR_MTIX_BIT] = mie_q[16]; + csr_rdata_int[CSR_MEIX_BIT] = mie_q[15]; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mie_q[14-:15]; + end + CSR_MSCRATCH: csr_rdata_int = mscratch_q; + CSR_MTVEC: csr_rdata_int = mtvec_q; + CSR_MEPC: csr_rdata_int = mepc_q; + CSR_MCAUSE: csr_rdata_int = {mcause_q[5], 26'b00000000000000000000000000, mcause_q[4:0]}; + CSR_MTVAL: csr_rdata_int = mtval_q; + CSR_MIP: begin + csr_rdata_int = {32 {1'sb0}}; + csr_rdata_int[CSR_MSIX_BIT] = mip[17]; + csr_rdata_int[CSR_MTIX_BIT] = mip[16]; + csr_rdata_int[CSR_MEIX_BIT] = mip[15]; + csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip[14-:15]; + end + CSR_PMPCFG0: csr_rdata_int = {pmp_cfg_rdata[3], pmp_cfg_rdata[2], pmp_cfg_rdata[1], pmp_cfg_rdata[0]}; + CSR_PMPCFG1: csr_rdata_int = {pmp_cfg_rdata[7], pmp_cfg_rdata[6], pmp_cfg_rdata[5], pmp_cfg_rdata[4]}; + CSR_PMPCFG2: csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10], pmp_cfg_rdata[9], pmp_cfg_rdata[8]}; + CSR_PMPCFG3: csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14], pmp_cfg_rdata[13], pmp_cfg_rdata[12]}; + CSR_PMPADDR0: csr_rdata_int = pmp_addr_rdata[0]; + CSR_PMPADDR1: csr_rdata_int = pmp_addr_rdata[1]; + CSR_PMPADDR2: csr_rdata_int = pmp_addr_rdata[2]; + CSR_PMPADDR3: csr_rdata_int = pmp_addr_rdata[3]; + CSR_PMPADDR4: csr_rdata_int = pmp_addr_rdata[4]; + CSR_PMPADDR5: csr_rdata_int = pmp_addr_rdata[5]; + CSR_PMPADDR6: csr_rdata_int = pmp_addr_rdata[6]; + CSR_PMPADDR7: csr_rdata_int = pmp_addr_rdata[7]; + CSR_PMPADDR8: csr_rdata_int = pmp_addr_rdata[8]; + CSR_PMPADDR9: csr_rdata_int = pmp_addr_rdata[9]; + CSR_PMPADDR10: csr_rdata_int = pmp_addr_rdata[10]; + CSR_PMPADDR11: csr_rdata_int = pmp_addr_rdata[11]; + CSR_PMPADDR12: csr_rdata_int = pmp_addr_rdata[12]; + CSR_PMPADDR13: csr_rdata_int = pmp_addr_rdata[13]; + CSR_PMPADDR14: csr_rdata_int = pmp_addr_rdata[14]; + CSR_PMPADDR15: csr_rdata_int = pmp_addr_rdata[15]; + CSR_DCSR: begin + csr_rdata_int = dcsr_q; + illegal_csr = ~debug_mode_i; + end + CSR_DPC: begin + csr_rdata_int = depc_q; + illegal_csr = ~debug_mode_i; + end + CSR_DSCRATCH0: begin + csr_rdata_int = dscratch0_q; + illegal_csr = ~debug_mode_i; + end + CSR_DSCRATCH1: begin + csr_rdata_int = dscratch1_q; + illegal_csr = ~debug_mode_i; + end + CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit; + CSR_MHPMEVENT3, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, CSR_MHPMEVENT9, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: csr_rdata_int = mhpmevent[mhpmcounter_idx]; + CSR_MCYCLE, CSR_MINSTRET, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0]; + CSR_MCYCLEH, CSR_MINSTRETH, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32]; + CSR_TSELECT: begin + csr_rdata_int = tselect_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA1: begin + csr_rdata_int = tmatch_control_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA2: begin + csr_rdata_int = tmatch_value_rdata; + illegal_csr = ~DbgTriggerEn; + end + CSR_TDATA3: begin + csr_rdata_int = {32 {1'sb0}}; + illegal_csr = ~DbgTriggerEn; + end + CSR_MCONTEXT: begin + csr_rdata_int = {32 {1'sb0}}; + illegal_csr = ~DbgTriggerEn; + end + CSR_SCONTEXT: begin + csr_rdata_int = {32 {1'sb0}}; + illegal_csr = ~DbgTriggerEn; + end + CSR_CPUCTRL: csr_rdata_int = cpuctrl_rdata; + CSR_SECURESEED: csr_rdata_int = {32 {1'sb0}}; + default: illegal_csr = 1'b1; + endcase + end + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + function automatic [1:0] sv2v_cast_2; + input reg [1:0] inp; + sv2v_cast_2 = inp; + endfunction + always @(*) begin + exception_pc = pc_id_i; + priv_lvl_d = priv_lvl_q; + mstatus_d = mstatus_q; + mie_d = mie_q; + mscratch_d = mscratch_q; + mepc_d = mepc_q; + mcause_d = mcause_q; + mtval_d = mtval_q; + mtvec_d = (csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b000000, 2'b01} : mtvec_q); + dcsr_d = dcsr_q; + depc_d = depc_q; + dscratch0_d = dscratch0_q; + dscratch1_d = dscratch1_q; + mstack_d = mstack_q; + mstack_epc_d = mstack_epc_q; + mstack_cause_d = mstack_cause_q; + mcountinhibit_we = 1'b0; + mhpmcounter_we = {32 {1'sb0}}; + mhpmcounterh_we = {32 {1'sb0}}; + if (csr_we_int) + case (csr_addr_i) + CSR_MSTATUS: begin + mstatus_d = {sv2v_cast_1(csr_wdata_int[CSR_MSTATUS_MIE_BIT]), sv2v_cast_1(csr_wdata_int[CSR_MSTATUS_MPIE_BIT]), sv2v_cast_2(sv2v_cast_2(csr_wdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW])), sv2v_cast_1(csr_wdata_int[CSR_MSTATUS_MPRV_BIT]), sv2v_cast_1(csr_wdata_int[CSR_MSTATUS_TW_BIT])}; + if ((mstatus_d[3-:2] != PRIV_LVL_M) && (mstatus_d[3-:2] != PRIV_LVL_U)) + mstatus_d[3-:2] = PRIV_LVL_M; + end + CSR_MIE: begin + mie_d[17] = csr_wdata_int[CSR_MSIX_BIT]; + mie_d[16] = csr_wdata_int[CSR_MTIX_BIT]; + mie_d[15] = csr_wdata_int[CSR_MEIX_BIT]; + mie_d[14-:15] = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW]; + end + CSR_MSCRATCH: mscratch_d = csr_wdata_int; + CSR_MEPC: mepc_d = {csr_wdata_int[31:1], 1'b0}; + CSR_MCAUSE: mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]}; + CSR_MTVAL: mtval_d = csr_wdata_int; + CSR_MTVEC: mtvec_d = {csr_wdata_int[31:8], 6'b000000, 2'b01}; + CSR_DCSR: begin + dcsr_d = csr_wdata_int; + dcsr_d[31-:4] = XDEBUGVER_STD; + if ((dcsr_d[1-:2] != PRIV_LVL_M) && (dcsr_d[1-:2] != PRIV_LVL_U)) + dcsr_d[1-:2] = PRIV_LVL_M; + dcsr_d[3] = 1'b0; + dcsr_d[4] = 1'b0; + dcsr_d[10] = 1'b0; + dcsr_d[9] = 1'b0; + dcsr_d[5] = 1'b0; + dcsr_d[14] = 1'b0; + dcsr_d[27-:12] = 12'h000; + end + CSR_DPC: depc_d = {csr_wdata_int[31:1], 1'b0}; + CSR_DSCRATCH0: dscratch0_d = csr_wdata_int; + CSR_DSCRATCH1: dscratch1_d = csr_wdata_int; + CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1; + CSR_MCYCLE, CSR_MINSTRET, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER9, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: mhpmcounter_we[mhpmcounter_idx] = 1'b1; + CSR_MCYCLEH, CSR_MINSTRETH, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9H, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: mhpmcounterh_we[mhpmcounter_idx] = 1'b1; + default: + ; + endcase + case (1'b1) + csr_save_cause_i: begin + case (1'b1) + csr_save_if_i: exception_pc = pc_if_i; + csr_save_id_i: exception_pc = pc_id_i; + csr_save_wb_i: exception_pc = pc_wb_i; + default: + ; + endcase + priv_lvl_d = PRIV_LVL_M; + if (debug_csr_save_i) begin + dcsr_d[1-:2] = priv_lvl_q; + dcsr_d[8-:3] = debug_cause_i; + depc_d = exception_pc; + end + else if (!debug_mode_i) begin + mtval_d = csr_mtval_i; + mstatus_d[5] = 1'b0; + mstatus_d[4] = mstatus_q[5]; + mstatus_d[3-:2] = priv_lvl_q; + mepc_d = exception_pc; + mcause_d = csr_mcause_i; + mstack_d[2] = mstatus_q[4]; + mstack_d[1-:2] = mstatus_q[3-:2]; + mstack_epc_d = mepc_q; + mstack_cause_d = mcause_q; + end + end + csr_restore_dret_i: priv_lvl_d = dcsr_q[1-:2]; + csr_restore_mret_i: begin + priv_lvl_d = mstatus_q[3-:2]; + mstatus_d[5] = mstatus_q[4]; + if (nmi_mode_i) begin + mstatus_d[4] = mstack_q[2]; + mstatus_d[3-:2] = mstack_q[1-:2]; + mepc_d = mstack_epc_q; + mcause_d = mstack_cause_q; + end + else begin + mstatus_d[4] = 1'b1; + mstatus_d[3-:2] = PRIV_LVL_U; + end + end + default: + ; + endcase + end + always @(*) + case (csr_op_i) + CSR_OP_WRITE: csr_wdata_int = csr_wdata_i; + CSR_OP_SET: csr_wdata_int = csr_wdata_i | csr_rdata_o; + CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o; + CSR_OP_READ: csr_wdata_int = csr_wdata_i; + default: csr_wdata_int = csr_wdata_i; + endcase + assign csr_wreq = csr_op_en_i & |{csr_op_i == CSR_OP_WRITE, csr_op_i == CSR_OP_SET, csr_op_i == CSR_OP_CLEAR}; + assign csr_we_int = csr_wreq & ~illegal_csr_insn_o; + assign csr_rdata_o = csr_rdata_int; + assign csr_mepc_o = mepc_q; + assign csr_depc_o = depc_q; + assign csr_mtvec_o = mtvec_q; + assign csr_mstatus_mie_o = mstatus_q[5]; + assign csr_mstatus_tw_o = mstatus_q[0]; + assign debug_single_step_o = dcsr_q[2]; + assign debug_ebreakm_o = dcsr_q[15]; + assign debug_ebreaku_o = dcsr_q[12]; + assign irqs_o = mip & mie_q; + assign irq_pending_o = |irqs_o; + function automatic [3:0] sv2v_cast_4; + input reg [3:0] inp; + sv2v_cast_4 = inp; + endfunction + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + priv_lvl_q <= PRIV_LVL_M; + mstatus_q <= {1'b0, 1'b1, sv2v_cast_2(PRIV_LVL_U), 1'b0, 1'b0}; + mie_q <= {18 {1'sb0}}; + mscratch_q <= {32 {1'sb0}}; + mepc_q <= {32 {1'sb0}}; + mcause_q <= {6 {1'sb0}}; + mtval_q <= {32 {1'sb0}}; + mtvec_q <= 32'h00000001; + dcsr_q <= {sv2v_cast_4(XDEBUGVER_STD), 12'b000000000000, 1'sb0, 1'sb0, 1'sb0, 1'sb0, 1'sb0, 1'sb0, 1'sb0, sv2v_cast_3(DBG_CAUSE_NONE), 1'sb0, 1'sb0, 1'sb0, 1'sb0, sv2v_cast_2(PRIV_LVL_M)}; + depc_q <= {32 {1'sb0}}; + dscratch0_q <= {32 {1'sb0}}; + dscratch1_q <= {32 {1'sb0}}; + mstack_q <= {1'b1, sv2v_cast_2(PRIV_LVL_U)}; + mstack_epc_q <= {32 {1'sb0}}; + mstack_cause_q <= {6 {1'sb0}}; + end + else begin + priv_lvl_q <= priv_lvl_d; + mstatus_q <= mstatus_d; + mie_q <= mie_d; + mscratch_q <= mscratch_d; + mepc_q <= mepc_d; + mcause_q <= mcause_d; + mtval_q <= mtval_d; + mtvec_q <= mtvec_d; + dcsr_q <= dcsr_d; + depc_q <= depc_d; + dscratch0_q <= dscratch0_d; + dscratch1_q <= dscratch1_d; + mstack_q <= mstack_d; + mstack_epc_q <= mstack_epc_d; + mstack_cause_q <= mstack_cause_d; + end + assign priv_mode_id_o = priv_lvl_q; + assign priv_mode_if_o = priv_lvl_d; + assign priv_mode_lsu_o = (mstatus_q[1] ? mstatus_q[3-:2] : priv_lvl_q); + generate + if (PMPEnable) begin : g_pmp_registers + reg [5:0] pmp_cfg [0:PMPNumRegions - 1]; + reg [5:0] pmp_cfg_wdata [0:PMPNumRegions - 1]; + reg [31:0] pmp_addr [0:PMPNumRegions - 1]; + wire [PMPNumRegions - 1:0] pmp_cfg_we; + wire [PMPNumRegions - 1:0] pmp_addr_we; + genvar i; + for (i = 0; i < PMP_MAX_REGIONS; i = i + 1) begin : g_exp_rd_data + if (i < PMPNumRegions) begin : g_implemented_regions + assign pmp_cfg_rdata[i] = {pmp_cfg[i][5], 2'b00, pmp_cfg[i][4-:2], pmp_cfg[i][2], pmp_cfg[i][1], pmp_cfg[i][0]}; + if (PMPGranularity == 0) begin : g_pmp_g0 + always @(*) pmp_addr_rdata[i] = pmp_addr[i]; + end + else if (PMPGranularity == 1) begin : g_pmp_g1 + always @(*) begin + pmp_addr_rdata[i] = pmp_addr[i]; + if ((pmp_cfg[i][4-:2] == PMP_MODE_OFF) || (pmp_cfg[i][4-:2] == PMP_MODE_TOR)) + pmp_addr_rdata[i][PMPGranularity - 1:0] = {PMPGranularity {1'sb0}}; + end + end + else begin : g_pmp_g2 + always @(*) begin + pmp_addr_rdata[i] = pmp_addr[i]; + if ((pmp_cfg[i][4-:2] == PMP_MODE_OFF) || (pmp_cfg[i][4-:2] == PMP_MODE_TOR)) + pmp_addr_rdata[i][PMPGranularity - 1:0] = {PMPGranularity {1'sb0}}; + else if (pmp_cfg[i][4-:2] == PMP_MODE_NAPOT) + pmp_addr_rdata[i][PMPGranularity - 2:0] = {((PMPGranularity - 2) >= 0 ? PMPGranularity - 1 : 3 - PMPGranularity) {1'sb1}}; + end + end + end + else begin : g_other_regions + assign pmp_cfg_rdata[i] = {PMP_CFG_W {1'sb0}}; + always @(*) pmp_addr_rdata[i] = {32 {1'sb0}}; + end + end + for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_pmp_csrs + assign pmp_cfg_we[i] = (csr_we_int & ~pmp_cfg[i][5]) & (csr_addr == (CSR_OFF_PMP_CFG + (i[11:0] >> 2))); + always @(*) pmp_cfg_wdata[i][5] = csr_wdata_int[((i % 4) * PMP_CFG_W) + 7]; + always @(*) + case (csr_wdata_int[((i % 4) * PMP_CFG_W) + 3+:2]) + 2'b00: pmp_cfg_wdata[i][4-:2] = PMP_MODE_OFF; + 2'b01: pmp_cfg_wdata[i][4-:2] = PMP_MODE_TOR; + 2'b10: pmp_cfg_wdata[i][4-:2] = (PMPGranularity == 0 ? PMP_MODE_NA4 : PMP_MODE_OFF); + 2'b11: pmp_cfg_wdata[i][4-:2] = PMP_MODE_NAPOT; + default: pmp_cfg_wdata[i][4-:2] = PMP_MODE_OFF; + endcase + always @(*) pmp_cfg_wdata[i][2] = csr_wdata_int[((i % 4) * PMP_CFG_W) + 2]; + always @(*) pmp_cfg_wdata[i][1] = &csr_wdata_int[(i % 4) * PMP_CFG_W+:2]; + always @(*) pmp_cfg_wdata[i][0] = csr_wdata_int[(i % 4) * PMP_CFG_W]; + function automatic [5:0] sv2v_cast_6; + input reg [5:0] inp; + sv2v_cast_6 = inp; + endfunction + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + pmp_cfg[i] <= sv2v_cast_6('b0); + else if (pmp_cfg_we[i]) + pmp_cfg[i] <= pmp_cfg_wdata[i]; + if (i < (PMPNumRegions - 1)) begin : g_lower + assign pmp_addr_we[i] = ((csr_we_int & ~pmp_cfg[i][5]) & (~pmp_cfg[i + 1][5] | (pmp_cfg[i + 1][4-:2] != PMP_MODE_TOR))) & (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0])); + end + else begin : g_upper + assign pmp_addr_we[i] = (csr_we_int & ~pmp_cfg[i][5]) & (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0])); + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + pmp_addr[i] <= 'b0; + else if (pmp_addr_we[i]) + pmp_addr[i] <= csr_wdata_int; + assign csr_pmp_cfg_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 6+:6] = pmp_cfg[i]; + assign csr_pmp_addr_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 34+:34] = {pmp_addr[i], 2'b00}; + end + end + else begin : g_no_pmp_tieoffs + genvar i; + for (i = 0; i < PMP_MAX_REGIONS; i = i + 1) begin : g_rdata + always @(*) pmp_addr_rdata[i] = {32 {1'sb0}}; + assign pmp_cfg_rdata[i] = {PMP_CFG_W {1'sb0}}; + end + for (i = 0; i < PMPNumRegions; i = i + 1) begin : g_outputs + function automatic [5:0] sv2v_cast_6; + input reg [5:0] inp; + sv2v_cast_6 = inp; + endfunction + assign csr_pmp_cfg_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 6+:6] = sv2v_cast_6(1'b0); + assign csr_pmp_addr_o[(0 >= (PMPNumRegions - 1) ? i : (PMPNumRegions - 1) - i) * 34+:34] = {34 {1'sb0}}; + end + end + endgenerate + always @(*) begin : mcountinhibit_update + if (mcountinhibit_we == 1'b1) + mcountinhibit_d = {csr_wdata_int[MHPMCounterNum + 2:2], 1'b0, csr_wdata_int[0]}; + else + mcountinhibit_d = mcountinhibit_q; + end + always @(*) begin : gen_mhpmcounter_incr + begin : sv2v_autoblock_53 + reg [31:0] i; + for (i = 0; i < 32; i = i + 1) + begin : gen_mhpmcounter_incr_inactive + mhpmcounter_incr[i] = 1'b0; + end + end + mhpmcounter_incr[0] = 1'b1; + mhpmcounter_incr[1] = 1'b0; + mhpmcounter_incr[2] = instr_ret_i; + mhpmcounter_incr[3] = dside_wait_i; + mhpmcounter_incr[4] = iside_wait_i; + mhpmcounter_incr[5] = mem_load_i; + mhpmcounter_incr[6] = mem_store_i; + mhpmcounter_incr[7] = jump_i; + mhpmcounter_incr[8] = branch_i; + mhpmcounter_incr[9] = branch_taken_i; + mhpmcounter_incr[10] = instr_ret_compressed_i; + mhpmcounter_incr[11] = mul_wait_i; + mhpmcounter_incr[12] = div_wait_i; + end + always @(*) begin : gen_mhpmevent + begin : sv2v_autoblock_54 + reg signed [31:0] i; + for (i = 0; i < 32; i = i + 1) + begin : gen_mhpmevent_active + mhpmevent[i] = {32 {1'sb0}}; + mhpmevent[i][i] = 1'b1; + end + end + mhpmevent[1] = {32 {1'sb0}}; + begin : sv2v_autoblock_55 + reg [31:0] i; + for (i = 3 + MHPMCounterNum; i < 32; i = i + 1) + begin : gen_mhpmevent_inactive + mhpmevent[i] = {32 {1'sb0}}; + end + end + end + brqrv_csr_mcounter #(.CounterWidth(64)) mcycle_counter_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]), + .counterh_we_i(mhpmcounterh_we[0]), + .counter_we_i(mhpmcounter_we[0]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[0]) + ); + brqrv_csr_mcounter #(.CounterWidth(64)) minstret_counter_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]), + .counterh_we_i(mhpmcounterh_we[2]), + .counter_we_i(mhpmcounter_we[2]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[2]) + ); + assign mhpmcounter[1] = {64 {1'sb0}}; + generate + genvar cnt; + for (cnt = 0; cnt < MHPMCounterNum; cnt = cnt + 1) begin : gen_cntrs + brqrv_csr_mcounter #(.CounterWidth(MHPMCounterWidth)) mcounters_variable_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .counter_inc_i(mhpmcounter_incr[cnt + 3] & ~mcountinhibit[cnt + 3]), + .counterh_we_i(mhpmcounterh_we[cnt + 3]), + .counter_we_i(mhpmcounter_we[cnt + 3]), + .counter_val_i(csr_wdata_int), + .counter_val_o(mhpmcounter[cnt + 3]) + ); + end + endgenerate + generate + if (MHPMCounterNum < 29) begin : g_mcountinhibit_reduced + wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_we; + wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounterh_we; + wire [(29 - MHPMCounterNum) - 1:0] unused_mhphcounter_incr; + assign mcountinhibit = {{29 - MHPMCounterNum {1'b1}}, mcountinhibit_q}; + assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum + 3]; + assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum + 3]; + assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum + 3]; + end + else begin : g_mcountinhibit_full + assign mcountinhibit = mcountinhibit_q; + end + endgenerate + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mcountinhibit_q <= {((MHPMCounterNum + 2) >= 0 ? MHPMCounterNum + 3 : 1 - (MHPMCounterNum + 2)) {1'sb0}}; + else + mcountinhibit_q <= mcountinhibit_d; + generate + if (DbgTriggerEn) begin : gen_trigger_regs + wire tmatch_control_d; + reg tmatch_control_q; + wire [31:0] tmatch_value_d; + reg [31:0] tmatch_value_q; + wire tmatch_control_we; + wire tmatch_value_we; + assign tmatch_control_we = (csr_we_int & debug_mode_i) & (csr_addr_i == CSR_TDATA1); + assign tmatch_value_we = (csr_we_int & debug_mode_i) & (csr_addr_i == CSR_TDATA2); + assign tmatch_control_d = (tmatch_control_we ? csr_wdata_int[2] : tmatch_control_q); + assign tmatch_value_d = csr_wdata_int[31:0]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + tmatch_control_q <= 'b0; + else + tmatch_control_q <= tmatch_control_d; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + tmatch_value_q <= 'b0; + else if (tmatch_value_we) + tmatch_value_q <= tmatch_value_d; + assign tselect_rdata = 'b0; + assign tmatch_control_rdata = {4'h2, 1'b1, 6'h00, 1'b0, 1'b0, 1'b0, 2'b00, 4'h1, 1'b0, 4'h0, 1'b1, 1'b0, 1'b0, 1'b1, tmatch_control_q, 1'b0, 1'b0}; + assign tmatch_value_rdata = tmatch_value_q; + assign trigger_match_o = tmatch_control_q & (pc_if_i[31:0] == tmatch_value_q[31:0]); + end + else begin : gen_no_trigger_regs + assign tselect_rdata = 'b0; + assign tmatch_control_rdata = 'b0; + assign tmatch_value_rdata = 'b0; + assign trigger_match_o = 'b0; + end + endgenerate + assign cpuctrl_rdata[31-:26] = {26 {1'sb0}}; + assign cpuctrl_wdata = sv2v_cast_32(csr_wdata_int); + generate + if (DataIndTiming) begin : gen_dit + wire data_ind_timing_d; + reg data_ind_timing_q; + assign data_ind_timing_d = (csr_we_int && (csr_addr == CSR_CPUCTRL) ? cpuctrl_wdata[1] : data_ind_timing_q); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + data_ind_timing_q <= 1'b0; + else + data_ind_timing_q <= data_ind_timing_d; + assign cpuctrl_rdata[1] = data_ind_timing_q; + end + else begin : gen_no_dit + wire unused_dit; + assign unused_dit = cpuctrl_wdata[1]; + assign cpuctrl_rdata[1] = 1'b0; + end + endgenerate + assign data_ind_timing_o = cpuctrl_rdata[1]; + generate + if (DummyInstructions) begin : gen_dummy + wire dummy_instr_en_d; + reg dummy_instr_en_q; + wire [2:0] dummy_instr_mask_d; + reg [2:0] dummy_instr_mask_q; + assign dummy_instr_en_d = (csr_we_int && (csr_addr == CSR_CPUCTRL) ? cpuctrl_wdata[2] : dummy_instr_en_q); + assign dummy_instr_mask_d = (csr_we_int && (csr_addr == CSR_CPUCTRL) ? cpuctrl_wdata[5-:3] : dummy_instr_mask_q); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + dummy_instr_en_q <= 1'b0; + dummy_instr_mask_q <= 3'b000; + end + else begin + dummy_instr_en_q <= dummy_instr_en_d; + dummy_instr_mask_q <= dummy_instr_mask_d; + end + assign cpuctrl_rdata[2] = dummy_instr_en_q; + assign cpuctrl_rdata[5-:3] = dummy_instr_mask_q; + assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == CSR_SECURESEED); + assign dummy_instr_seed_o = csr_wdata_int; + end + else begin : gen_no_dummy + wire unused_dummy_en; + wire [2:0] unused_dummy_mask; + assign unused_dummy_en = cpuctrl_wdata[2]; + assign unused_dummy_mask = cpuctrl_wdata[5-:3]; + assign cpuctrl_rdata[2] = 1'b0; + assign cpuctrl_rdata[5-:3] = 3'b000; + assign dummy_instr_seed_en_o = 1'b0; + assign dummy_instr_seed_o = {32 {1'sb0}}; + end + endgenerate + assign dummy_instr_en_o = cpuctrl_rdata[2]; + assign dummy_instr_mask_o = cpuctrl_rdata[5-:3]; + generate + if (ICache) begin : gen_icache_enable + wire icache_enable_d; + reg icache_enable_q; + assign icache_enable_d = (csr_we_int & (csr_addr == CSR_CPUCTRL) ? cpuctrl_wdata[0] : icache_enable_q); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + icache_enable_q <= 1'b0; + else + icache_enable_q <= icache_enable_d; + assign cpuctrl_rdata[0] = icache_enable_q; + end + else begin : gen_no_icache + wire unused_icen; + assign unused_icen = cpuctrl_wdata[0]; + assign cpuctrl_rdata[0] = 1'b0; + end + endgenerate + assign icache_enable_o = cpuctrl_rdata[0]; + wire [31:6] unused_cpuctrl; + assign unused_cpuctrl = cpuctrl_wdata[31:6]; +endmodule +module brqrv_csr_mcounter ( + clk_i, + rst_ni, + counter_inc_i, + counterh_we_i, + counter_we_i, + counter_val_i, + counter_val_o +); + parameter signed [31:0] CounterWidth = 32; + input wire clk_i; + input wire rst_ni; + input wire counter_inc_i; + input wire counterh_we_i; + input wire counter_we_i; + input wire [31:0] counter_val_i; + output wire [63:0] counter_val_o; + wire [63:0] counter; + reg [CounterWidth - 1:0] counter_upd; + reg [63:0] counter_load; + reg we; + reg [CounterWidth - 1:0] counter_d; + always @(*) begin + we = counter_we_i | counterh_we_i; + counter_load[63:32] = counter[63:32]; + counter_load[31:0] = counter_val_i; + if (counterh_we_i) begin + counter_load[63:32] = counter_val_i; + counter_load[31:0] = counter[31:0]; + end + counter_upd = counter[CounterWidth - 1:0] + {{CounterWidth - 1 {1'b0}}, 1'b1}; + if (we) + counter_d = counter_load[CounterWidth - 1:0]; + else if (counter_inc_i) + counter_d = counter_upd[CounterWidth - 1:0]; + else + counter_d = counter[CounterWidth - 1:0]; + end + reg [CounterWidth - 1:0] counter_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + counter_q <= {CounterWidth {1'sb0}}; + else + counter_q <= counter_d; + generate + if (CounterWidth < 64) begin : g_counter_narrow + wire [63:CounterWidth] unused_counter_load; + assign counter[CounterWidth - 1:0] = counter_q; + assign counter[63:CounterWidth] = {(63 >= CounterWidth ? 64 - CounterWidth : CounterWidth - 62) {1'sb0}}; + assign unused_counter_load = counter_load[63:CounterWidth]; + end + else begin : g_counter_full + assign counter = counter_q; + end + endgenerate + assign counter_val_o = counter; +endmodule +module brqrv_exu ( + clk_i, + rst_ni, + alu_operator_i, + alu_operand_a_i, + alu_operand_b_i, + alu_instr_first_cycle_i, + bt_a_operand_i, + bt_b_operand_i, + multdiv_operator_i, + mult_en_i, + div_en_i, + mult_sel_i, + div_sel_i, + multdiv_signed_mode_i, + multdiv_operand_a_i, + multdiv_operand_b_i, + multdiv_ready_id_i, + data_ind_timing_i, + imd_val_we_o, + imd_val_d_o, + imd_val_q_i, + alu_adder_result_ex_o, + result_ex_o, + branch_target_o, + branch_decision_o, + ex_valid_o +); + localparam integer brqrv_pkg_RV32MFast = 2; + parameter integer RV32M = brqrv_pkg_RV32MFast; + localparam integer brqrv_pkg_RV32BNone = 0; + parameter integer RV32B = brqrv_pkg_RV32BNone; + parameter [0:0] BranchTargetALU = 0; + input wire clk_i; + input wire rst_ni; + input wire [5:0] alu_operator_i; + input wire [31:0] alu_operand_a_i; + input wire [31:0] alu_operand_b_i; + input wire alu_instr_first_cycle_i; + input wire [31:0] bt_a_operand_i; + input wire [31:0] bt_b_operand_i; + input wire [1:0] multdiv_operator_i; + input wire mult_en_i; + input wire div_en_i; + input wire mult_sel_i; + input wire div_sel_i; + input wire [1:0] multdiv_signed_mode_i; + input wire [31:0] multdiv_operand_a_i; + input wire [31:0] multdiv_operand_b_i; + input wire multdiv_ready_id_i; + input wire data_ind_timing_i; + output wire [1:0] imd_val_we_o; + output wire [67:0] imd_val_d_o; + input wire [67:0] imd_val_q_i; + output wire [31:0] alu_adder_result_ex_o; + output wire [31:0] result_ex_o; + output wire [31:0] branch_target_o; + output wire branch_decision_o; + output wire ex_valid_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire [31:0] alu_result; + wire [31:0] multdiv_result; + wire [32:0] multdiv_alu_operand_b; + wire [32:0] multdiv_alu_operand_a; + wire [33:0] alu_adder_result_ext; + wire alu_cmp_result; + wire alu_is_equal_result; + wire multdiv_valid; + wire multdiv_sel; + wire [63:0] alu_imd_val_q; + wire [63:0] alu_imd_val_d; + wire [1:0] alu_imd_val_we; + wire [67:0] multdiv_imd_val_d; + wire [1:0] multdiv_imd_val_we; + generate + if (RV32M != RV32MNone) begin : gen_multdiv_m + assign multdiv_sel = mult_sel_i | div_sel_i; + end + else begin : gen_multdiv_no_m + assign multdiv_sel = 1'b0; + end + endgenerate + assign imd_val_d_o[34+:34] = (multdiv_sel ? multdiv_imd_val_d[34+:34] : {2'b00, alu_imd_val_d[32+:32]}); + assign imd_val_d_o[0+:34] = (multdiv_sel ? multdiv_imd_val_d[0+:34] : {2'b00, alu_imd_val_d[0+:32]}); + assign imd_val_we_o = (multdiv_sel ? multdiv_imd_val_we : alu_imd_val_we); + assign alu_imd_val_q = {imd_val_q_i[65-:32], imd_val_q_i[31-:32]}; + assign result_ex_o = (multdiv_sel ? multdiv_result : alu_result); + assign branch_decision_o = alu_cmp_result; + generate + if (BranchTargetALU) begin : g_branch_target_alu + wire [32:0] bt_alu_result; + wire unused_bt_carry; + assign bt_alu_result = bt_a_operand_i + bt_b_operand_i; + assign unused_bt_carry = bt_alu_result[32]; + assign branch_target_o = bt_alu_result[31:0]; + end + else begin : g_no_branch_target_alu + wire [31:0] unused_bt_a_operand; + wire [31:0] unused_bt_b_operand; + assign unused_bt_a_operand = bt_a_operand_i; + assign unused_bt_b_operand = bt_b_operand_i; + assign branch_target_o = alu_adder_result_ex_o; + end + endgenerate + brqrv_exu_alu #(.RV32B(RV32B)) alu_i( + .operator_i(alu_operator_i), + .operand_a_i(alu_operand_a_i), + .operand_b_i(alu_operand_b_i), + .instr_first_cycle_i(alu_instr_first_cycle_i), + .imd_val_q_i(alu_imd_val_q), + .imd_val_we_o(alu_imd_val_we), + .imd_val_d_o(alu_imd_val_d), + .multdiv_operand_a_i(multdiv_alu_operand_a), + .multdiv_operand_b_i(multdiv_alu_operand_b), + .multdiv_sel_i(multdiv_sel), + .adder_result_o(alu_adder_result_ex_o), + .adder_result_ext_o(alu_adder_result_ext), + .result_o(alu_result), + .comparison_result_o(alu_cmp_result), + .is_equal_result_o(alu_is_equal_result) + ); + generate + if (RV32M == RV32MSlow) begin : gen_multdiv_slow + brqrv_exu_multdiv_slow multdiv_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .mult_en_i(mult_en_i), + .div_en_i(div_en_i), + .mult_sel_i(mult_sel_i), + .div_sel_i(div_sel_i), + .operator_i(multdiv_operator_i), + .signed_mode_i(multdiv_signed_mode_i), + .op_a_i(multdiv_operand_a_i), + .op_b_i(multdiv_operand_b_i), + .alu_adder_ext_i(alu_adder_result_ext), + .alu_adder_i(alu_adder_result_ex_o), + .equal_to_zero_i(alu_is_equal_result), + .data_ind_timing_i(data_ind_timing_i), + .valid_o(multdiv_valid), + .alu_operand_a_o(multdiv_alu_operand_a), + .alu_operand_b_o(multdiv_alu_operand_b), + .imd_val_q_i(imd_val_q_i), + .imd_val_d_o(multdiv_imd_val_d), + .imd_val_we_o(multdiv_imd_val_we), + .multdiv_ready_id_i(multdiv_ready_id_i), + .multdiv_result_o(multdiv_result) + ); + end + else if ((RV32M == RV32MFast) || (RV32M == RV32MSingleCycle)) begin : gen_multdiv_fast + brqrv_exu_multdiv_fast #(.RV32M(RV32M)) multdiv_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .mult_en_i(mult_en_i), + .div_en_i(div_en_i), + .mult_sel_i(mult_sel_i), + .div_sel_i(div_sel_i), + .operator_i(multdiv_operator_i), + .signed_mode_i(multdiv_signed_mode_i), + .op_a_i(multdiv_operand_a_i), + .op_b_i(multdiv_operand_b_i), + .alu_operand_a_o(multdiv_alu_operand_a), + .alu_operand_b_o(multdiv_alu_operand_b), + .alu_adder_ext_i(alu_adder_result_ext), + .alu_adder_i(alu_adder_result_ex_o), + .equal_to_zero_i(alu_is_equal_result), + .data_ind_timing_i(data_ind_timing_i), + .imd_val_q_i(imd_val_q_i), + .imd_val_d_o(multdiv_imd_val_d), + .imd_val_we_o(multdiv_imd_val_we), + .multdiv_ready_id_i(multdiv_ready_id_i), + .valid_o(multdiv_valid), + .multdiv_result_o(multdiv_result) + ); + end + endgenerate + assign ex_valid_o = (multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we)); +endmodule +module brqrv_exu_alu ( + operator_i, + operand_a_i, + operand_b_i, + instr_first_cycle_i, + multdiv_operand_a_i, + multdiv_operand_b_i, + multdiv_sel_i, + imd_val_q_i, + imd_val_d_o, + imd_val_we_o, + adder_result_o, + adder_result_ext_o, + result_o, + comparison_result_o, + is_equal_result_o +); + localparam integer brqrv_pkg_RV32BNone = 0; + parameter integer RV32B = brqrv_pkg_RV32BNone; + input wire [5:0] operator_i; + input wire [31:0] operand_a_i; + input wire [31:0] operand_b_i; + input wire instr_first_cycle_i; + input wire [32:0] multdiv_operand_a_i; + input wire [32:0] multdiv_operand_b_i; + input wire multdiv_sel_i; + input wire [63:0] imd_val_q_i; + output reg [63:0] imd_val_d_o; + output reg [1:0] imd_val_we_o; + output wire [31:0] adder_result_o; + output wire [33:0] adder_result_ext_o; + output reg [31:0] result_o; + output wire comparison_result_o; + output wire is_equal_result_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire [31:0] operand_a_rev; + wire [32:0] operand_b_neg; + generate + genvar k; + for (k = 0; k < 32; k = k + 1) begin : gen_rev_operand_a + assign operand_a_rev[k] = operand_a_i[31 - k]; + end + endgenerate + reg adder_op_b_negate; + wire [32:0] adder_in_a; + reg [32:0] adder_in_b; + wire [31:0] adder_result; + always @(*) begin + adder_op_b_negate = 1'b0; + case (operator_i) + ALU_SUB, ALU_EQ, ALU_NE, ALU_GE, ALU_GEU, ALU_LT, ALU_LTU, ALU_SLT, ALU_SLTU, ALU_MIN, ALU_MINU, ALU_MAX, ALU_MAXU: adder_op_b_negate = 1'b1; + default: + ; + endcase + end + assign adder_in_a = (multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i, 1'b1}); + assign operand_b_neg = {operand_b_i, 1'b0} ^ {33 {1'b1}}; + always @(*) + case (1'b1) + multdiv_sel_i: adder_in_b = multdiv_operand_b_i; + adder_op_b_negate: adder_in_b = operand_b_neg; + default: adder_in_b = {operand_b_i, 1'b0}; + endcase + assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b); + assign adder_result = adder_result_ext_o[32:1]; + assign adder_result_o = adder_result; + wire is_equal; + reg is_greater_equal; + reg cmp_signed; + always @(*) + case (operator_i) + ALU_GE, ALU_LT, ALU_SLT, ALU_MIN, ALU_MAX: cmp_signed = 1'b1; + default: cmp_signed = 1'b0; + endcase + assign is_equal = adder_result == 32'b00000000000000000000000000000000; + assign is_equal_result_o = is_equal; + always @(*) + if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0) + is_greater_equal = adder_result[31] == 1'b0; + else + is_greater_equal = operand_a_i[31] ^ cmp_signed; + reg cmp_result; + always @(*) + case (operator_i) + ALU_EQ: cmp_result = is_equal; + ALU_NE: cmp_result = ~is_equal; + ALU_GE, ALU_GEU, ALU_MAX, ALU_MAXU: cmp_result = is_greater_equal; + ALU_LT, ALU_LTU, ALU_MIN, ALU_MINU, ALU_SLT, ALU_SLTU: cmp_result = ~is_greater_equal; + default: cmp_result = is_equal; + endcase + assign comparison_result_o = cmp_result; + reg shift_left; + wire shift_ones; + wire shift_arith; + wire shift_funnel; + wire shift_sbmode; + reg [5:0] shift_amt; + wire [5:0] shift_amt_compl; + reg [31:0] shift_result; + reg [32:0] shift_result_ext; + reg [31:0] shift_result_rev; + wire bfp_op; + wire [4:0] bfp_len; + wire [4:0] bfp_off; + wire [31:0] bfp_mask; + wire [31:0] bfp_mask_rev; + wire [31:0] bfp_result; + assign bfp_op = (RV32B != RV32BNone ? operator_i == ALU_BFP : 1'b0); + assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; + assign bfp_off = operand_b_i[20:16]; + assign bfp_mask = (RV32B != RV32BNone ? ~(32'hffffffff << bfp_len) : {32 {1'sb0}}); + generate + genvar i; + for (i = 0; i < 32; i = i + 1) begin : gen_rev_bfp_mask + assign bfp_mask_rev[i] = bfp_mask[31 - i]; + end + endgenerate + assign bfp_result = (RV32B != RV32BNone ? (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : {32 {1'sb0}}); + always @(*) shift_amt[5] = operand_b_i[5] & shift_funnel; + assign shift_amt_compl = 32 - operand_b_i[4:0]; + always @(*) + if (bfp_op) + shift_amt[4:0] = bfp_off; + else + shift_amt[4:0] = (instr_first_cycle_i ? (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0])); + assign shift_sbmode = (RV32B != RV32BNone ? ((operator_i == ALU_SBSET) | (operator_i == ALU_SBCLR)) | (operator_i == ALU_SBINV) : 1'b0); + always @(*) begin + case (operator_i) + ALU_SLL: shift_left = 1'b1; + ALU_SLO, ALU_BFP: shift_left = (RV32B != RV32BNone ? 1'b1 : 1'b0); + ALU_ROL: shift_left = (RV32B != RV32BNone ? instr_first_cycle_i : 0); + ALU_ROR: shift_left = (RV32B != RV32BNone ? ~instr_first_cycle_i : 0); + ALU_FSL: shift_left = (RV32B != RV32BNone ? (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0); + ALU_FSR: shift_left = (RV32B != RV32BNone ? (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0); + default: shift_left = 1'b0; + endcase + if (shift_sbmode) + shift_left = 1'b1; + end + assign shift_arith = operator_i == ALU_SRA; + assign shift_ones = (RV32B != RV32BNone ? (operator_i == ALU_SLO) | (operator_i == ALU_SRO) : 1'b0); + assign shift_funnel = (RV32B != RV32BNone ? (operator_i == ALU_FSL) | (operator_i == ALU_FSR) : 1'b0); + always @(*) begin + if (RV32B == RV32BNone) + shift_result = (shift_left ? operand_a_rev : operand_a_i); + else + case (1'b1) + bfp_op: shift_result = bfp_mask_rev; + shift_sbmode: shift_result = 32'h80000000; + default: shift_result = (shift_left ? operand_a_rev : operand_a_i); + endcase + shift_result_ext = $signed({shift_ones | (shift_arith & shift_result[31]), shift_result}) >>> shift_amt[4:0]; + shift_result = shift_result_ext[31:0]; + begin : sv2v_autoblock_56 + reg [31:0] i; + for (i = 0; i < 32; i = i + 1) + shift_result_rev[i] = shift_result[31 - i]; + end + shift_result = (shift_left ? shift_result_rev : shift_result); + end + wire bwlogic_or; + wire bwlogic_and; + wire [31:0] bwlogic_operand_b; + wire [31:0] bwlogic_or_result; + wire [31:0] bwlogic_and_result; + wire [31:0] bwlogic_xor_result; + reg [31:0] bwlogic_result; + reg bwlogic_op_b_negate; + always @(*) + case (operator_i) + ALU_XNOR, ALU_ORN, ALU_ANDN: bwlogic_op_b_negate = (RV32B != RV32BNone ? 1'b1 : 1'b0); + ALU_CMIX: bwlogic_op_b_negate = (RV32B != RV32BNone ? ~instr_first_cycle_i : 1'b0); + default: bwlogic_op_b_negate = 1'b0; + endcase + assign bwlogic_operand_b = (bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i); + assign bwlogic_or_result = operand_a_i | bwlogic_operand_b; + assign bwlogic_and_result = operand_a_i & bwlogic_operand_b; + assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b; + assign bwlogic_or = (operator_i == ALU_OR) | (operator_i == ALU_ORN); + assign bwlogic_and = (operator_i == ALU_AND) | (operator_i == ALU_ANDN); + always @(*) + case (1'b1) + bwlogic_or: bwlogic_result = bwlogic_or_result; + bwlogic_and: bwlogic_result = bwlogic_and_result; + default: bwlogic_result = bwlogic_xor_result; + endcase + wire [5:0] bitcnt_result; + wire [31:0] minmax_result; + reg [31:0] pack_result; + wire [31:0] sext_result; + reg [31:0] singlebit_result; + reg [31:0] rev_result; + reg [31:0] shuffle_result; + reg [31:0] butterfly_result; + reg [31:0] invbutterfly_result; + reg [31:0] clmul_result; + reg [31:0] multicycle_result; + generate + if (RV32B != RV32BNone) begin : g_alu_rvb + wire zbe_op; + wire bitcnt_ctz; + wire bitcnt_clz; + wire bitcnt_cz; + reg [31:0] bitcnt_bits; + wire [31:0] bitcnt_mask_op; + reg [31:0] bitcnt_bit_mask; + reg [191:0] bitcnt_partial; + wire [31:0] bitcnt_partial_lsb_d; + wire [31:0] bitcnt_partial_msb_d; + assign bitcnt_ctz = operator_i == ALU_CTZ; + assign bitcnt_clz = operator_i == ALU_CLZ; + assign bitcnt_cz = bitcnt_ctz | bitcnt_clz; + assign bitcnt_result = bitcnt_partial[0+:6]; + assign bitcnt_mask_op = (bitcnt_clz ? operand_a_rev : operand_a_i); + always @(*) begin + bitcnt_bit_mask = bitcnt_mask_op; + bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 1); + bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 2); + bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 4); + bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 8); + bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 16); + bitcnt_bit_mask = ~bitcnt_bit_mask; + end + assign zbe_op = (operator_i == ALU_BEXT) | (operator_i == ALU_BDEP); + always @(*) + case (1'b1) + zbe_op: bitcnt_bits = operand_b_i; + bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; + default: bitcnt_bits = operand_a_i; + endcase + always @(*) begin + bitcnt_partial = {32 {6'b000000}}; + begin : sv2v_autoblock_57 + reg [31:0] i; + for (i = 1; i < 32; i = i + 2) + bitcnt_partial[(31 - i) * 6+:6] = {5'h00, bitcnt_bits[i]} + {5'h00, bitcnt_bits[i - 1]}; + end + begin : sv2v_autoblock_58 + reg [31:0] i; + for (i = 3; i < 32; i = i + 4) + bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; + end + begin : sv2v_autoblock_59 + reg [31:0] i; + for (i = 7; i < 32; i = i + 8) + bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; + end + begin : sv2v_autoblock_60 + reg [31:0] i; + for (i = 15; i < 32; i = i + 16) + bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(39 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; + end + bitcnt_partial[0+:6] = bitcnt_partial[96+:6] + bitcnt_partial[0+:6]; + bitcnt_partial[48+:6] = bitcnt_partial[96+:6] + bitcnt_partial[48+:6]; + begin : sv2v_autoblock_61 + reg [31:0] i; + for (i = 11; i < 32; i = i + 8) + bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; + end + begin : sv2v_autoblock_62 + reg [31:0] i; + for (i = 5; i < 32; i = i + 4) + bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6]; + end + bitcnt_partial[186+:6] = {5'h00, bitcnt_bits[0]}; + begin : sv2v_autoblock_63 + reg [31:0] i; + for (i = 2; i < 32; i = i + 2) + bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(32 - i) * 6+:6] + {5'h00, bitcnt_bits[i]}; + end + end + assign minmax_result = (cmp_result ? operand_a_i : operand_b_i); + wire packu; + wire packh; + assign packu = operator_i == ALU_PACKU; + assign packh = operator_i == ALU_PACKH; + always @(*) + case (1'b1) + packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]}; + packh: pack_result = {16'h0000, operand_b_i[7:0], operand_a_i[7:0]}; + default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]}; + endcase + assign sext_result = (operator_i == ALU_SEXTB ? {{24 {operand_a_i[7]}}, operand_a_i[7:0]} : {{16 {operand_a_i[15]}}, operand_a_i[15:0]}); + always @(*) + case (operator_i) + ALU_SBSET: singlebit_result = operand_a_i | shift_result; + ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result; + ALU_SBINV: singlebit_result = operand_a_i ^ shift_result; + default: singlebit_result = {31'h00000000, shift_result[0]}; + endcase + wire [4:0] zbp_shift_amt; + wire gorc_op; + assign gorc_op = operator_i == ALU_GORC; + assign zbp_shift_amt[2:0] = (RV32B == RV32BFull ? shift_amt[2:0] : {3 {&shift_amt[2:0]}}); + assign zbp_shift_amt[4:3] = (RV32B == RV32BFull ? shift_amt[4:3] : {2 {&shift_amt[4:3]}}); + always @(*) begin + rev_result = operand_a_i; + if (zbp_shift_amt[0]) + rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h55555555) << 1)) | ((rev_result & 32'haaaaaaaa) >> 1); + if (zbp_shift_amt[1]) + rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h33333333) << 2)) | ((rev_result & 32'hcccccccc) >> 2); + if (zbp_shift_amt[2]) + rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h0f0f0f0f) << 4)) | ((rev_result & 32'hf0f0f0f0) >> 4); + if (zbp_shift_amt[3]) + rev_result = ((gorc_op & (RV32B == RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h00ff00ff) << 8)) | ((rev_result & 32'hff00ff00) >> 8); + if (zbp_shift_amt[4]) + rev_result = ((gorc_op & (RV32B == RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h0000ffff) << 16)) | ((rev_result & 32'hffff0000) >> 16); + end + wire crc_hmode; + wire crc_bmode; + wire [31:0] clmul_result_rev; + if (RV32B == RV32BFull) begin : gen_alu_rvb_full + localparam [127:0] SHUFFLE_MASK_L = {32'h00ff0000, 32'h0f000f00, 32'h30303030, 32'h44444444}; + localparam [127:0] SHUFFLE_MASK_R = {32'h0000ff00, 32'h00f000f0, 32'h0c0c0c0c, 32'h22222222}; + localparam [127:0] FLIP_MASK_L = {32'h22001100, 32'h00440000, 32'h44110000, 32'h11000000}; + localparam [127:0] FLIP_MASK_R = {32'h00880044, 32'h00002200, 32'h00008822, 32'h00000088}; + wire [31:0] SHUFFLE_MASK_NOT [0:3]; + for (i = 0; i < 4; i = i + 1) begin : gen_shuffle_mask_not + assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[(3 - i) * 32+:32] | SHUFFLE_MASK_R[(3 - i) * 32+:32]); + end + wire shuffle_flip; + assign shuffle_flip = operator_i == ALU_UNSHFL; + reg [3:0] shuffle_mode; + always @(*) begin + shuffle_result = operand_a_i; + if (shuffle_flip) begin + shuffle_mode[3] = shift_amt[0]; + shuffle_mode[2] = shift_amt[1]; + shuffle_mode[1] = shift_amt[2]; + shuffle_mode[0] = shift_amt[3]; + end + else + shuffle_mode = shift_amt[3:0]; + if (shuffle_flip) + shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]); + if (shuffle_mode[3]) + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | (((shuffle_result << 8) & SHUFFLE_MASK_L[96+:32]) | ((shuffle_result >> 8) & SHUFFLE_MASK_R[96+:32])); + if (shuffle_mode[2]) + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | (((shuffle_result << 4) & SHUFFLE_MASK_L[64+:32]) | ((shuffle_result >> 4) & SHUFFLE_MASK_R[64+:32])); + if (shuffle_mode[1]) + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | (((shuffle_result << 2) & SHUFFLE_MASK_L[32+:32]) | ((shuffle_result >> 2) & SHUFFLE_MASK_R[32+:32])); + if (shuffle_mode[0]) + shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | (((shuffle_result << 1) & SHUFFLE_MASK_L[0+:32]) | ((shuffle_result >> 1) & SHUFFLE_MASK_R[0+:32])); + if (shuffle_flip) + shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]); + end + reg [191:0] bitcnt_partial_q; + for (i = 0; i < 32; i = i + 1) begin : gen_bitcnt_reg_in_lsb + assign bitcnt_partial_lsb_d[i] = bitcnt_partial[(31 - i) * 6]; + end + for (i = 0; i < 16; i = i + 1) begin : gen_bitcnt_reg_in_b1 + assign bitcnt_partial_msb_d[i] = bitcnt_partial[((31 - ((2 * i) + 1)) * 6) + 1]; + end + for (i = 0; i < 8; i = i + 1) begin : gen_bitcnt_reg_in_b2 + assign bitcnt_partial_msb_d[16 + i] = bitcnt_partial[((31 - ((4 * i) + 3)) * 6) + 2]; + end + for (i = 0; i < 4; i = i + 1) begin : gen_bitcnt_reg_in_b3 + assign bitcnt_partial_msb_d[24 + i] = bitcnt_partial[((31 - ((8 * i) + 7)) * 6) + 3]; + end + for (i = 0; i < 2; i = i + 1) begin : gen_bitcnt_reg_in_b4 + assign bitcnt_partial_msb_d[28 + i] = bitcnt_partial[((31 - ((16 * i) + 15)) * 6) + 4]; + end + assign bitcnt_partial_msb_d[30] = bitcnt_partial[5]; + assign bitcnt_partial_msb_d[31] = 1'b0; + always @(*) begin + bitcnt_partial_q = {32 {6'b000000}}; + begin : sv2v_autoblock_64 + reg [31:0] i; + for (i = 0; i < 32; i = i + 1) + begin : gen_bitcnt_reg_out_lsb + bitcnt_partial_q[(31 - i) * 6] = imd_val_q_i[32 + i]; + end + end + begin : sv2v_autoblock_65 + reg [31:0] i; + for (i = 0; i < 16; i = i + 1) + begin : gen_bitcnt_reg_out_b1 + bitcnt_partial_q[((31 - ((2 * i) + 1)) * 6) + 1] = imd_val_q_i[i]; + end + end + begin : sv2v_autoblock_66 + reg [31:0] i; + for (i = 0; i < 8; i = i + 1) + begin : gen_bitcnt_reg_out_b2 + bitcnt_partial_q[((31 - ((4 * i) + 3)) * 6) + 2] = imd_val_q_i[16 + i]; + end + end + begin : sv2v_autoblock_67 + reg [31:0] i; + for (i = 0; i < 4; i = i + 1) + begin : gen_bitcnt_reg_out_b3 + bitcnt_partial_q[((31 - ((8 * i) + 7)) * 6) + 3] = imd_val_q_i[24 + i]; + end + end + begin : sv2v_autoblock_68 + reg [31:0] i; + for (i = 0; i < 2; i = i + 1) + begin : gen_bitcnt_reg_out_b4 + bitcnt_partial_q[((31 - ((16 * i) + 15)) * 6) + 4] = imd_val_q_i[28 + i]; + end + end + bitcnt_partial_q[5] = imd_val_q_i[30]; + end + wire [31:0] butterfly_mask_l [0:4]; + wire [31:0] butterfly_mask_r [0:4]; + wire [31:0] butterfly_mask_not [0:4]; + wire [31:0] lrotc_stage [0:4]; + genvar stg; + for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_ctrl_stage + genvar seg; + for (seg = 0; seg < (2 ** stg); seg = seg + 1) begin : gen_butterfly_ctrl + assign lrotc_stage[stg][((2 * (16 >> stg)) * (seg + 1)) - 1:(2 * (16 >> stg)) * seg] = {{16 >> stg {1'b0}}, {16 >> stg {1'b1}}} << bitcnt_partial_q[((32 - ((16 >> stg) * ((2 * seg) + 1))) * 6) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) : ($clog2(16 >> stg) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))) - 1)-:($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))]; + assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)]; + assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)]; + assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = {((((16 >> stg) * ((2 * seg) + 1)) - 1) >= ((16 >> stg) * (2 * seg)) ? ((((16 >> stg) * ((2 * seg) + 1)) - 1) - ((16 >> stg) * (2 * seg))) + 1 : (((16 >> stg) * (2 * seg)) - (((16 >> stg) * ((2 * seg) + 1)) - 1)) + 1) {1'sb0}}; + assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = {((((16 >> stg) * ((2 * seg) + 2)) - 1) >= ((16 >> stg) * ((2 * seg) + 1)) ? ((((16 >> stg) * ((2 * seg) + 2)) - 1) - ((16 >> stg) * ((2 * seg) + 1))) + 1 : (((16 >> stg) * ((2 * seg) + 1)) - (((16 >> stg) * ((2 * seg) + 2)) - 1)) + 1) {1'sb0}}; + end + end + for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_not + assign butterfly_mask_not[stg] = ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]); + end + always @(*) begin + butterfly_result = operand_a_i; + butterfly_result = ((butterfly_result & butterfly_mask_not[0]) | ((butterfly_result & butterfly_mask_l[0]) >> 16)) | ((butterfly_result & butterfly_mask_r[0]) << 16); + butterfly_result = ((butterfly_result & butterfly_mask_not[1]) | ((butterfly_result & butterfly_mask_l[1]) >> 8)) | ((butterfly_result & butterfly_mask_r[1]) << 8); + butterfly_result = ((butterfly_result & butterfly_mask_not[2]) | ((butterfly_result & butterfly_mask_l[2]) >> 4)) | ((butterfly_result & butterfly_mask_r[2]) << 4); + butterfly_result = ((butterfly_result & butterfly_mask_not[3]) | ((butterfly_result & butterfly_mask_l[3]) >> 2)) | ((butterfly_result & butterfly_mask_r[3]) << 2); + butterfly_result = ((butterfly_result & butterfly_mask_not[4]) | ((butterfly_result & butterfly_mask_l[4]) >> 1)) | ((butterfly_result & butterfly_mask_r[4]) << 1); + butterfly_result = butterfly_result & operand_b_i; + end + always @(*) begin + invbutterfly_result = operand_a_i & operand_b_i; + invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[4]) | ((invbutterfly_result & butterfly_mask_l[4]) >> 1)) | ((invbutterfly_result & butterfly_mask_r[4]) << 1); + invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[3]) | ((invbutterfly_result & butterfly_mask_l[3]) >> 2)) | ((invbutterfly_result & butterfly_mask_r[3]) << 2); + invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[2]) | ((invbutterfly_result & butterfly_mask_l[2]) >> 4)) | ((invbutterfly_result & butterfly_mask_r[2]) << 4); + invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[1]) | ((invbutterfly_result & butterfly_mask_l[1]) >> 8)) | ((invbutterfly_result & butterfly_mask_r[1]) << 8); + invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[0]) | ((invbutterfly_result & butterfly_mask_l[0]) >> 16)) | ((invbutterfly_result & butterfly_mask_r[0]) << 16); + end + wire clmul_rmode; + wire clmul_hmode; + reg [31:0] clmul_op_a; + reg [31:0] clmul_op_b; + wire [31:0] operand_b_rev; + wire [31:0] clmul_and_stage [0:31]; + wire [31:0] clmul_xor_stage1 [0:15]; + wire [31:0] clmul_xor_stage2 [0:7]; + wire [31:0] clmul_xor_stage3 [0:3]; + wire [31:0] clmul_xor_stage4 [0:1]; + wire [31:0] clmul_result_raw; + for (i = 0; i < 32; i = i + 1) begin : gen_rev_operand_b + assign operand_b_rev[i] = operand_b_i[31 - i]; + end + assign clmul_rmode = operator_i == ALU_CLMULR; + assign clmul_hmode = operator_i == ALU_CLMULH; + localparam [31:0] CRC32_POLYNOMIAL = 32'h04c11db7; + localparam [31:0] CRC32_MU_REV = 32'hf7011641; + localparam [31:0] CRC32C_POLYNOMIAL = 32'h1edc6f41; + localparam [31:0] CRC32C_MU_REV = 32'hdea713f1; + wire crc_op; + wire crc_cpoly; + reg [31:0] crc_operand; + wire [31:0] crc_poly; + wire [31:0] crc_mu_rev; + assign crc_op = (((((operator_i == ALU_CRC32C_W) | (operator_i == ALU_CRC32_W)) | (operator_i == ALU_CRC32C_H)) | (operator_i == ALU_CRC32_H)) | (operator_i == ALU_CRC32C_B)) | (operator_i == ALU_CRC32_B); + assign crc_cpoly = ((operator_i == ALU_CRC32C_W) | (operator_i == ALU_CRC32C_H)) | (operator_i == ALU_CRC32C_B); + assign crc_hmode = (operator_i == ALU_CRC32_H) | (operator_i == ALU_CRC32C_H); + assign crc_bmode = (operator_i == ALU_CRC32_B) | (operator_i == ALU_CRC32C_B); + assign crc_poly = (crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL); + assign crc_mu_rev = (crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV); + always @(*) + case (1'b1) + crc_bmode: crc_operand = {operand_a_i[7:0], 24'h000000}; + crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0000}; + default: crc_operand = operand_a_i; + endcase + always @(*) + if (crc_op) begin + clmul_op_a = (instr_first_cycle_i ? crc_operand : imd_val_q_i[32+:32]); + clmul_op_b = (instr_first_cycle_i ? crc_mu_rev : crc_poly); + end + else begin + clmul_op_a = (clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i); + clmul_op_b = (clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i); + end + for (i = 0; i < 32; i = i + 1) begin : gen_clmul_and_op + assign clmul_and_stage[i] = (clmul_op_b[i] ? clmul_op_a << i : {32 {1'sb0}}); + end + for (i = 0; i < 16; i = i + 1) begin : gen_clmul_xor_op_l1 + assign clmul_xor_stage1[i] = clmul_and_stage[2 * i] ^ clmul_and_stage[(2 * i) + 1]; + end + for (i = 0; i < 8; i = i + 1) begin : gen_clmul_xor_op_l2 + assign clmul_xor_stage2[i] = clmul_xor_stage1[2 * i] ^ clmul_xor_stage1[(2 * i) + 1]; + end + for (i = 0; i < 4; i = i + 1) begin : gen_clmul_xor_op_l3 + assign clmul_xor_stage3[i] = clmul_xor_stage2[2 * i] ^ clmul_xor_stage2[(2 * i) + 1]; + end + for (i = 0; i < 2; i = i + 1) begin : gen_clmul_xor_op_l4 + assign clmul_xor_stage4[i] = clmul_xor_stage3[2 * i] ^ clmul_xor_stage3[(2 * i) + 1]; + end + assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1]; + for (i = 0; i < 32; i = i + 1) begin : gen_rev_clmul_result + assign clmul_result_rev[i] = clmul_result_raw[31 - i]; + end + always @(*) + case (1'b1) + clmul_rmode: clmul_result = clmul_result_rev; + clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]}; + default: clmul_result = clmul_result_raw; + endcase + end + else begin : gen_alu_rvb_notfull + always @(*) shuffle_result = {32 {1'sb0}}; + always @(*) butterfly_result = {32 {1'sb0}}; + always @(*) invbutterfly_result = {32 {1'sb0}}; + always @(*) clmul_result = {32 {1'sb0}}; + assign bitcnt_partial_lsb_d = {32 {1'sb0}}; + assign bitcnt_partial_msb_d = {32 {1'sb0}}; + assign clmul_result_rev = {32 {1'sb0}}; + assign crc_bmode = 1'sb0; + assign crc_hmode = 1'sb0; + end + always @(*) + case (operator_i) + ALU_CMOV: begin + multicycle_result = (operand_b_i == 32'h00000000 ? operand_a_i : imd_val_q_i[32+:32]); + imd_val_d_o = {operand_a_i, 32'h00000000}; + if (instr_first_cycle_i) + imd_val_we_o = 2'b01; + else + imd_val_we_o = 2'b00; + end + ALU_CMIX: begin + multicycle_result = imd_val_q_i[32+:32] | bwlogic_and_result; + imd_val_d_o = {bwlogic_and_result, 32'h00000000}; + if (instr_first_cycle_i) + imd_val_we_o = 2'b01; + else + imd_val_we_o = 2'b00; + end + ALU_FSR, ALU_FSL, ALU_ROL, ALU_ROR: begin + if (shift_amt[4:0] == 5'h00) + multicycle_result = (shift_amt[5] ? operand_a_i : imd_val_q_i[32+:32]); + else + multicycle_result = imd_val_q_i[32+:32] | shift_result; + imd_val_d_o = {shift_result, 32'h00000000}; + if (instr_first_cycle_i) + imd_val_we_o = 2'b01; + else + imd_val_we_o = 2'b00; + end + ALU_CRC32_W, ALU_CRC32C_W, ALU_CRC32_H, ALU_CRC32C_H, ALU_CRC32_B, ALU_CRC32C_B: + if (RV32B == RV32BFull) begin + case (1'b1) + crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8); + crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16); + default: multicycle_result = clmul_result_rev; + endcase + imd_val_d_o = {clmul_result_rev, 32'h00000000}; + if (instr_first_cycle_i) + imd_val_we_o = 2'b01; + else + imd_val_we_o = 2'b00; + end + else begin + imd_val_d_o = {operand_a_i, 32'h00000000}; + imd_val_we_o = 2'b00; + multicycle_result = {32 {1'sb0}}; + end + ALU_BEXT, ALU_BDEP: + if (RV32B == RV32BFull) begin + multicycle_result = (operator_i == ALU_BDEP ? butterfly_result : invbutterfly_result); + imd_val_d_o = {bitcnt_partial_lsb_d, bitcnt_partial_msb_d}; + if (instr_first_cycle_i) + imd_val_we_o = 2'b11; + else + imd_val_we_o = 2'b00; + end + else begin + imd_val_d_o = {operand_a_i, 32'h00000000}; + imd_val_we_o = 2'b00; + multicycle_result = {32 {1'sb0}}; + end + default: begin + imd_val_d_o = {operand_a_i, 32'h00000000}; + imd_val_we_o = 2'b00; + multicycle_result = {32 {1'sb0}}; + end + endcase + end + else begin : g_no_alu_rvb + assign bitcnt_result = {6 {1'sb0}}; + assign minmax_result = {32 {1'sb0}}; + always @(*) pack_result = {32 {1'sb0}}; + assign sext_result = {32 {1'sb0}}; + always @(*) singlebit_result = {32 {1'sb0}}; + always @(*) rev_result = {32 {1'sb0}}; + always @(*) shuffle_result = {32 {1'sb0}}; + always @(*) butterfly_result = {32 {1'sb0}}; + always @(*) invbutterfly_result = {32 {1'sb0}}; + always @(*) clmul_result = {32 {1'sb0}}; + always @(*) multicycle_result = {32 {1'sb0}}; + always @(*) imd_val_d_o = {2 {32'b00000000000000000000000000000000}}; + always @(*) imd_val_we_o = {2 {1'sb0}}; + end + endgenerate + always @(*) begin + result_o = {32 {1'sb0}}; + case (operator_i) + ALU_XOR, ALU_XNOR, ALU_OR, ALU_ORN, ALU_AND, ALU_ANDN: result_o = bwlogic_result; + ALU_ADD, ALU_SUB: result_o = adder_result; + ALU_SLL, ALU_SRL, ALU_SRA, ALU_SLO, ALU_SRO: result_o = shift_result; + ALU_SHFL, ALU_UNSHFL: result_o = shuffle_result; + ALU_EQ, ALU_NE, ALU_GE, ALU_GEU, ALU_LT, ALU_LTU, ALU_SLT, ALU_SLTU: result_o = {31'h00000000, cmp_result}; + ALU_MIN, ALU_MAX, ALU_MINU, ALU_MAXU: result_o = minmax_result; + ALU_CLZ, ALU_CTZ, ALU_PCNT: result_o = {26'h0000000, bitcnt_result}; + ALU_PACK, ALU_PACKH, ALU_PACKU: result_o = pack_result; + ALU_SEXTB, ALU_SEXTH: result_o = sext_result; + ALU_CMIX, ALU_CMOV, ALU_FSL, ALU_FSR, ALU_ROL, ALU_ROR, ALU_CRC32_W, ALU_CRC32C_W, ALU_CRC32_H, ALU_CRC32C_H, ALU_CRC32_B, ALU_CRC32C_B, ALU_BEXT, ALU_BDEP: result_o = multicycle_result; + ALU_SBSET, ALU_SBCLR, ALU_SBINV, ALU_SBEXT: result_o = singlebit_result; + ALU_GREV, ALU_GORC: result_o = rev_result; + ALU_BFP: result_o = bfp_result; + ALU_CLMUL, ALU_CLMULR, ALU_CLMULH: result_o = clmul_result; + default: + ; + endcase + end +endmodule +module brqrv_exu_multdiv_fast ( + clk_i, + rst_ni, + mult_en_i, + div_en_i, + mult_sel_i, + div_sel_i, + operator_i, + signed_mode_i, + op_a_i, + op_b_i, + alu_adder_ext_i, + alu_adder_i, + equal_to_zero_i, + data_ind_timing_i, + alu_operand_a_o, + alu_operand_b_o, + imd_val_q_i, + imd_val_d_o, + imd_val_we_o, + multdiv_ready_id_i, + multdiv_result_o, + valid_o +); + localparam integer brqrv_pkg_RV32MFast = 2; + parameter integer RV32M = brqrv_pkg_RV32MFast; + input wire clk_i; + input wire rst_ni; + input wire mult_en_i; + input wire div_en_i; + input wire mult_sel_i; + input wire div_sel_i; + input wire [1:0] operator_i; + input wire [1:0] signed_mode_i; + input wire [31:0] op_a_i; + input wire [31:0] op_b_i; + input wire [33:0] alu_adder_ext_i; + input wire [31:0] alu_adder_i; + input wire equal_to_zero_i; + input wire data_ind_timing_i; + output reg [32:0] alu_operand_a_o; + output reg [32:0] alu_operand_b_o; + input wire [67:0] imd_val_q_i; + output wire [67:0] imd_val_d_o; + output wire [1:0] imd_val_we_o; + input wire multdiv_ready_id_i; + output wire [31:0] multdiv_result_o; + output wire valid_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire signed [34:0] mac_res_signed; + wire [34:0] mac_res_ext; + reg [33:0] accum; + reg sign_a; + reg sign_b; + reg mult_valid; + wire signed_mult; + reg [33:0] mac_res_d; + reg [33:0] op_remainder_d; + wire [33:0] mac_res; + wire div_sign_a; + wire div_sign_b; + reg is_greater_equal; + wire div_change_sign; + wire rem_change_sign; + wire [31:0] one_shift; + wire [31:0] op_denominator_q; + reg [31:0] op_numerator_q; + reg [31:0] op_quotient_q; + reg [31:0] op_denominator_d; + reg [31:0] op_numerator_d; + reg [31:0] op_quotient_d; + wire [31:0] next_remainder; + wire [32:0] next_quotient; + wire [32:0] res_adder_h; + reg div_valid; + reg [4:0] div_counter_q; + reg [4:0] div_counter_d; + wire multdiv_en; + reg mult_hold; + reg div_hold; + reg div_by_zero_d; + reg div_by_zero_q; + wire mult_en_internal; + wire div_en_internal; + reg [2:0] md_state_q; + reg [2:0] md_state_d; + wire unused_mult_sel_i; + assign unused_mult_sel_i = mult_sel_i; + assign mult_en_internal = mult_en_i & ~mult_hold; + assign div_en_internal = div_en_i & ~div_hold; + localparam [2:0] MD_IDLE = 0; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + div_counter_q <= {5 {1'sb0}}; + md_state_q <= MD_IDLE; + op_numerator_q <= {32 {1'sb0}}; + op_quotient_q <= {32 {1'sb0}}; + div_by_zero_q <= 1'sb0; + end + else if (div_en_internal) begin + div_counter_q <= div_counter_d; + op_numerator_q <= op_numerator_d; + op_quotient_q <= op_quotient_d; + md_state_q <= md_state_d; + div_by_zero_q <= div_by_zero_d; + end + assign multdiv_en = mult_en_internal | div_en_internal; + assign imd_val_d_o[34+:34] = (div_sel_i ? op_remainder_d : mac_res_d); + assign imd_val_we_o[0] = multdiv_en; + assign imd_val_d_o[0+:34] = {2'b00, op_denominator_d}; + assign imd_val_we_o[1] = div_en_internal; + assign op_denominator_q = imd_val_q_i[31-:32]; + wire [1:0] unused_imd_val; + assign unused_imd_val = imd_val_q_i[33-:2]; + assign signed_mult = signed_mode_i != 2'b00; + assign multdiv_result_o = (div_sel_i ? imd_val_q_i[65-:32] : mac_res_d[31:0]); + localparam [1:0] AHBH = 3; + localparam [1:0] AHBL = 2; + localparam [1:0] ALBH = 1; + localparam [1:0] ALBL = 0; + localparam [0:0] MULH = 1; + localparam [0:0] MULL = 0; + generate + if (RV32M == RV32MSingleCycle) begin : gen_mult_single_cycle + reg mult_state_q; + reg mult_state_d; + wire signed [33:0] mult1_res; + wire signed [33:0] mult2_res; + wire signed [33:0] mult3_res; + wire [15:0] mult1_op_a; + wire [15:0] mult1_op_b; + wire [15:0] mult2_op_a; + wire [15:0] mult2_op_b; + reg [15:0] mult3_op_a; + reg [15:0] mult3_op_b; + wire mult1_sign_a; + wire mult1_sign_b; + wire mult2_sign_a; + wire mult2_sign_b; + reg mult3_sign_a; + reg mult3_sign_b; + reg [33:0] summand1; + reg [33:0] summand2; + reg [33:0] summand3; + assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b}); + assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b}); + assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b}); + assign mac_res_signed = ($signed(summand1) + $signed(summand2)) + $signed(summand3); + assign mac_res_ext = $unsigned(mac_res_signed); + assign mac_res = mac_res_ext[33:0]; + always @(*) sign_a = signed_mode_i[0] & op_a_i[31]; + always @(*) sign_b = signed_mode_i[1] & op_b_i[31]; + assign mult1_sign_a = 1'b0; + assign mult1_sign_b = 1'b0; + assign mult1_op_a = op_a_i[15:0]; + assign mult1_op_b = op_b_i[15:0]; + assign mult2_sign_a = 1'b0; + assign mult2_sign_b = sign_b; + assign mult2_op_a = op_a_i[15:0]; + assign mult2_op_b = op_b_i[31:16]; + always @(*) accum[17:0] = imd_val_q_i[67-:18]; + always @(*) accum[33:18] = {16 {signed_mult & imd_val_q_i[67]}}; + always @(*) begin + mult3_sign_a = sign_a; + mult3_sign_b = 1'b0; + mult3_op_a = op_a_i[31:16]; + mult3_op_b = op_b_i[15:0]; + summand1 = {18'h00000, mult1_res[31:16]}; + summand2 = mult2_res; + summand3 = mult3_res; + mac_res_d = {2'b00, mac_res[15:0], mult1_res[15:0]}; + mult_valid = mult_en_i; + mult_state_d = MULL; + mult_hold = 1'b0; + case (mult_state_q) + MULL: + if (operator_i != MD_OP_MULL) begin + mac_res_d = mac_res; + mult_valid = 1'b0; + mult_state_d = MULH; + end + else + mult_hold = ~multdiv_ready_id_i; + MULH: begin + mult3_sign_a = sign_a; + mult3_sign_b = sign_b; + mult3_op_a = op_a_i[31:16]; + mult3_op_b = op_b_i[31:16]; + mac_res_d = mac_res; + summand1 = {34 {1'sb0}}; + summand2 = accum; + summand3 = mult3_res; + mult_state_d = MULL; + mult_valid = 1'b1; + mult_hold = ~multdiv_ready_id_i; + end + default: mult_state_d = MULL; + endcase + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mult_state_q <= MULL; + else if (mult_en_internal) + mult_state_q <= mult_state_d; + end + else begin : gen_mult_fast + reg [15:0] mult_op_a; + reg [15:0] mult_op_b; + reg [1:0] mult_state_q; + reg [1:0] mult_state_d; + assign mac_res_signed = ($signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b})) + $signed(accum); + assign mac_res_ext = $unsigned(mac_res_signed); + assign mac_res = mac_res_ext[33:0]; + always @(*) begin + mult_op_a = op_a_i[15:0]; + mult_op_b = op_b_i[15:0]; + sign_a = 1'b0; + sign_b = 1'b0; + accum = imd_val_q_i[34+:34]; + mac_res_d = mac_res; + mult_state_d = mult_state_q; + mult_valid = 1'b0; + mult_hold = 1'b0; + case (mult_state_q) + ALBL: begin + mult_op_a = op_a_i[15:0]; + mult_op_b = op_b_i[15:0]; + sign_a = 1'b0; + sign_b = 1'b0; + accum = {34 {1'sb0}}; + mac_res_d = mac_res; + mult_state_d = ALBH; + end + ALBH: begin + mult_op_a = op_a_i[15:0]; + mult_op_b = op_b_i[31:16]; + sign_a = 1'b0; + sign_b = signed_mode_i[1] & op_b_i[31]; + accum = {18'b000000000000000000, imd_val_q_i[65-:16]}; + if (operator_i == MD_OP_MULL) + mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]}; + else + mac_res_d = mac_res; + mult_state_d = AHBL; + end + AHBL: begin + mult_op_a = op_a_i[31:16]; + mult_op_b = op_b_i[15:0]; + sign_a = signed_mode_i[0] & op_a_i[31]; + sign_b = 1'b0; + if (operator_i == MD_OP_MULL) begin + accum = {18'b000000000000000000, imd_val_q_i[65-:16]}; + mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]}; + mult_valid = 1'b1; + mult_state_d = ALBL; + mult_hold = ~multdiv_ready_id_i; + end + else begin + accum = imd_val_q_i[34+:34]; + mac_res_d = mac_res; + mult_state_d = AHBH; + end + end + AHBH: begin + mult_op_a = op_a_i[31:16]; + mult_op_b = op_b_i[31:16]; + sign_a = signed_mode_i[0] & op_a_i[31]; + sign_b = signed_mode_i[1] & op_b_i[31]; + accum[17:0] = imd_val_q_i[67-:18]; + accum[33:18] = {16 {signed_mult & imd_val_q_i[67]}}; + mac_res_d = mac_res; + mult_valid = 1'b1; + mult_state_d = ALBL; + mult_hold = ~multdiv_ready_id_i; + end + default: mult_state_d = ALBL; + endcase + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mult_state_q <= ALBL; + else if (mult_en_internal) + mult_state_q <= mult_state_d; + end + endgenerate + assign res_adder_h = alu_adder_ext_i[33:1]; + assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[65-:32]); + assign next_quotient = (is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : {1'b0, op_quotient_q}); + assign one_shift = {31'b0000000000000000000000000000000, 1'b1} << div_counter_q; + always @(*) + if ((imd_val_q_i[65] ^ op_denominator_q[31]) == 1'b0) + is_greater_equal = res_adder_h[31] == 1'b0; + else + is_greater_equal = imd_val_q_i[65]; + assign div_sign_a = op_a_i[31] & signed_mode_i[0]; + assign div_sign_b = op_b_i[31] & signed_mode_i[1]; + assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q; + assign rem_change_sign = div_sign_a; + localparam [2:0] MD_ABS_A = 1; + localparam [2:0] MD_ABS_B = 2; + localparam [2:0] MD_CHANGE_SIGN = 5; + localparam [2:0] MD_COMP = 3; + localparam [2:0] MD_FINISH = 6; + localparam [2:0] MD_LAST = 4; + always @(*) begin + div_counter_d = div_counter_q - 5'h01; + op_remainder_d = imd_val_q_i[34+:34]; + op_quotient_d = op_quotient_q; + md_state_d = md_state_q; + op_numerator_d = op_numerator_q; + op_denominator_d = op_denominator_q; + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + div_valid = 1'b0; + div_hold = 1'b0; + div_by_zero_d = div_by_zero_q; + case (md_state_q) + MD_IDLE: begin + if (operator_i == MD_OP_DIV) begin + op_remainder_d = {34 {1'sb1}}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); + div_by_zero_d = equal_to_zero_i; + end + else begin + op_remainder_d = {2'b00, op_a_i}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); + end + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + div_counter_d = 5'd31; + end + MD_ABS_A: begin + op_quotient_d = {32 {1'sb0}}; + op_numerator_d = (div_sign_a ? alu_adder_i : op_a_i); + md_state_d = MD_ABS_B; + div_counter_d = 5'd31; + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_a_i, 1'b1}; + end + MD_ABS_B: begin + op_remainder_d = {33'h000000000, op_numerator_q[31]}; + op_denominator_d = (div_sign_b ? alu_adder_i : op_b_i); + md_state_d = MD_COMP; + div_counter_d = 5'd31; + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_COMP: begin + op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]}; + op_quotient_d = next_quotient[31:0]; + md_state_d = (div_counter_q == 5'd1 ? MD_LAST : MD_COMP); + alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1}; + alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; + end + MD_LAST: begin + if (operator_i == MD_OP_DIV) + op_remainder_d = {1'b0, next_quotient}; + else + op_remainder_d = {2'b00, next_remainder[31:0]}; + alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1}; + alu_operand_b_o = {~op_denominator_q[31:0], 1'b1}; + md_state_d = MD_CHANGE_SIGN; + end + MD_CHANGE_SIGN: begin + md_state_d = MD_FINISH; + if (operator_i == MD_OP_DIV) + op_remainder_d = (div_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]); + else + op_remainder_d = (rem_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]); + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~imd_val_q_i[65-:32], 1'b1}; + end + MD_FINISH: begin + md_state_d = MD_IDLE; + div_hold = ~multdiv_ready_id_i; + div_valid = 1'b1; + end + default: md_state_d = MD_IDLE; + endcase + end + assign valid_o = mult_valid | div_valid; +endmodule +module brqrv_exu_multdiv_slow ( + clk_i, + rst_ni, + mult_en_i, + div_en_i, + mult_sel_i, + div_sel_i, + operator_i, + signed_mode_i, + op_a_i, + op_b_i, + alu_adder_ext_i, + alu_adder_i, + equal_to_zero_i, + data_ind_timing_i, + alu_operand_a_o, + alu_operand_b_o, + imd_val_q_i, + imd_val_d_o, + imd_val_we_o, + multdiv_ready_id_i, + multdiv_result_o, + valid_o +); + input wire clk_i; + input wire rst_ni; + input wire mult_en_i; + input wire div_en_i; + input wire mult_sel_i; + input wire div_sel_i; + input wire [1:0] operator_i; + input wire [1:0] signed_mode_i; + input wire [31:0] op_a_i; + input wire [31:0] op_b_i; + input wire [33:0] alu_adder_ext_i; + input wire [31:0] alu_adder_i; + input wire equal_to_zero_i; + input wire data_ind_timing_i; + output reg [32:0] alu_operand_a_o; + output reg [32:0] alu_operand_b_o; + input wire [67:0] imd_val_q_i; + output wire [67:0] imd_val_d_o; + output wire [1:0] imd_val_we_o; + input wire multdiv_ready_id_i; + output wire [31:0] multdiv_result_o; + output wire valid_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + reg [2:0] md_state_q; + reg [2:0] md_state_d; + wire [32:0] accum_window_q; + reg [32:0] accum_window_d; + wire unused_imd_val0; + wire [1:0] unused_imd_val1; + wire [32:0] res_adder_l; + wire [32:0] res_adder_h; + reg [4:0] multdiv_count_q; + reg [4:0] multdiv_count_d; + reg [32:0] op_b_shift_q; + reg [32:0] op_b_shift_d; + reg [32:0] op_a_shift_q; + reg [32:0] op_a_shift_d; + wire [32:0] op_a_ext; + wire [32:0] op_b_ext; + wire [32:0] one_shift; + wire [32:0] op_a_bw_pp; + wire [32:0] op_a_bw_last_pp; + wire [31:0] b_0; + wire sign_a; + wire sign_b; + wire [32:0] next_quotient; + wire [31:0] next_remainder; + wire [31:0] op_numerator_q; + reg [31:0] op_numerator_d; + wire is_greater_equal; + wire div_change_sign; + wire rem_change_sign; + reg div_by_zero_d; + reg div_by_zero_q; + reg multdiv_hold; + wire multdiv_en; + assign res_adder_l = alu_adder_ext_i[32:0]; + assign res_adder_h = alu_adder_ext_i[33:1]; + assign imd_val_d_o[34+:34] = {1'b0, accum_window_d}; + assign imd_val_we_o[0] = ~multdiv_hold; + assign accum_window_q = imd_val_q_i[66-:33]; + assign unused_imd_val0 = imd_val_q_i[67]; + assign imd_val_d_o[0+:34] = {2'b00, op_numerator_d}; + assign imd_val_we_o[1] = multdiv_en; + assign op_numerator_q = imd_val_q_i[31-:32]; + assign unused_imd_val1 = imd_val_q_i[33-:2]; + localparam [2:0] MD_ABS_A = 1; + localparam [2:0] MD_ABS_B = 2; + localparam [2:0] MD_CHANGE_SIGN = 5; + localparam [2:0] MD_IDLE = 0; + localparam [2:0] MD_LAST = 4; + always @(*) begin + alu_operand_a_o = accum_window_q; + case (operator_i) + MD_OP_MULL: alu_operand_b_o = op_a_bw_pp; + MD_OP_MULH: alu_operand_b_o = (md_state_q == MD_LAST ? op_a_bw_last_pp : op_a_bw_pp); + MD_OP_DIV, MD_OP_REM: + case (md_state_q) + MD_IDLE: begin + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_ABS_A: begin + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_a_i, 1'b1}; + end + MD_ABS_B: begin + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~op_b_i, 1'b1}; + end + MD_CHANGE_SIGN: begin + alu_operand_a_o = {32'h00000000, 1'b1}; + alu_operand_b_o = {~accum_window_q[31:0], 1'b1}; + end + default: begin + alu_operand_a_o = {accum_window_q[31:0], 1'b1}; + alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; + end + endcase + default: begin + alu_operand_a_o = accum_window_q; + alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1}; + end + endcase + end + assign b_0 = {32 {op_b_shift_q[0]}}; + assign op_a_bw_pp = {~(op_a_shift_q[32] & op_b_shift_q[0]), op_a_shift_q[31:0] & b_0}; + assign op_a_bw_last_pp = {op_a_shift_q[32] & op_b_shift_q[0], ~(op_a_shift_q[31:0] & b_0)}; + assign sign_a = op_a_i[31] & signed_mode_i[0]; + assign sign_b = op_b_i[31] & signed_mode_i[1]; + assign op_a_ext = {sign_a, op_a_i}; + assign op_b_ext = {sign_b, op_b_i}; + assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31] ? ~res_adder_h[31] : accum_window_q[31]); + assign one_shift = {32'b00000000000000000000000000000000, 1'b1} << multdiv_count_q; + assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : accum_window_q[31:0]); + assign next_quotient = (is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q); + assign div_change_sign = (sign_a ^ sign_b) & ~div_by_zero_q; + assign rem_change_sign = sign_a; + localparam [2:0] MD_COMP = 3; + localparam [2:0] MD_FINISH = 6; + always @(*) begin + multdiv_count_d = multdiv_count_q; + accum_window_d = accum_window_q; + op_b_shift_d = op_b_shift_q; + op_a_shift_d = op_a_shift_q; + op_numerator_d = op_numerator_q; + md_state_d = md_state_q; + multdiv_hold = 1'b0; + div_by_zero_d = div_by_zero_q; + if (mult_sel_i || div_sel_i) + case (md_state_q) + MD_IDLE: begin + case (operator_i) + MD_OP_MULL: begin + op_a_shift_d = op_a_ext << 1; + accum_window_d = {~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:0] & {32 {op_b_i[0]}}}; + op_b_shift_d = op_b_ext >> 1; + md_state_d = (!data_ind_timing_i && ((op_b_ext >> 1) == 0) ? MD_LAST : MD_COMP); + end + MD_OP_MULH: begin + op_a_shift_d = op_a_ext; + accum_window_d = {1'b1, ~(op_a_ext[32] & op_b_i[0]), op_a_ext[31:1] & {31 {op_b_i[0]}}}; + op_b_shift_d = op_b_ext >> 1; + md_state_d = MD_COMP; + end + MD_OP_DIV: begin + accum_window_d = {33 {1'b1}}; + md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); + div_by_zero_d = equal_to_zero_i; + end + MD_OP_REM: begin + accum_window_d = op_a_ext; + md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A); + end + default: + ; + endcase + multdiv_count_d = 5'd31; + end + MD_ABS_A: begin + op_a_shift_d = {33 {1'sb0}}; + op_numerator_d = (sign_a ? alu_adder_i : op_a_i); + md_state_d = MD_ABS_B; + end + MD_ABS_B: begin + accum_window_d = {32'h00000000, op_numerator_q[31]}; + op_b_shift_d = (sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i}); + md_state_d = MD_COMP; + end + MD_COMP: begin + multdiv_count_d = multdiv_count_q - 5'h01; + case (operator_i) + MD_OP_MULL: begin + accum_window_d = res_adder_l; + op_a_shift_d = op_a_shift_q << 1; + op_b_shift_d = op_b_shift_q >> 1; + md_state_d = ((!data_ind_timing_i && (op_b_shift_d == 0)) || (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP); + end + MD_OP_MULH: begin + accum_window_d = res_adder_h; + op_a_shift_d = op_a_shift_q; + op_b_shift_d = op_b_shift_q >> 1; + md_state_d = (multdiv_count_q == 5'd1 ? MD_LAST : MD_COMP); + end + MD_OP_DIV, MD_OP_REM: begin + accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]}; + op_a_shift_d = next_quotient; + md_state_d = (multdiv_count_q == 5'd1 ? MD_LAST : MD_COMP); + end + default: + ; + endcase + end + MD_LAST: + case (operator_i) + MD_OP_MULL: begin + accum_window_d = res_adder_l; + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + MD_OP_MULH: begin + accum_window_d = res_adder_l; + md_state_d = MD_IDLE; + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + MD_OP_DIV: begin + accum_window_d = next_quotient; + md_state_d = MD_CHANGE_SIGN; + end + MD_OP_REM: begin + accum_window_d = {1'b0, next_remainder[31:0]}; + md_state_d = MD_CHANGE_SIGN; + end + default: + ; + endcase + MD_CHANGE_SIGN: begin + md_state_d = MD_FINISH; + case (operator_i) + MD_OP_DIV: accum_window_d = (div_change_sign ? {1'b0, alu_adder_i} : accum_window_q); + MD_OP_REM: accum_window_d = (rem_change_sign ? {1'b0, alu_adder_i} : accum_window_q); + default: + ; + endcase + end + MD_FINISH: begin + md_state_d = MD_IDLE; + multdiv_hold = ~multdiv_ready_id_i; + end + default: md_state_d = MD_IDLE; + endcase + end + assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + multdiv_count_q <= 5'h00; + op_b_shift_q <= 33'h000000000; + op_a_shift_q <= 33'h000000000; + md_state_q <= MD_IDLE; + div_by_zero_q <= 1'b0; + end + else if (multdiv_en) begin + multdiv_count_q <= multdiv_count_d; + op_b_shift_q <= op_b_shift_d; + op_a_shift_q <= op_a_shift_d; + md_state_q <= md_state_d; + div_by_zero_q <= div_by_zero_d; + end + assign valid_o = (md_state_q == MD_FINISH) | ((md_state_q == MD_LAST) & ((operator_i == MD_OP_MULL) | (operator_i == MD_OP_MULH))); + assign multdiv_result_o = (div_en_i ? accum_window_q[31:0] : res_adder_l[31:0]); +endmodule +module brqrv_idu ( + clk_i, + rst_ni, + ctrl_busy_o, + illegal_insn_o, + instr_valid_i, + instr_rdata_i, + instr_rdata_alu_i, + instr_rdata_c_i, + instr_is_compressed_i, + instr_bp_taken_i, + instr_req_o, + instr_first_cycle_id_o, + instr_valid_clear_o, + id_in_ready_o, + icache_inval_o, + branch_decision_i, + pc_set_o, + pc_set_spec_o, + pc_mux_o, + nt_branch_mispredict_o, + exc_pc_mux_o, + exc_cause_o, + illegal_c_insn_i, + instr_fetch_err_i, + instr_fetch_err_plus2_i, + pc_id_i, + ex_valid_i, + lsu_resp_valid_i, + alu_operator_ex_o, + alu_operand_a_ex_o, + alu_operand_b_ex_o, + imd_val_we_ex_i, + imd_val_d_ex_i, + imd_val_q_ex_o, + bt_a_operand_o, + bt_b_operand_o, + mult_en_ex_o, + div_en_ex_o, + mult_sel_ex_o, + div_sel_ex_o, + multdiv_operator_ex_o, + multdiv_signed_mode_ex_o, + multdiv_operand_a_ex_o, + multdiv_operand_b_ex_o, + multdiv_ready_id_o, + csr_access_o, + csr_op_o, + csr_op_en_o, + csr_save_if_o, + csr_save_id_o, + csr_save_wb_o, + csr_restore_mret_id_o, + csr_restore_dret_id_o, + csr_save_cause_o, + csr_mtval_o, + priv_mode_i, + csr_mstatus_tw_i, + illegal_csr_insn_i, + data_ind_timing_i, + lsu_req_o, + lsu_we_o, + lsu_type_o, + lsu_sign_ext_o, + lsu_wdata_o, + lsu_req_done_i, + lsu_addr_incr_req_i, + lsu_addr_last_i, + csr_mstatus_mie_i, + irq_pending_i, + irqs_i, + irq_nm_i, + nmi_mode_o, + lsu_load_err_i, + lsu_store_err_i, + debug_mode_o, + debug_cause_o, + debug_csr_save_o, + debug_req_i, + debug_single_step_i, + debug_ebreakm_i, + debug_ebreaku_i, + trigger_match_i, + result_ex_i, + csr_rdata_i, + rf_raddr_a_o, + rf_rdata_a_i, + rf_raddr_b_o, + rf_rdata_b_i, + rf_ren_a_o, + rf_ren_b_o, + rf_waddr_id_o, + rf_wdata_id_o, + rf_we_id_o, + rf_rd_a_wb_match_o, + rf_rd_b_wb_match_o, + rf_waddr_wb_i, + rf_wdata_fwd_wb_i, + rf_write_wb_i, + en_wb_o, + instr_type_wb_o, + ready_wb_i, + outstanding_load_wb_i, + outstanding_store_wb_i, + perf_jump_o, + perf_branch_o, + perf_tbranch_o, + perf_dside_wait_o, + perf_mul_wait_o, + perf_div_wait_o, + instr_id_done_o, + instr_id_done_compressed_o +); + parameter [0:0] RV32E = 0; + localparam integer brqrv_pkg_RV32MFast = 2; + parameter integer RV32M = brqrv_pkg_RV32MFast; + localparam integer brqrv_pkg_RV32BNone = 0; + parameter integer RV32B = brqrv_pkg_RV32BNone; + parameter [0:0] DataIndTiming = 1'b0; + parameter [0:0] BranchTargetALU = 0; + parameter [0:0] SpecBranch = 0; + parameter [0:0] WritebackStage = 0; + parameter [0:0] BranchPredictor = 0; + input wire clk_i; + input wire rst_ni; + output wire ctrl_busy_o; + output wire illegal_insn_o; + input wire instr_valid_i; + input wire [31:0] instr_rdata_i; + input wire [31:0] instr_rdata_alu_i; + input wire [15:0] instr_rdata_c_i; + input wire instr_is_compressed_i; + input wire instr_bp_taken_i; + output wire instr_req_o; + output wire instr_first_cycle_id_o; + output wire instr_valid_clear_o; + output wire id_in_ready_o; + output wire icache_inval_o; + input wire branch_decision_i; + output wire pc_set_o; + output wire pc_set_spec_o; + output wire [2:0] pc_mux_o; + output wire nt_branch_mispredict_o; + output wire [1:0] exc_pc_mux_o; + output wire [5:0] exc_cause_o; + input wire illegal_c_insn_i; + input wire instr_fetch_err_i; + input wire instr_fetch_err_plus2_i; + input wire [31:0] pc_id_i; + input wire ex_valid_i; + input wire lsu_resp_valid_i; + output wire [5:0] alu_operator_ex_o; + output wire [31:0] alu_operand_a_ex_o; + output wire [31:0] alu_operand_b_ex_o; + input wire [1:0] imd_val_we_ex_i; + input wire [67:0] imd_val_d_ex_i; + output wire [67:0] imd_val_q_ex_o; + output reg [31:0] bt_a_operand_o; + output reg [31:0] bt_b_operand_o; + output wire mult_en_ex_o; + output wire div_en_ex_o; + output wire mult_sel_ex_o; + output wire div_sel_ex_o; + output wire [1:0] multdiv_operator_ex_o; + output wire [1:0] multdiv_signed_mode_ex_o; + output wire [31:0] multdiv_operand_a_ex_o; + output wire [31:0] multdiv_operand_b_ex_o; + output wire multdiv_ready_id_o; + output wire csr_access_o; + output wire [1:0] csr_op_o; + output wire csr_op_en_o; + output wire csr_save_if_o; + output wire csr_save_id_o; + output wire csr_save_wb_o; + output wire csr_restore_mret_id_o; + output wire csr_restore_dret_id_o; + output wire csr_save_cause_o; + output wire [31:0] csr_mtval_o; + input wire [1:0] priv_mode_i; + input wire csr_mstatus_tw_i; + input wire illegal_csr_insn_i; + input wire data_ind_timing_i; + output wire lsu_req_o; + output wire lsu_we_o; + output wire [1:0] lsu_type_o; + output wire lsu_sign_ext_o; + output wire [31:0] lsu_wdata_o; + input wire lsu_req_done_i; + input wire lsu_addr_incr_req_i; + input wire [31:0] lsu_addr_last_i; + input wire csr_mstatus_mie_i; + input wire irq_pending_i; + input wire [17:0] irqs_i; + input wire irq_nm_i; + output wire nmi_mode_o; + input wire lsu_load_err_i; + input wire lsu_store_err_i; + output wire debug_mode_o; + output wire [2:0] debug_cause_o; + output wire debug_csr_save_o; + input wire debug_req_i; + input wire debug_single_step_i; + input wire debug_ebreakm_i; + input wire debug_ebreaku_i; + input wire trigger_match_i; + input wire [31:0] result_ex_i; + input wire [31:0] csr_rdata_i; + output wire [4:0] rf_raddr_a_o; + input wire [31:0] rf_rdata_a_i; + output wire [4:0] rf_raddr_b_o; + input wire [31:0] rf_rdata_b_i; + output wire rf_ren_a_o; + output wire rf_ren_b_o; + output wire [4:0] rf_waddr_id_o; + output reg [31:0] rf_wdata_id_o; + output wire rf_we_id_o; + output wire rf_rd_a_wb_match_o; + output wire rf_rd_b_wb_match_o; + input wire [4:0] rf_waddr_wb_i; + input wire [31:0] rf_wdata_fwd_wb_i; + input wire rf_write_wb_i; + output wire en_wb_o; + output wire [1:0] instr_type_wb_o; + input wire ready_wb_i; + input wire outstanding_load_wb_i; + input wire outstanding_store_wb_i; + output wire perf_jump_o; + output reg perf_branch_o; + output wire perf_tbranch_o; + output wire perf_dside_wait_o; + output wire perf_mul_wait_o; + output wire perf_div_wait_o; + output wire instr_id_done_o; + output wire instr_id_done_compressed_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire illegal_insn_dec; + wire ebrk_insn; + wire mret_insn_dec; + wire dret_insn_dec; + wire ecall_insn_dec; + wire wfi_insn_dec; + wire wb_exception; + wire branch_in_dec; + reg branch_spec; + wire branch_set_spec; + wire branch_set; + reg branch_set_d; + reg branch_not_set; + wire branch_taken; + wire jump_in_dec; + wire jump_set_dec; + reg jump_set; + wire instr_first_cycle; + wire instr_executing; + wire instr_done; + wire controller_run; + wire stall_ld_hz; + wire stall_mem; + reg stall_multdiv; + reg stall_branch; + reg stall_jump; + wire stall_id; + wire stall_wb; + wire flush_id; + wire multicycle_done; + wire [31:0] imm_i_type; + wire [31:0] imm_s_type; + wire [31:0] imm_b_type; + wire [31:0] imm_u_type; + wire [31:0] imm_j_type; + wire [31:0] zimm_rs1_type; + wire [31:0] imm_a; + reg [31:0] imm_b; + wire rf_wdata_sel; + wire rf_we_dec; + reg rf_we_raw; + wire rf_ren_a; + wire rf_ren_b; + assign rf_ren_a_o = rf_ren_a; + assign rf_ren_b_o = rf_ren_b; + wire [31:0] rf_rdata_a_fwd; + wire [31:0] rf_rdata_b_fwd; + wire [5:0] alu_operator; + wire [1:0] alu_op_a_mux_sel; + wire [1:0] alu_op_a_mux_sel_dec; + wire alu_op_b_mux_sel; + wire alu_op_b_mux_sel_dec; + wire alu_multicycle_dec; + reg stall_alu; + reg [67:0] imd_val_q; + wire [1:0] bt_a_mux_sel; + wire [2:0] bt_b_mux_sel; + wire imm_a_mux_sel; + wire [2:0] imm_b_mux_sel; + wire [2:0] imm_b_mux_sel_dec; + wire mult_en_id; + wire mult_en_dec; + wire div_en_id; + wire div_en_dec; + wire multdiv_en_dec; + wire [1:0] multdiv_operator; + wire [1:0] multdiv_signed_mode; + wire lsu_we; + wire [1:0] lsu_type; + wire lsu_sign_ext; + wire lsu_req; + wire lsu_req_dec; + wire data_req_allowed; + reg csr_pipe_flush; + reg [31:0] alu_operand_a; + wire [31:0] alu_operand_b; + assign alu_op_a_mux_sel = (lsu_addr_incr_req_i ? OP_A_FWD : alu_op_a_mux_sel_dec); + assign alu_op_b_mux_sel = (lsu_addr_incr_req_i ? OP_B_IMM : alu_op_b_mux_sel_dec); + assign imm_b_mux_sel = (lsu_addr_incr_req_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec); + assign imm_a = (imm_a_mux_sel == IMM_A_Z ? zimm_rs1_type : {32 {1'sb0}}); + always @(*) begin : alu_operand_a_mux + case (alu_op_a_mux_sel) + OP_A_REG_A: alu_operand_a = rf_rdata_a_fwd; + OP_A_FWD: alu_operand_a = lsu_addr_last_i; + OP_A_CURRPC: alu_operand_a = pc_id_i; + OP_A_IMM: alu_operand_a = imm_a; + default: alu_operand_a = pc_id_i; + endcase + end + generate + if (BranchTargetALU) begin : g_btalu_muxes + always @(*) begin : bt_operand_a_mux + case (bt_a_mux_sel) + OP_A_REG_A: bt_a_operand_o = rf_rdata_a_fwd; + OP_A_CURRPC: bt_a_operand_o = pc_id_i; + default: bt_a_operand_o = pc_id_i; + endcase + end + always @(*) begin : bt_immediate_b_mux + case (bt_b_mux_sel) + IMM_B_I: bt_b_operand_o = imm_i_type; + IMM_B_B: bt_b_operand_o = imm_b_type; + IMM_B_J: bt_b_operand_o = imm_j_type; + IMM_B_INCR_PC: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); + default: bt_b_operand_o = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); + endcase + end + always @(*) begin : immediate_b_mux + case (imm_b_mux_sel) + IMM_B_I: imm_b = imm_i_type; + IMM_B_S: imm_b = imm_s_type; + IMM_B_U: imm_b = imm_u_type; + IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); + IMM_B_INCR_ADDR: imm_b = 32'h00000004; + default: imm_b = 32'h00000004; + endcase + end + end + else begin : g_nobtalu + wire [1:0] unused_a_mux_sel; + wire [2:0] unused_b_mux_sel; + assign unused_a_mux_sel = bt_a_mux_sel; + assign unused_b_mux_sel = bt_b_mux_sel; + always @(*) bt_a_operand_o = {32 {1'sb0}}; + always @(*) bt_b_operand_o = {32 {1'sb0}}; + always @(*) begin : immediate_b_mux + case (imm_b_mux_sel) + IMM_B_I: imm_b = imm_i_type; + IMM_B_S: imm_b = imm_s_type; + IMM_B_B: imm_b = imm_b_type; + IMM_B_U: imm_b = imm_u_type; + IMM_B_J: imm_b = imm_j_type; + IMM_B_INCR_PC: imm_b = (instr_is_compressed_i ? 32'h00000002 : 32'h00000004); + IMM_B_INCR_ADDR: imm_b = 32'h00000004; + default: imm_b = 32'h00000004; + endcase + end + end + endgenerate + assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM ? imm_b : rf_rdata_b_fwd); + generate + genvar i; + for (i = 0; i < 2; i = i + 1) begin : gen_intermediate_val_reg + always @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg + if (!rst_ni) + imd_val_q[(1 - i) * 34+:34] <= {34 {1'sb0}}; + else if (imd_val_we_ex_i[i]) + imd_val_q[(1 - i) * 34+:34] <= imd_val_d_ex_i[(1 - i) * 34+:34]; + end + end + endgenerate + assign imd_val_q_ex_o = imd_val_q; + assign rf_we_id_o = (rf_we_raw & instr_executing) & ~illegal_csr_insn_i; + always @(*) begin : rf_wdata_id_mux + case (rf_wdata_sel) + RF_WD_EX: rf_wdata_id_o = result_ex_i; + RF_WD_CSR: rf_wdata_id_o = csr_rdata_i; + default: rf_wdata_id_o = result_ex_i; + endcase + end + brqrv_idu_dec #( + .RV32E(RV32E), + .RV32M(RV32M), + .RV32B(RV32B), + .BranchTargetALU(BranchTargetALU) + ) decoder_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .illegal_insn_o(illegal_insn_dec), + .ebrk_insn_o(ebrk_insn), + .mret_insn_o(mret_insn_dec), + .dret_insn_o(dret_insn_dec), + .ecall_insn_o(ecall_insn_dec), + .wfi_insn_o(wfi_insn_dec), + .jump_set_o(jump_set_dec), + .branch_taken_i(branch_taken), + .icache_inval_o(icache_inval_o), + .instr_first_cycle_i(instr_first_cycle), + .instr_rdata_i(instr_rdata_i), + .instr_rdata_alu_i(instr_rdata_alu_i), + .illegal_c_insn_i(illegal_c_insn_i), + .imm_a_mux_sel_o(imm_a_mux_sel), + .imm_b_mux_sel_o(imm_b_mux_sel_dec), + .bt_a_mux_sel_o(bt_a_mux_sel), + .bt_b_mux_sel_o(bt_b_mux_sel), + .imm_i_type_o(imm_i_type), + .imm_s_type_o(imm_s_type), + .imm_b_type_o(imm_b_type), + .imm_u_type_o(imm_u_type), + .imm_j_type_o(imm_j_type), + .zimm_rs1_type_o(zimm_rs1_type), + .rf_wdata_sel_o(rf_wdata_sel), + .rf_we_o(rf_we_dec), + .rf_raddr_a_o(rf_raddr_a_o), + .rf_raddr_b_o(rf_raddr_b_o), + .rf_waddr_o(rf_waddr_id_o), + .rf_ren_a_o(rf_ren_a), + .rf_ren_b_o(rf_ren_b), + .alu_operator_o(alu_operator), + .alu_op_a_mux_sel_o(alu_op_a_mux_sel_dec), + .alu_op_b_mux_sel_o(alu_op_b_mux_sel_dec), + .alu_multicycle_o(alu_multicycle_dec), + .mult_en_o(mult_en_dec), + .div_en_o(div_en_dec), + .mult_sel_o(mult_sel_ex_o), + .div_sel_o(div_sel_ex_o), + .multdiv_operator_o(multdiv_operator), + .multdiv_signed_mode_o(multdiv_signed_mode), + .csr_access_o(csr_access_o), + .csr_op_o(csr_op_o), + .data_req_o(lsu_req_dec), + .data_we_o(lsu_we), + .data_type_o(lsu_type), + .data_sign_extension_o(lsu_sign_ext), + .jump_in_dec_o(jump_in_dec), + .branch_in_dec_o(branch_in_dec) + ); + function automatic [11:0] sv2v_cast_12; + input reg [11:0] inp; + sv2v_cast_12 = inp; + endfunction + always @(*) begin : csr_pipeline_flushes + csr_pipe_flush = 1'b0; + if ((csr_op_en_o == 1'b1) && ((csr_op_o == CSR_OP_WRITE) || (csr_op_o == CSR_OP_SET))) begin + if ((sv2v_cast_12(instr_rdata_i[31:20]) == CSR_MSTATUS) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_MIE)) + csr_pipe_flush = 1'b1; + end + else if ((csr_op_en_o == 1'b1) && (csr_op_o != CSR_OP_READ)) + if ((((sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DCSR) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DPC)) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DSCRATCH0)) || (sv2v_cast_12(instr_rdata_i[31:20]) == CSR_DSCRATCH1)) + csr_pipe_flush = 1'b1; + end + assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i); + brqrv_idu_controller #( + .WritebackStage(WritebackStage), + .BranchPredictor(BranchPredictor) + ) controller_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .ctrl_busy_o(ctrl_busy_o), + .illegal_insn_i(illegal_insn_o), + .ecall_insn_i(ecall_insn_dec), + .mret_insn_i(mret_insn_dec), + .dret_insn_i(dret_insn_dec), + .wfi_insn_i(wfi_insn_dec), + .ebrk_insn_i(ebrk_insn), + .csr_pipe_flush_i(csr_pipe_flush), + .instr_valid_i(instr_valid_i), + .instr_i(instr_rdata_i), + .instr_compressed_i(instr_rdata_c_i), + .instr_is_compressed_i(instr_is_compressed_i), + .instr_bp_taken_i(instr_bp_taken_i), + .instr_fetch_err_i(instr_fetch_err_i), + .instr_fetch_err_plus2_i(instr_fetch_err_plus2_i), + .pc_id_i(pc_id_i), + .instr_valid_clear_o(instr_valid_clear_o), + .id_in_ready_o(id_in_ready_o), + .controller_run_o(controller_run), + .instr_req_o(instr_req_o), + .pc_set_o(pc_set_o), + .pc_set_spec_o(pc_set_spec_o), + .pc_mux_o(pc_mux_o), + .nt_branch_mispredict_o(nt_branch_mispredict_o), + .exc_pc_mux_o(exc_pc_mux_o), + .exc_cause_o(exc_cause_o), + .lsu_addr_last_i(lsu_addr_last_i), + .load_err_i(lsu_load_err_i), + .store_err_i(lsu_store_err_i), + .wb_exception_o(wb_exception), + .branch_set_i(branch_set), + .branch_set_spec_i(branch_set_spec), + .branch_not_set_i(branch_not_set), + .jump_set_i(jump_set), + .csr_mstatus_mie_i(csr_mstatus_mie_i), + .irq_pending_i(irq_pending_i), + .irqs_i(irqs_i), + .irq_nm_i(irq_nm_i), + .nmi_mode_o(nmi_mode_o), + .csr_save_if_o(csr_save_if_o), + .csr_save_id_o(csr_save_id_o), + .csr_save_wb_o(csr_save_wb_o), + .csr_restore_mret_id_o(csr_restore_mret_id_o), + .csr_restore_dret_id_o(csr_restore_dret_id_o), + .csr_save_cause_o(csr_save_cause_o), + .csr_mtval_o(csr_mtval_o), + .priv_mode_i(priv_mode_i), + .csr_mstatus_tw_i(csr_mstatus_tw_i), + .debug_mode_o(debug_mode_o), + .debug_cause_o(debug_cause_o), + .debug_csr_save_o(debug_csr_save_o), + .debug_req_i(debug_req_i), + .debug_single_step_i(debug_single_step_i), + .debug_ebreakm_i(debug_ebreakm_i), + .debug_ebreaku_i(debug_ebreaku_i), + .trigger_match_i(trigger_match_i), + .stall_id_i(stall_id), + .stall_wb_i(stall_wb), + .flush_id_o(flush_id), + .ready_wb_i(ready_wb_i), + .perf_jump_o(perf_jump_o), + .perf_tbranch_o(perf_tbranch_o) + ); + assign multdiv_en_dec = mult_en_dec | div_en_dec; + assign lsu_req = (instr_executing ? data_req_allowed & lsu_req_dec : 1'b0); + assign mult_en_id = (instr_executing ? mult_en_dec : 1'b0); + assign div_en_id = (instr_executing ? div_en_dec : 1'b0); + assign lsu_req_o = lsu_req; + assign lsu_we_o = lsu_we; + assign lsu_type_o = lsu_type; + assign lsu_sign_ext_o = lsu_sign_ext; + assign lsu_wdata_o = rf_rdata_b_fwd; + assign csr_op_en_o = (csr_access_o & instr_executing) & instr_id_done_o; + assign alu_operator_ex_o = alu_operator; + assign alu_operand_a_ex_o = alu_operand_a; + assign alu_operand_b_ex_o = alu_operand_b; + assign mult_en_ex_o = mult_en_id; + assign div_en_ex_o = div_en_id; + assign multdiv_operator_ex_o = multdiv_operator; + assign multdiv_signed_mode_ex_o = multdiv_signed_mode; + assign multdiv_operand_a_ex_o = rf_rdata_a_fwd; + assign multdiv_operand_b_ex_o = rf_rdata_b_fwd; + generate + if (BranchTargetALU && !DataIndTiming) begin : g_branch_set_direct + assign branch_set = branch_set_d; + assign branch_set_spec = branch_spec; + end + else begin : g_branch_set_flop + reg branch_set_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + branch_set_q <= 1'b0; + else + branch_set_q <= branch_set_d; + assign branch_set = (BranchTargetALU && !data_ind_timing_i ? branch_set_d : branch_set_q); + assign branch_set_spec = (BranchTargetALU && !data_ind_timing_i ? branch_spec : branch_set_q); + end + endgenerate + generate + if (DataIndTiming) begin : g_sec_branch_taken + reg branch_taken_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + branch_taken_q <= 1'b0; + else + branch_taken_q <= branch_decision_i; + assign branch_taken = ~data_ind_timing_i | branch_taken_q; + end + else begin : g_nosec_branch_taken + assign branch_taken = 1'b1; + end + endgenerate + reg id_fsm_q; + reg id_fsm_d; + localparam [0:0] FIRST_CYCLE = 0; + always @(posedge clk_i or negedge rst_ni) begin : id_pipeline_reg + if (!rst_ni) + id_fsm_q <= FIRST_CYCLE; + else + id_fsm_q <= id_fsm_d; + end + localparam [0:0] MULTI_CYCLE = 1; + always @(*) begin + id_fsm_d = id_fsm_q; + rf_we_raw = rf_we_dec; + stall_multdiv = 1'b0; + stall_jump = 1'b0; + stall_branch = 1'b0; + stall_alu = 1'b0; + branch_set_d = 1'b0; + branch_spec = 1'b0; + branch_not_set = 1'b0; + jump_set = 1'b0; + perf_branch_o = 1'b0; + if (instr_executing) + case (id_fsm_q) + FIRST_CYCLE: + case (1'b1) + lsu_req_dec: + if (!WritebackStage) + id_fsm_d = MULTI_CYCLE; + else if (~lsu_req_done_i) + id_fsm_d = MULTI_CYCLE; + multdiv_en_dec: + if (~ex_valid_i) begin + id_fsm_d = MULTI_CYCLE; + rf_we_raw = 1'b0; + stall_multdiv = 1'b1; + end + branch_in_dec: begin + id_fsm_d = (data_ind_timing_i || (!BranchTargetALU && branch_decision_i) ? MULTI_CYCLE : FIRST_CYCLE); + stall_branch = (~BranchTargetALU & branch_decision_i) | data_ind_timing_i; + branch_set_d = branch_decision_i | data_ind_timing_i; + if (BranchPredictor) + branch_not_set = ~branch_decision_i; + branch_spec = (SpecBranch ? 1'b1 : branch_decision_i); + perf_branch_o = 1'b1; + end + jump_in_dec: begin + id_fsm_d = (BranchTargetALU ? FIRST_CYCLE : MULTI_CYCLE); + stall_jump = ~BranchTargetALU; + jump_set = jump_set_dec; + end + alu_multicycle_dec: begin + stall_alu = 1'b1; + id_fsm_d = MULTI_CYCLE; + rf_we_raw = 1'b0; + end + default: id_fsm_d = FIRST_CYCLE; + endcase + MULTI_CYCLE: begin + if (multdiv_en_dec) + rf_we_raw = rf_we_dec & ex_valid_i; + if (multicycle_done & ready_wb_i) + id_fsm_d = FIRST_CYCLE; + else begin + stall_multdiv = multdiv_en_dec; + stall_branch = branch_in_dec; + stall_jump = jump_in_dec; + end + end + default: id_fsm_d = FIRST_CYCLE; + endcase + end + assign multdiv_ready_id_o = ready_wb_i; + assign stall_id = ((((stall_ld_hz | stall_mem) | stall_multdiv) | stall_jump) | stall_branch) | stall_alu; + assign instr_done = (~stall_id & ~flush_id) & instr_executing; + assign instr_first_cycle = instr_valid_i & (id_fsm_q == FIRST_CYCLE); + assign instr_first_cycle_id_o = instr_first_cycle; + generate + if (WritebackStage) begin : gen_stall_mem + wire rf_rd_a_wb_match; + wire rf_rd_b_wb_match; + wire rf_rd_a_hz; + wire rf_rd_b_hz; + wire outstanding_memory_access; + wire instr_kill; + assign multicycle_done = (lsu_req_dec ? ~stall_mem : ex_valid_i); + assign outstanding_memory_access = (outstanding_load_wb_i | outstanding_store_wb_i) & ~lsu_resp_valid_i; + assign data_req_allowed = ~outstanding_memory_access; + assign instr_kill = (instr_fetch_err_i | wb_exception) | ~controller_run; + assign instr_executing = ((instr_valid_i & ~instr_kill) & ~stall_ld_hz) & ~outstanding_memory_access; + assign stall_mem = instr_valid_i & (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); + assign rf_rd_a_wb_match = (rf_waddr_wb_i == rf_raddr_a_o) & |rf_raddr_a_o; + assign rf_rd_b_wb_match = (rf_waddr_wb_i == rf_raddr_b_o) & |rf_raddr_b_o; + assign rf_rd_a_wb_match_o = rf_rd_a_wb_match; + assign rf_rd_b_wb_match_o = rf_rd_b_wb_match; + assign rf_rd_a_hz = rf_rd_a_wb_match & rf_ren_a; + assign rf_rd_b_hz = rf_rd_b_wb_match & rf_ren_b; + assign rf_rdata_a_fwd = (rf_rd_a_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_a_i); + assign rf_rdata_b_fwd = (rf_rd_b_wb_match & rf_write_wb_i ? rf_wdata_fwd_wb_i : rf_rdata_b_i); + assign stall_ld_hz = outstanding_load_wb_i & (rf_rd_a_hz | rf_rd_b_hz); + assign instr_type_wb_o = (~lsu_req_dec ? WB_INSTR_OTHER : (lsu_we ? WB_INSTR_STORE : WB_INSTR_LOAD)); + assign en_wb_o = instr_done; + assign instr_id_done_o = en_wb_o & ready_wb_i; + assign stall_wb = en_wb_o & ~ready_wb_i; + assign perf_dside_wait_o = (instr_valid_i & ~instr_kill) & (outstanding_memory_access | stall_ld_hz); + end + else begin : gen_no_stall_mem + assign multicycle_done = (lsu_req_dec ? lsu_resp_valid_i : ex_valid_i); + assign data_req_allowed = instr_first_cycle; + assign stall_mem = instr_valid_i & (lsu_req_dec & (~lsu_resp_valid_i | instr_first_cycle)); + assign stall_ld_hz = 1'b0; + assign instr_executing = (instr_valid_i & ~instr_fetch_err_i) & controller_run; + assign rf_rdata_a_fwd = rf_rdata_a_i; + assign rf_rdata_b_fwd = rf_rdata_b_i; + assign rf_rd_a_wb_match_o = 1'b0; + assign rf_rd_b_wb_match_o = 1'b0; + wire unused_data_req_done_ex; + wire unused_lsu_load; + wire [4:0] unused_rf_waddr_wb; + wire unused_rf_write_wb; + wire unused_outstanding_load_wb; + wire unused_outstanding_store_wb; + wire unused_wb_exception; + wire [31:0] unused_rf_wdata_fwd_wb; + assign unused_data_req_done_ex = lsu_req_done_i; + assign unused_rf_waddr_wb = rf_waddr_wb_i; + assign unused_rf_write_wb = rf_write_wb_i; + assign unused_outstanding_load_wb = outstanding_load_wb_i; + assign unused_outstanding_store_wb = outstanding_store_wb_i; + assign unused_wb_exception = wb_exception; + assign unused_rf_wdata_fwd_wb = rf_wdata_fwd_wb_i; + assign instr_type_wb_o = WB_INSTR_OTHER; + assign stall_wb = 1'b0; + assign perf_dside_wait_o = (instr_executing & lsu_req_dec) & ~lsu_resp_valid_i; + assign en_wb_o = 1'b0; + assign instr_id_done_o = instr_done; + end + endgenerate + assign perf_mul_wait_o = stall_multdiv & mult_en_dec; + assign perf_div_wait_o = stall_multdiv & div_en_dec; + assign instr_id_done_compressed_o = instr_id_done_o & instr_is_compressed_i; +endmodule +module brqrv_idu_controller ( + clk_i, + rst_ni, + ctrl_busy_o, + illegal_insn_i, + ecall_insn_i, + mret_insn_i, + dret_insn_i, + wfi_insn_i, + ebrk_insn_i, + csr_pipe_flush_i, + instr_valid_i, + instr_i, + instr_compressed_i, + instr_is_compressed_i, + instr_bp_taken_i, + instr_fetch_err_i, + instr_fetch_err_plus2_i, + pc_id_i, + instr_valid_clear_o, + id_in_ready_o, + controller_run_o, + instr_req_o, + pc_set_o, + pc_set_spec_o, + pc_mux_o, + nt_branch_mispredict_o, + exc_pc_mux_o, + exc_cause_o, + lsu_addr_last_i, + load_err_i, + store_err_i, + wb_exception_o, + branch_set_i, + branch_set_spec_i, + branch_not_set_i, + jump_set_i, + csr_mstatus_mie_i, + irq_pending_i, + irqs_i, + irq_nm_i, + nmi_mode_o, + debug_req_i, + debug_cause_o, + debug_csr_save_o, + debug_mode_o, + debug_single_step_i, + debug_ebreakm_i, + debug_ebreaku_i, + trigger_match_i, + csr_save_if_o, + csr_save_id_o, + csr_save_wb_o, + csr_restore_mret_id_o, + csr_restore_dret_id_o, + csr_save_cause_o, + csr_mtval_o, + priv_mode_i, + csr_mstatus_tw_i, + stall_id_i, + stall_wb_i, + flush_id_o, + ready_wb_i, + perf_jump_o, + perf_tbranch_o +); + parameter [0:0] WritebackStage = 0; + parameter [0:0] BranchPredictor = 0; + input wire clk_i; + input wire rst_ni; + output reg ctrl_busy_o; + input wire illegal_insn_i; + input wire ecall_insn_i; + input wire mret_insn_i; + input wire dret_insn_i; + input wire wfi_insn_i; + input wire ebrk_insn_i; + input wire csr_pipe_flush_i; + input wire instr_valid_i; + input wire [31:0] instr_i; + input wire [15:0] instr_compressed_i; + input wire instr_is_compressed_i; + input wire instr_bp_taken_i; + input wire instr_fetch_err_i; + input wire instr_fetch_err_plus2_i; + input wire [31:0] pc_id_i; + output wire instr_valid_clear_o; + output wire id_in_ready_o; + output reg controller_run_o; + output reg instr_req_o; + output reg pc_set_o; + output reg pc_set_spec_o; + output reg [2:0] pc_mux_o; + output reg nt_branch_mispredict_o; + output reg [1:0] exc_pc_mux_o; + output reg [5:0] exc_cause_o; + input wire [31:0] lsu_addr_last_i; + input wire load_err_i; + input wire store_err_i; + output wire wb_exception_o; + input wire branch_set_i; + input wire branch_set_spec_i; + input wire branch_not_set_i; + input wire jump_set_i; + input wire csr_mstatus_mie_i; + input wire irq_pending_i; + input wire [17:0] irqs_i; + input wire irq_nm_i; + output wire nmi_mode_o; + input wire debug_req_i; + output reg [2:0] debug_cause_o; + output reg debug_csr_save_o; + output wire debug_mode_o; + input wire debug_single_step_i; + input wire debug_ebreakm_i; + input wire debug_ebreaku_i; + input wire trigger_match_i; + output reg csr_save_if_o; + output reg csr_save_id_o; + output reg csr_save_wb_o; + output reg csr_restore_mret_id_o; + output reg csr_restore_dret_id_o; + output reg csr_save_cause_o; + output reg [31:0] csr_mtval_o; + input wire [1:0] priv_mode_i; + input wire csr_mstatus_tw_i; + input wire stall_id_i; + input wire stall_wb_i; + output wire flush_id_o; + input wire ready_wb_i; + output reg perf_jump_o; + output reg perf_tbranch_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + reg [3:0] ctrl_fsm_cs; + reg [3:0] ctrl_fsm_ns; + reg nmi_mode_q; + reg nmi_mode_d; + reg debug_mode_q; + reg debug_mode_d; + reg load_err_q; + wire load_err_d; + reg store_err_q; + wire store_err_d; + reg exc_req_q; + wire exc_req_d; + reg illegal_insn_q; + wire illegal_insn_d; + reg instr_fetch_err_prio; + reg illegal_insn_prio; + reg ecall_insn_prio; + reg ebrk_insn_prio; + reg store_err_prio; + reg load_err_prio; + wire stall; + reg halt_if; + reg retain_id; + reg flush_id; + wire illegal_dret; + wire illegal_umode; + wire exc_req_lsu; + wire special_req_all; + wire special_req_branch; + wire enter_debug_mode; + wire ebreak_into_debug; + wire handle_irq; + reg [3:0] mfip_id; + wire unused_irq_timer; + wire ecall_insn; + wire mret_insn; + wire dret_insn; + wire wfi_insn; + wire ebrk_insn; + wire csr_pipe_flush; + wire instr_fetch_err; + localparam [3:0] DECODE = 5; + /*always @(negedge clk_i) + if ((((ctrl_fsm_cs == DECODE) && instr_valid_i) && !instr_fetch_err_i) && illegal_insn_d) + $display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, brqrv_core.hart_id_i, brqrv_idu.pc_id_i, brqrv_idu.instr_rdata_i); + */ + assign load_err_d = load_err_i; + assign store_err_d = store_err_i; + assign ecall_insn = ecall_insn_i & instr_valid_i; + assign mret_insn = mret_insn_i & instr_valid_i; + assign dret_insn = dret_insn_i & instr_valid_i; + assign wfi_insn = wfi_insn_i & instr_valid_i; + assign ebrk_insn = ebrk_insn_i & instr_valid_i; + assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i; + assign instr_fetch_err = instr_fetch_err_i & instr_valid_i; + assign illegal_dret = dret_insn & ~debug_mode_q; + assign illegal_umode = (priv_mode_i != PRIV_LVL_M) & (mret_insn | (csr_mstatus_tw_i & wfi_insn)); + localparam [3:0] FLUSH = 6; + assign illegal_insn_d = ((illegal_insn_i | illegal_dret) | illegal_umode) & (ctrl_fsm_cs != FLUSH); + assign exc_req_d = (((ecall_insn | ebrk_insn) | illegal_insn_d) | instr_fetch_err) & (ctrl_fsm_cs != FLUSH); + assign exc_req_lsu = store_err_i | load_err_i; + assign special_req_all = ((((mret_insn | dret_insn) | wfi_insn) | csr_pipe_flush) | exc_req_d) | exc_req_lsu; + assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH); + generate + if (WritebackStage) begin : g_wb_exceptions + always @(*) begin + instr_fetch_err_prio = 0; + illegal_insn_prio = 0; + ecall_insn_prio = 0; + ebrk_insn_prio = 0; + store_err_prio = 0; + load_err_prio = 0; + if (store_err_q) + store_err_prio = 1'b1; + else if (load_err_q) + load_err_prio = 1'b1; + else if (instr_fetch_err) + instr_fetch_err_prio = 1'b1; + else if (illegal_insn_q) + illegal_insn_prio = 1'b1; + else if (ecall_insn) + ecall_insn_prio = 1'b1; + else if (ebrk_insn) + ebrk_insn_prio = 1'b1; + end + assign wb_exception_o = ((load_err_q | store_err_q) | load_err_i) | store_err_i; + end + else begin : g_no_wb_exceptions + always @(*) begin + instr_fetch_err_prio = 0; + illegal_insn_prio = 0; + ecall_insn_prio = 0; + ebrk_insn_prio = 0; + store_err_prio = 0; + load_err_prio = 0; + if (instr_fetch_err) + instr_fetch_err_prio = 1'b1; + else if (illegal_insn_q) + illegal_insn_prio = 1'b1; + else if (ecall_insn) + ecall_insn_prio = 1'b1; + else if (ebrk_insn) + ebrk_insn_prio = 1'b1; + else if (store_err_q) + store_err_prio = 1'b1; + else if (load_err_q) + load_err_prio = 1'b1; + end + assign wb_exception_o = 1'b0; + end + endgenerate + assign enter_debug_mode = ((debug_req_i | (debug_single_step_i & instr_valid_i)) | trigger_match_i) & ~debug_mode_q; + assign ebreak_into_debug = (priv_mode_i == PRIV_LVL_M ? debug_ebreakm_i : (priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i : 1'b0)); + assign handle_irq = (~debug_mode_q & ~nmi_mode_q) & (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i)); + always @(*) begin : gen_mfip_id + if (irqs_i[14]) + mfip_id = 4'd14; + else if (irqs_i[13]) + mfip_id = 4'd13; + else if (irqs_i[12]) + mfip_id = 4'd12; + else if (irqs_i[11]) + mfip_id = 4'd11; + else if (irqs_i[10]) + mfip_id = 4'd10; + else if (irqs_i[9]) + mfip_id = 4'd9; + else if (irqs_i[8]) + mfip_id = 4'd8; + else if (irqs_i[7]) + mfip_id = 4'd7; + else if (irqs_i[6]) + mfip_id = 4'd6; + else if (irqs_i[5]) + mfip_id = 4'd5; + else if (irqs_i[4]) + mfip_id = 4'd4; + else if (irqs_i[3]) + mfip_id = 4'd3; + else if (irqs_i[2]) + mfip_id = 4'd2; + else if (irqs_i[1]) + mfip_id = 4'd1; + else + mfip_id = 4'd0; + end + assign unused_irq_timer = irqs_i[16]; + function automatic [5:0] sv2v_cast_6; + input reg [5:0] inp; + sv2v_cast_6 = inp; + endfunction + localparam [3:0] BOOT_SET = 1; + localparam [3:0] DBG_TAKEN_ID = 9; + localparam [3:0] DBG_TAKEN_IF = 8; + localparam [3:0] FIRST_FETCH = 4; + localparam [3:0] IRQ_TAKEN = 7; + localparam [3:0] RESET = 0; + localparam [3:0] SLEEP = 3; + localparam [3:0] WAIT_SLEEP = 2; + always @(*) begin + instr_req_o = 1'b1; + csr_save_if_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_wb_o = 1'b0; + csr_restore_mret_id_o = 1'b0; + csr_restore_dret_id_o = 1'b0; + csr_save_cause_o = 1'b0; + csr_mtval_o = {32 {1'sb0}}; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b0; + pc_set_spec_o = 1'b0; + nt_branch_mispredict_o = 1'b0; + exc_pc_mux_o = EXC_PC_IRQ; + exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; + ctrl_fsm_ns = ctrl_fsm_cs; + ctrl_busy_o = 1'b1; + halt_if = 1'b0; + retain_id = 1'b0; + flush_id = 1'b0; + debug_csr_save_o = 1'b0; + debug_cause_o = DBG_CAUSE_EBREAK; + debug_mode_d = debug_mode_q; + nmi_mode_d = nmi_mode_q; + perf_tbranch_o = 1'b0; + perf_jump_o = 1'b0; + controller_run_o = 1'b0; + case (ctrl_fsm_cs) + RESET: begin + instr_req_o = 1'b0; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + ctrl_fsm_ns = BOOT_SET; + end + BOOT_SET: begin + instr_req_o = 1'b1; + pc_mux_o = PC_BOOT; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + ctrl_fsm_ns = FIRST_FETCH; + end + WAIT_SLEEP: begin + ctrl_busy_o = 1'b0; + instr_req_o = 1'b0; + halt_if = 1'b1; + flush_id = 1'b1; + ctrl_fsm_ns = SLEEP; + end + SLEEP: begin + instr_req_o = 1'b0; + halt_if = 1'b1; + flush_id = 1'b1; + if ((((irq_nm_i || irq_pending_i) || debug_req_i) || debug_mode_q) || debug_single_step_i) + ctrl_fsm_ns = FIRST_FETCH; + else + ctrl_busy_o = 1'b0; + end + FIRST_FETCH: begin + if (id_in_ready_o) + ctrl_fsm_ns = DECODE; + if (handle_irq) begin + ctrl_fsm_ns = IRQ_TAKEN; + halt_if = 1'b1; + end + if (enter_debug_mode) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + halt_if = 1'b1; + end + end + DECODE: begin + controller_run_o = 1'b1; + pc_mux_o = PC_JUMP; + if (special_req_all) begin + retain_id = 1'b1; + if (ready_wb_i | wb_exception_o) + ctrl_fsm_ns = FLUSH; + end + if (!special_req_branch) begin + if (branch_set_i || jump_set_i) begin + pc_set_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); + perf_tbranch_o = branch_set_i; + perf_jump_o = jump_set_i; + end + if (BranchPredictor) + if (instr_bp_taken_i & branch_not_set_i) + nt_branch_mispredict_o = 1'b1; + end + if ((branch_set_spec_i || jump_set_i) && !special_req_branch) + pc_set_spec_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1); + if ((enter_debug_mode || handle_irq) && stall) + halt_if = 1'b1; + if (!stall && !special_req_all) + if (enter_debug_mode) begin + ctrl_fsm_ns = DBG_TAKEN_IF; + halt_if = 1'b1; + end + else if (handle_irq) begin + ctrl_fsm_ns = IRQ_TAKEN; + halt_if = 1'b1; + end + end + IRQ_TAKEN: begin + pc_mux_o = PC_EXC; + exc_pc_mux_o = EXC_PC_IRQ; + if (handle_irq) begin + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + csr_save_if_o = 1'b1; + csr_save_cause_o = 1'b1; + if (irq_nm_i && !nmi_mode_q) begin + exc_cause_o = EXC_CAUSE_IRQ_NM; + nmi_mode_d = 1'b1; + end + else if (irqs_i[14-:15] != 15'b000000000000000) + exc_cause_o = sv2v_cast_6({2'b11, mfip_id}); + else if (irqs_i[15]) + exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M; + else if (irqs_i[17]) + exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M; + else + exc_cause_o = EXC_CAUSE_IRQ_TIMER_M; + end + ctrl_fsm_ns = DECODE; + end + DBG_TAKEN_IF: begin + pc_mux_o = PC_EXC; + exc_pc_mux_o = EXC_PC_DBD; + if ((debug_single_step_i || debug_req_i) || trigger_match_i) begin + flush_id = 1'b1; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + csr_save_if_o = 1'b1; + debug_csr_save_o = 1'b1; + csr_save_cause_o = 1'b1; + if (trigger_match_i) + debug_cause_o = DBG_CAUSE_TRIGGER; + else if (debug_single_step_i) + debug_cause_o = DBG_CAUSE_STEP; + else + debug_cause_o = DBG_CAUSE_HALTREQ; + debug_mode_d = 1'b1; + end + ctrl_fsm_ns = DECODE; + end + DBG_TAKEN_ID: begin + flush_id = 1'b1; + pc_mux_o = PC_EXC; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + exc_pc_mux_o = EXC_PC_DBD; + if (ebreak_into_debug && !debug_mode_q) begin + csr_save_cause_o = 1'b1; + csr_save_id_o = 1'b1; + debug_csr_save_o = 1'b1; + debug_cause_o = DBG_CAUSE_EBREAK; + end + debug_mode_d = 1'b1; + ctrl_fsm_ns = DECODE; + end + FLUSH: begin + halt_if = 1'b1; + flush_id = 1'b1; + ctrl_fsm_ns = DECODE; + if ((exc_req_q || store_err_q) || load_err_q) begin + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + pc_mux_o = PC_EXC; + exc_pc_mux_o = (debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC); + if (WritebackStage) begin : g_writeback_mepc_save + csr_save_id_o = ~(store_err_q | load_err_q); + csr_save_wb_o = store_err_q | load_err_q; + end + else begin : g_no_writeback_mepc_save + csr_save_id_o = 1'b0; + end + csr_save_cause_o = 1'b1; + case (1'b1) + instr_fetch_err_prio: begin + exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT; + csr_mtval_o = (instr_fetch_err_plus2_i ? pc_id_i + 32'd2 : pc_id_i); + end + illegal_insn_prio: begin + exc_cause_o = EXC_CAUSE_ILLEGAL_INSN; + csr_mtval_o = (instr_is_compressed_i ? {16'b0000000000000000, instr_compressed_i} : instr_i); + end + ecall_insn_prio: exc_cause_o = (priv_mode_i == PRIV_LVL_M ? EXC_CAUSE_ECALL_MMODE : EXC_CAUSE_ECALL_UMODE); + ebrk_insn_prio: + if (debug_mode_q | ebreak_into_debug) begin + pc_set_o = 1'b0; + pc_set_spec_o = 1'b0; + csr_save_id_o = 1'b0; + csr_save_cause_o = 1'b0; + ctrl_fsm_ns = DBG_TAKEN_ID; + flush_id = 1'b0; + end + else + exc_cause_o = EXC_CAUSE_BREAKPOINT; + store_err_prio: begin + exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT; + csr_mtval_o = lsu_addr_last_i; + end + load_err_prio: begin + exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT; + csr_mtval_o = lsu_addr_last_i; + end + default: + ; + endcase + end + else if (mret_insn) begin + pc_mux_o = PC_ERET; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + csr_restore_mret_id_o = 1'b1; + if (nmi_mode_q) + nmi_mode_d = 1'b0; + end + else if (dret_insn) begin + pc_mux_o = PC_DRET; + pc_set_o = 1'b1; + pc_set_spec_o = 1'b1; + debug_mode_d = 1'b0; + csr_restore_dret_id_o = 1'b1; + end + else if (wfi_insn) + ctrl_fsm_ns = WAIT_SLEEP; + else if (csr_pipe_flush && handle_irq) + ctrl_fsm_ns = IRQ_TAKEN; + if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug)) + ctrl_fsm_ns = DBG_TAKEN_IF; + end + default: begin + instr_req_o = 1'b0; + ctrl_fsm_ns = RESET; + end + endcase + end + assign flush_id_o = flush_id; + assign debug_mode_o = debug_mode_q; + assign nmi_mode_o = nmi_mode_q; + assign stall = stall_id_i | stall_wb_i; + assign id_in_ready_o = (~stall & ~halt_if) & ~retain_id; + assign instr_valid_clear_o = ~(stall | retain_id) | flush_id; + always @(posedge clk_i or negedge rst_ni) begin : update_regs + if (!rst_ni) begin + ctrl_fsm_cs <= RESET; + nmi_mode_q <= 1'b0; + debug_mode_q <= 1'b0; + load_err_q <= 1'b0; + store_err_q <= 1'b0; + exc_req_q <= 1'b0; + illegal_insn_q <= 1'b0; + end + else begin + ctrl_fsm_cs <= ctrl_fsm_ns; + nmi_mode_q <= nmi_mode_d; + debug_mode_q <= debug_mode_d; + load_err_q <= load_err_d; + store_err_q <= store_err_d; + exc_req_q <= exc_req_d; + illegal_insn_q <= illegal_insn_d; + end + end +endmodule +module brqrv_idu_dec ( + clk_i, + rst_ni, + illegal_insn_o, + ebrk_insn_o, + mret_insn_o, + dret_insn_o, + ecall_insn_o, + wfi_insn_o, + jump_set_o, + branch_taken_i, + icache_inval_o, + instr_first_cycle_i, + instr_rdata_i, + instr_rdata_alu_i, + illegal_c_insn_i, + imm_a_mux_sel_o, + imm_b_mux_sel_o, + bt_a_mux_sel_o, + bt_b_mux_sel_o, + imm_i_type_o, + imm_s_type_o, + imm_b_type_o, + imm_u_type_o, + imm_j_type_o, + zimm_rs1_type_o, + rf_wdata_sel_o, + rf_we_o, + rf_raddr_a_o, + rf_raddr_b_o, + rf_waddr_o, + rf_ren_a_o, + rf_ren_b_o, + alu_operator_o, + alu_op_a_mux_sel_o, + alu_op_b_mux_sel_o, + alu_multicycle_o, + mult_en_o, + div_en_o, + mult_sel_o, + div_sel_o, + multdiv_operator_o, + multdiv_signed_mode_o, + csr_access_o, + csr_op_o, + data_req_o, + data_we_o, + data_type_o, + data_sign_extension_o, + jump_in_dec_o, + branch_in_dec_o +); + parameter [0:0] RV32E = 0; + localparam integer brqrv_pkg_RV32MFast = 2; + parameter integer RV32M = brqrv_pkg_RV32MFast; + localparam integer brqrv_pkg_RV32BNone = 0; + parameter integer RV32B = brqrv_pkg_RV32BNone; + parameter [0:0] BranchTargetALU = 0; + input wire clk_i; + input wire rst_ni; + output wire illegal_insn_o; + output reg ebrk_insn_o; + output reg mret_insn_o; + output reg dret_insn_o; + output reg ecall_insn_o; + output reg wfi_insn_o; + output reg jump_set_o; + input wire branch_taken_i; + output reg icache_inval_o; + input wire instr_first_cycle_i; + input wire [31:0] instr_rdata_i; + input wire [31:0] instr_rdata_alu_i; + input wire illegal_c_insn_i; + output reg imm_a_mux_sel_o; + output reg [2:0] imm_b_mux_sel_o; + output reg [1:0] bt_a_mux_sel_o; + output reg [2:0] bt_b_mux_sel_o; + output wire [31:0] imm_i_type_o; + output wire [31:0] imm_s_type_o; + output wire [31:0] imm_b_type_o; + output wire [31:0] imm_u_type_o; + output wire [31:0] imm_j_type_o; + output wire [31:0] zimm_rs1_type_o; + output reg rf_wdata_sel_o; + output wire rf_we_o; + output wire [4:0] rf_raddr_a_o; + output wire [4:0] rf_raddr_b_o; + output wire [4:0] rf_waddr_o; + output reg rf_ren_a_o; + output reg rf_ren_b_o; + output reg [5:0] alu_operator_o; + output reg [1:0] alu_op_a_mux_sel_o; + output reg alu_op_b_mux_sel_o; + output reg alu_multicycle_o; + output wire mult_en_o; + output wire div_en_o; + output reg mult_sel_o; + output reg div_sel_o; + output reg [1:0] multdiv_operator_o; + output reg [1:0] multdiv_signed_mode_o; + output reg csr_access_o; + output reg [1:0] csr_op_o; + output reg data_req_o; + output reg data_we_o; + output reg [1:0] data_type_o; + output reg data_sign_extension_o; + output reg jump_in_dec_o; + output reg branch_in_dec_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + reg illegal_insn; + wire illegal_reg_rv32e; + reg csr_illegal; + reg rf_we; + wire [31:0] instr; + wire [31:0] instr_alu; + wire [4:0] instr_rs1; + wire [4:0] instr_rs2; + wire [4:0] instr_rs3; + wire [4:0] instr_rd; + reg use_rs3_d; + reg use_rs3_q; + reg [1:0] csr_op; + reg [6:0] opcode; + reg [6:0] opcode_alu; + assign instr = instr_rdata_i; + assign instr_alu = instr_rdata_alu_i; + assign imm_i_type_o = {{20 {instr[31]}}, instr[31:20]}; + assign imm_s_type_o = {{20 {instr[31]}}, instr[31:25], instr[11:7]}; + assign imm_b_type_o = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; + assign imm_u_type_o = {instr[31:12], 12'b000000000000}; + assign imm_j_type_o = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0}; + assign zimm_rs1_type_o = {27'b000000000000000000000000000, instr_rs1}; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + use_rs3_q <= 1'b0; + else + use_rs3_q <= use_rs3_d; + assign instr_rs1 = instr[19:15]; + assign instr_rs2 = instr[24:20]; + assign instr_rs3 = instr[31:27]; + assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i ? instr_rs3 : instr_rs1); + assign rf_raddr_b_o = instr_rs2; + assign instr_rd = instr[11:7]; + assign rf_waddr_o = instr_rd; + generate + if (RV32E) begin : gen_rv32e_reg_check_active + assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == OP_A_REG_A)) | (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == OP_B_REG_B))) | (rf_waddr_o[4] & rf_we); + end + else begin : gen_rv32e_reg_check_inactive + assign illegal_reg_rv32e = 1'b0; + end + endgenerate + always @(*) begin : csr_operand_check + csr_op_o = csr_op; + if (((csr_op == CSR_OP_SET) || (csr_op == CSR_OP_CLEAR)) && (instr_rs1 == {5 {1'sb0}})) + csr_op_o = CSR_OP_READ; + end + function automatic [6:0] sv2v_cast_7; + input reg [6:0] inp; + sv2v_cast_7 = inp; + endfunction + always @(*) begin + jump_in_dec_o = 1'b0; + jump_set_o = 1'b0; + branch_in_dec_o = 1'b0; + icache_inval_o = 1'b0; + multdiv_operator_o = MD_OP_MULL; + multdiv_signed_mode_o = 2'b00; + rf_wdata_sel_o = RF_WD_EX; + rf_we = 1'b0; + rf_ren_a_o = 1'b0; + rf_ren_b_o = 1'b0; + csr_access_o = 1'b0; + csr_illegal = 1'b0; + csr_op = CSR_OP_READ; + data_we_o = 1'b0; + data_type_o = 2'b00; + data_sign_extension_o = 1'b0; + data_req_o = 1'b0; + illegal_insn = 1'b0; + ebrk_insn_o = 1'b0; + mret_insn_o = 1'b0; + dret_insn_o = 1'b0; + ecall_insn_o = 1'b0; + wfi_insn_o = 1'b0; + opcode = sv2v_cast_7(instr[6:0]); + case (opcode) + OPCODE_JAL: begin + jump_in_dec_o = 1'b1; + if (instr_first_cycle_i) begin + rf_we = BranchTargetALU; + jump_set_o = 1'b1; + end + else + rf_we = 1'b1; + end + OPCODE_JALR: begin + jump_in_dec_o = 1'b1; + if (instr_first_cycle_i) begin + rf_we = BranchTargetALU; + jump_set_o = 1'b1; + end + else + rf_we = 1'b1; + if (instr[14:12] != 3'b000) + illegal_insn = 1'b1; + rf_ren_a_o = 1'b1; + end + OPCODE_BRANCH: begin + branch_in_dec_o = 1'b1; + case (instr[14:12]) + 3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: illegal_insn = 1'b0; + default: illegal_insn = 1'b1; + endcase + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + end + OPCODE_STORE: begin + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + data_req_o = 1'b1; + data_we_o = 1'b1; + if (instr[14]) + illegal_insn = 1'b1; + case (instr[13:12]) + 2'b00: data_type_o = 2'b10; + 2'b01: data_type_o = 2'b01; + 2'b10: data_type_o = 2'b00; + default: illegal_insn = 1'b1; + endcase + end + OPCODE_LOAD: begin + rf_ren_a_o = 1'b1; + data_req_o = 1'b1; + data_type_o = 2'b00; + data_sign_extension_o = ~instr[14]; + case (instr[13:12]) + 2'b00: data_type_o = 2'b10; + 2'b01: data_type_o = 2'b01; + 2'b10: begin + data_type_o = 2'b00; + if (instr[14]) + illegal_insn = 1'b1; + end + default: illegal_insn = 1'b1; + endcase + end + OPCODE_LUI: rf_we = 1'b1; + OPCODE_AUIPC: rf_we = 1'b1; + OPCODE_OP_IMM: begin + rf_ren_a_o = 1'b1; + rf_we = 1'b1; + case (instr[14:12]) + 3'b000, 3'b010, 3'b011, 3'b100, 3'b110, 3'b111: illegal_insn = 1'b0; + 3'b001: + case (instr[31:27]) + 5'b00000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1); + 5'b00100, 5'b01001, 5'b00101, 5'b01101: illegal_insn = (RV32B != RV32BNone ? 1'b0 : 1'b1); + 5'b00001: + if (instr[26] == 1'b0) + illegal_insn = (RV32B == RV32BFull ? 1'b0 : 1'b1); + else + illegal_insn = 1'b1; + 5'b01100: + case (instr[26:20]) + 7'b0000000, 7'b0000001, 7'b0000010, 7'b0000100, 7'b0000101: illegal_insn = (RV32B != RV32BNone ? 1'b0 : 1'b1); + 7'b0010000, 7'b0010001, 7'b0010010, 7'b0011000, 7'b0011001, 7'b0011010: illegal_insn = (RV32B == RV32BFull ? 1'b0 : 1'b1); + default: illegal_insn = 1'b1; + endcase + default: illegal_insn = 1'b1; + endcase + 3'b101: + if (instr[26]) + illegal_insn = (RV32B != RV32BNone ? 1'b0 : 1'b1); + else + case (instr[31:27]) + 5'b00000, 5'b01000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1); + 5'b00100, 5'b01100, 5'b01001: illegal_insn = (RV32B != RV32BNone ? 1'b0 : 1'b1); + 5'b01101: + if (RV32B == RV32BFull) + illegal_insn = 1'b0; + else + case (instr[24:20]) + 5'b11111, 5'b11000: illegal_insn = (RV32B == RV32BBalanced ? 1'b0 : 1'b1); + default: illegal_insn = 1'b1; + endcase + 5'b00101: + if (RV32B == RV32BFull) + illegal_insn = 1'b0; + else if (instr[24:20] == 5'b00111) + illegal_insn = (RV32B == RV32BBalanced ? 1'b0 : 1'b1); + 5'b00001: + if (instr[26] == 1'b0) + illegal_insn = (RV32B == RV32BFull ? 1'b0 : 1'b1); + else + illegal_insn = 1'b1; + default: illegal_insn = 1'b1; + endcase + default: illegal_insn = 1'b1; + endcase + end + OPCODE_OP: begin + rf_ren_a_o = 1'b1; + rf_ren_b_o = 1'b1; + rf_we = 1'b1; + if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) + illegal_insn = (RV32B != RV32BNone ? 1'b0 : 1'b1); + else + case ({instr[31:25], instr[14:12]}) + {7'b0000000, 3'b000}, {7'b0100000, 3'b000}, {7'b0000000, 3'b010}, {7'b0000000, 3'b011}, {7'b0000000, 3'b100}, {7'b0000000, 3'b110}, {7'b0000000, 3'b111}, {7'b0000000, 3'b001}, {7'b0000000, 3'b101}, {7'b0100000, 3'b101}: illegal_insn = 1'b0; + {7'b0100000, 3'b111}, {7'b0100000, 3'b110}, {7'b0100000, 3'b100}, {7'b0010000, 3'b001}, {7'b0010000, 3'b101}, {7'b0110000, 3'b001}, {7'b0110000, 3'b101}, {7'b0000101, 3'b100}, {7'b0000101, 3'b101}, {7'b0000101, 3'b110}, {7'b0000101, 3'b111}, {7'b0000100, 3'b100}, {7'b0100100, 3'b100}, {7'b0000100, 3'b111}, {7'b0100100, 3'b001}, {7'b0010100, 3'b001}, {7'b0110100, 3'b001}, {7'b0100100, 3'b101}, {7'b0100100, 3'b111}: illegal_insn = (RV32B != RV32BNone ? 1'b0 : 1'b1); + {7'b0100100, 3'b110}, {7'b0000100, 3'b110}, {7'b0110100, 3'b101}, {7'b0010100, 3'b101}, {7'b0000100, 3'b001}, {7'b0000100, 3'b101}, {7'b0000101, 3'b001}, {7'b0000101, 3'b010}, {7'b0000101, 3'b011}: illegal_insn = (RV32B == RV32BFull ? 1'b0 : 1'b1); + {7'b0000001, 3'b000}: begin + multdiv_operator_o = MD_OP_MULL; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b001}: begin + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b010}: begin + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b01; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b011}: begin + multdiv_operator_o = MD_OP_MULH; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b100}: begin + multdiv_operator_o = MD_OP_DIV; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b101}: begin + multdiv_operator_o = MD_OP_DIV; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b110}: begin + multdiv_operator_o = MD_OP_REM; + multdiv_signed_mode_o = 2'b11; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + {7'b0000001, 3'b111}: begin + multdiv_operator_o = MD_OP_REM; + multdiv_signed_mode_o = 2'b00; + illegal_insn = (RV32M == RV32MNone ? 1'b1 : 1'b0); + end + default: illegal_insn = 1'b1; + endcase + end + OPCODE_MISC_MEM: + case (instr[14:12]) + 3'b000: rf_we = 1'b0; + 3'b001: begin + jump_in_dec_o = 1'b1; + rf_we = 1'b0; + if (instr_first_cycle_i) begin + jump_set_o = 1'b1; + icache_inval_o = 1'b1; + end + end + default: illegal_insn = 1'b1; + endcase + OPCODE_SYSTEM: + if (instr[14:12] == 3'b000) begin + case (instr[31:20]) + 12'h000: ecall_insn_o = 1'b1; + 12'h001: ebrk_insn_o = 1'b1; + 12'h302: mret_insn_o = 1'b1; + 12'h7b2: dret_insn_o = 1'b1; + 12'h105: wfi_insn_o = 1'b1; + default: illegal_insn = 1'b1; + endcase + if ((instr_rs1 != 5'b00000) || (instr_rd != 5'b00000)) + illegal_insn = 1'b1; + end + else begin + csr_access_o = 1'b1; + rf_wdata_sel_o = RF_WD_CSR; + rf_we = 1'b1; + if (~instr[14]) + rf_ren_a_o = 1'b1; + case (instr[13:12]) + 2'b01: csr_op = CSR_OP_WRITE; + 2'b10: csr_op = CSR_OP_SET; + 2'b11: csr_op = CSR_OP_CLEAR; + default: csr_illegal = 1'b1; + endcase + illegal_insn = csr_illegal; + end + default: illegal_insn = 1'b1; + endcase + if (illegal_c_insn_i) + illegal_insn = 1'b1; + if (illegal_insn) begin + rf_we = 1'b0; + data_req_o = 1'b0; + data_we_o = 1'b0; + jump_in_dec_o = 1'b0; + jump_set_o = 1'b0; + branch_in_dec_o = 1'b0; + csr_access_o = 1'b0; + end + end + always @(*) begin + alu_operator_o = ALU_SLTU; + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_ZERO; + imm_b_mux_sel_o = IMM_B_I; + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_I; + opcode_alu = sv2v_cast_7(instr_alu[6:0]); + use_rs3_d = 1'b0; + alu_multicycle_o = 1'b0; + mult_sel_o = 1'b0; + div_sel_o = 1'b0; + case (opcode_alu) + OPCODE_JAL: begin + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_J; + end + if (instr_first_cycle_i && !BranchTargetALU) begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_J; + alu_operator_o = ALU_ADD; + end + else begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + OPCODE_JALR: begin + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_REG_A; + bt_b_mux_sel_o = IMM_B_I; + end + if (instr_first_cycle_i && !BranchTargetALU) begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + alu_operator_o = ALU_ADD; + end + else begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + end + OPCODE_BRANCH: begin + case (instr_alu[14:12]) + 3'b000: alu_operator_o = ALU_EQ; + 3'b001: alu_operator_o = ALU_NE; + 3'b100: alu_operator_o = ALU_LT; + 3'b101: alu_operator_o = ALU_GE; + 3'b110: alu_operator_o = ALU_LTU; + 3'b111: alu_operator_o = ALU_GEU; + default: + ; + endcase + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = (branch_taken_i ? IMM_B_B : IMM_B_INCR_PC); + end + if (instr_first_cycle_i) begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + end + else begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = (branch_taken_i ? IMM_B_B : IMM_B_INCR_PC); + alu_operator_o = ALU_ADD; + end + end + OPCODE_STORE: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + alu_operator_o = ALU_ADD; + if (!instr_alu[14]) begin + imm_b_mux_sel_o = IMM_B_S; + alu_op_b_mux_sel_o = OP_B_IMM; + end + end + OPCODE_LOAD: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_operator_o = ALU_ADD; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + end + OPCODE_LUI: begin + alu_op_a_mux_sel_o = OP_A_IMM; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_ZERO; + imm_b_mux_sel_o = IMM_B_U; + alu_operator_o = ALU_ADD; + end + OPCODE_AUIPC: begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_U; + alu_operator_o = ALU_ADD; + end + OPCODE_OP_IMM: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_I; + case (instr_alu[14:12]) + 3'b000: alu_operator_o = ALU_ADD; + 3'b010: alu_operator_o = ALU_SLT; + 3'b011: alu_operator_o = ALU_SLTU; + 3'b100: alu_operator_o = ALU_XOR; + 3'b110: alu_operator_o = ALU_OR; + 3'b111: alu_operator_o = ALU_AND; + 3'b001: + if (RV32B != RV32BNone) + case (instr_alu[31:27]) + 5'b00000: alu_operator_o = ALU_SLL; + 5'b00100: alu_operator_o = ALU_SLO; + 5'b01001: alu_operator_o = ALU_SBCLR; + 5'b00101: alu_operator_o = ALU_SBSET; + 5'b01101: alu_operator_o = ALU_SBINV; + 5'b00001: + if (instr_alu[26] == 0) + alu_operator_o = ALU_SHFL; + 5'b01100: + case (instr_alu[26:20]) + 7'b0000000: alu_operator_o = ALU_CLZ; + 7'b0000001: alu_operator_o = ALU_CTZ; + 7'b0000010: alu_operator_o = ALU_PCNT; + 7'b0000100: alu_operator_o = ALU_SEXTB; + 7'b0000101: alu_operator_o = ALU_SEXTH; + 7'b0010000: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_B; + alu_multicycle_o = 1'b1; + end + 7'b0010001: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_H; + alu_multicycle_o = 1'b1; + end + 7'b0010010: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32_W; + alu_multicycle_o = 1'b1; + end + 7'b0011000: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_B; + alu_multicycle_o = 1'b1; + end + 7'b0011001: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_H; + alu_multicycle_o = 1'b1; + end + 7'b0011010: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_CRC32C_W; + alu_multicycle_o = 1'b1; + end + default: + ; + endcase + default: + ; + endcase + else + alu_operator_o = ALU_SLL; + 3'b101: + if (RV32B != RV32BNone) begin + if (instr_alu[26] == 1'b1) begin + alu_operator_o = ALU_FSR; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) + use_rs3_d = 1'b1; + else + use_rs3_d = 1'b0; + end + else + case (instr_alu[31:27]) + 5'b00000: alu_operator_o = ALU_SRL; + 5'b01000: alu_operator_o = ALU_SRA; + 5'b00100: alu_operator_o = ALU_SRO; + 5'b01001: alu_operator_o = ALU_SBEXT; + 5'b01100: begin + alu_operator_o = ALU_ROR; + alu_multicycle_o = 1'b1; + end + 5'b01101: alu_operator_o = ALU_GREV; + 5'b00101: alu_operator_o = ALU_GORC; + 5'b00001: + if (RV32B == RV32BFull) + if (instr_alu[26] == 1'b0) + alu_operator_o = ALU_UNSHFL; + default: + ; + endcase + end + else if (instr_alu[31:27] == 5'b00000) + alu_operator_o = ALU_SRL; + else if (instr_alu[31:27] == 5'b01000) + alu_operator_o = ALU_SRA; + default: + ; + endcase + end + OPCODE_OP: begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_REG_B; + if (instr_alu[26]) begin + if (RV32B != RV32BNone) + case ({instr_alu[26:25], instr_alu[14:12]}) + {2'b11, 3'b001}: begin + alu_operator_o = ALU_CMIX; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) + use_rs3_d = 1'b1; + else + use_rs3_d = 1'b0; + end + {2'b11, 3'b101}: begin + alu_operator_o = ALU_CMOV; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) + use_rs3_d = 1'b1; + else + use_rs3_d = 1'b0; + end + {2'b10, 3'b001}: begin + alu_operator_o = ALU_FSL; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) + use_rs3_d = 1'b1; + else + use_rs3_d = 1'b0; + end + {2'b10, 3'b101}: begin + alu_operator_o = ALU_FSR; + alu_multicycle_o = 1'b1; + if (instr_first_cycle_i) + use_rs3_d = 1'b1; + else + use_rs3_d = 1'b0; + end + default: + ; + endcase + end + else + case ({instr_alu[31:25], instr_alu[14:12]}) + {7'b0000000, 3'b000}: alu_operator_o = ALU_ADD; + {7'b0100000, 3'b000}: alu_operator_o = ALU_SUB; + {7'b0000000, 3'b010}: alu_operator_o = ALU_SLT; + {7'b0000000, 3'b011}: alu_operator_o = ALU_SLTU; + {7'b0000000, 3'b100}: alu_operator_o = ALU_XOR; + {7'b0000000, 3'b110}: alu_operator_o = ALU_OR; + {7'b0000000, 3'b111}: alu_operator_o = ALU_AND; + {7'b0000000, 3'b001}: alu_operator_o = ALU_SLL; + {7'b0000000, 3'b101}: alu_operator_o = ALU_SRL; + {7'b0100000, 3'b101}: alu_operator_o = ALU_SRA; + {7'b0010000, 3'b001}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_SLO; + {7'b0010000, 3'b101}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_SRO; + {7'b0110000, 3'b001}: + if (RV32B != RV32BNone) begin + alu_operator_o = ALU_ROL; + alu_multicycle_o = 1'b1; + end + {7'b0110000, 3'b101}: + if (RV32B != RV32BNone) begin + alu_operator_o = ALU_ROR; + alu_multicycle_o = 1'b1; + end + {7'b0000101, 3'b100}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_MIN; + {7'b0000101, 3'b101}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_MAX; + {7'b0000101, 3'b110}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_MINU; + {7'b0000101, 3'b111}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_MAXU; + {7'b0000100, 3'b100}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_PACK; + {7'b0100100, 3'b100}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_PACKU; + {7'b0000100, 3'b111}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_PACKH; + {7'b0100000, 3'b100}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_XNOR; + {7'b0100000, 3'b110}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_ORN; + {7'b0100000, 3'b111}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_ANDN; + {7'b0100100, 3'b001}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_SBCLR; + {7'b0010100, 3'b001}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_SBSET; + {7'b0110100, 3'b001}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_SBINV; + {7'b0100100, 3'b101}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_SBEXT; + {7'b0100100, 3'b111}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_BFP; + {7'b0110100, 3'b101}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_GREV; + {7'b0010100, 3'b101}: + if (RV32B != RV32BNone) + alu_operator_o = ALU_GORC; + {7'b0000100, 3'b001}: + if (RV32B == RV32BFull) + alu_operator_o = ALU_SHFL; + {7'b0000100, 3'b101}: + if (RV32B == RV32BFull) + alu_operator_o = ALU_UNSHFL; + {7'b0000101, 3'b001}: + if (RV32B == RV32BFull) + alu_operator_o = ALU_CLMUL; + {7'b0000101, 3'b010}: + if (RV32B == RV32BFull) + alu_operator_o = ALU_CLMULR; + {7'b0000101, 3'b011}: + if (RV32B == RV32BFull) + alu_operator_o = ALU_CLMULH; + {7'b0100100, 3'b110}: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_BDEP; + alu_multicycle_o = 1'b1; + end + {7'b0000100, 3'b110}: + if (RV32B == RV32BFull) begin + alu_operator_o = ALU_BEXT; + alu_multicycle_o = 1'b1; + end + {7'b0000001, 3'b000}: begin + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b001}: begin + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b010}: begin + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b011}: begin + alu_operator_o = ALU_ADD; + mult_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b100}: begin + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b101}: begin + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b110}: begin + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + {7'b0000001, 3'b111}: begin + alu_operator_o = ALU_ADD; + div_sel_o = (RV32M == RV32MNone ? 1'b0 : 1'b1); + end + default: + ; + endcase + end + OPCODE_MISC_MEM: + case (instr_alu[14:12]) + 3'b000: begin + alu_operator_o = ALU_ADD; + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + end + 3'b001: + if (BranchTargetALU) begin + bt_a_mux_sel_o = OP_A_CURRPC; + bt_b_mux_sel_o = IMM_B_INCR_PC; + end + else begin + alu_op_a_mux_sel_o = OP_A_CURRPC; + alu_op_b_mux_sel_o = OP_B_IMM; + imm_b_mux_sel_o = IMM_B_INCR_PC; + alu_operator_o = ALU_ADD; + end + default: + ; + endcase + OPCODE_SYSTEM: + if (instr_alu[14:12] == 3'b000) begin + alu_op_a_mux_sel_o = OP_A_REG_A; + alu_op_b_mux_sel_o = OP_B_IMM; + end + else begin + alu_op_b_mux_sel_o = OP_B_IMM; + imm_a_mux_sel_o = IMM_A_Z; + imm_b_mux_sel_o = IMM_B_I; + if (instr_alu[14]) + alu_op_a_mux_sel_o = OP_A_IMM; + else + alu_op_a_mux_sel_o = OP_A_REG_A; + end + default: + ; + endcase + end + assign mult_en_o = (illegal_insn ? 1'b0 : mult_sel_o); + assign div_en_o = (illegal_insn ? 1'b0 : div_sel_o); + assign illegal_insn_o = illegal_insn | illegal_reg_rv32e; + assign rf_we_o = rf_we & ~illegal_reg_rv32e; +endmodule +module brqrv_ifu ( + clk_i, + rst_ni, + boot_addr_i, + req_i, + instr_req_o, + instr_addr_o, + instr_gnt_i, + instr_rvalid_i, + instr_rdata_i, + instr_err_i, + instr_pmp_err_i, + instr_valid_id_o, + instr_new_id_o, + instr_rdata_id_o, + instr_rdata_alu_id_o, + instr_rdata_c_id_o, + instr_is_compressed_id_o, + instr_bp_taken_o, + instr_fetch_err_o, + instr_fetch_err_plus2_o, + illegal_c_insn_id_o, + dummy_instr_id_o, + pc_if_o, + pc_id_o, + instr_valid_clear_i, + pc_set_i, + pc_set_spec_i, + pc_mux_i, + nt_branch_mispredict_i, + exc_pc_mux_i, + exc_cause, + dummy_instr_en_i, + dummy_instr_mask_i, + dummy_instr_seed_en_i, + dummy_instr_seed_i, + icache_enable_i, + icache_inval_i, + branch_target_ex_i, + csr_mepc_i, + csr_depc_i, + csr_mtvec_i, + csr_mtvec_init_o, + id_in_ready_i, + pc_mismatch_alert_o, + if_busy_o +); + parameter [31:0] DmHaltAddr = 32'h1a110800; + parameter [31:0] DmExceptionAddr = 32'h1a110808; + parameter [0:0] DummyInstructions = 1'b0; + parameter [0:0] ICache = 1'b0; + parameter [0:0] ICacheECC = 1'b0; + parameter [0:0] SecureBuraq = 1'b0; + parameter [0:0] BranchPredictor = 1'b0; + input wire clk_i; + input wire rst_ni; + input wire [31:0] boot_addr_i; + input wire req_i; + output wire instr_req_o; + output wire [31:0] instr_addr_o; + input wire instr_gnt_i; + input wire instr_rvalid_i; + input wire [31:0] instr_rdata_i; + input wire instr_err_i; + input wire instr_pmp_err_i; + output wire instr_valid_id_o; + output wire instr_new_id_o; + output reg [31:0] instr_rdata_id_o; + output reg [31:0] instr_rdata_alu_id_o; + output reg [15:0] instr_rdata_c_id_o; + output reg instr_is_compressed_id_o; + output wire instr_bp_taken_o; + output reg instr_fetch_err_o; + output reg instr_fetch_err_plus2_o; + output reg illegal_c_insn_id_o; + output wire dummy_instr_id_o; + output wire [31:0] pc_if_o; + output reg [31:0] pc_id_o; + input wire instr_valid_clear_i; + input wire pc_set_i; + input wire pc_set_spec_i; + input wire [2:0] pc_mux_i; + input wire nt_branch_mispredict_i; + input wire [1:0] exc_pc_mux_i; + input wire [5:0] exc_cause; + input wire dummy_instr_en_i; + input wire [2:0] dummy_instr_mask_i; + input wire dummy_instr_seed_en_i; + input wire [31:0] dummy_instr_seed_i; + input wire icache_enable_i; + input wire icache_inval_i; + input wire [31:0] branch_target_ex_i; + input wire [31:0] csr_mepc_i; + input wire [31:0] csr_depc_i; + input wire [31:0] csr_mtvec_i; + output wire csr_mtvec_init_o; + input wire id_in_ready_i; + output wire pc_mismatch_alert_o; + output wire if_busy_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire instr_valid_id_d; + reg instr_valid_id_q; + wire instr_new_id_d; + reg instr_new_id_q; + wire prefetch_busy; + wire branch_req; + wire branch_spec; + wire predicted_branch; + reg [31:0] fetch_addr_n; + wire fetch_valid; + wire fetch_ready; + wire [31:0] fetch_rdata; + wire [31:0] fetch_addr; + wire fetch_err; + wire fetch_err_plus2; + wire if_instr_valid; + wire [31:0] if_instr_rdata; + wire [31:0] if_instr_addr; + wire if_instr_err; + reg [31:0] exc_pc; + wire [5:0] irq_id; + wire unused_irq_bit; + wire if_id_pipe_reg_we; + wire stall_dummy_instr; + wire [31:0] instr_out; + wire instr_is_compressed_out; + wire illegal_c_instr_out; + wire instr_err_out; + wire predict_branch_taken; + wire [31:0] predict_branch_pc; + wire [2:0] pc_mux_internal; + wire [7:0] unused_boot_addr; + wire [7:0] unused_csr_mtvec; + assign unused_boot_addr = boot_addr_i[7:0]; + assign unused_csr_mtvec = csr_mtvec_i[7:0]; + assign irq_id = exc_cause; + assign unused_irq_bit = irq_id[5]; + always @(*) begin : exc_pc_mux + case (exc_pc_mux_i) + EXC_PC_EXC: exc_pc = {csr_mtvec_i[31:8], 8'h00}; + EXC_PC_IRQ: exc_pc = {csr_mtvec_i[31:8], 1'b0, irq_id[4:0], 2'b00}; + EXC_PC_DBD: exc_pc = DmHaltAddr; + EXC_PC_DBG_EXC: exc_pc = DmExceptionAddr; + default: exc_pc = {csr_mtvec_i[31:8], 8'h00}; + endcase + end + assign pc_mux_internal = ((BranchPredictor && predict_branch_taken) && !pc_set_i ? PC_BP : pc_mux_i); + always @(*) begin : fetch_addr_mux + case (pc_mux_internal) + PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; + PC_JUMP: fetch_addr_n = branch_target_ex_i; + PC_EXC: fetch_addr_n = exc_pc; + PC_ERET: fetch_addr_n = csr_mepc_i; + PC_DRET: fetch_addr_n = csr_depc_i; + PC_BP: fetch_addr_n = (BranchPredictor ? predict_branch_pc : {boot_addr_i[31:8], 8'h80}); + default: fetch_addr_n = {boot_addr_i[31:8], 8'h80}; + endcase + end + assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i; + brqrv_ifu_prefetch #(.BranchPredictor(BranchPredictor)) prefetch_buffer_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_i(req_i), + .branch_i(branch_req), + .branch_spec_i(branch_spec), + .predicted_branch_i(predicted_branch), + .branch_mispredict_i(nt_branch_mispredict_i), + .addr_i({fetch_addr_n[31:1], 1'b0}), + .ready_i(fetch_ready), + .valid_o(fetch_valid), + .rdata_o(fetch_rdata), + .addr_o(fetch_addr), + .err_o(fetch_err), + .err_plus2_o(fetch_err_plus2), + .instr_req_o(instr_req_o), + .instr_addr_o(instr_addr_o), + .instr_gnt_i(instr_gnt_i), + .instr_rvalid_i(instr_rvalid_i), + .instr_rdata_i(instr_rdata_i), + .instr_err_i(instr_err_i), + .instr_pmp_err_i(instr_pmp_err_i), + .busy_o(prefetch_busy) + ); + wire unused_icen; + wire unused_icinv; + assign unused_icen = icache_enable_i; + assign unused_icinv = icache_inval_i; + assign branch_req = pc_set_i | predict_branch_taken; + assign branch_spec = pc_set_spec_i | predict_branch_taken; + assign pc_if_o = if_instr_addr; + assign if_busy_o = prefetch_busy; + wire [31:0] instr_decompressed; + wire illegal_c_insn; + wire instr_is_compressed; + brqrv_ifu_compressed_decoder compressed_decoder_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .valid_i(fetch_valid & ~fetch_err), + .instr_i(if_instr_rdata), + .instr_o(instr_decompressed), + .is_compressed_o(instr_is_compressed), + .illegal_instr_o(illegal_c_insn) + ); + wire unused_dummy_en; + wire [2:0] unused_dummy_mask; + wire unused_dummy_seed_en; + wire [31:0] unused_dummy_seed; + assign unused_dummy_en = dummy_instr_en_i; + assign unused_dummy_mask = dummy_instr_mask_i; + assign unused_dummy_seed_en = dummy_instr_seed_en_i; + assign unused_dummy_seed = dummy_instr_seed_i; + assign instr_out = instr_decompressed; + assign instr_is_compressed_out = instr_is_compressed; + assign illegal_c_instr_out = illegal_c_insn; + assign instr_err_out = if_instr_err; + assign stall_dummy_instr = 1'b0; + assign dummy_instr_id_o = 1'b0; + assign instr_valid_id_d = ((if_instr_valid & id_in_ready_i) & ~pc_set_i) | (instr_valid_id_q & ~instr_valid_clear_i); + assign instr_new_id_d = if_instr_valid & id_in_ready_i; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + instr_valid_id_q <= 1'b0; + instr_new_id_q <= 1'b0; + end + else begin + instr_valid_id_q <= instr_valid_id_d; + instr_new_id_q <= instr_new_id_d; + end + assign instr_valid_id_o = instr_valid_id_q; + assign instr_new_id_o = instr_new_id_q; + assign if_id_pipe_reg_we = instr_new_id_d; + always @(posedge clk_i) + if (if_id_pipe_reg_we) begin + instr_rdata_id_o <= instr_out; + instr_rdata_alu_id_o <= instr_out; + instr_fetch_err_o <= instr_err_out; + instr_fetch_err_plus2_o <= fetch_err_plus2; + instr_rdata_c_id_o <= if_instr_rdata[15:0]; + instr_is_compressed_id_o <= instr_is_compressed_out; + illegal_c_insn_id_o <= illegal_c_instr_out; + pc_id_o <= pc_if_o; + end + generate + if (SecureBuraq) begin : g_secure_pc + wire [31:0] prev_instr_addr_incr; + reg prev_instr_seq_q; + wire prev_instr_seq_d; + assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) & ~branch_req; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + prev_instr_seq_q <= 1'b0; + else + prev_instr_seq_q <= prev_instr_seq_d; + assign prev_instr_addr_incr = pc_id_o + (instr_is_compressed_id_o ? 32'd2 : 32'd4); + assign pc_mismatch_alert_o = prev_instr_seq_q & (pc_if_o != prev_instr_addr_incr); + end + else begin : g_no_secure_pc + assign pc_mismatch_alert_o = 1'b0; + end + endgenerate + assign instr_bp_taken_o = 1'b0; + assign predict_branch_taken = 1'b0; + assign predicted_branch = 1'b0; + assign predict_branch_pc = 32'b00000000000000000000000000000000; + assign if_instr_valid = fetch_valid; + assign if_instr_rdata = fetch_rdata; + assign if_instr_addr = fetch_addr; + assign if_instr_err = fetch_err; + assign fetch_ready = id_in_ready_i & ~stall_dummy_instr; +endmodule +module brqrv_ifu_compressed_decoder ( + clk_i, + rst_ni, + valid_i, + instr_i, + instr_o, + is_compressed_o, + illegal_instr_o +); + input wire clk_i; + input wire rst_ni; + input wire valid_i; + input wire [31:0] instr_i; + output reg [31:0] instr_o; + output wire is_compressed_o; + output reg illegal_instr_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire unused_valid; + assign unused_valid = valid_i; + always @(*) begin + instr_o = instr_i; + illegal_instr_o = 1'b0; + case (instr_i[1:0]) + 2'b00: + case (instr_i[15:13]) + 3'b000: begin + instr_o = {2'b00, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], OPCODE_OP_IMM}; + if (instr_i[12:5] == 8'b00000000) + illegal_instr_o = 1'b1; + end + 3'b010: instr_o = {5'b00000, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], OPCODE_LOAD}; + 3'b110: instr_o = {5'b00000, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, OPCODE_STORE}; + 3'b001, 3'b011, 3'b100, 3'b101, 3'b111: illegal_instr_o = 1'b1; + default: illegal_instr_o = 1'b1; + endcase + 2'b01: + case (instr_i[15:13]) + 3'b000: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], OPCODE_OP_IMM}; + 3'b001, 3'b101: instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0000, ~instr_i[15], OPCODE_JAL}; + 3'b010: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], OPCODE_OP_IMM}; + 3'b011: begin + instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], OPCODE_LUI}; + if (instr_i[11:7] == 5'h02) + instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0000, 5'h02, 3'b000, 5'h02, OPCODE_OP_IMM}; + if ({instr_i[12], instr_i[6:2]} == 6'b000000) + illegal_instr_o = 1'b1; + end + 3'b100: + case (instr_i[11:10]) + 2'b00, 2'b01: begin + instr_o = {1'b0, instr_i[10], 5'b00000, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], OPCODE_OP_IMM}; + if (instr_i[12] == 1'b1) + illegal_instr_o = 1'b1; + end + 2'b10: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OP_IMM}; + 2'b11: + case ({instr_i[12], instr_i[6:5]}) + 3'b000: instr_o = {2'b01, 5'b00000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], OPCODE_OP}; + 3'b001: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], OPCODE_OP}; + 3'b010: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], OPCODE_OP}; + 3'b011: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], OPCODE_OP}; + 3'b100, 3'b101, 3'b110, 3'b111: illegal_instr_o = 1'b1; + default: illegal_instr_o = 1'b1; + endcase + default: illegal_instr_o = 1'b1; + endcase + 3'b110, 3'b111: instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b00000, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], OPCODE_BRANCH}; + default: illegal_instr_o = 1'b1; + endcase + 2'b10: + case (instr_i[15:13]) + 3'b000: begin + instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], OPCODE_OP_IMM}; + if (instr_i[12] == 1'b1) + illegal_instr_o = 1'b1; + end + 3'b010: begin + instr_o = {4'b0000, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], OPCODE_LOAD}; + if (instr_i[11:7] == 5'b00000) + illegal_instr_o = 1'b1; + end + 3'b100: + if (instr_i[12] == 1'b0) begin + if (instr_i[6:2] != 5'b00000) + instr_o = {7'b0000000, instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], OPCODE_OP}; + else begin + instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00000, OPCODE_JALR}; + if (instr_i[11:7] == 5'b00000) + illegal_instr_o = 1'b1; + end + end + else if (instr_i[6:2] != 5'b00000) + instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], OPCODE_OP}; + else if (instr_i[11:7] == 5'b00000) + instr_o = 32'h00100073; + else + instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00001, OPCODE_JALR}; + 3'b110: instr_o = {4'b0000, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, OPCODE_STORE}; + 3'b001, 3'b011, 3'b101, 3'b111: illegal_instr_o = 1'b1; + default: illegal_instr_o = 1'b1; + endcase + 2'b11: + ; + default: illegal_instr_o = 1'b1; + endcase + end + assign is_compressed_o = instr_i[1:0] != 2'b11; +endmodule +/*module brqrv_ifu_dummy_instr ( + clk_i, + rst_ni, + dummy_instr_en_i, + dummy_instr_mask_i, + dummy_instr_seed_en_i, + dummy_instr_seed_i, + fetch_valid_i, + id_in_ready_i, + insert_dummy_instr_o, + dummy_instr_data_o +); + input wire clk_i; + input wire rst_ni; + input wire dummy_instr_en_i; + input wire [2:0] dummy_instr_mask_i; + input wire dummy_instr_seed_en_i; + input wire [31:0] dummy_instr_seed_i; + input wire fetch_valid_i; + input wire id_in_ready_i; + output wire insert_dummy_instr_o; + output wire [31:0] dummy_instr_data_o; + localparam [31:0] TIMEOUT_CNT_W = 5; + localparam [31:0] OP_W = 5; + localparam [31:0] LFSR_OUT_W = ((2 + OP_W) + OP_W) + TIMEOUT_CNT_W; + wire [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] lfsr_data; + wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_incr; + wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_threshold; + wire [TIMEOUT_CNT_W - 1:0] dummy_cnt_d; + reg [TIMEOUT_CNT_W - 1:0] dummy_cnt_q; + wire dummy_cnt_en; + wire lfsr_en; + wire [LFSR_OUT_W - 1:0] lfsr_state; + wire insert_dummy_instr; + reg [6:0] dummy_set; + reg [2:0] dummy_opcode; + wire [31:0] dummy_instr; + reg [31:0] dummy_instr_seed_q; + wire [31:0] dummy_instr_seed_d; + assign lfsr_en = insert_dummy_instr & id_in_ready_i; + assign dummy_instr_seed_d = dummy_instr_seed_q ^ dummy_instr_seed_i; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + dummy_instr_seed_q <= {32 {1'sb0}}; + else if (dummy_instr_seed_en_i) + dummy_instr_seed_q <= dummy_instr_seed_d; + prim_lfsr #( + .LfsrDw(32), + .StateOutDw(LFSR_OUT_W) + ) lfsr_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .seed_en_i(dummy_instr_seed_en_i), + .seed_i(dummy_instr_seed_d), + .lfsr_en_i(lfsr_en), + .entropy_i('0), + .state_o(lfsr_state) + ); + function automatic [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] sv2v_cast_4AF33; + input reg [(((2 + OP_W) + OP_W) + TIMEOUT_CNT_W) - 1:0] inp; + sv2v_cast_4AF33 = inp; + endfunction + assign lfsr_data = sv2v_cast_4AF33(lfsr_state); + assign dummy_cnt_threshold = lfsr_data[TIMEOUT_CNT_W - 1-:TIMEOUT_CNT_W] & {dummy_instr_mask_i, {TIMEOUT_CNT_W - 3 {1'b1}}}; + assign dummy_cnt_incr = dummy_cnt_q + {{TIMEOUT_CNT_W - 1 {1'b0}}, 1'b1}; + assign dummy_cnt_d = (insert_dummy_instr ? {TIMEOUT_CNT_W {1'sb0}} : dummy_cnt_incr); + assign dummy_cnt_en = (dummy_instr_en_i & id_in_ready_i) & (fetch_valid_i | insert_dummy_instr); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + dummy_cnt_q <= {TIMEOUT_CNT_W {1'sb0}}; + else if (dummy_cnt_en) + dummy_cnt_q <= dummy_cnt_d; + assign insert_dummy_instr = dummy_instr_en_i & (dummy_cnt_q == dummy_cnt_threshold); + localparam [1:0] DUMMY_ADD = 2'b00; + localparam [1:0] DUMMY_AND = 2'b11; + localparam [1:0] DUMMY_DIV = 2'b10; + localparam [1:0] DUMMY_MUL = 2'b01; + always @(*) + case (lfsr_data[2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))-:((2 + (OP_W + (OP_W + (TIMEOUT_CNT_W - 1)))) - (OP_W + (OP_W + TIMEOUT_CNT_W))) + 1]) + DUMMY_ADD: begin + dummy_set = 7'b0000000; + dummy_opcode = 3'b000; + end + DUMMY_MUL: begin + dummy_set = 7'b0000001; + dummy_opcode = 3'b000; + end + DUMMY_DIV: begin + dummy_set = 7'b0000001; + dummy_opcode = 3'b100; + end + DUMMY_AND: begin + dummy_set = 7'b0000000; + dummy_opcode = 3'b111; + end + default: begin + dummy_set = 7'b0000000; + dummy_opcode = 3'b000; + end + endcase + assign dummy_instr = {dummy_set, lfsr_data[OP_W + (OP_W + (TIMEOUT_CNT_W - 1))-:((OP_W + (OP_W + (TIMEOUT_CNT_W - 1))) - (OP_W + TIMEOUT_CNT_W)) + 1], lfsr_data[OP_W + (TIMEOUT_CNT_W - 1)-:((OP_W + (TIMEOUT_CNT_W - 1)) - TIMEOUT_CNT_W) + 1], dummy_opcode, 5'h00, 7'h33}; + assign insert_dummy_instr_o = insert_dummy_instr; + assign dummy_instr_data_o = dummy_instr; +endmodule +*/ +module brqrv_ifu_prefetch ( + clk_i, + rst_ni, + req_i, + branch_i, + branch_spec_i, + predicted_branch_i, + branch_mispredict_i, + addr_i, + ready_i, + valid_o, + rdata_o, + addr_o, + err_o, + err_plus2_o, + instr_req_o, + instr_gnt_i, + instr_addr_o, + instr_rdata_i, + instr_err_i, + instr_pmp_err_i, + instr_rvalid_i, + busy_o +); + parameter [0:0] BranchPredictor = 1'b0; + input wire clk_i; + input wire rst_ni; + input wire req_i; + input wire branch_i; + input wire branch_spec_i; + input wire predicted_branch_i; + input wire branch_mispredict_i; + input wire [31:0] addr_i; + input wire ready_i; + output wire valid_o; + output wire [31:0] rdata_o; + output wire [31:0] addr_o; + output wire err_o; + output wire err_plus2_o; + output wire instr_req_o; + input wire instr_gnt_i; + output wire [31:0] instr_addr_o; + input wire [31:0] instr_rdata_i; + input wire instr_err_i; + input wire instr_pmp_err_i; + input wire instr_rvalid_i; + output wire busy_o; + localparam [31:0] NUM_REQS = 2; + wire branch_suppress; + wire valid_new_req; + wire valid_req; + wire valid_req_d; + reg valid_req_q; + wire discard_req_d; + reg discard_req_q; + wire gnt_or_pmp_err; + wire rvalid_or_pmp_err; + wire [NUM_REQS - 1:0] rdata_outstanding_n; + wire [NUM_REQS - 1:0] rdata_outstanding_s; + reg [NUM_REQS - 1:0] rdata_outstanding_q; + wire [NUM_REQS - 1:0] branch_discard_n; + wire [NUM_REQS - 1:0] branch_discard_s; + reg [NUM_REQS - 1:0] branch_discard_q; + wire [NUM_REQS - 1:0] rdata_pmp_err_n; + wire [NUM_REQS - 1:0] rdata_pmp_err_s; + reg [NUM_REQS - 1:0] rdata_pmp_err_q; + wire [NUM_REQS - 1:0] rdata_outstanding_rev; + wire [31:0] stored_addr_d; + reg [31:0] stored_addr_q; + wire stored_addr_en; + wire [31:0] fetch_addr_d; + reg [31:0] fetch_addr_q; + wire fetch_addr_en; + wire [31:0] branch_mispredict_addr; + wire [31:0] instr_addr; + wire [31:0] instr_addr_w_aligned; + wire instr_or_pmp_err; + wire fifo_valid; + wire [31:0] fifo_addr; + wire fifo_ready; + wire fifo_clear; + wire [NUM_REQS - 1:0] fifo_busy; + wire valid_raw; + wire [31:0] addr_next; + wire branch_or_mispredict; + assign busy_o = |rdata_outstanding_q | instr_req_o; + assign branch_or_mispredict = branch_i | branch_mispredict_i; + assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0]; + assign fifo_clear = branch_or_mispredict; + generate + genvar i; + for (i = 0; i < NUM_REQS; i = i + 1) begin : gen_rd_rev + assign rdata_outstanding_rev[i] = rdata_outstanding_q[(NUM_REQS - 1) - i]; + end + endgenerate + assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev); + brqrv_ifu_prefetch_fifo #(.NUM_REQS(NUM_REQS)) fifo_i( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clear_i(fifo_clear), + .busy_o(fifo_busy), + .in_valid_i(fifo_valid), + .in_addr_i(fifo_addr), + .in_rdata_i(instr_rdata_i), + .in_err_i(instr_or_pmp_err), + .out_valid_o(valid_raw), + .out_ready_i(ready_i), + .out_rdata_o(rdata_o), + .out_addr_o(addr_o), + .out_addr_next_o(addr_next), + .out_err_o(err_o), + .out_err_plus2_o(err_plus2_o) + ); + assign branch_suppress = branch_spec_i & ~branch_i; + assign valid_new_req = ((~branch_suppress & req_i) & (fifo_ready | branch_or_mispredict)) & ~rdata_outstanding_q[NUM_REQS - 1]; + assign valid_req = valid_req_q | valid_new_req; + assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i; + assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]); + assign valid_req_d = valid_req & ~gnt_or_pmp_err; + assign discard_req_d = valid_req_q & (branch_or_mispredict | discard_req_q); + assign stored_addr_en = (valid_new_req & ~valid_req_q) & ~gnt_or_pmp_err; + assign stored_addr_d = instr_addr; + always @(posedge clk_i) + if (stored_addr_en) + stored_addr_q <= stored_addr_d; + generate + if (BranchPredictor) begin : g_branch_predictor + reg [31:0] branch_mispredict_addr_q; + wire branch_mispredict_addr_en; + assign branch_mispredict_addr_en = branch_i & predicted_branch_i; + always @(posedge clk_i) + if (branch_mispredict_addr_en) + branch_mispredict_addr_q <= addr_next; + assign branch_mispredict_addr = branch_mispredict_addr_q; + end + else begin : g_no_branch_predictor + wire unused_predicted_branch; + wire [31:0] unused_addr_next; + assign unused_predicted_branch = predicted_branch_i; + assign unused_addr_next = addr_next; + assign branch_mispredict_addr = {32 {1'sb0}}; + end + endgenerate + assign fetch_addr_en = branch_or_mispredict | (valid_new_req & ~valid_req_q); + assign fetch_addr_d = (branch_i ? addr_i : (branch_mispredict_i ? {branch_mispredict_addr[31:2], 2'b00} : {fetch_addr_q[31:2], 2'b00})) + {{29 {1'b0}}, valid_new_req & ~valid_req_q, 2'b00}; + always @(posedge clk_i) + if (fetch_addr_en) + fetch_addr_q <= fetch_addr_d; + assign instr_addr = (valid_req_q ? stored_addr_q : (branch_spec_i ? addr_i : (branch_mispredict_i ? branch_mispredict_addr : fetch_addr_q))); + assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00}; + generate + for (i = 0; i < NUM_REQS; i = i + 1) begin : g_outstanding_reqs + if (i == 0) begin : g_req0 + assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) | rdata_outstanding_q[i]; + assign branch_discard_n[i] = (((valid_req & gnt_or_pmp_err) & discard_req_d) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i]; + assign rdata_pmp_err_n[i] = ((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) | rdata_pmp_err_q[i]; + end + else begin : g_reqtop + assign rdata_outstanding_n[i] = ((valid_req & gnt_or_pmp_err) & rdata_outstanding_q[i - 1]) | rdata_outstanding_q[i]; + assign branch_discard_n[i] = ((((valid_req & gnt_or_pmp_err) & discard_req_d) & rdata_outstanding_q[i - 1]) | (branch_or_mispredict & rdata_outstanding_q[i])) | branch_discard_q[i]; + assign rdata_pmp_err_n[i] = (((valid_req & ~rdata_outstanding_q[i]) & instr_pmp_err_i) & rdata_outstanding_q[i - 1]) | rdata_pmp_err_q[i]; + end + end + endgenerate + assign rdata_outstanding_s = (rvalid_or_pmp_err ? {1'b0, rdata_outstanding_n[NUM_REQS - 1:1]} : rdata_outstanding_n); + assign branch_discard_s = (rvalid_or_pmp_err ? {1'b0, branch_discard_n[NUM_REQS - 1:1]} : branch_discard_n); + assign rdata_pmp_err_s = (rvalid_or_pmp_err ? {1'b0, rdata_pmp_err_n[NUM_REQS - 1:1]} : rdata_pmp_err_n); + assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0]; + assign fifo_addr = (branch_mispredict_i ? branch_mispredict_addr : addr_i); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + valid_req_q <= 1'b0; + discard_req_q <= 1'b0; + rdata_outstanding_q <= 'b0; + branch_discard_q <= 'b0; + rdata_pmp_err_q <= 'b0; + end + else begin + valid_req_q <= valid_req_d; + discard_req_q <= discard_req_d; + rdata_outstanding_q <= rdata_outstanding_s; + branch_discard_q <= branch_discard_s; + rdata_pmp_err_q <= rdata_pmp_err_s; + end + assign instr_req_o = valid_req; + assign instr_addr_o = instr_addr_w_aligned; + assign valid_o = valid_raw & ~branch_mispredict_i; +endmodule +module brqrv_ifu_prefetch_fifo ( + clk_i, + rst_ni, + clear_i, + busy_o, + in_valid_i, + in_addr_i, + in_rdata_i, + in_err_i, + out_valid_o, + out_ready_i, + out_addr_o, + out_addr_next_o, + out_rdata_o, + out_err_o, + out_err_plus2_o +); + parameter [31:0] NUM_REQS = 2; + input wire clk_i; + input wire rst_ni; + input wire clear_i; + output wire [NUM_REQS - 1:0] busy_o; + input wire in_valid_i; + input wire [31:0] in_addr_i; + input wire [31:0] in_rdata_i; + input wire in_err_i; + output reg out_valid_o; + input wire out_ready_i; + output wire [31:0] out_addr_o; + output wire [31:0] out_addr_next_o; + output reg [31:0] out_rdata_o; + output reg out_err_o; + output reg out_err_plus2_o; + localparam [31:0] DEPTH = NUM_REQS + 1; + wire [(DEPTH * 32) - 1:0] rdata_d; + reg [(DEPTH * 32) - 1:0] rdata_q; + wire [DEPTH - 1:0] err_d; + reg [DEPTH - 1:0] err_q; + wire [DEPTH - 1:0] valid_d; + reg [DEPTH - 1:0] valid_q; + wire [DEPTH - 1:0] lowest_free_entry; + wire [DEPTH - 1:0] valid_pushed; + wire [DEPTH - 1:0] valid_popped; + wire [DEPTH - 1:0] entry_en; + wire pop_fifo; + wire [31:0] rdata; + wire [31:0] rdata_unaligned; + wire err; + wire err_unaligned; + wire err_plus2; + wire valid; + wire valid_unaligned; + wire aligned_is_compressed; + wire unaligned_is_compressed; + wire addr_incr_two; + wire [31:1] instr_addr_next; + wire [31:1] instr_addr_d; + reg [31:1] instr_addr_q; + wire instr_addr_en; + wire unused_addr_in; + assign rdata = (valid_q[0] ? rdata_q[0+:32] : in_rdata_i); + assign err = (valid_q[0] ? err_q[0] : in_err_i); + assign valid = valid_q[0] | in_valid_i; + assign rdata_unaligned = (valid_q[1] ? {rdata_q[47-:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]}); + assign err_unaligned = (valid_q[1] ? (err_q[1] & ~unaligned_is_compressed) | err_q[0] : (valid_q[0] & err_q[0]) | (in_err_i & (~valid_q[0] | ~unaligned_is_compressed))); + assign err_plus2 = (valid_q[1] ? err_q[1] & ~err_q[0] : (in_err_i & valid_q[0]) & ~err_q[0]); + assign valid_unaligned = (valid_q[1] ? 1'b1 : valid_q[0] & in_valid_i); + assign unaligned_is_compressed = (rdata[17:16] != 2'b11) | err; + assign aligned_is_compressed = (rdata[1:0] != 2'b11) & ~err; + always @(*) + if (out_addr_o[1]) begin + out_rdata_o = rdata_unaligned; + out_err_o = err_unaligned; + out_err_plus2_o = err_plus2; + if (unaligned_is_compressed) + out_valid_o = valid; + else + out_valid_o = valid_unaligned; + end + else begin + out_rdata_o = rdata; + out_err_o = err; + out_err_plus2_o = 1'b0; + out_valid_o = valid; + end + assign instr_addr_en = clear_i | (out_ready_i & out_valid_o); + assign addr_incr_two = (instr_addr_q[1] ? unaligned_is_compressed : aligned_is_compressed); + assign instr_addr_next = instr_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two}; + assign instr_addr_d = (clear_i ? in_addr_i[31:1] : instr_addr_next); + always @(posedge clk_i) + if (instr_addr_en) + instr_addr_q <= instr_addr_d; + assign out_addr_next_o = {instr_addr_next, 1'b0}; + assign out_addr_o = {instr_addr_q, 1'b0}; + assign unused_addr_in = in_addr_i[0]; + assign busy_o = valid_q[DEPTH - 1:DEPTH - NUM_REQS]; + assign pop_fifo = (out_ready_i & out_valid_o) & (~aligned_is_compressed | out_addr_o[1]); + generate + genvar i; + for (i = 0; i < (DEPTH - 1); i = i + 1) begin : g_fifo_next + if (i == 0) begin : g_ent0 + assign lowest_free_entry[i] = ~valid_q[i]; + end + else begin : g_ent_others + assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i - 1]; + end + assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | valid_q[i]; + assign valid_popped[i] = (pop_fifo ? valid_pushed[i + 1] : valid_pushed[i]); + assign valid_d[i] = valid_popped[i] & ~clear_i; + assign entry_en[i] = (valid_pushed[i + 1] & pop_fifo) | ((in_valid_i & lowest_free_entry[i]) & ~pop_fifo); + assign rdata_d[i * 32+:32] = (valid_q[i + 1] ? rdata_q[(i + 1) * 32+:32] : in_rdata_i); + assign err_d[i] = (valid_q[i + 1] ? err_q[i + 1] : in_err_i); + end + endgenerate + assign lowest_free_entry[DEPTH - 1] = ~valid_q[DEPTH - 1] & valid_q[DEPTH - 2]; + assign valid_pushed[DEPTH - 1] = valid_q[DEPTH - 1] | (in_valid_i & lowest_free_entry[DEPTH - 1]); + assign valid_popped[DEPTH - 1] = (pop_fifo ? 1'b0 : valid_pushed[DEPTH - 1]); + assign valid_d[DEPTH - 1] = valid_popped[DEPTH - 1] & ~clear_i; + assign entry_en[DEPTH - 1] = in_valid_i & lowest_free_entry[DEPTH - 1]; + assign rdata_d[(DEPTH - 1) * 32+:32] = in_rdata_i; + assign err_d[DEPTH - 1] = in_err_i; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + valid_q <= {DEPTH {1'sb0}}; + else + valid_q <= valid_d; + generate + for (i = 0; i < DEPTH; i = i + 1) begin : g_fifo_regs + always @(posedge clk_i) + if (entry_en[i]) begin + rdata_q[i * 32+:32] <= rdata_d[i * 32+:32]; + err_q[i] <= err_d[i]; + end + end + endgenerate +endmodule +module brqrv_lsu ( + clk_i, + rst_ni, + data_req_o, + data_gnt_i, + data_rvalid_i, + data_err_i, + data_pmp_err_i, + data_addr_o, + data_we_o, + data_be_o, + data_wdata_o, + data_rdata_i, + lsu_we_i, + lsu_type_i, + lsu_wdata_i, + lsu_sign_ext_i, + lsu_rdata_o, + lsu_rdata_valid_o, + lsu_req_i, + adder_result_ex_i, + addr_incr_req_o, + addr_last_o, + lsu_req_done_o, + lsu_resp_valid_o, + load_err_o, + store_err_o, + busy_o, + perf_load_o, + perf_store_o +); + input wire clk_i; + input wire rst_ni; + output reg data_req_o; + input wire data_gnt_i; + input wire data_rvalid_i; + input wire data_err_i; + input wire data_pmp_err_i; + output wire [31:0] data_addr_o; + output wire data_we_o; + output wire [3:0] data_be_o; + output wire [31:0] data_wdata_o; + input wire [31:0] data_rdata_i; + input wire lsu_we_i; + input wire [1:0] lsu_type_i; + input wire [31:0] lsu_wdata_i; + input wire lsu_sign_ext_i; + output wire [31:0] lsu_rdata_o; + output wire lsu_rdata_valid_o; + input wire lsu_req_i; + input wire [31:0] adder_result_ex_i; + output reg addr_incr_req_o; + output wire [31:0] addr_last_o; + output wire lsu_req_done_o; + output wire lsu_resp_valid_o; + output wire load_err_o; + output wire store_err_o; + output wire busy_o; + output reg perf_load_o; + output reg perf_store_o; + wire [31:0] data_addr; + wire [31:0] data_addr_w_aligned; + reg [31:0] addr_last_q; + reg addr_update; + reg ctrl_update; + reg rdata_update; + reg [31:8] rdata_q; + reg [1:0] rdata_offset_q; + reg [1:0] data_type_q; + reg data_sign_ext_q; + reg data_we_q; + wire [1:0] data_offset; + reg [3:0] data_be; + reg [31:0] data_wdata; + reg [31:0] data_rdata_ext; + reg [31:0] rdata_w_ext; + reg [31:0] rdata_h_ext; + reg [31:0] rdata_b_ext; + wire split_misaligned_access; + reg handle_misaligned_q; + reg handle_misaligned_d; + reg pmp_err_q; + reg pmp_err_d; + reg lsu_err_q; + reg lsu_err_d; + wire data_or_pmp_err; + reg [2:0] ls_fsm_cs; + reg [2:0] ls_fsm_ns; + assign data_addr = adder_result_ex_i; + assign data_offset = data_addr[1:0]; + always @(*) + case (lsu_type_i) + 2'b00: + if (!handle_misaligned_q) + case (data_offset) + 2'b00: data_be = 4'b1111; + 2'b01: data_be = 4'b1110; + 2'b10: data_be = 4'b1100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase + else + case (data_offset) + 2'b00: data_be = 4'b0000; + 2'b01: data_be = 4'b0001; + 2'b10: data_be = 4'b0011; + 2'b11: data_be = 4'b0111; + default: data_be = 4'b1111; + endcase + 2'b01: + if (!handle_misaligned_q) + case (data_offset) + 2'b00: data_be = 4'b0011; + 2'b01: data_be = 4'b0110; + 2'b10: data_be = 4'b1100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase + else + data_be = 4'b0001; + 2'b10, 2'b11: + case (data_offset) + 2'b00: data_be = 4'b0001; + 2'b01: data_be = 4'b0010; + 2'b10: data_be = 4'b0100; + 2'b11: data_be = 4'b1000; + default: data_be = 4'b1111; + endcase + default: data_be = 4'b1111; + endcase + always @(*) + case (data_offset) + 2'b00: data_wdata = lsu_wdata_i[31:0]; + 2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]}; + 2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]}; + 2'b11: data_wdata = {lsu_wdata_i[7:0], lsu_wdata_i[31:8]}; + default: data_wdata = lsu_wdata_i[31:0]; + endcase + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + rdata_q <= {24 {1'sb0}}; + else if (rdata_update) + rdata_q <= data_rdata_i[31:8]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + rdata_offset_q <= 2'h0; + data_type_q <= 2'h0; + data_sign_ext_q <= 1'b0; + data_we_q <= 1'b0; + end + else if (ctrl_update) begin + rdata_offset_q <= data_offset; + data_type_q <= lsu_type_i; + data_sign_ext_q <= lsu_sign_ext_i; + data_we_q <= lsu_we_i; + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + addr_last_q <= {32 {1'sb0}}; + else if (addr_update) + addr_last_q <= data_addr; + always @(*) + case (rdata_offset_q) + 2'b00: rdata_w_ext = data_rdata_i[31:0]; + 2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]}; + 2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]}; + 2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]}; + default: rdata_w_ext = data_rdata_i[31:0]; + endcase + always @(*) + case (rdata_offset_q) + 2'b00: + if (!data_sign_ext_q) + rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; + else + rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]}; + 2'b01: + if (!data_sign_ext_q) + rdata_h_ext = {16'h0000, data_rdata_i[23:8]}; + else + rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]}; + 2'b10: + if (!data_sign_ext_q) + rdata_h_ext = {16'h0000, data_rdata_i[31:16]}; + else + rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]}; + 2'b11: + if (!data_sign_ext_q) + rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]}; + else + rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]}; + default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]}; + endcase + always @(*) + case (rdata_offset_q) + 2'b00: + if (!data_sign_ext_q) + rdata_b_ext = {24'h000000, data_rdata_i[7:0]}; + else + rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]}; + 2'b01: + if (!data_sign_ext_q) + rdata_b_ext = {24'h000000, data_rdata_i[15:8]}; + else + rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]}; + 2'b10: + if (!data_sign_ext_q) + rdata_b_ext = {24'h000000, data_rdata_i[23:16]}; + else + rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]}; + 2'b11: + if (!data_sign_ext_q) + rdata_b_ext = {24'h000000, data_rdata_i[31:24]}; + else + rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]}; + default: rdata_b_ext = {24'h000000, data_rdata_i[7:0]}; + endcase + always @(*) + case (data_type_q) + 2'b00: data_rdata_ext = rdata_w_ext; + 2'b01: data_rdata_ext = rdata_h_ext; + 2'b10, 2'b11: data_rdata_ext = rdata_b_ext; + default: data_rdata_ext = rdata_w_ext; + endcase + assign split_misaligned_access = ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || ((lsu_type_i == 2'b01) && (data_offset == 2'b11)); + localparam [2:0] IDLE = 0; + localparam [2:0] WAIT_GNT = 3; + localparam [2:0] WAIT_GNT_MIS = 1; + localparam [2:0] WAIT_RVALID_MIS = 2; + localparam [2:0] WAIT_RVALID_MIS_GNTS_DONE = 4; + always @(*) begin + ls_fsm_ns = ls_fsm_cs; + data_req_o = 1'b0; + addr_incr_req_o = 1'b0; + handle_misaligned_d = handle_misaligned_q; + pmp_err_d = pmp_err_q; + lsu_err_d = lsu_err_q; + addr_update = 1'b0; + ctrl_update = 1'b0; + rdata_update = 1'b0; + perf_load_o = 1'b0; + perf_store_o = 1'b0; + case (ls_fsm_cs) + IDLE: begin + pmp_err_d = 1'b0; + if (lsu_req_i) begin + data_req_o = 1'b1; + pmp_err_d = data_pmp_err_i; + lsu_err_d = 1'b0; + perf_load_o = ~lsu_we_i; + perf_store_o = lsu_we_i; + if (data_gnt_i) begin + ctrl_update = 1'b1; + addr_update = 1'b1; + handle_misaligned_d = split_misaligned_access; + ls_fsm_ns = (split_misaligned_access ? WAIT_RVALID_MIS : IDLE); + end + else + ls_fsm_ns = (split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT); + end + end + WAIT_GNT_MIS: begin + data_req_o = 1'b1; + if (data_gnt_i || pmp_err_q) begin + addr_update = 1'b1; + ctrl_update = 1'b1; + handle_misaligned_d = 1'b1; + ls_fsm_ns = WAIT_RVALID_MIS; + end + end + WAIT_RVALID_MIS: begin + data_req_o = 1'b1; + addr_incr_req_o = 1'b1; + if (data_rvalid_i || pmp_err_q) begin + pmp_err_d = data_pmp_err_i; + lsu_err_d = data_err_i | pmp_err_q; + rdata_update = ~data_we_q; + ls_fsm_ns = (data_gnt_i ? IDLE : WAIT_GNT); + addr_update = data_gnt_i & ~(data_err_i | pmp_err_q); + handle_misaligned_d = ~data_gnt_i; + end + else if (data_gnt_i) begin + ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE; + handle_misaligned_d = 1'b0; + end + end + WAIT_GNT: begin + addr_incr_req_o = handle_misaligned_q; + data_req_o = 1'b1; + if (data_gnt_i || pmp_err_q) begin + ctrl_update = 1'b1; + addr_update = ~lsu_err_q; + ls_fsm_ns = IDLE; + handle_misaligned_d = 1'b0; + end + end + WAIT_RVALID_MIS_GNTS_DONE: begin + addr_incr_req_o = 1'b1; + if (data_rvalid_i) begin + pmp_err_d = data_pmp_err_i; + lsu_err_d = data_err_i; + addr_update = ~data_err_i; + rdata_update = ~data_we_q; + ls_fsm_ns = IDLE; + end + end + default: ls_fsm_ns = IDLE; + endcase + end + assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + ls_fsm_cs <= IDLE; + handle_misaligned_q <= 1'sb0; + pmp_err_q <= 1'sb0; + lsu_err_q <= 1'sb0; + end + else begin + ls_fsm_cs <= ls_fsm_ns; + handle_misaligned_q <= handle_misaligned_d; + pmp_err_q <= pmp_err_d; + lsu_err_q <= lsu_err_d; + end + assign data_or_pmp_err = (lsu_err_q | data_err_i) | pmp_err_q; + assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE); + assign lsu_rdata_valid_o = (((ls_fsm_cs == IDLE) & data_rvalid_i) & ~data_or_pmp_err) & ~data_we_q; + assign lsu_rdata_o = data_rdata_ext; + assign data_addr_w_aligned = {data_addr[31:2], 2'b00}; + assign data_addr_o = data_addr_w_aligned; + assign data_wdata_o = data_wdata; + assign data_we_o = lsu_we_i; + assign data_be_o = data_be; + assign addr_last_o = addr_last_q; + assign load_err_o = (data_or_pmp_err & ~data_we_q) & lsu_resp_valid_o; + assign store_err_o = (data_or_pmp_err & data_we_q) & lsu_resp_valid_o; + assign busy_o = ls_fsm_cs != IDLE; +endmodule +module brqrv_pmp ( + clk_i, + rst_ni, + csr_pmp_cfg_i, + csr_pmp_addr_i, + priv_mode_i, + pmp_req_addr_i, + pmp_req_type_i, + pmp_req_err_o +); + parameter [31:0] PMPGranularity = 0; + parameter [31:0] PMPNumChan = 2; + parameter [31:0] PMPNumRegions = 4; + input wire clk_i; + input wire rst_ni; + input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_i; + input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_i; + input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] priv_mode_i; + input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 34) + (((PMPNumChan - 1) * 34) - 1) : (PMPNumChan * 34) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 34 : 0)] pmp_req_addr_i; + input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] pmp_req_type_i; + output wire [PMPNumChan - 1:0] pmp_req_err_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire [33:0] region_start_addr [0:PMPNumRegions - 1]; + wire [33:PMPGranularity + 2] region_addr_mask [0:PMPNumRegions - 1]; + wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_gt; + wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_lt; + wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_eq; + reg [(PMPNumChan * PMPNumRegions) - 1:0] region_match_all; + wire [(PMPNumChan * PMPNumRegions) - 1:0] region_perm_check; + reg [PMPNumChan - 1:0] access_fault; + generate + genvar r; + for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_addr_exp + if (r == 0) begin : g_entry0 + assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == PMP_MODE_TOR ? 34'h000000000 : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]); + end + else begin : g_oth + assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == PMP_MODE_TOR ? csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r - 1 : (PMPNumRegions - 1) - (r - 1)) * 34+:34] : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]); + end + genvar b; + for (b = PMPGranularity + 2; b < 34; b = b + 1) begin : g_bitmask + if (b == (PMPGranularity + 2)) begin : g_bit0 + assign region_addr_mask[r][b] = csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != PMP_MODE_NAPOT; + end + else begin : g_others + assign region_addr_mask[r][b] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != PMP_MODE_NAPOT) | ~&csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + ((b - 1) >= (PMPGranularity + 2) ? b - 1 : ((b - 1) + ((b - 1) >= (PMPGranularity + 2) ? ((b - 1) - (PMPGranularity + 2)) + 1 : ((PMPGranularity + 2) - (b - 1)) + 1)) - 1)-:((b - 1) >= (PMPGranularity + 2) ? ((b - 1) - (PMPGranularity + 2)) + 1 : ((PMPGranularity + 2) - (b - 1)) + 1)]; + end + end + end + endgenerate + generate + genvar c; + for (c = 0; c < PMPNumChan; c = c + 1) begin : g_access_check + for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_regions + assign region_match_eq[(c * PMPNumRegions) + r] = (pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] & region_addr_mask[r]) == (region_start_addr[r][33:PMPGranularity + 2] & region_addr_mask[r]); + assign region_match_gt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] > region_start_addr[r][33:PMPGranularity + 2]; + assign region_match_lt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] < csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)]; + always @(*) begin + region_match_all[(c * PMPNumRegions) + r] = 1'b0; + case (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2]) + PMP_MODE_OFF: region_match_all[(c * PMPNumRegions) + r] = 1'b0; + PMP_MODE_NA4: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r]; + PMP_MODE_NAPOT: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r]; + PMP_MODE_TOR: region_match_all[(c * PMPNumRegions) + r] = (region_match_eq[(c * PMPNumRegions) + r] | region_match_gt[(c * PMPNumRegions) + r]) & region_match_lt[(c * PMPNumRegions) + r]; + default: region_match_all[(c * PMPNumRegions) + r] = 1'b0; + endcase + end + assign region_perm_check[(c * PMPNumRegions) + r] = (((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == PMP_ACC_EXEC) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 2]) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == PMP_ACC_WRITE) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 1])) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == PMP_ACC_READ) & csr_pmp_cfg_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6]); + end + always @(*) begin + access_fault[c] = priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] != PRIV_LVL_M; + begin : sv2v_autoblock_69 + reg signed [31:0] r; + for (r = PMPNumRegions - 1; r >= 0; r = r - 1) + if (region_match_all[(c * PMPNumRegions) + r]) + access_fault[c] = (priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == PRIV_LVL_M ? csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 5] & ~region_perm_check[(c * PMPNumRegions) + r] : ~region_perm_check[(c * PMPNumRegions) + r]); + end + end + assign pmp_req_err_o[c] = access_fault[c]; + end + endgenerate +endmodule +module brqrv_register_file_ff ( + clk_i, + rst_ni, + test_en_i, + dummy_instr_id_i, + raddr_a_i, + rdata_a_o, + raddr_b_i, + rdata_b_o, + waddr_a_i, + wdata_a_i, + we_a_i +); + parameter [0:0] RV32E = 0; + parameter [31:0] DataWidth = 32; + parameter [0:0] DummyInstructions = 0; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire dummy_instr_id_i; + input wire [4:0] raddr_a_i; + output wire [DataWidth - 1:0] rdata_a_o; + input wire [4:0] raddr_b_i; + output wire [DataWidth - 1:0] rdata_b_o; + input wire [4:0] waddr_a_i; + input wire [DataWidth - 1:0] wdata_a_i; + input wire we_a_i; + localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); + localparam [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; + wire [(NUM_WORDS * DataWidth) - 1:0] rf_reg; + reg [((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) * DataWidth) + (DataWidth - 1) : ((3 - NUM_WORDS) * DataWidth) + (((NUM_WORDS - 1) * DataWidth) - 1)):((NUM_WORDS - 1) >= 1 ? DataWidth : (NUM_WORDS - 1) * DataWidth)] rf_reg_q; + reg [NUM_WORDS - 1:1] we_a_dec; + function automatic [4:0] sv2v_cast_5_unsigned; + input reg [4:0] inp; + sv2v_cast_5_unsigned = inp; + endfunction + always @(*) begin : we_a_decoder + begin : sv2v_autoblock_70 + reg [31:0] i; + for (i = 1; i < NUM_WORDS; i = i + 1) + we_a_dec[i] = (waddr_a_i == sv2v_cast_5_unsigned(i) ? we_a_i : 1'b0); + end + end + generate + genvar i; + for (i = 1; i < NUM_WORDS; i = i + 1) begin : g_rf_flops + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= {DataWidth {1'sb0}}; + else if (we_a_dec[i]) + rf_reg_q[((NUM_WORDS - 1) >= 1 ? i : 1 - (i - (NUM_WORDS - 1))) * DataWidth+:DataWidth] <= wdata_a_i; + end + endgenerate + generate + if (DummyInstructions) begin : g_dummy_r0 + wire we_r0_dummy; + reg [DataWidth - 1:0] rf_r0_q; + assign we_r0_dummy = we_a_i & dummy_instr_id_i; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + rf_r0_q <= {DataWidth {1'sb0}}; + else if (we_r0_dummy) + rf_r0_q <= wdata_a_i; + assign rf_reg[0+:DataWidth] = (dummy_instr_id_i ? rf_r0_q : {DataWidth {1'sb0}}); + end + else begin : g_normal_r0 + wire unused_dummy_instr_id; + assign unused_dummy_instr_id = dummy_instr_id_i; + assign rf_reg[0+:DataWidth] = {DataWidth {1'sb0}}; + end + endgenerate + assign rf_reg[DataWidth * (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)] = rf_reg_q[DataWidth * ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) : 1 - (((NUM_WORDS - 1) >= 1 ? ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1) - (((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS) - 1) : ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : ((NUM_WORDS - 1) + ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)) - 1)) - (NUM_WORDS - 1)))+:DataWidth * ((NUM_WORDS - 1) >= 1 ? NUM_WORDS - 1 : 3 - NUM_WORDS)]; + assign rdata_a_o = rf_reg[raddr_a_i * DataWidth+:DataWidth]; + assign rdata_b_o = rf_reg[raddr_b_i * DataWidth+:DataWidth]; +endmodule +module brqrv_register_file_fpga ( + clk_i, + rst_ni, + test_en_i, + dummy_instr_id_i, + raddr_a_i, + rdata_a_o, + raddr_b_i, + rdata_b_o, + waddr_a_i, + wdata_a_i, + we_a_i +); + parameter [0:0] RV32E = 0; + parameter [31:0] DataWidth = 32; + parameter [0:0] DummyInstructions = 0; + input wire clk_i; + input wire rst_ni; + input wire test_en_i; + input wire dummy_instr_id_i; + input wire [4:0] raddr_a_i; + output wire [DataWidth - 1:0] rdata_a_o; + input wire [4:0] raddr_b_i; + output wire [DataWidth - 1:0] rdata_b_o; + input wire [4:0] waddr_a_i; + input wire [DataWidth - 1:0] wdata_a_i; + input wire we_a_i; + localparam signed [31:0] ADDR_WIDTH = (RV32E ? 4 : 5); + localparam signed [31:0] NUM_WORDS = 2 ** ADDR_WIDTH; + reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1]; + wire we; + assign rdata_a_o = (raddr_a_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_a_i]); + assign rdata_b_o = (raddr_b_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_b_i]); + assign we = (waddr_a_i == {5 {1'sb0}} ? 1'b0 : we_a_i); + always @(posedge clk_i) begin : sync_write + if (we == 1'b1) + mem[waddr_a_i] <= wdata_a_i; + end + wire unused_rst_ni; + assign unused_rst_ni = rst_ni; + wire unused_dummy_instr; + assign unused_dummy_instr = dummy_instr_id_i; +endmodule +module brqrv_wbu ( + clk_i, + rst_ni, + en_wb_i, + instr_type_wb_i, + pc_id_i, + ready_wb_o, + rf_write_wb_o, + outstanding_load_wb_o, + outstanding_store_wb_o, + pc_wb_o, + rf_waddr_id_i, + rf_wdata_id_i, + rf_we_id_i, + rf_wdata_lsu_i, + rf_we_lsu_i, + rf_wdata_fwd_wb_o, + rf_waddr_wb_o, + rf_wdata_wb_o, + rf_we_wb_o, + lsu_resp_valid_i, + instr_done_wb_o +); + parameter [0:0] WritebackStage = 1'b0; + input wire clk_i; + input wire rst_ni; + input wire en_wb_i; + input wire [1:0] instr_type_wb_i; + input wire [31:0] pc_id_i; + output wire ready_wb_o; + output wire rf_write_wb_o; + output wire outstanding_load_wb_o; + output wire outstanding_store_wb_o; + output wire [31:0] pc_wb_o; + input wire [4:0] rf_waddr_id_i; + input wire [31:0] rf_wdata_id_i; + input wire rf_we_id_i; + input wire [31:0] rf_wdata_lsu_i; + input wire rf_we_lsu_i; + output wire [31:0] rf_wdata_fwd_wb_o; + output wire [4:0] rf_waddr_wb_o; + output wire [31:0] rf_wdata_wb_o; + output wire rf_we_wb_o; + input wire lsu_resp_valid_i; + output wire instr_done_wb_o; + localparam integer RegFileFF = 0; + localparam integer RegFileFPGA = 1; + localparam integer RegFileLatch = 2; + localparam integer RV32MNone = 0; + localparam integer RV32MSlow = 1; + localparam integer RV32MFast = 2; + localparam integer RV32MSingleCycle = 3; + localparam integer RV32BNone = 0; + localparam integer RV32BBalanced = 1; + localparam integer RV32BFull = 2; + localparam [6:0] OPCODE_LOAD = 7'h03; + localparam [6:0] OPCODE_MISC_MEM = 7'h0f; + localparam [6:0] OPCODE_OP_IMM = 7'h13; + localparam [6:0] OPCODE_AUIPC = 7'h17; + localparam [6:0] OPCODE_STORE = 7'h23; + localparam [6:0] OPCODE_OP = 7'h33; + localparam [6:0] OPCODE_LUI = 7'h37; + localparam [6:0] OPCODE_BRANCH = 7'h63; + localparam [6:0] OPCODE_JALR = 7'h67; + localparam [6:0] OPCODE_JAL = 7'h6f; + localparam [6:0] OPCODE_SYSTEM = 7'h73; + localparam [5:0] ALU_ADD = 0; + localparam [5:0] ALU_SUB = 1; + localparam [5:0] ALU_XOR = 2; + localparam [5:0] ALU_OR = 3; + localparam [5:0] ALU_AND = 4; + localparam [5:0] ALU_XNOR = 5; + localparam [5:0] ALU_ORN = 6; + localparam [5:0] ALU_ANDN = 7; + localparam [5:0] ALU_SRA = 8; + localparam [5:0] ALU_SRL = 9; + localparam [5:0] ALU_SLL = 10; + localparam [5:0] ALU_SRO = 11; + localparam [5:0] ALU_SLO = 12; + localparam [5:0] ALU_ROR = 13; + localparam [5:0] ALU_ROL = 14; + localparam [5:0] ALU_GREV = 15; + localparam [5:0] ALU_GORC = 16; + localparam [5:0] ALU_SHFL = 17; + localparam [5:0] ALU_UNSHFL = 18; + localparam [5:0] ALU_LT = 19; + localparam [5:0] ALU_LTU = 20; + localparam [5:0] ALU_GE = 21; + localparam [5:0] ALU_GEU = 22; + localparam [5:0] ALU_EQ = 23; + localparam [5:0] ALU_NE = 24; + localparam [5:0] ALU_MIN = 25; + localparam [5:0] ALU_MINU = 26; + localparam [5:0] ALU_MAX = 27; + localparam [5:0] ALU_MAXU = 28; + localparam [5:0] ALU_PACK = 29; + localparam [5:0] ALU_PACKU = 30; + localparam [5:0] ALU_PACKH = 31; + localparam [5:0] ALU_SEXTB = 32; + localparam [5:0] ALU_SEXTH = 33; + localparam [5:0] ALU_CLZ = 34; + localparam [5:0] ALU_CTZ = 35; + localparam [5:0] ALU_PCNT = 36; + localparam [5:0] ALU_SLT = 37; + localparam [5:0] ALU_SLTU = 38; + localparam [5:0] ALU_CMOV = 39; + localparam [5:0] ALU_CMIX = 40; + localparam [5:0] ALU_FSL = 41; + localparam [5:0] ALU_FSR = 42; + localparam [5:0] ALU_SBSET = 43; + localparam [5:0] ALU_SBCLR = 44; + localparam [5:0] ALU_SBINV = 45; + localparam [5:0] ALU_SBEXT = 46; + localparam [5:0] ALU_BEXT = 47; + localparam [5:0] ALU_BDEP = 48; + localparam [5:0] ALU_BFP = 49; + localparam [5:0] ALU_CLMUL = 50; + localparam [5:0] ALU_CLMULR = 51; + localparam [5:0] ALU_CLMULH = 52; + localparam [5:0] ALU_CRC32_B = 53; + localparam [5:0] ALU_CRC32C_B = 54; + localparam [5:0] ALU_CRC32_H = 55; + localparam [5:0] ALU_CRC32C_H = 56; + localparam [5:0] ALU_CRC32_W = 57; + localparam [5:0] ALU_CRC32C_W = 58; + localparam [1:0] MD_OP_MULL = 0; + localparam [1:0] MD_OP_MULH = 1; + localparam [1:0] MD_OP_DIV = 2; + localparam [1:0] MD_OP_REM = 3; + localparam [1:0] CSR_OP_READ = 0; + localparam [1:0] CSR_OP_WRITE = 1; + localparam [1:0] CSR_OP_SET = 2; + localparam [1:0] CSR_OP_CLEAR = 3; + localparam [1:0] PRIV_LVL_M = 2'b11; + localparam [1:0] PRIV_LVL_H = 2'b10; + localparam [1:0] PRIV_LVL_S = 2'b01; + localparam [1:0] PRIV_LVL_U = 2'b00; + localparam [3:0] XDEBUGVER_NO = 4'd0; + localparam [3:0] XDEBUGVER_STD = 4'd4; + localparam [3:0] XDEBUGVER_NONSTD = 4'd15; + localparam [1:0] WB_INSTR_LOAD = 0; + localparam [1:0] WB_INSTR_STORE = 1; + localparam [1:0] WB_INSTR_OTHER = 2; + localparam [1:0] OP_A_REG_A = 0; + localparam [1:0] OP_A_FWD = 1; + localparam [1:0] OP_A_CURRPC = 2; + localparam [1:0] OP_A_IMM = 3; + localparam [0:0] IMM_A_Z = 0; + localparam [0:0] IMM_A_ZERO = 1; + localparam [0:0] OP_B_REG_B = 0; + localparam [0:0] OP_B_IMM = 1; + localparam [2:0] IMM_B_I = 0; + localparam [2:0] IMM_B_S = 1; + localparam [2:0] IMM_B_B = 2; + localparam [2:0] IMM_B_U = 3; + localparam [2:0] IMM_B_J = 4; + localparam [2:0] IMM_B_INCR_PC = 5; + localparam [2:0] IMM_B_INCR_ADDR = 6; + localparam [0:0] RF_WD_EX = 0; + localparam [0:0] RF_WD_CSR = 1; + localparam [2:0] PC_BOOT = 0; + localparam [2:0] PC_JUMP = 1; + localparam [2:0] PC_EXC = 2; + localparam [2:0] PC_ERET = 3; + localparam [2:0] PC_DRET = 4; + localparam [2:0] PC_BP = 5; + localparam [1:0] EXC_PC_EXC = 0; + localparam [1:0] EXC_PC_IRQ = 1; + localparam [1:0] EXC_PC_DBD = 2; + localparam [1:0] EXC_PC_DBG_EXC = 3; + localparam [5:0] EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3}; + localparam [5:0] EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7}; + localparam [5:0] EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}; + localparam [5:0] EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}; + localparam [5:0] EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0}; + localparam [5:0] EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1}; + localparam [5:0] EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2}; + localparam [5:0] EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3}; + localparam [5:0] EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5}; + localparam [5:0] EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7}; + localparam [5:0] EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8}; + localparam [5:0] EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}; + localparam [2:0] DBG_CAUSE_NONE = 3'h0; + localparam [2:0] DBG_CAUSE_EBREAK = 3'h1; + localparam [2:0] DBG_CAUSE_TRIGGER = 3'h2; + localparam [2:0] DBG_CAUSE_HALTREQ = 3'h3; + localparam [2:0] DBG_CAUSE_STEP = 3'h4; + localparam [31:0] PMP_MAX_REGIONS = 16; + localparam [31:0] PMP_CFG_W = 8; + localparam [31:0] PMP_I = 0; + localparam [31:0] PMP_D = 1; + localparam [1:0] PMP_ACC_EXEC = 2'b00; + localparam [1:0] PMP_ACC_WRITE = 2'b01; + localparam [1:0] PMP_ACC_READ = 2'b10; + localparam [1:0] PMP_MODE_OFF = 2'b00; + localparam [1:0] PMP_MODE_TOR = 2'b01; + localparam [1:0] PMP_MODE_NA4 = 2'b10; + localparam [1:0] PMP_MODE_NAPOT = 2'b11; + localparam [11:0] CSR_MHARTID = 12'hf14; + localparam [11:0] CSR_MSTATUS = 12'h300; + localparam [11:0] CSR_MISA = 12'h301; + localparam [11:0] CSR_MIE = 12'h304; + localparam [11:0] CSR_MTVEC = 12'h305; + localparam [11:0] CSR_MSCRATCH = 12'h340; + localparam [11:0] CSR_MEPC = 12'h341; + localparam [11:0] CSR_MCAUSE = 12'h342; + localparam [11:0] CSR_MTVAL = 12'h343; + localparam [11:0] CSR_MIP = 12'h344; + localparam [11:0] CSR_PMPCFG0 = 12'h3a0; + localparam [11:0] CSR_PMPCFG1 = 12'h3a1; + localparam [11:0] CSR_PMPCFG2 = 12'h3a2; + localparam [11:0] CSR_PMPCFG3 = 12'h3a3; + localparam [11:0] CSR_PMPADDR0 = 12'h3b0; + localparam [11:0] CSR_PMPADDR1 = 12'h3b1; + localparam [11:0] CSR_PMPADDR2 = 12'h3b2; + localparam [11:0] CSR_PMPADDR3 = 12'h3b3; + localparam [11:0] CSR_PMPADDR4 = 12'h3b4; + localparam [11:0] CSR_PMPADDR5 = 12'h3b5; + localparam [11:0] CSR_PMPADDR6 = 12'h3b6; + localparam [11:0] CSR_PMPADDR7 = 12'h3b7; + localparam [11:0] CSR_PMPADDR8 = 12'h3b8; + localparam [11:0] CSR_PMPADDR9 = 12'h3b9; + localparam [11:0] CSR_PMPADDR10 = 12'h3ba; + localparam [11:0] CSR_PMPADDR11 = 12'h3bb; + localparam [11:0] CSR_PMPADDR12 = 12'h3bc; + localparam [11:0] CSR_PMPADDR13 = 12'h3bd; + localparam [11:0] CSR_PMPADDR14 = 12'h3be; + localparam [11:0] CSR_PMPADDR15 = 12'h3bf; + localparam [11:0] CSR_TSELECT = 12'h7a0; + localparam [11:0] CSR_TDATA1 = 12'h7a1; + localparam [11:0] CSR_TDATA2 = 12'h7a2; + localparam [11:0] CSR_TDATA3 = 12'h7a3; + localparam [11:0] CSR_MCONTEXT = 12'h7a8; + localparam [11:0] CSR_SCONTEXT = 12'h7aa; + localparam [11:0] CSR_DCSR = 12'h7b0; + localparam [11:0] CSR_DPC = 12'h7b1; + localparam [11:0] CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] CSR_DSCRATCH1 = 12'h7b3; + localparam [11:0] CSR_MCOUNTINHIBIT = 12'h320; + localparam [11:0] CSR_MHPMEVENT3 = 12'h323; + localparam [11:0] CSR_MHPMEVENT4 = 12'h324; + localparam [11:0] CSR_MHPMEVENT5 = 12'h325; + localparam [11:0] CSR_MHPMEVENT6 = 12'h326; + localparam [11:0] CSR_MHPMEVENT7 = 12'h327; + localparam [11:0] CSR_MHPMEVENT8 = 12'h328; + localparam [11:0] CSR_MHPMEVENT9 = 12'h329; + localparam [11:0] CSR_MHPMEVENT10 = 12'h32a; + localparam [11:0] CSR_MHPMEVENT11 = 12'h32b; + localparam [11:0] CSR_MHPMEVENT12 = 12'h32c; + localparam [11:0] CSR_MHPMEVENT13 = 12'h32d; + localparam [11:0] CSR_MHPMEVENT14 = 12'h32e; + localparam [11:0] CSR_MHPMEVENT15 = 12'h32f; + localparam [11:0] CSR_MHPMEVENT16 = 12'h330; + localparam [11:0] CSR_MHPMEVENT17 = 12'h331; + localparam [11:0] CSR_MHPMEVENT18 = 12'h332; + localparam [11:0] CSR_MHPMEVENT19 = 12'h333; + localparam [11:0] CSR_MHPMEVENT20 = 12'h334; + localparam [11:0] CSR_MHPMEVENT21 = 12'h335; + localparam [11:0] CSR_MHPMEVENT22 = 12'h336; + localparam [11:0] CSR_MHPMEVENT23 = 12'h337; + localparam [11:0] CSR_MHPMEVENT24 = 12'h338; + localparam [11:0] CSR_MHPMEVENT25 = 12'h339; + localparam [11:0] CSR_MHPMEVENT26 = 12'h33a; + localparam [11:0] CSR_MHPMEVENT27 = 12'h33b; + localparam [11:0] CSR_MHPMEVENT28 = 12'h33c; + localparam [11:0] CSR_MHPMEVENT29 = 12'h33d; + localparam [11:0] CSR_MHPMEVENT30 = 12'h33e; + localparam [11:0] CSR_MHPMEVENT31 = 12'h33f; + localparam [11:0] CSR_MCYCLE = 12'hb00; + localparam [11:0] CSR_MINSTRET = 12'hb02; + localparam [11:0] CSR_MHPMCOUNTER3 = 12'hb03; + localparam [11:0] CSR_MHPMCOUNTER4 = 12'hb04; + localparam [11:0] CSR_MHPMCOUNTER5 = 12'hb05; + localparam [11:0] CSR_MHPMCOUNTER6 = 12'hb06; + localparam [11:0] CSR_MHPMCOUNTER7 = 12'hb07; + localparam [11:0] CSR_MHPMCOUNTER8 = 12'hb08; + localparam [11:0] CSR_MHPMCOUNTER9 = 12'hb09; + localparam [11:0] CSR_MHPMCOUNTER10 = 12'hb0a; + localparam [11:0] CSR_MHPMCOUNTER11 = 12'hb0b; + localparam [11:0] CSR_MHPMCOUNTER12 = 12'hb0c; + localparam [11:0] CSR_MHPMCOUNTER13 = 12'hb0d; + localparam [11:0] CSR_MHPMCOUNTER14 = 12'hb0e; + localparam [11:0] CSR_MHPMCOUNTER15 = 12'hb0f; + localparam [11:0] CSR_MHPMCOUNTER16 = 12'hb10; + localparam [11:0] CSR_MHPMCOUNTER17 = 12'hb11; + localparam [11:0] CSR_MHPMCOUNTER18 = 12'hb12; + localparam [11:0] CSR_MHPMCOUNTER19 = 12'hb13; + localparam [11:0] CSR_MHPMCOUNTER20 = 12'hb14; + localparam [11:0] CSR_MHPMCOUNTER21 = 12'hb15; + localparam [11:0] CSR_MHPMCOUNTER22 = 12'hb16; + localparam [11:0] CSR_MHPMCOUNTER23 = 12'hb17; + localparam [11:0] CSR_MHPMCOUNTER24 = 12'hb18; + localparam [11:0] CSR_MHPMCOUNTER25 = 12'hb19; + localparam [11:0] CSR_MHPMCOUNTER26 = 12'hb1a; + localparam [11:0] CSR_MHPMCOUNTER27 = 12'hb1b; + localparam [11:0] CSR_MHPMCOUNTER28 = 12'hb1c; + localparam [11:0] CSR_MHPMCOUNTER29 = 12'hb1d; + localparam [11:0] CSR_MHPMCOUNTER30 = 12'hb1e; + localparam [11:0] CSR_MHPMCOUNTER31 = 12'hb1f; + localparam [11:0] CSR_MCYCLEH = 12'hb80; + localparam [11:0] CSR_MINSTRETH = 12'hb82; + localparam [11:0] CSR_MHPMCOUNTER3H = 12'hb83; + localparam [11:0] CSR_MHPMCOUNTER4H = 12'hb84; + localparam [11:0] CSR_MHPMCOUNTER5H = 12'hb85; + localparam [11:0] CSR_MHPMCOUNTER6H = 12'hb86; + localparam [11:0] CSR_MHPMCOUNTER7H = 12'hb87; + localparam [11:0] CSR_MHPMCOUNTER8H = 12'hb88; + localparam [11:0] CSR_MHPMCOUNTER9H = 12'hb89; + localparam [11:0] CSR_MHPMCOUNTER10H = 12'hb8a; + localparam [11:0] CSR_MHPMCOUNTER11H = 12'hb8b; + localparam [11:0] CSR_MHPMCOUNTER12H = 12'hb8c; + localparam [11:0] CSR_MHPMCOUNTER13H = 12'hb8d; + localparam [11:0] CSR_MHPMCOUNTER14H = 12'hb8e; + localparam [11:0] CSR_MHPMCOUNTER15H = 12'hb8f; + localparam [11:0] CSR_MHPMCOUNTER16H = 12'hb90; + localparam [11:0] CSR_MHPMCOUNTER17H = 12'hb91; + localparam [11:0] CSR_MHPMCOUNTER18H = 12'hb92; + localparam [11:0] CSR_MHPMCOUNTER19H = 12'hb93; + localparam [11:0] CSR_MHPMCOUNTER20H = 12'hb94; + localparam [11:0] CSR_MHPMCOUNTER21H = 12'hb95; + localparam [11:0] CSR_MHPMCOUNTER22H = 12'hb96; + localparam [11:0] CSR_MHPMCOUNTER23H = 12'hb97; + localparam [11:0] CSR_MHPMCOUNTER24H = 12'hb98; + localparam [11:0] CSR_MHPMCOUNTER25H = 12'hb99; + localparam [11:0] CSR_MHPMCOUNTER26H = 12'hb9a; + localparam [11:0] CSR_MHPMCOUNTER27H = 12'hb9b; + localparam [11:0] CSR_MHPMCOUNTER28H = 12'hb9c; + localparam [11:0] CSR_MHPMCOUNTER29H = 12'hb9d; + localparam [11:0] CSR_MHPMCOUNTER30H = 12'hb9e; + localparam [11:0] CSR_MHPMCOUNTER31H = 12'hb9f; + localparam [11:0] CSR_CPUCTRL = 12'h7c0; + localparam [11:0] CSR_SECURESEED = 12'h7c1; + localparam [11:0] CSR_OFF_PMP_CFG = 12'h3a0; + localparam [11:0] CSR_OFF_PMP_ADDR = 12'h3b0; + localparam [31:0] CSR_MSTATUS_MIE_BIT = 3; + localparam [31:0] CSR_MSTATUS_MPIE_BIT = 7; + localparam [31:0] CSR_MSTATUS_MPP_BIT_LOW = 11; + localparam [31:0] CSR_MSTATUS_MPP_BIT_HIGH = 12; + localparam [31:0] CSR_MSTATUS_MPRV_BIT = 17; + localparam [31:0] CSR_MSTATUS_TW_BIT = 21; + localparam [1:0] CSR_MISA_MXL = 2'd1; + localparam [31:0] CSR_MSIX_BIT = 3; + localparam [31:0] CSR_MTIX_BIT = 7; + localparam [31:0] CSR_MEIX_BIT = 11; + localparam [31:0] CSR_MFIX_BIT_LOW = 16; + localparam [31:0] CSR_MFIX_BIT_HIGH = 30; + wire [31:0] rf_wdata_wb_mux [0:1]; + wire [1:0] rf_wdata_wb_mux_we; + generate + if (WritebackStage) begin : g_writeback_stage + reg [31:0] rf_wdata_wb_q; + reg rf_we_wb_q; + reg [4:0] rf_waddr_wb_q; + wire wb_done; + reg wb_valid_q; + reg [31:0] wb_pc_q; + reg [1:0] wb_instr_type_q; + wire wb_valid_d; + assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done); + assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i; + always @(posedge clk_i or negedge rst_ni) + if (~rst_ni) + wb_valid_q <= 1'b0; + else + wb_valid_q <= wb_valid_d; + always @(posedge clk_i) + if (en_wb_i) begin + rf_we_wb_q <= rf_we_id_i; + rf_waddr_wb_q <= rf_waddr_id_i; + rf_wdata_wb_q <= rf_wdata_id_i; + wb_instr_type_q <= instr_type_wb_i; + wb_pc_q <= pc_id_i; + end + assign rf_waddr_wb_o = rf_waddr_wb_q; + assign rf_wdata_wb_mux[0] = rf_wdata_wb_q; + assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q; + assign ready_wb_o = ~wb_valid_q | wb_done; + assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == WB_INSTR_LOAD)); + assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_LOAD); + assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == WB_INSTR_STORE); + assign pc_wb_o = wb_pc_q; + assign instr_done_wb_o = wb_valid_q & wb_done; + assign rf_wdata_fwd_wb_o = rf_wdata_wb_q; + end + else begin : g_bypass_wb + assign rf_waddr_wb_o = rf_waddr_id_i; + assign rf_wdata_wb_mux[0] = rf_wdata_id_i; + assign rf_wdata_wb_mux_we[0] = rf_we_id_i; + assign ready_wb_o = 1'b1; + wire unused_clk; + wire unused_rst; + wire unused_en_wb; + wire [1:0] unused_instr_type_wb; + wire [31:0] unused_pc_id; + wire unused_lsu_resp_valid; + assign unused_clk = clk_i; + assign unused_rst = rst_ni; + assign unused_en_wb = en_wb_i; + assign unused_instr_type_wb = instr_type_wb_i; + assign unused_pc_id = pc_id_i; + assign unused_lsu_resp_valid = lsu_resp_valid_i; + assign outstanding_load_wb_o = 1'b0; + assign outstanding_store_wb_o = 1'b0; + assign pc_wb_o = {32 {1'sb0}}; + assign rf_write_wb_o = 1'b0; + assign rf_wdata_fwd_wb_o = 32'b00000000000000000000000000000000; + assign instr_done_wb_o = 1'b0; + end + endgenerate + assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i; + assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i; + assign rf_wdata_wb_o = (rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1]); + assign rf_we_wb_o = |rf_wdata_wb_mux_we; +endmodule +module tlul_gpio ( + clk_i, + rst_ni, + tl_i, + tl_o, + cio_gpio_i, + cio_gpio_o, + cio_gpio_en_o, + intr_gpio_o +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + input [31:0] cio_gpio_i; + output wire [31:0] cio_gpio_o; + output wire [31:0] cio_gpio_en_o; + output wire [31:0] intr_gpio_o; + localparam [5:0] GPIO_INTR_STATE_OFFSET = 6'h00; + localparam [5:0] GPIO_INTR_ENABLE_OFFSET = 6'h04; + localparam [5:0] GPIO_INTR_TEST_OFFSET = 6'h08; + localparam [5:0] GPIO_DATA_IN_OFFSET = 6'h0c; + localparam [5:0] GPIO_DIRECT_OUT_OFFSET = 6'h10; + localparam [5:0] GPIO_MASKED_OUT_LOWER_OFFSET = 6'h14; + localparam [5:0] GPIO_MASKED_OUT_UPPER_OFFSET = 6'h18; + localparam [5:0] GPIO_DIRECT_OE_OFFSET = 6'h1c; + localparam [5:0] GPIO_MASKED_OE_LOWER_OFFSET = 6'h20; + localparam [5:0] GPIO_MASKED_OE_UPPER_OFFSET = 6'h24; + localparam [5:0] GPIO_INTR_CTRL_EN_RISING_OFFSET = 6'h28; + localparam [5:0] GPIO_INTR_CTRL_EN_FALLING_OFFSET = 6'h2c; + localparam [5:0] GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET = 6'h30; + localparam [5:0] GPIO_INTR_CTRL_EN_LVLLOW_OFFSET = 6'h34; + localparam [5:0] GPIO_CTRL_EN_INPUT_FILTER_OFFSET = 6'h38; + localparam signed [31:0] GPIO_INTR_STATE = 0; + localparam signed [31:0] GPIO_INTR_ENABLE = 1; + localparam signed [31:0] GPIO_INTR_TEST = 2; + localparam signed [31:0] GPIO_DATA_IN = 3; + localparam signed [31:0] GPIO_DIRECT_OUT = 4; + localparam signed [31:0] GPIO_MASKED_OUT_LOWER = 5; + localparam signed [31:0] GPIO_MASKED_OUT_UPPER = 6; + localparam signed [31:0] GPIO_DIRECT_OE = 7; + localparam signed [31:0] GPIO_MASKED_OE_LOWER = 8; + localparam signed [31:0] GPIO_MASKED_OE_UPPER = 9; + localparam signed [31:0] GPIO_INTR_CTRL_EN_RISING = 10; + localparam signed [31:0] GPIO_INTR_CTRL_EN_FALLING = 11; + localparam signed [31:0] GPIO_INTR_CTRL_EN_LVLHIGH = 12; + localparam signed [31:0] GPIO_INTR_CTRL_EN_LVLLOW = 13; + localparam signed [31:0] GPIO_CTRL_EN_INPUT_FILTER = 14; + localparam [59:0] GPIO_PERMIT = {4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111}; + wire [458:0] reg2hw; + wire [257:0] hw2reg; + reg [31:0] cio_gpio_q; + reg [31:0] cio_gpio_en_q; + wire [31:0] data_in_d; + generate + genvar i; + for (i = 0; i < 32; i = i + 1) begin : gen_filter + prim_filter_ctr #(.Cycles(16)) filter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .enable_i(reg2hw[i]), + .filter_i(cio_gpio_i[i]), + .filter_o(data_in_d[i]) + ); + end + endgenerate + assign hw2reg[192] = 1'b1; + assign hw2reg[224-:32] = data_in_d; + assign cio_gpio_o = cio_gpio_q; + assign cio_gpio_en_o = cio_gpio_en_q; + assign hw2reg[191-:32] = cio_gpio_q; + assign hw2reg[127-:16] = cio_gpio_q[31:16]; + assign hw2reg[111-:16] = 16'h0000; + assign hw2reg[159-:16] = cio_gpio_q[15:0]; + assign hw2reg[143-:16] = 16'h0000; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + cio_gpio_q <= {32 {1'sb0}}; + else if (reg2hw[329]) + cio_gpio_q <= reg2hw[361-:32]; + else if (reg2hw[278]) + cio_gpio_q[31:16] <= (reg2hw[277-:16] & reg2hw[294-:16]) | (~reg2hw[277-:16] & cio_gpio_q[31:16]); + else if (reg2hw[312]) + cio_gpio_q[15:0] <= (reg2hw[311-:16] & reg2hw[328-:16]) | (~reg2hw[311-:16] & cio_gpio_q[15:0]); + assign hw2reg[95-:32] = cio_gpio_en_q; + assign hw2reg[31-:16] = cio_gpio_en_q[31:16]; + assign hw2reg[15-:16] = 16'h0000; + assign hw2reg[63-:16] = cio_gpio_en_q[15:0]; + assign hw2reg[47-:16] = 16'h0000; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + cio_gpio_en_q <= {32 {1'sb0}}; + else if (reg2hw[228]) + cio_gpio_en_q <= reg2hw[260-:32]; + else if (reg2hw[177]) + cio_gpio_en_q[31:16] <= (reg2hw[176-:16] & reg2hw[193-:16]) | (~reg2hw[176-:16] & cio_gpio_en_q[31:16]); + else if (reg2hw[211]) + cio_gpio_en_q[15:0] <= (reg2hw[210-:16] & reg2hw[227-:16]) | (~reg2hw[210-:16] & cio_gpio_en_q[15:0]); + reg [31:0] data_in_q; + always @(posedge clk_i) data_in_q <= data_in_d; + wire [31:0] event_intr_rise; + wire [31:0] event_intr_fall; + wire [31:0] event_intr_actlow; + wire [31:0] event_intr_acthigh; + wire [31:0] event_intr_combined; + prim_intr_hw #(.Width(32)) intr_hw( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_intr_combined), + .reg2hw_intr_enable_q_i(reg2hw[426-:32]), + .reg2hw_intr_test_q_i(reg2hw[394-:32]), + .reg2hw_intr_test_qe_i(reg2hw[362]), + .reg2hw_intr_state_q_i(reg2hw[458-:32]), + .hw2reg_intr_state_de_o(hw2reg[225]), + .hw2reg_intr_state_d_o(hw2reg[257-:32]), + .intr_o(intr_gpio_o) + ); + assign event_intr_rise = (~data_in_q & data_in_d) & reg2hw[159-:32]; + assign event_intr_fall = (data_in_q & ~data_in_d) & reg2hw[127-:32]; + assign event_intr_acthigh = data_in_d & reg2hw[95-:32]; + assign event_intr_actlow = ~data_in_d & reg2hw[63-:32]; + assign event_intr_combined = ((event_intr_rise | event_intr_fall) | event_intr_actlow) | event_intr_acthigh; + gpio_reg_top u_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_i), + .tl_o(tl_o), + .reg2hw(reg2hw), + .hw2reg(hw2reg), + .devmode_i(1'b1) + ); +endmodule +module gpio_reg_top ( + clk_i, + rst_ni, + tl_i, + tl_o, + reg2hw, + hw2reg, + devmode_i +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire [458:0] reg2hw; + input wire [257:0] hw2reg; + input devmode_i; + localparam [5:0] GPIO_INTR_STATE_OFFSET = 6'h00; + localparam [5:0] GPIO_INTR_ENABLE_OFFSET = 6'h04; + localparam [5:0] GPIO_INTR_TEST_OFFSET = 6'h08; + localparam [5:0] GPIO_DATA_IN_OFFSET = 6'h0c; + localparam [5:0] GPIO_DIRECT_OUT_OFFSET = 6'h10; + localparam [5:0] GPIO_MASKED_OUT_LOWER_OFFSET = 6'h14; + localparam [5:0] GPIO_MASKED_OUT_UPPER_OFFSET = 6'h18; + localparam [5:0] GPIO_DIRECT_OE_OFFSET = 6'h1c; + localparam [5:0] GPIO_MASKED_OE_LOWER_OFFSET = 6'h20; + localparam [5:0] GPIO_MASKED_OE_UPPER_OFFSET = 6'h24; + localparam [5:0] GPIO_INTR_CTRL_EN_RISING_OFFSET = 6'h28; + localparam [5:0] GPIO_INTR_CTRL_EN_FALLING_OFFSET = 6'h2c; + localparam [5:0] GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET = 6'h30; + localparam [5:0] GPIO_INTR_CTRL_EN_LVLLOW_OFFSET = 6'h34; + localparam [5:0] GPIO_CTRL_EN_INPUT_FILTER_OFFSET = 6'h38; + localparam signed [31:0] GPIO_INTR_STATE = 0; + localparam signed [31:0] GPIO_INTR_ENABLE = 1; + localparam signed [31:0] GPIO_INTR_TEST = 2; + localparam signed [31:0] GPIO_DATA_IN = 3; + localparam signed [31:0] GPIO_DIRECT_OUT = 4; + localparam signed [31:0] GPIO_MASKED_OUT_LOWER = 5; + localparam signed [31:0] GPIO_MASKED_OUT_UPPER = 6; + localparam signed [31:0] GPIO_DIRECT_OE = 7; + localparam signed [31:0] GPIO_MASKED_OE_LOWER = 8; + localparam signed [31:0] GPIO_MASKED_OE_UPPER = 9; + localparam signed [31:0] GPIO_INTR_CTRL_EN_RISING = 10; + localparam signed [31:0] GPIO_INTR_CTRL_EN_FALLING = 11; + localparam signed [31:0] GPIO_INTR_CTRL_EN_LVLHIGH = 12; + localparam signed [31:0] GPIO_INTR_CTRL_EN_LVLLOW = 13; + localparam signed [31:0] GPIO_CTRL_EN_INPUT_FILTER = 14; + localparam [59:0] GPIO_PERMIT = {4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b1111}; + localparam signed [31:0] AW = 6; + localparam signed [31:0] DW = 32; + localparam signed [31:0] DBW = DW / 8; + wire reg_we; + wire reg_re; + wire [AW - 1:0] reg_addr; + wire [DW - 1:0] reg_wdata; + wire [DBW - 1:0] reg_be; + wire [DW - 1:0] reg_rdata; + wire reg_error; + wire addrmiss; + reg wr_err; + reg [DW - 1:0] reg_rdata_next; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_reg_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_reg_d2h; + assign tl_reg_h2d = tl_i; + assign tl_o = tl_reg_d2h; + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW) + ) u_reg_if( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_reg_h2d), + .tl_o(tl_reg_d2h), + .we_o(reg_we), + .re_o(reg_re), + .addr_o(reg_addr), + .wdata_o(reg_wdata), + .be_o(reg_be), + .rdata_i(reg_rdata), + .error_i(reg_error) + ); + assign reg_rdata = reg_rdata_next; + assign reg_error = (devmode_i & addrmiss) | wr_err; + wire [31:0] intr_state_qs; + wire [31:0] intr_state_wd; + wire intr_state_we; + wire [31:0] intr_enable_qs; + wire [31:0] intr_enable_wd; + wire intr_enable_we; + wire [31:0] intr_test_wd; + wire intr_test_we; + wire [31:0] data_in_qs; + wire [31:0] direct_out_qs; + wire [31:0] direct_out_wd; + wire direct_out_we; + wire direct_out_re; + wire [15:0] masked_out_lower_data_qs; + wire [15:0] masked_out_lower_data_wd; + wire masked_out_lower_data_we; + wire masked_out_lower_data_re; + wire [15:0] masked_out_lower_mask_wd; + wire masked_out_lower_mask_we; + wire [15:0] masked_out_upper_data_qs; + wire [15:0] masked_out_upper_data_wd; + wire masked_out_upper_data_we; + wire masked_out_upper_data_re; + wire [15:0] masked_out_upper_mask_wd; + wire masked_out_upper_mask_we; + wire [31:0] direct_oe_qs; + wire [31:0] direct_oe_wd; + wire direct_oe_we; + wire direct_oe_re; + wire [15:0] masked_oe_lower_data_qs; + wire [15:0] masked_oe_lower_data_wd; + wire masked_oe_lower_data_we; + wire masked_oe_lower_data_re; + wire [15:0] masked_oe_lower_mask_qs; + wire [15:0] masked_oe_lower_mask_wd; + wire masked_oe_lower_mask_we; + wire masked_oe_lower_mask_re; + wire [15:0] masked_oe_upper_data_qs; + wire [15:0] masked_oe_upper_data_wd; + wire masked_oe_upper_data_we; + wire masked_oe_upper_data_re; + wire [15:0] masked_oe_upper_mask_qs; + wire [15:0] masked_oe_upper_mask_wd; + wire masked_oe_upper_mask_we; + wire masked_oe_upper_mask_re; + wire [31:0] intr_ctrl_en_rising_qs; + wire [31:0] intr_ctrl_en_rising_wd; + wire intr_ctrl_en_rising_we; + wire [31:0] intr_ctrl_en_falling_qs; + wire [31:0] intr_ctrl_en_falling_wd; + wire intr_ctrl_en_falling_we; + wire [31:0] intr_ctrl_en_lvlhigh_qs; + wire [31:0] intr_ctrl_en_lvlhigh_wd; + wire intr_ctrl_en_lvlhigh_we; + wire [31:0] intr_ctrl_en_lvllow_qs; + wire [31:0] intr_ctrl_en_lvllow_wd; + wire intr_ctrl_en_lvllow_we; + wire [31:0] ctrl_en_input_filter_qs; + wire [31:0] ctrl_en_input_filter_wd; + wire ctrl_en_input_filter_we; + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(32'h00000000) + ) u_intr_state( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_we), + .wd(intr_state_wd), + .de(hw2reg[225]), + .d(hw2reg[257-:32]), + .qe(), + .q(reg2hw[458-:32]), + .qs(intr_state_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_intr_enable( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_we), + .wd(intr_enable_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(), + .q(reg2hw[426-:32]), + .qs(intr_enable_qs) + ); + prim_subreg_ext #(.DW(32)) u_intr_test( + .re(1'b0), + .we(intr_test_we), + .wd(intr_test_wd), + .d({32 {1'sb0}}), + .qre(), + .qe(reg2hw[362]), + .q(reg2hw[394-:32]), + .qs() + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(32'h00000000) + ) u_data_in( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd({32 {1'sb0}}), + .de(hw2reg[192]), + .d(hw2reg[224-:32]), + .qe(), + .q(), + .qs(data_in_qs) + ); + prim_subreg_ext #(.DW(32)) u_direct_out( + .re(direct_out_re), + .we(direct_out_we), + .wd(direct_out_wd), + .d(hw2reg[191-:32]), + .qre(), + .qe(reg2hw[329]), + .q(reg2hw[361-:32]), + .qs(direct_out_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_out_lower_data( + .re(masked_out_lower_data_re), + .we(masked_out_lower_data_we), + .wd(masked_out_lower_data_wd), + .d(hw2reg[159-:16]), + .qre(), + .qe(reg2hw[312]), + .q(reg2hw[328-:16]), + .qs(masked_out_lower_data_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_out_lower_mask( + .re(1'b0), + .we(masked_out_lower_mask_we), + .wd(masked_out_lower_mask_wd), + .d(hw2reg[143-:16]), + .qre(), + .qe(reg2hw[295]), + .q(reg2hw[311-:16]), + .qs() + ); + prim_subreg_ext #(.DW(16)) u_masked_out_upper_data( + .re(masked_out_upper_data_re), + .we(masked_out_upper_data_we), + .wd(masked_out_upper_data_wd), + .d(hw2reg[127-:16]), + .qre(), + .qe(reg2hw[278]), + .q(reg2hw[294-:16]), + .qs(masked_out_upper_data_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_out_upper_mask( + .re(1'b0), + .we(masked_out_upper_mask_we), + .wd(masked_out_upper_mask_wd), + .d(hw2reg[111-:16]), + .qre(), + .qe(reg2hw[261]), + .q(reg2hw[277-:16]), + .qs() + ); + prim_subreg_ext #(.DW(32)) u_direct_oe( + .re(direct_oe_re), + .we(direct_oe_we), + .wd(direct_oe_wd), + .d(hw2reg[95-:32]), + .qre(), + .qe(reg2hw[228]), + .q(reg2hw[260-:32]), + .qs(direct_oe_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_oe_lower_data( + .re(masked_oe_lower_data_re), + .we(masked_oe_lower_data_we), + .wd(masked_oe_lower_data_wd), + .d(hw2reg[63-:16]), + .qre(), + .qe(reg2hw[211]), + .q(reg2hw[227-:16]), + .qs(masked_oe_lower_data_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_oe_lower_mask( + .re(masked_oe_lower_mask_re), + .we(masked_oe_lower_mask_we), + .wd(masked_oe_lower_mask_wd), + .d(hw2reg[47-:16]), + .qre(), + .qe(reg2hw[194]), + .q(reg2hw[210-:16]), + .qs(masked_oe_lower_mask_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_oe_upper_data( + .re(masked_oe_upper_data_re), + .we(masked_oe_upper_data_we), + .wd(masked_oe_upper_data_wd), + .d(hw2reg[31-:16]), + .qre(), + .qe(reg2hw[177]), + .q(reg2hw[193-:16]), + .qs(masked_oe_upper_data_qs) + ); + prim_subreg_ext #(.DW(16)) u_masked_oe_upper_mask( + .re(masked_oe_upper_mask_re), + .we(masked_oe_upper_mask_we), + .wd(masked_oe_upper_mask_wd), + .d(hw2reg[15-:16]), + .qre(), + .qe(reg2hw[160]), + .q(reg2hw[176-:16]), + .qs(masked_oe_upper_mask_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_intr_ctrl_en_rising( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_ctrl_en_rising_we), + .wd(intr_ctrl_en_rising_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(), + .q(reg2hw[159-:32]), + .qs(intr_ctrl_en_rising_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_intr_ctrl_en_falling( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_ctrl_en_falling_we), + .wd(intr_ctrl_en_falling_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(), + .q(reg2hw[127-:32]), + .qs(intr_ctrl_en_falling_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_intr_ctrl_en_lvlhigh( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_ctrl_en_lvlhigh_we), + .wd(intr_ctrl_en_lvlhigh_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(), + .q(reg2hw[95-:32]), + .qs(intr_ctrl_en_lvlhigh_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_intr_ctrl_en_lvllow( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_ctrl_en_lvllow_we), + .wd(intr_ctrl_en_lvllow_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(), + .q(reg2hw[63-:32]), + .qs(intr_ctrl_en_lvllow_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_ctrl_en_input_filter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_en_input_filter_we), + .wd(ctrl_en_input_filter_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(), + .q(reg2hw[31-:32]), + .qs(ctrl_en_input_filter_qs) + ); + reg [14:0] addr_hit; + always @(*) begin + addr_hit = {15 {1'sb0}}; + addr_hit[0] = reg_addr == GPIO_INTR_STATE_OFFSET; + addr_hit[1] = reg_addr == GPIO_INTR_ENABLE_OFFSET; + addr_hit[2] = reg_addr == GPIO_INTR_TEST_OFFSET; + addr_hit[3] = reg_addr == GPIO_DATA_IN_OFFSET; + addr_hit[4] = reg_addr == GPIO_DIRECT_OUT_OFFSET; + addr_hit[5] = reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET; + addr_hit[6] = reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET; + addr_hit[7] = reg_addr == GPIO_DIRECT_OE_OFFSET; + addr_hit[8] = reg_addr == GPIO_MASKED_OE_LOWER_OFFSET; + addr_hit[9] = reg_addr == GPIO_MASKED_OE_UPPER_OFFSET; + addr_hit[10] = reg_addr == GPIO_INTR_CTRL_EN_RISING_OFFSET; + addr_hit[11] = reg_addr == GPIO_INTR_CTRL_EN_FALLING_OFFSET; + addr_hit[12] = reg_addr == GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET; + addr_hit[13] = reg_addr == GPIO_INTR_CTRL_EN_LVLLOW_OFFSET; + addr_hit[14] = reg_addr == GPIO_CTRL_EN_INPUT_FILTER_OFFSET; + end + assign addrmiss = (reg_re || reg_we ? ~|addr_hit : 1'b0); + always @(*) begin + wr_err = 1'b0; + if ((addr_hit[0] && reg_we) && (GPIO_PERMIT[56+:4] != (GPIO_PERMIT[56+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[1] && reg_we) && (GPIO_PERMIT[52+:4] != (GPIO_PERMIT[52+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[2] && reg_we) && (GPIO_PERMIT[48+:4] != (GPIO_PERMIT[48+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[3] && reg_we) && (GPIO_PERMIT[44+:4] != (GPIO_PERMIT[44+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[4] && reg_we) && (GPIO_PERMIT[40+:4] != (GPIO_PERMIT[40+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[5] && reg_we) && (GPIO_PERMIT[36+:4] != (GPIO_PERMIT[36+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[6] && reg_we) && (GPIO_PERMIT[32+:4] != (GPIO_PERMIT[32+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[7] && reg_we) && (GPIO_PERMIT[28+:4] != (GPIO_PERMIT[28+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[8] && reg_we) && (GPIO_PERMIT[24+:4] != (GPIO_PERMIT[24+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[9] && reg_we) && (GPIO_PERMIT[20+:4] != (GPIO_PERMIT[20+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[10] && reg_we) && (GPIO_PERMIT[16+:4] != (GPIO_PERMIT[16+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[11] && reg_we) && (GPIO_PERMIT[12+:4] != (GPIO_PERMIT[12+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[12] && reg_we) && (GPIO_PERMIT[8+:4] != (GPIO_PERMIT[8+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[13] && reg_we) && (GPIO_PERMIT[4+:4] != (GPIO_PERMIT[4+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[14] && reg_we) && (GPIO_PERMIT[0+:4] != (GPIO_PERMIT[0+:4] & reg_be))) + wr_err = 1'b1; + end + assign intr_state_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_wd = reg_wdata[31:0]; + assign intr_enable_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_wd = reg_wdata[31:0]; + assign intr_test_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_wd = reg_wdata[31:0]; + assign direct_out_we = (addr_hit[4] & reg_we) & ~wr_err; + assign direct_out_wd = reg_wdata[31:0]; + assign direct_out_re = addr_hit[4] && reg_re; + assign masked_out_lower_data_we = (addr_hit[5] & reg_we) & ~wr_err; + assign masked_out_lower_data_wd = reg_wdata[15:0]; + assign masked_out_lower_data_re = addr_hit[5] && reg_re; + assign masked_out_lower_mask_we = (addr_hit[5] & reg_we) & ~wr_err; + assign masked_out_lower_mask_wd = reg_wdata[31:16]; + assign masked_out_upper_data_we = (addr_hit[6] & reg_we) & ~wr_err; + assign masked_out_upper_data_wd = reg_wdata[15:0]; + assign masked_out_upper_data_re = addr_hit[6] && reg_re; + assign masked_out_upper_mask_we = (addr_hit[6] & reg_we) & ~wr_err; + assign masked_out_upper_mask_wd = reg_wdata[31:16]; + assign direct_oe_we = (addr_hit[7] & reg_we) & ~wr_err; + assign direct_oe_wd = reg_wdata[31:0]; + assign direct_oe_re = addr_hit[7] && reg_re; + assign masked_oe_lower_data_we = (addr_hit[8] & reg_we) & ~wr_err; + assign masked_oe_lower_data_wd = reg_wdata[15:0]; + assign masked_oe_lower_data_re = addr_hit[8] && reg_re; + assign masked_oe_lower_mask_we = (addr_hit[8] & reg_we) & ~wr_err; + assign masked_oe_lower_mask_wd = reg_wdata[31:16]; + assign masked_oe_lower_mask_re = addr_hit[8] && reg_re; + assign masked_oe_upper_data_we = (addr_hit[9] & reg_we) & ~wr_err; + assign masked_oe_upper_data_wd = reg_wdata[15:0]; + assign masked_oe_upper_data_re = addr_hit[9] && reg_re; + assign masked_oe_upper_mask_we = (addr_hit[9] & reg_we) & ~wr_err; + assign masked_oe_upper_mask_wd = reg_wdata[31:16]; + assign masked_oe_upper_mask_re = addr_hit[9] && reg_re; + assign intr_ctrl_en_rising_we = (addr_hit[10] & reg_we) & ~wr_err; + assign intr_ctrl_en_rising_wd = reg_wdata[31:0]; + assign intr_ctrl_en_falling_we = (addr_hit[11] & reg_we) & ~wr_err; + assign intr_ctrl_en_falling_wd = reg_wdata[31:0]; + assign intr_ctrl_en_lvlhigh_we = (addr_hit[12] & reg_we) & ~wr_err; + assign intr_ctrl_en_lvlhigh_wd = reg_wdata[31:0]; + assign intr_ctrl_en_lvllow_we = (addr_hit[13] & reg_we) & ~wr_err; + assign intr_ctrl_en_lvllow_wd = reg_wdata[31:0]; + assign ctrl_en_input_filter_we = (addr_hit[14] & reg_we) & ~wr_err; + assign ctrl_en_input_filter_wd = reg_wdata[31:0]; + always @(*) begin + reg_rdata_next = {DW {1'sb0}}; + case (1'b1) + addr_hit[0]: reg_rdata_next[31:0] = intr_state_qs; + addr_hit[1]: reg_rdata_next[31:0] = intr_enable_qs; + addr_hit[2]: reg_rdata_next[31:0] = {32 {1'sb0}}; + addr_hit[3]: reg_rdata_next[31:0] = data_in_qs; + addr_hit[4]: reg_rdata_next[31:0] = direct_out_qs; + addr_hit[5]: begin + reg_rdata_next[15:0] = masked_out_lower_data_qs; + reg_rdata_next[31:16] = {16 {1'sb0}}; + end + addr_hit[6]: begin + reg_rdata_next[15:0] = masked_out_upper_data_qs; + reg_rdata_next[31:16] = {16 {1'sb0}}; + end + addr_hit[7]: reg_rdata_next[31:0] = direct_oe_qs; + addr_hit[8]: begin + reg_rdata_next[15:0] = masked_oe_lower_data_qs; + reg_rdata_next[31:16] = masked_oe_lower_mask_qs; + end + addr_hit[9]: begin + reg_rdata_next[15:0] = masked_oe_upper_data_qs; + reg_rdata_next[31:16] = masked_oe_upper_mask_qs; + end + addr_hit[10]: reg_rdata_next[31:0] = intr_ctrl_en_rising_qs; + addr_hit[11]: reg_rdata_next[31:0] = intr_ctrl_en_falling_qs; + addr_hit[12]: reg_rdata_next[31:0] = intr_ctrl_en_lvlhigh_qs; + addr_hit[13]: reg_rdata_next[31:0] = intr_ctrl_en_lvllow_qs; + addr_hit[14]: reg_rdata_next[31:0] = ctrl_en_input_filter_qs; + default: reg_rdata_next = {DW {1'sb1}}; + endcase + end +endmodule +module prim_arbiter_ppc ( + clk_i, + rst_ni, + req_i, + data_i, + gnt_o, + idx_o, + valid_o, + data_o, + ready_i +); + parameter [31:0] N = 8; + parameter [31:0] DW = 32; + parameter [0:0] EnDataPort = 1; + parameter [0:0] EnReqStabA = 1; + localparam signed [31:0] IdxW = $clog2(N); + input clk_i; + input rst_ni; + input [N - 1:0] req_i; + input [(0 >= (N - 1) ? ((2 - N) * DW) + (((N - 1) * DW) - 1) : (N * DW) - 1):(0 >= (N - 1) ? (N - 1) * DW : 0)] data_i; + output wire [N - 1:0] gnt_o; + output reg [IdxW - 1:0] idx_o; + output wire valid_o; + output reg [DW - 1:0] data_o; + input ready_i; + generate + if (N == 1) begin : gen_degenerate_case + assign valid_o = req_i[0]; + always @(*) data_o = data_i[(0 >= (N - 1) ? 0 : N - 1) * DW+:DW]; + assign gnt_o[0] = valid_o & ready_i; + always @(*) idx_o = {IdxW {1'sb0}}; + end + else begin : gen_normal_case + wire [N - 1:0] masked_req; + reg [N - 1:0] ppc_out; + wire [N - 1:0] arb_req; + reg [N - 1:0] mask; + wire [N - 1:0] mask_next; + wire [N - 1:0] winner; + assign masked_req = mask & req_i; + assign arb_req = (|masked_req ? masked_req : req_i); + always @(*) begin + ppc_out[0] = arb_req[0]; + begin : sv2v_autoblock_71 + reg signed [31:0] i; + for (i = 1; i < N; i = i + 1) + ppc_out[i] = ppc_out[i - 1] | arb_req[i]; + end + end + assign winner = ppc_out ^ {ppc_out[N - 2:0], 1'b0}; + assign gnt_o = (ready_i ? winner : {N {1'sb0}}); + assign valid_o = |req_i; + assign mask_next = {ppc_out[N - 2:0], 1'b0}; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mask <= {N {1'sb0}}; + else if (valid_o && ready_i) + mask <= mask_next; + else if (valid_o && !ready_i) + mask <= ppc_out; + if (EnDataPort == 1) begin : gen_datapath + always @(*) begin + data_o = {DW {1'sb0}}; + begin : sv2v_autoblock_72 + reg signed [31:0] i; + for (i = 0; i < N; i = i + 1) + if (winner[i]) + data_o = data_i[(0 >= (N - 1) ? i : (N - 1) - i) * DW+:DW]; + end + end + end + else begin : gen_nodatapath + always @(*) data_o = {DW {1'sb1}}; + end + always @(*) begin + idx_o = {IdxW {1'sb0}}; + begin : sv2v_autoblock_73 + reg signed [31:0] i; + for (i = 0; i < N; i = i + 1) + if (winner[i]) + idx_o = i[IdxW - 1:0]; + end + end + end + endgenerate +endmodule +module prim_clock_gating ( + clk_i, + en_i, + test_en_i, + clk_o +); + input clk_i; + input en_i; + input test_en_i; + output wire clk_o; + localparam integer prim_pkg_ImplGeneric = 0; + parameter integer Impl = prim_pkg_ImplGeneric; + generate + if (Impl == prim_pkg_ImplGeneric) begin : gen_generic + prim_generic_clock_gating u_impl_generic( + .clk_i(clk_i), + .en_i(en_i), + .test_en_i(test_en_i), + .clk_o(clk_o) + ); + end + endgenerate +endmodule +module prim_diff_decode ( + clk_i, + rst_ni, + diff_pi, + diff_ni, + level_o, + rise_o, + fall_o, + event_o, + sigint_o +); + parameter [0:0] AsyncOn = 1'b0; + input clk_i; + input rst_ni; + input diff_pi; + input diff_ni; + output wire level_o; + output reg rise_o; + output reg fall_o; + output wire event_o; + output reg sigint_o; + reg level_d; + reg level_q; + localparam [1:0] IsSkewed = 1; + localparam [1:0] IsStd = 0; + localparam [1:0] SigInt = 2; + generate + if (AsyncOn) begin : gen_async + reg [1:0] state_d; + reg [1:0] state_q; + wire diff_p_edge; + wire diff_n_edge; + wire diff_check_ok; + wire level; + reg diff_pq; + reg diff_nq; + wire diff_pd; + wire diff_nd; + prim_generic_flop_2sync #( + .Width(1), + .ResetValue(1'sb0) + ) i_sync_p( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(diff_pi), + .q_o(diff_pd) + ); + prim_generic_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) i_sync_n( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(diff_ni), + .q_o(diff_nd) + ); + assign diff_p_edge = diff_pq ^ diff_pd; + assign diff_n_edge = diff_nq ^ diff_nd; + assign diff_check_ok = diff_pd ^ diff_nd; + assign level = diff_pd; + assign level_o = level_d; + assign event_o = rise_o | fall_o; + always @(*) begin : p_diff_fsm + state_d = state_q; + level_d = level_q; + rise_o = 1'b0; + fall_o = 1'b0; + sigint_o = 1'b0; + case (state_q) + IsStd: + if (diff_check_ok) begin + level_d = level; + if (diff_p_edge && diff_n_edge) + if (level) + rise_o = 1'b1; + else + fall_o = 1'b1; + end + else if (diff_p_edge || diff_n_edge) + state_d = IsSkewed; + else begin + state_d = SigInt; + sigint_o = 1'b1; + end + IsSkewed: + if (diff_check_ok) begin + state_d = IsStd; + level_d = level; + if (level) + rise_o = 1'b1; + else + fall_o = 1'b1; + end + else begin + state_d = SigInt; + sigint_o = 1'b1; + end + SigInt: begin + sigint_o = 1'b1; + if (diff_check_ok) begin + state_d = IsStd; + sigint_o = 1'b0; + end + end + default: + ; + endcase + end + always @(posedge clk_i or negedge rst_ni) begin : p_sync_reg + if (!rst_ni) begin + state_q <= IsStd; + diff_pq <= 1'b0; + diff_nq <= 1'b1; + level_q <= 1'b0; + end + else begin + state_q <= state_d; + diff_pq <= diff_pd; + diff_nq <= diff_nd; + level_q <= level_d; + end + end + end + else begin : gen_no_async + reg diff_pq; + wire diff_pd; + assign diff_pd = diff_pi; + always @(*) sigint_o = ~(diff_pi ^ diff_ni); + assign level_o = (sigint_o ? level_q : diff_pi); + always @(*) level_d = level_o; + always @(*) rise_o = (~diff_pq & diff_pi) & ~sigint_o; + always @(*) fall_o = (diff_pq & ~diff_pi) & ~sigint_o; + assign event_o = rise_o | fall_o; + always @(posedge clk_i or negedge rst_ni) begin : p_edge_reg + if (!rst_ni) begin + diff_pq <= 1'b0; + level_q <= 1'b0; + end + else begin + diff_pq <= diff_pd; + level_q <= level_d; + end + end + end + endgenerate +endmodule +module prim_esc_receiver ( + clk_i, + rst_ni, + esc_en_o, + esc_rx_o, + esc_tx_i +); + input clk_i; + input rst_ni; + output reg esc_en_o; + output wire [1:0] esc_rx_o; + input wire [1:0] esc_tx_i; + wire esc_level; + wire sigint_detected; + prim_diff_decode #(.AsyncOn(1'b0)) i_decode_esc( + .clk_i(clk_i), + .rst_ni(rst_ni), + .diff_pi(esc_tx_i[1]), + .diff_ni(esc_tx_i[0]), + .level_o(esc_level), + .rise_o(), + .fall_o(), + .event_o(), + .sigint_o(sigint_detected) + ); + reg [2:0] state_d; + reg [2:0] state_q; + reg resp_pd; + reg resp_pq; + reg resp_nd; + reg resp_nq; + assign esc_rx_o[1] = resp_pq; + assign esc_rx_o[0] = resp_nq; + localparam [2:0] Check = 1; + localparam [2:0] EscResp = 3; + localparam [2:0] Idle = 0; + localparam [2:0] PingResp = 2; + localparam [2:0] SigInt = 4; + always @(*) begin : p_fsm + state_d = state_q; + resp_pd = 1'b0; + resp_nd = 1'b1; + esc_en_o = 1'b0; + case (state_q) + Idle: + if (esc_level) begin + state_d = Check; + resp_pd = 1'b1; + resp_nd = 1'b0; + end + Check: begin + state_d = PingResp; + if (esc_level) begin + state_d = EscResp; + esc_en_o = 1'b1; + end + end + PingResp: begin + state_d = Idle; + resp_pd = 1'b1; + resp_nd = 1'b0; + if (esc_level) begin + state_d = EscResp; + esc_en_o = 1'b1; + end + end + EscResp: begin + state_d = Idle; + if (esc_level) begin + state_d = EscResp; + resp_pd = ~resp_pq; + resp_nd = resp_pq; + esc_en_o = 1'b1; + end + end + SigInt: begin + state_d = Idle; + if (sigint_detected) begin + state_d = SigInt; + resp_pd = ~resp_pq; + resp_nd = ~resp_pq; + end + end + default: state_d = Idle; + endcase + if (sigint_detected && (state_q != SigInt)) begin + state_d = SigInt; + resp_pd = 1'b0; + resp_nd = 1'b0; + end + end + always @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + state_q <= Idle; + resp_pq <= 1'b0; + resp_nq <= 1'b1; + end + else begin + state_q <= state_d; + resp_pq <= resp_pd; + resp_nq <= resp_nd; + end + end +endmodule +module prim_fifo_async ( + clk_wr_i, + rst_wr_ni, + wvalid_i, + wready_o, + wdata_i, + wdepth_o, + clk_rd_i, + rst_rd_ni, + rvalid_o, + rready_i, + rdata_o, + rdepth_o +); + parameter [31:0] Width = 16; + parameter [31:0] Depth = 3; + localparam [31:0] DepthW = $clog2(Depth + 1); + input clk_wr_i; + input rst_wr_ni; + input wvalid_i; + output wready_o; + input [Width - 1:0] wdata_i; + output [DepthW - 1:0] wdepth_o; + input clk_rd_i; + input rst_rd_ni; + output rvalid_o; + input rready_i; + output [Width - 1:0] rdata_o; + output [DepthW - 1:0] rdepth_o; + localparam [31:0] PTRV_W = $clog2(Depth); + function automatic [PTRV_W - 1:0] sv2v_cast_2173F_unsigned; + input reg [PTRV_W - 1:0] inp; + sv2v_cast_2173F_unsigned = inp; + endfunction + localparam [PTRV_W - 1:0] DepthMinus1 = sv2v_cast_2173F_unsigned(Depth - 1); + localparam [31:0] PTR_WIDTH = PTRV_W + 1; + reg [PTR_WIDTH - 1:0] fifo_wptr; + reg [PTR_WIDTH - 1:0] fifo_rptr; + wire [PTR_WIDTH - 1:0] fifo_wptr_sync_combi; + reg [PTR_WIDTH - 1:0] fifo_rptr_sync; + wire [PTR_WIDTH - 1:0] fifo_wptr_gray_sync; + wire [PTR_WIDTH - 1:0] fifo_rptr_gray_sync; + reg [PTR_WIDTH - 1:0] fifo_wptr_gray; + reg [PTR_WIDTH - 1:0] fifo_rptr_gray; + wire fifo_incr_wptr; + wire fifo_incr_rptr; + wire empty; + wire full_wclk; + wire full_rclk; + assign wready_o = !full_wclk; + assign rvalid_o = !empty; + assign fifo_incr_wptr = wvalid_i & wready_o; + assign fifo_incr_rptr = rvalid_o & rready_i; + always @(posedge clk_wr_i or negedge rst_wr_ni) + if (!rst_wr_ni) + fifo_wptr <= {PTR_WIDTH {1'b0}}; + else if (fifo_incr_wptr) + if (fifo_wptr[PTR_WIDTH - 2:0] == DepthMinus1) + fifo_wptr <= {~fifo_wptr[PTR_WIDTH - 1], {PTR_WIDTH - 1 {1'b0}}}; + else + fifo_wptr <= fifo_wptr + {{PTR_WIDTH - 1 {1'b0}}, 1'b1}; + function automatic [PTR_WIDTH - 1:0] dec2gray; + input reg [PTR_WIDTH - 1:0] decval; + reg [PTR_WIDTH - 1:0] decval_sub; + reg [PTR_WIDTH - 2:0] decval_in; + reg unused_decval_msb; + begin + decval_sub = (Depth - {1'b0, decval[PTR_WIDTH - 2:0]}) - 1'b1; + {unused_decval_msb, decval_in} = (decval[PTR_WIDTH - 1] ? decval_sub : decval); + dec2gray = {decval[PTR_WIDTH - 1], {1'b0, decval_in[PTR_WIDTH - 2:1]} ^ decval_in[PTR_WIDTH - 2:0]}; + end + endfunction + always @(posedge clk_wr_i or negedge rst_wr_ni) + if (!rst_wr_ni) + fifo_wptr_gray <= {PTR_WIDTH {1'b0}}; + else if (fifo_incr_wptr) + if (fifo_wptr[PTR_WIDTH - 2:0] == DepthMinus1) + fifo_wptr_gray <= dec2gray({~fifo_wptr[PTR_WIDTH - 1], {PTR_WIDTH - 1 {1'b0}}}); + else + fifo_wptr_gray <= dec2gray(fifo_wptr + {{PTR_WIDTH - 1 {1'b0}}, 1'b1}); + prim_generic_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr( + .clk_i(clk_rd_i), + .rst_ni(rst_rd_ni), + .d_i(fifo_wptr_gray), + .q_o(fifo_wptr_gray_sync) + ); + function automatic [PTR_WIDTH - 1:0] gray2dec; + input reg [PTR_WIDTH - 1:0] grayval; + reg [PTR_WIDTH - 2:0] dec_tmp; + reg [PTR_WIDTH - 2:0] dec_tmp_sub; + reg unused_decsub_msb; + begin + dec_tmp[PTR_WIDTH - 2] = grayval[PTR_WIDTH - 2]; + begin : sv2v_autoblock_74 + reg signed [31:0] i; + for (i = PTR_WIDTH - 3; i >= 0; i = i - 1) + dec_tmp[i] = dec_tmp[i + 1] ^ grayval[i]; + end + {unused_decsub_msb, dec_tmp_sub} = (Depth - {1'b0, dec_tmp}) - 1'b1; + if (grayval[PTR_WIDTH - 1]) + gray2dec = {1'b1, dec_tmp_sub}; + else + gray2dec = {1'b0, dec_tmp}; + end + endfunction + assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync); + always @(posedge clk_rd_i or negedge rst_rd_ni) + if (!rst_rd_ni) + fifo_rptr <= {PTR_WIDTH {1'b0}}; + else if (fifo_incr_rptr) + if (fifo_rptr[PTR_WIDTH - 2:0] == DepthMinus1) + fifo_rptr <= {~fifo_rptr[PTR_WIDTH - 1], {PTR_WIDTH - 1 {1'b0}}}; + else + fifo_rptr <= fifo_rptr + {{PTR_WIDTH - 1 {1'b0}}, 1'b1}; + always @(posedge clk_rd_i or negedge rst_rd_ni) + if (!rst_rd_ni) + fifo_rptr_gray <= {PTR_WIDTH {1'b0}}; + else if (fifo_incr_rptr) + if (fifo_rptr[PTR_WIDTH - 2:0] == DepthMinus1) + fifo_rptr_gray <= dec2gray({~fifo_rptr[PTR_WIDTH - 1], {PTR_WIDTH - 1 {1'b0}}}); + else + fifo_rptr_gray <= dec2gray(fifo_rptr + {{PTR_WIDTH - 1 {1'b0}}, 1'b1}); + prim_generic_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr( + .clk_i(clk_wr_i), + .rst_ni(rst_wr_ni), + .d_i(fifo_rptr_gray), + .q_o(fifo_rptr_gray_sync) + ); + always @(posedge clk_wr_i or negedge rst_wr_ni) + if (!rst_wr_ni) + fifo_rptr_sync <= {PTR_WIDTH {1'b0}}; + else + fifo_rptr_sync <= gray2dec(fifo_rptr_gray_sync); + assign full_wclk = fifo_wptr == (fifo_rptr_sync ^ {1'b1, {PTR_WIDTH - 1 {1'b0}}}); + assign full_rclk = fifo_wptr_sync_combi == (fifo_rptr ^ {1'b1, {PTR_WIDTH - 1 {1'b0}}}); + wire wptr_msb; + wire rptr_sync_msb; + wire [PTRV_W - 1:0] wptr_value; + wire [PTRV_W - 1:0] rptr_sync_value; + assign wptr_msb = fifo_wptr[PTR_WIDTH - 1]; + assign rptr_sync_msb = fifo_rptr_sync[PTR_WIDTH - 1]; + assign wptr_value = fifo_wptr[0+:PTRV_W]; + assign rptr_sync_value = fifo_rptr_sync[0+:PTRV_W]; + function automatic [DepthW - 1:0] sv2v_cast_37EEB_unsigned; + input reg [DepthW - 1:0] inp; + sv2v_cast_37EEB_unsigned = inp; + endfunction + function automatic [DepthW - 1:0] sv2v_cast_37EEB; + input reg [DepthW - 1:0] inp; + sv2v_cast_37EEB = inp; + endfunction + assign wdepth_o = (full_wclk ? sv2v_cast_37EEB_unsigned(Depth) : (wptr_msb == rptr_sync_msb ? sv2v_cast_37EEB(wptr_value) - sv2v_cast_37EEB(rptr_sync_value) : (sv2v_cast_37EEB_unsigned(Depth) - sv2v_cast_37EEB(rptr_sync_value)) + sv2v_cast_37EEB(wptr_value))); + assign empty = fifo_wptr_sync_combi == fifo_rptr; + wire rptr_msb; + wire wptr_sync_msb; + wire [PTRV_W - 1:0] rptr_value; + wire [PTRV_W - 1:0] wptr_sync_value; + assign wptr_sync_msb = fifo_wptr_sync_combi[PTR_WIDTH - 1]; + assign rptr_msb = fifo_rptr[PTR_WIDTH - 1]; + assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W]; + assign rptr_value = fifo_rptr[0+:PTRV_W]; + assign rdepth_o = (full_rclk ? sv2v_cast_37EEB_unsigned(Depth) : (wptr_sync_msb == rptr_msb ? sv2v_cast_37EEB(wptr_sync_value) - sv2v_cast_37EEB(rptr_value) : (sv2v_cast_37EEB_unsigned(Depth) - sv2v_cast_37EEB(rptr_value)) + sv2v_cast_37EEB(wptr_sync_value))); + reg [Width - 1:0] storage [0:Depth - 1]; + always @(posedge clk_wr_i) + if (fifo_incr_wptr) + storage[fifo_wptr[PTR_WIDTH - 2:0]] <= wdata_i; + assign rdata_o = storage[fifo_rptr[PTR_WIDTH - 2:0]]; +endmodule +module prim_fifo_sync ( + clk_i, + rst_ni, + clr_i, + wvalid_i, + wready_o, + wdata_i, + rvalid_o, + rready_i, + rdata_o, + depth_o +); + parameter [31:0] Width = 16; + parameter [0:0] Pass = 1'b1; + parameter [31:0] Depth = 4; + parameter [0:0] OutputZeroIfEmpty = 1'b1; + function automatic integer prim_util_pkg_vbits; + input integer value; + prim_util_pkg_vbits = (value == 1 ? 1 : $clog2(value)); + endfunction + localparam signed [31:0] DepthW = prim_util_pkg_vbits(Depth + 1); + input clk_i; + input rst_ni; + input clr_i; + input wvalid_i; + output wready_o; + input [Width - 1:0] wdata_i; + output rvalid_o; + input rready_i; + output [Width - 1:0] rdata_o; + output [DepthW - 1:0] depth_o; + generate + if (Depth == 0) begin : gen_passthru_fifo + assign depth_o = 1'b0; + assign rvalid_o = wvalid_i; + assign rdata_o = wdata_i; + assign wready_o = rready_i; + wire unused_clr; + assign unused_clr = clr_i; + end + else begin : gen_normal_fifo + localparam [31:0] PTRV_W = prim_util_pkg_vbits(Depth); + localparam [31:0] PTR_WIDTH = PTRV_W + 1; + reg [PTR_WIDTH - 1:0] fifo_wptr; + reg [PTR_WIDTH - 1:0] fifo_rptr; + wire fifo_incr_wptr; + wire fifo_incr_rptr; + wire fifo_empty; + wire full; + wire empty; + wire wptr_msb; + wire rptr_msb; + wire [PTRV_W - 1:0] wptr_value; + wire [PTRV_W - 1:0] rptr_value; + assign wptr_msb = fifo_wptr[PTR_WIDTH - 1]; + assign rptr_msb = fifo_rptr[PTR_WIDTH - 1]; + assign wptr_value = fifo_wptr[0+:PTRV_W]; + assign rptr_value = fifo_rptr[0+:PTRV_W]; + function automatic [DepthW - 1:0] sv2v_cast_37EEB_unsigned; + input reg [DepthW - 1:0] inp; + sv2v_cast_37EEB_unsigned = inp; + endfunction + function automatic [DepthW - 1:0] sv2v_cast_37EEB; + input reg [DepthW - 1:0] inp; + sv2v_cast_37EEB = inp; + endfunction + assign depth_o = (full ? sv2v_cast_37EEB_unsigned(Depth) : (wptr_msb == rptr_msb ? sv2v_cast_37EEB(wptr_value) - sv2v_cast_37EEB(rptr_value) : (sv2v_cast_37EEB_unsigned(Depth) - sv2v_cast_37EEB(rptr_value)) + sv2v_cast_37EEB(wptr_value))); + assign fifo_incr_wptr = wvalid_i & wready_o; + assign fifo_incr_rptr = rvalid_o & rready_i; + assign wready_o = ~full; + assign rvalid_o = ~empty; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + fifo_wptr <= {PTR_WIDTH {1'b0}}; + else if (clr_i) + fifo_wptr <= {PTR_WIDTH {1'b0}}; + else if (fifo_incr_wptr) + if (fifo_wptr[PTR_WIDTH - 2:0] == (Depth - 1)) + fifo_wptr <= {~fifo_wptr[PTR_WIDTH - 1], {PTR_WIDTH - 1 {1'b0}}}; + else + fifo_wptr <= fifo_wptr + {{PTR_WIDTH - 1 {1'b0}}, 1'b1}; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + fifo_rptr <= {PTR_WIDTH {1'b0}}; + else if (clr_i) + fifo_rptr <= {PTR_WIDTH {1'b0}}; + else if (fifo_incr_rptr) + if (fifo_rptr[PTR_WIDTH - 2:0] == (Depth - 1)) + fifo_rptr <= {~fifo_rptr[PTR_WIDTH - 1], {PTR_WIDTH - 1 {1'b0}}}; + else + fifo_rptr <= fifo_rptr + {{PTR_WIDTH - 1 {1'b0}}, 1'b1}; + assign full = fifo_wptr == (fifo_rptr ^ {1'b1, {PTR_WIDTH - 1 {1'b0}}}); + assign fifo_empty = fifo_wptr == fifo_rptr; + reg [(Depth * Width) - 1:0] storage; + wire [Width - 1:0] storage_rdata; + if (Depth == 1) begin : gen_depth_eq1 + assign storage_rdata = storage[0+:Width]; + always @(posedge clk_i) + if (fifo_incr_wptr) + storage[0+:Width] <= wdata_i; + end + else begin : gen_depth_gt1 + assign storage_rdata = storage[fifo_rptr[PTR_WIDTH - 2:0] * Width+:Width]; + always @(posedge clk_i) + if (fifo_incr_wptr) + storage[fifo_wptr[PTR_WIDTH - 2:0] * Width+:Width] <= wdata_i; + end + wire [Width - 1:0] rdata_int; + if (Pass == 1'b1) begin : gen_pass + assign rdata_int = (fifo_empty && wvalid_i ? wdata_i : storage_rdata); + assign empty = fifo_empty & ~wvalid_i; + end + else begin : gen_nopass + assign rdata_int = storage_rdata; + assign empty = fifo_empty; + end + if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero + assign rdata_o = (empty ? 'b0 : rdata_int); + end + else begin : gen_no_output_zero + assign rdata_o = rdata_int; + end + end + endgenerate +endmodule +module prim_filter_ctr ( + clk_i, + rst_ni, + enable_i, + filter_i, + filter_o +); + parameter [31:0] Cycles = 4; + input clk_i; + input rst_ni; + input enable_i; + input filter_i; + output filter_o; + localparam [31:0] CTR_WIDTH = $clog2(Cycles); + function automatic [CTR_WIDTH - 1:0] sv2v_cast_AF84E_unsigned; + input reg [CTR_WIDTH - 1:0] inp; + sv2v_cast_AF84E_unsigned = inp; + endfunction + localparam [CTR_WIDTH - 1:0] CYCLESM1 = sv2v_cast_AF84E_unsigned(Cycles - 1); + reg [CTR_WIDTH - 1:0] diff_ctr_q; + wire [CTR_WIDTH - 1:0] diff_ctr_d; + reg filter_q; + reg stored_value_q; + wire update_stored_value; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + filter_q <= 1'b0; + else + filter_q <= filter_i; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + stored_value_q <= 1'b0; + else if (update_stored_value) + stored_value_q <= filter_i; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + diff_ctr_q <= {CTR_WIDTH {1'b0}}; + else + diff_ctr_q <= diff_ctr_d; + assign diff_ctr_d = (filter_i != filter_q ? {CTR_WIDTH {1'sb0}} : (diff_ctr_q == CYCLESM1 ? CYCLESM1 : diff_ctr_q + 1'b1)); + assign update_stored_value = diff_ctr_d == CYCLESM1; + assign filter_o = (enable_i ? stored_value_q : filter_i); +endmodule +module prim_generic_clock_gating ( + clk_i, + en_i, + test_en_i, + clk_o +); + input clk_i; + input en_i; + input test_en_i; + output wire clk_o; + reg en_latch; + /*always @(clk_i or en_i or test_en_i) + if (!clk_i) + en_latch = en_i | test_en_i; + //else + //en_latch = 1; + assign clk_o = en_latch & clk_i;*/ + sky130_fd_sc_hd__dlclkp_1 CG( .CLK(clk_i), .GCLK(clk_o), .GATE(en_i | test_en_i)); + /*sky130_fd_sc_hd__dlclkp cell_1 ( + .GCLK(clk_o), + .GATE(en_i), + .CLK(clk_i) + );*/ +endmodule + +/*`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_V +`define SKY130_FD_SC_HD__UDP_DLATCH_P_V + +`timescale 1ns / 1ps +//`default_nettype none + +`ifdef NO_PRIMITIVES +//`include "./sky130_fd_sc_hd__udp_dlatch_p.blackbox.v" +`else +primitive sky130_fd_sc_hd__udp_dlatch$P ( + Q , + D , + GATE +); + + output Q ; + input D ; + input GATE; + + reg Q; + + table + // D GATE : Qt : Qt+1 + ? 0 : ? : - ; // hold + 0 1 : ? : 0 ; // pass 0 + 1 1 : ? : 1 ; // pass 1 + 0 x : 0 : 0 ; // reduce pessimism + 1 x : 1 : 1 ; // reduce pessimism + endtable +endprimitive +`endif // NO_PRIMITIVES + +`default_nettype wire +`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_V +*/ + +/*`ifndef SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V +`define SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V + + +`timescale 1ns / 1ps +//`default_nettype none + +// Import user defined primitives. +//`include "../../models/udp_dlatch_p/sky130_fd_sc_hd__udp_dlatch_p.v" + +`celldefine +module sky130_fd_sc_hd__dlclkp ( + GCLK, + GATE, + CLK +); + + // Module ports + output GCLK; + input GATE; + input CLK ; + + // Local signals + wire m0 ; + wire clkn; + + // Name Output Other arguments + not not0 (clkn , CLK ); + sky130_fd_sc_hd__udp_dlatch$P dlatch0 (m0 , GATE, clkn ); + and and0 (GCLK , m0, CLK ); + +endmodule +`endcelldefine + +`default_nettype wire +`endif // SKY130_FD_SC_HD__DLCLKP_FUNCTIONAL_V +*/ +module prim_generic_clock_inv ( + clk_i, + scanmode_i, + clk_no +); + parameter [0:0] HasScanMode = 1'b1; + input clk_i; + input scanmode_i; + output wire clk_no; + generate + if (HasScanMode) begin : gen_scan + prim_generic_clock_mux2 i_dft_tck_mux( + .clk0_i(~clk_i), + .clk1_i(clk_i), + .sel_i(scanmode_i), + .clk_o(clk_no) + ); + end + else begin : gen_noscan + wire unused_scanmode; + assign unused_scanmode = scanmode_i; + assign clk_no = ~clk_i; + end + endgenerate +endmodule +module prim_generic_clock_mux2 ( + clk0_i, + clk1_i, + sel_i, + clk_o +); + input clk0_i; + input clk1_i; + input sel_i; + output wire clk_o; + assign clk_o = (sel_i ? clk1_i : clk0_i); +endmodule +module prim_generic_flop ( + clk_i, + rst_ni, + d_i, + q_o +); + parameter signed [31:0] Width = 1; + localparam signed [31:0] WidthSubOne = Width - 1; + parameter [WidthSubOne:0] ResetValue = 0; + input clk_i; + input rst_ni; + input [Width - 1:0] d_i; + output reg [Width - 1:0] q_o; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + q_o <= ResetValue; + else + q_o <= d_i; +endmodule +module prim_generic_flop_2sync ( + clk_i, + rst_ni, + d_i, + q_o +); + parameter signed [31:0] Width = 16; + localparam signed [31:0] WidthSubOne = Width - 1; + parameter [WidthSubOne:0] ResetValue = 1'sb0; + input clk_i; + input rst_ni; + input [Width - 1:0] d_i; + output wire [Width - 1:0] q_o; + wire [Width - 1:0] intq; + prim_generic_flop #( + .Width(Width), + .ResetValue(ResetValue) + ) u_sync_1( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(d_i), + .q_o(intq) + ); + prim_generic_flop #( + .Width(Width), + .ResetValue(ResetValue) + ) u_sync_2( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(intq), + .q_o(q_o) + ); +endmodule +module prim_intr_hw ( + clk_i, + rst_ni, + event_intr_i, + reg2hw_intr_enable_q_i, + reg2hw_intr_test_q_i, + reg2hw_intr_test_qe_i, + reg2hw_intr_state_q_i, + hw2reg_intr_state_de_o, + hw2reg_intr_state_d_o, + intr_o +); + parameter [31:0] Width = 1; + parameter [0:0] FlopOutput = 1; + input clk_i; + input rst_ni; + input [Width - 1:0] event_intr_i; + input [Width - 1:0] reg2hw_intr_enable_q_i; + input [Width - 1:0] reg2hw_intr_test_q_i; + input reg2hw_intr_test_qe_i; + input [Width - 1:0] reg2hw_intr_state_q_i; + output hw2reg_intr_state_de_o; + output [Width - 1:0] hw2reg_intr_state_d_o; + output reg [Width - 1:0] intr_o; + wire [Width - 1:0] new_event; + assign new_event = ({Width {reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i; + assign hw2reg_intr_state_de_o = |new_event; + assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; + generate + if (FlopOutput == 1) begin : gen_flop_intr_output + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + intr_o <= 1'b0; + else + intr_o <= reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i; + end + else begin : gen_intr_passthrough_output + wire unused_clk; + wire unused_rst_n; + assign unused_clk = clk_i; + assign unused_rst_n = rst_ni; + always @(*) intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i; + end + endgenerate +endmodule +module prim_subreg ( + clk_i, + rst_ni, + we, + wd, + de, + d, + qe, + q, + qs +); + parameter signed [31:0] DW = 32; + parameter _sv2v_width_SWACCESS = 16; + parameter [_sv2v_width_SWACCESS - 1:0] SWACCESS = "RW"; + parameter [DW - 1:0] RESVAL = 1'sb0; + input clk_i; + input rst_ni; + input we; + input [DW - 1:0] wd; + input de; + input [DW - 1:0] d; + output reg qe; + output reg [DW - 1:0] q; + output wire [DW - 1:0] qs; + wire wr_en; + wire [DW - 1:0] wr_data; + prim_subreg_arb #( + .DW(DW), + ._sv2v_width_SWACCESS(_sv2v_width_SWACCESS), + .SWACCESS(SWACCESS) + ) wr_en_data_arb( + .we(we), + .wd(wd), + .de(de), + .d(d), + .q(q), + .wr_en(wr_en), + .wr_data(wr_data) + ); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + qe <= 1'b0; + else + qe <= we; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + q <= RESVAL; + else if (wr_en) + q <= wr_data; + assign qs = q; +endmodule +module prim_subreg_arb ( + we, + wd, + de, + d, + q, + wr_en, + wr_data +); + parameter signed [31:0] DW = 32; + parameter _sv2v_width_SWACCESS = 16; + parameter [_sv2v_width_SWACCESS - 1:0] SWACCESS = "RW"; + input we; + input [DW - 1:0] wd; + input de; + input [DW - 1:0] d; + input [DW - 1:0] q; + output wire wr_en; + output wire [DW - 1:0] wr_data; + generate + if ((SWACCESS == "RW") || (SWACCESS == "WO")) begin : gen_w + assign wr_en = we | de; + assign wr_data = (we == 1'b1 ? wd : d); + wire [DW - 1:0] unused_q; + assign unused_q = q; + end + else if (SWACCESS == "RO") begin : gen_ro + assign wr_en = de; + assign wr_data = d; + wire unused_we; + wire [DW - 1:0] unused_wd; + wire [DW - 1:0] unused_q; + assign unused_we = we; + assign unused_wd = wd; + assign unused_q = q; + end + else if (SWACCESS == "W1S") begin : gen_w1s + assign wr_en = we | de; + assign wr_data = (de ? d : q) | (we ? wd : {DW {1'sb0}}); + end + else if (SWACCESS == "W1C") begin : gen_w1c + assign wr_en = we | de; + assign wr_data = (de ? d : q) & (we ? ~wd : {DW {1'sb1}}); + end + else if (SWACCESS == "W0C") begin : gen_w0c + assign wr_en = we | de; + assign wr_data = (de ? d : q) & (we ? wd : {DW {1'sb1}}); + end + else if (SWACCESS == "RC") begin : gen_rc + assign wr_en = we | de; + assign wr_data = (de ? d : q) & (we ? {DW {1'sb0}} : {DW {1'sb1}}); + wire [DW - 1:0] unused_wd; + assign unused_wd = wd; + end + else begin : gen_hw + assign wr_en = de; + assign wr_data = d; + wire unused_we; + wire [DW - 1:0] unused_wd; + wire [DW - 1:0] unused_q; + assign unused_we = we; + assign unused_wd = wd; + assign unused_q = q; + end + endgenerate +endmodule +module prim_subreg_ext ( + re, + we, + wd, + d, + qe, + qre, + q, + qs +); + parameter [31:0] DW = 32; + input re; + input we; + input [DW - 1:0] wd; + input [DW - 1:0] d; + output wire qe; + output wire qre; + output wire [DW - 1:0] q; + output wire [DW - 1:0] qs; + assign qs = d; + assign q = wd; + assign qe = we; + assign qre = re; +endmodule +module debug_rom ( + clk_i, + req_i, + addr_i, + rdata_o +); + input wire clk_i; + input wire req_i; + input wire [63:0] addr_i; + output reg [63:0] rdata_o; + localparam [31:0] RomSize = 19; + wire [(RomSize * 64) - 1:0] mem = {64'h000000007b200073, 64'h7b2024737b302573, 64'h10852423f1402473, 64'ha85ff06f7b202473, 64'h7b30257310052223, 64'h001000737b202473, 64'h7b30257310052623, 64'h00c5151300c55513, 64'h00000517fd5ff06f, 64'hfa041ce300247413, 64'h4004440300a40433, 64'hf140247302041c63, 64'h0014741340044403, 64'h00a4043310852023, 64'hf140247300c51513, 64'h00c5551300000517, 64'h7b3510737b241073, 64'h0ff0000f04c0006f, 64'h07c0006f00c0006f}; + reg [4:0] addr_q; + always @(posedge clk_i) + if (req_i) + addr_q <= addr_i[7:3]; + function automatic [4:0] sv2v_cast_5_unsigned; + input reg [4:0] inp; + sv2v_cast_5_unsigned = inp; + endfunction + always @(*) begin : p_outmux + rdata_o = {64 {1'sb0}}; + if (addr_q < sv2v_cast_5_unsigned(RomSize)) + rdata_o = mem[addr_q * 64+:64]; + end +endmodule +module dm_csrs ( + clk_i, + rst_ni, + testmode_i, + dmi_rst_ni, + dmi_req_valid_i, + dmi_req_ready_o, + dmi_req_i, + dmi_resp_valid_o, + dmi_resp_ready_i, + dmi_resp_o, + ndmreset_o, + dmactive_o, + hartinfo_i, + halted_i, + unavailable_i, + resumeack_i, + hartsel_o, + haltreq_o, + resumereq_o, + clear_resumeack_o, + cmd_valid_o, + cmd_o, + cmderror_valid_i, + cmderror_i, + cmdbusy_i, + progbuf_o, + data_o, + data_i, + data_valid_i, + sbaddress_o, + sbaddress_i, + sbaddress_write_valid_o, + sbreadonaddr_o, + sbautoincrement_o, + sbaccess_o, + sbreadondata_o, + sbdata_o, + sbdata_read_valid_o, + sbdata_write_valid_o, + sbdata_i, + sbdata_valid_i, + sbbusy_i, + sberror_valid_i, + sberror_i +); + parameter [31:0] NrHarts = 1; + parameter [31:0] BusWidth = 32; + parameter [NrHarts - 1:0] SelectableHarts = {NrHarts {1'b1}}; + input wire clk_i; + input wire rst_ni; + input wire testmode_i; + input wire dmi_rst_ni; + input wire dmi_req_valid_i; + output wire dmi_req_ready_o; + input wire [40:0] dmi_req_i; + output wire dmi_resp_valid_o; + input wire dmi_resp_ready_i; + output wire [33:0] dmi_resp_o; + output wire ndmreset_o; + output wire dmactive_o; + input wire [(NrHarts * 32) - 1:0] hartinfo_i; + input wire [NrHarts - 1:0] halted_i; + input wire [NrHarts - 1:0] unavailable_i; + input wire [NrHarts - 1:0] resumeack_i; + output wire [19:0] hartsel_o; + output reg [NrHarts - 1:0] haltreq_o; + output reg [NrHarts - 1:0] resumereq_o; + output reg clear_resumeack_o; + output wire cmd_valid_o; + output wire [31:0] cmd_o; + input wire cmderror_valid_i; + input wire [2:0] cmderror_i; + input wire cmdbusy_i; + localparam [4:0] dm_ProgBufSize = 5'h08; + output wire [(dm_ProgBufSize * 32) - 1:0] progbuf_o; + localparam [3:0] dm_DataCount = 4'h2; + output wire [(dm_DataCount * 32) - 1:0] data_o; + input wire [(dm_DataCount * 32) - 1:0] data_i; + input wire data_valid_i; + output wire [BusWidth - 1:0] sbaddress_o; + input wire [BusWidth - 1:0] sbaddress_i; + output reg sbaddress_write_valid_o; + output wire sbreadonaddr_o; + output wire sbautoincrement_o; + output wire [2:0] sbaccess_o; + output wire sbreadondata_o; + output wire [BusWidth - 1:0] sbdata_o; + output reg sbdata_read_valid_o; + output reg sbdata_write_valid_o; + input wire [BusWidth - 1:0] sbdata_i; + input wire sbdata_valid_i; + input wire sbbusy_i; + input wire sberror_valid_i; + input wire [2:0] sberror_i; + localparam [31:0] HartSelLen = (NrHarts == 1 ? 1 : $clog2(NrHarts)); + localparam [31:0] NrHartsAligned = 2 ** HartSelLen; + wire [1:0] dtm_op; + function automatic [1:0] sv2v_cast_2; + input reg [1:0] inp; + sv2v_cast_2 = inp; + endfunction + assign dtm_op = sv2v_cast_2(dmi_req_i[33-:2]); + reg [31:0] resp_queue_data; + localparam [7:0] dm_Data0 = 8'h04; + function automatic [7:0] sv2v_cast_8; + input reg [7:0] inp; + sv2v_cast_8 = inp; + endfunction + localparam [7:0] DataEnd = sv2v_cast_8((dm_Data0 + {4'b0000, dm_DataCount}) - 8'h01); + localparam [7:0] dm_ProgBuf0 = 8'h20; + localparam [7:0] ProgBufEnd = sv2v_cast_8((dm_ProgBuf0 + {4'b0000, dm_ProgBufSize}) - 8'h01); + reg [31:0] haltsum0; + reg [31:0] haltsum1; + reg [31:0] haltsum2; + reg [31:0] haltsum3; + reg [((((NrHarts - 1) / 32) + 1) * 32) - 1:0] halted; + reg [(((NrHarts - 1) / 32) >= 0 ? ((((NrHarts - 1) / 32) + 1) * 32) - 1 : ((1 - ((NrHarts - 1) / 32)) * 32) + ((((NrHarts - 1) / 32) * 32) - 1)):(((NrHarts - 1) / 32) >= 0 ? 0 : ((NrHarts - 1) / 32) * 32)] halted_reshaped0; + reg [(((NrHarts - 1) / 1024) >= 0 ? ((((NrHarts - 1) / 1024) + 1) * 32) - 1 : ((1 - ((NrHarts - 1) / 1024)) * 32) + ((((NrHarts - 1) / 1024) * 32) - 1)):(((NrHarts - 1) / 1024) >= 0 ? 0 : ((NrHarts - 1) / 1024) * 32)] halted_reshaped1; + reg [(((NrHarts - 1) / 32768) >= 0 ? ((((NrHarts - 1) / 32768) + 1) * 32) - 1 : ((1 - ((NrHarts - 1) / 32768)) * 32) + ((((NrHarts - 1) / 32768) * 32) - 1)):(((NrHarts - 1) / 32768) >= 0 ? 0 : ((NrHarts - 1) / 32768) * 32)] halted_reshaped2; + reg [((((NrHarts - 1) / 1024) + 1) * 32) - 1:0] halted_flat1; + reg [((((NrHarts - 1) / 32768) + 1) * 32) - 1:0] halted_flat2; + reg [31:0] halted_flat3; + reg [14:0] hartsel_idx0; + function automatic [14:0] sv2v_cast_15_unsigned; + input reg [14:0] inp; + sv2v_cast_15_unsigned = inp; + endfunction + always @(*) begin : p_haltsum0 + halted = {(((NrHarts - 1) / 32) + 1) * 32 {1'sb0}}; + haltsum0 = {32 {1'sb0}}; + hartsel_idx0 = hartsel_o[19:5]; + halted[NrHarts - 1:0] = halted_i; + halted_reshaped0 = halted; + if (hartsel_idx0 < sv2v_cast_15_unsigned(((NrHarts - 1) / 32) + 1)) + haltsum0 = halted_reshaped0[(((NrHarts - 1) / 32) >= 0 ? hartsel_idx0 : ((NrHarts - 1) / 32) - hartsel_idx0) * 32+:32]; + end + reg [9:0] hartsel_idx1; + function automatic [9:0] sv2v_cast_10_unsigned; + input reg [9:0] inp; + sv2v_cast_10_unsigned = inp; + endfunction + always @(*) begin : p_reduction1 + halted_flat1 = {(((NrHarts - 1) / 1024) + 1) * 32 {1'sb0}}; + haltsum1 = {32 {1'sb0}}; + hartsel_idx1 = hartsel_o[19:10]; + begin : sv2v_autoblock_75 + reg [31:0] k; + for (k = 0; k < (((NrHarts - 1) / 32) + 1); k = k + 1) + halted_flat1[k] = |halted_reshaped0[(((NrHarts - 1) / 32) >= 0 ? k : ((NrHarts - 1) / 32) - k) * 32+:32]; + end + halted_reshaped1 = halted_flat1; + if (hartsel_idx1 < sv2v_cast_10_unsigned(((NrHarts - 1) / 1024) + 1)) + haltsum1 = halted_reshaped1[(((NrHarts - 1) / 1024) >= 0 ? hartsel_idx1 : ((NrHarts - 1) / 1024) - hartsel_idx1) * 32+:32]; + end + reg [4:0] hartsel_idx2; + function automatic [4:0] sv2v_cast_5_unsigned; + input reg [4:0] inp; + sv2v_cast_5_unsigned = inp; + endfunction + always @(*) begin : p_reduction2 + halted_flat2 = {(((NrHarts - 1) / 32768) + 1) * 32 {1'sb0}}; + haltsum2 = {32 {1'sb0}}; + hartsel_idx2 = hartsel_o[19:15]; + begin : sv2v_autoblock_76 + reg [31:0] k; + for (k = 0; k < (((NrHarts - 1) / 1024) + 1); k = k + 1) + halted_flat2[k] = |halted_reshaped1[(((NrHarts - 1) / 1024) >= 0 ? k : ((NrHarts - 1) / 1024) - k) * 32+:32]; + end + halted_reshaped2 = halted_flat2; + if (hartsel_idx2 < sv2v_cast_5_unsigned(((NrHarts - 1) / 32768) + 1)) + haltsum2 = halted_reshaped2[(((NrHarts - 1) / 32768) >= 0 ? hartsel_idx2 : ((NrHarts - 1) / 32768) - hartsel_idx2) * 32+:32]; + end + always @(*) begin : p_reduction3 + halted_flat3 = {32 {1'sb0}}; + begin : sv2v_autoblock_77 + reg [31:0] k; + for (k = 0; k < ((NrHarts / 32768) + 1); k = k + 1) + halted_flat3[k] = |halted_reshaped2[(((NrHarts - 1) / 32768) >= 0 ? k : ((NrHarts - 1) / 32768) - k) * 32+:32]; + end + haltsum3 = halted_flat3; + end + reg [31:0] dmstatus; + reg [31:0] dmcontrol_d; + reg [31:0] dmcontrol_q; + reg [31:0] abstractcs; + reg [2:0] cmderr_d; + reg [2:0] cmderr_q; + reg [31:0] command_d; + reg [31:0] command_q; + reg cmd_valid_d; + reg cmd_valid_q; + reg [31:0] abstractauto_d; + reg [31:0] abstractauto_q; + reg [31:0] sbcs_d; + reg [31:0] sbcs_q; + reg [63:0] sbaddr_d; + reg [63:0] sbaddr_q; + reg [63:0] sbdata_d; + reg [63:0] sbdata_q; + wire [NrHarts - 1:0] havereset_d; + reg [NrHarts - 1:0] havereset_q; + reg [(dm_ProgBufSize * 32) - 1:0] progbuf_d; + reg [(dm_ProgBufSize * 32) - 1:0] progbuf_q; + reg [(dm_DataCount * 32) - 1:0] data_d; + reg [(dm_DataCount * 32) - 1:0] data_q; + reg [HartSelLen - 1:0] selected_hart; + localparam [1:0] dm_DTM_SUCCESS = 2'h0; + assign dmi_resp_o[1-:2] = dm_DTM_SUCCESS; + assign sbautoincrement_o = sbcs_q[16]; + assign sbreadonaddr_o = sbcs_q[20]; + assign sbreadondata_o = sbcs_q[15]; + assign sbaccess_o = sbcs_q[19-:3]; + assign sbdata_o = sbdata_q[BusWidth - 1:0]; + assign sbaddress_o = sbaddr_q[BusWidth - 1:0]; + assign hartsel_o = {dmcontrol_q[15-:10], dmcontrol_q[25-:10]}; + reg [NrHartsAligned - 1:0] havereset_d_aligned; + wire [NrHartsAligned - 1:0] havereset_q_aligned; + wire [NrHartsAligned - 1:0] resumeack_aligned; + wire [NrHartsAligned - 1:0] unavailable_aligned; + wire [NrHartsAligned - 1:0] halted_aligned; + function automatic [NrHartsAligned - 1:0] sv2v_cast_8FC1C; + input reg [NrHartsAligned - 1:0] inp; + sv2v_cast_8FC1C = inp; + endfunction + assign resumeack_aligned = sv2v_cast_8FC1C(resumeack_i); + assign unavailable_aligned = sv2v_cast_8FC1C(unavailable_i); + assign halted_aligned = sv2v_cast_8FC1C(halted_i); + function automatic [NrHarts - 1:0] sv2v_cast_50608; + input reg [NrHarts - 1:0] inp; + sv2v_cast_50608 = inp; + endfunction + assign havereset_d = sv2v_cast_50608(havereset_d_aligned); + assign havereset_q_aligned = sv2v_cast_8FC1C(havereset_q); + reg [(NrHartsAligned * 32) - 1:0] hartinfo_aligned; + always @(*) begin : p_hartinfo_align + hartinfo_aligned = {NrHartsAligned * 32 {1'sb0}}; + hartinfo_aligned[32 * ((NrHarts - 1) - (NrHarts - 1))+:32 * NrHarts] = hartinfo_i; + end + reg [31:0] sbcs; + reg [31:0] dmcontrol; + reg [31:0] a_abstractcs; + reg [4:0] autoexecdata_idx; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + function automatic [63:0] sv2v_cast_64; + input reg [63:0] inp; + sv2v_cast_64 = inp; + endfunction + function automatic [4:0] sv2v_cast_5; + input reg [4:0] inp; + sv2v_cast_5 = inp; + endfunction + function automatic [$clog2(4'h2) - 1:0] sv2v_cast_48325; + input reg [$clog2(4'h2) - 1:0] inp; + sv2v_cast_48325 = inp; + endfunction + function automatic [11:0] sv2v_cast_12; + input reg [11:0] inp; + sv2v_cast_12 = inp; + endfunction + function automatic [15:0] sv2v_cast_16; + input reg [15:0] inp; + sv2v_cast_16 = inp; + endfunction + localparam [7:0] dm_AbstractAuto = 8'h18; + localparam [7:0] dm_AbstractCS = 8'h16; + localparam [2:0] dm_CmdErrBusy = 1; + localparam [2:0] dm_CmdErrNone = 0; + localparam [7:0] dm_Command = 8'h17; + localparam [7:0] dm_DMControl = 8'h10; + localparam [7:0] dm_DMStatus = 8'h11; + localparam [1:0] dm_DTM_READ = 2'h1; + localparam [1:0] dm_DTM_WRITE = 2'h2; + localparam [3:0] dm_DbgVersion013 = 4'h2; + localparam [7:0] dm_HaltSum0 = 8'h40; + localparam [7:0] dm_HaltSum1 = 8'h13; + localparam [7:0] dm_HaltSum2 = 8'h34; + localparam [7:0] dm_HaltSum3 = 8'h35; + localparam [7:0] dm_Hartinfo = 8'h12; + localparam [7:0] dm_SBAddress0 = 8'h39; + localparam [7:0] dm_SBAddress1 = 8'h3a; + localparam [7:0] dm_SBCS = 8'h38; + localparam [7:0] dm_SBData0 = 8'h3c; + localparam [7:0] dm_SBData1 = 8'h3d; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [6:0] sv2v_cast_7; + input reg [6:0] inp; + sv2v_cast_7 = inp; + endfunction + always @(*) begin : csr_read_write + dmstatus = {32 {1'sb0}}; + dmstatus[3-:4] = dm_DbgVersion013; + dmstatus[7] = 1'b1; + dmstatus[5] = 1'b0; + dmstatus[19] = havereset_q_aligned[selected_hart]; + dmstatus[18] = havereset_q_aligned[selected_hart]; + dmstatus[17] = resumeack_aligned[selected_hart]; + dmstatus[16] = resumeack_aligned[selected_hart]; + dmstatus[13] = unavailable_aligned[selected_hart]; + dmstatus[12] = unavailable_aligned[selected_hart]; + dmstatus[15] = sv2v_cast_1(sv2v_cast_32(hartsel_o) > (NrHarts - 1)); + dmstatus[14] = sv2v_cast_1(sv2v_cast_32(hartsel_o) > (NrHarts - 1)); + dmstatus[9] = halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart]; + dmstatus[8] = halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart]; + dmstatus[11] = ~halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart]; + dmstatus[10] = ~halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart]; + abstractcs = {32 {1'sb0}}; + abstractcs[3-:4] = dm_DataCount; + abstractcs[28-:5] = dm_ProgBufSize; + abstractcs[12] = cmdbusy_i; + abstractcs[10-:3] = cmderr_q; + abstractauto_d = abstractauto_q; + abstractauto_d[15-:4] = {4 {1'sb0}}; + havereset_d_aligned = sv2v_cast_8FC1C(havereset_q); + dmcontrol_d = dmcontrol_q; + cmderr_d = cmderr_q; + command_d = command_q; + progbuf_d = progbuf_q; + data_d = data_q; + sbcs_d = sbcs_q; + sbaddr_d = sv2v_cast_64(sbaddress_i); + sbdata_d = sbdata_q; + resp_queue_data = 32'b00000000000000000000000000000000; + cmd_valid_d = 1'b0; + sbaddress_write_valid_o = 1'b0; + sbdata_read_valid_o = 1'b0; + sbdata_write_valid_o = 1'b0; + clear_resumeack_o = 1'b0; + sbcs = {32 {1'sb0}}; + dmcontrol = {32 {1'sb0}}; + a_abstractcs = {32 {1'sb0}}; + autoexecdata_idx = dmi_req_i[38:34] - sv2v_cast_5(dm_Data0); + if ((dmi_req_ready_o && dmi_req_valid_i) && (dtm_op == dm_DTM_READ)) + if ((dm_Data0 <= {1'b0, dmi_req_i[40-:7]}) && (DataEnd >= {1'b0, dmi_req_i[40-:7]})) begin + resp_queue_data = data_q[sv2v_cast_48325(autoexecdata_idx) * 32+:32]; + if (!cmdbusy_i) + if (autoexecdata_idx < 12) + cmd_valid_d = abstractauto_q[autoexecdata_idx]; + end + else if ({1'b0, dmi_req_i[40-:7]} == dm_DMControl) + resp_queue_data = dmcontrol_q; + else if ({1'b0, dmi_req_i[40-:7]} == dm_DMStatus) + resp_queue_data = dmstatus; + else if ({1'b0, dmi_req_i[40-:7]} == dm_Hartinfo) + resp_queue_data = hartinfo_aligned[selected_hart * 32+:32]; + else if ({1'b0, dmi_req_i[40-:7]} == dm_AbstractCS) + resp_queue_data = abstractcs; + else if ({1'b0, dmi_req_i[40-:7]} == dm_AbstractAuto) + resp_queue_data = abstractauto_q; + else if ({1'b0, dmi_req_i[40-:7]} == dm_Command) + resp_queue_data = {32 {1'sb0}}; + else if ((dm_ProgBuf0 <= {1'b0, dmi_req_i[40-:7]}) && (ProgBufEnd >= {1'b0, dmi_req_i[40-:7]})) begin + resp_queue_data = progbuf_q[dmi_req_i[$clog2(5'h08) + 33:34] * 32+:32]; + if (!cmdbusy_i) + cmd_valid_d = abstractauto_q[{1'b1, dmi_req_i[37:34]}]; + end + else if ({1'b0, dmi_req_i[40-:7]} == dm_HaltSum0) + resp_queue_data = haltsum0; + else if ({1'b0, dmi_req_i[40-:7]} == dm_HaltSum1) + resp_queue_data = haltsum1; + else if ({1'b0, dmi_req_i[40-:7]} == dm_HaltSum2) + resp_queue_data = haltsum2; + else if ({1'b0, dmi_req_i[40-:7]} == dm_HaltSum3) + resp_queue_data = haltsum3; + else if ({1'b0, dmi_req_i[40-:7]} == dm_SBCS) + resp_queue_data = sbcs_q; + else if ({1'b0, dmi_req_i[40-:7]} == dm_SBAddress0) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else + resp_queue_data = sbaddr_q[31:0]; + end + else if ({1'b0, dmi_req_i[40-:7]} == dm_SBAddress1) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else + resp_queue_data = sbaddr_q[63:32]; + end + else if ({1'b0, dmi_req_i[40-:7]} == dm_SBData0) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else begin + sbdata_read_valid_o = sbcs_q[14-:3] == {3 {1'sb0}}; + resp_queue_data = sbdata_q[31:0]; + end + end + else if ({1'b0, dmi_req_i[40-:7]} == dm_SBData1) + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else + resp_queue_data = sbdata_q[63:32]; + if ((dmi_req_ready_o && dmi_req_valid_i) && (dtm_op == dm_DTM_WRITE)) + if ((dm_Data0 <= sv2v_cast_8({1'b0, dmi_req_i[40-:7]})) && (DataEnd >= sv2v_cast_8({1'b0, dmi_req_i[40-:7]}))) begin + if (!cmdbusy_i && (dm_DataCount > 0)) begin + data_d[dmi_req_i[$clog2(4'h2) + 33:34] * 32+:32] = dmi_req_i[31-:32]; + if (autoexecdata_idx < 12) + cmd_valid_d = abstractauto_q[autoexecdata_idx]; + end + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_DMControl) begin + dmcontrol = sv2v_cast_32(dmi_req_i[31-:32]); + if (dmcontrol[28]) + havereset_d_aligned[selected_hart] = 1'b0; + dmcontrol_d = dmi_req_i[31-:32]; + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_DMStatus) + ; + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_Hartinfo) + ; + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_AbstractCS) begin + a_abstractcs = sv2v_cast_32(dmi_req_i[31-:32]); + if (!cmdbusy_i) + cmderr_d = sv2v_cast_3(~a_abstractcs[10-:3] & cmderr_q); + else if (cmderr_q == dm_CmdErrNone) + cmderr_d = dm_CmdErrBusy; + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_Command) begin + if (!cmdbusy_i) begin + cmd_valid_d = 1'b1; + command_d = sv2v_cast_32(dmi_req_i[31-:32]); + end + else if (cmderr_q == dm_CmdErrNone) + cmderr_d = dm_CmdErrBusy; + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_AbstractAuto) begin + if (!cmdbusy_i) begin + abstractauto_d = 32'b00000000000000000000000000000000; + abstractauto_d[11-:12] = sv2v_cast_12(dmi_req_i[dm_DataCount - 1:0]); + abstractauto_d[31-:16] = sv2v_cast_16(dmi_req_i[dm_ProgBufSize + 15:16]); + end + else if (cmderr_q == dm_CmdErrNone) + cmderr_d = dm_CmdErrBusy; + end + else if ((dm_ProgBuf0 <= sv2v_cast_8({1'b0, dmi_req_i[40-:7]})) && (ProgBufEnd >= sv2v_cast_8({1'b0, dmi_req_i[40-:7]}))) begin + if (!cmdbusy_i) begin + progbuf_d[dmi_req_i[$clog2(5'h08) + 33:34] * 32+:32] = dmi_req_i[31-:32]; + cmd_valid_d = abstractauto_q[{1'b1, dmi_req_i[37:34]}]; + end + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_SBCS) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else begin + sbcs = sv2v_cast_32(dmi_req_i[31-:32]); + sbcs_d = sbcs; + sbcs_d[22] = sbcs_q[22] & ~sbcs[22]; + sbcs_d[14-:3] = sbcs_q[14-:3] & ~sbcs[14-:3]; + end + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_SBAddress0) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else begin + sbaddr_d[31:0] = dmi_req_i[31-:32]; + sbaddress_write_valid_o = sbcs_q[14-:3] == {3 {1'sb0}}; + end + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_SBAddress1) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else + sbaddr_d[63:32] = dmi_req_i[31-:32]; + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_SBData0) begin + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else begin + sbdata_d[31:0] = dmi_req_i[31-:32]; + sbdata_write_valid_o = sbcs_q[14-:3] == {3 {1'sb0}}; + end + end + else if (sv2v_cast_8({1'b0, dmi_req_i[40-:7]}) == dm_SBData1) + if (sbbusy_i) + sbcs_d[22] = 1'b1; + else + sbdata_d[63:32] = dmi_req_i[31-:32]; + if (cmderror_valid_i) + cmderr_d = cmderror_i; + if (data_valid_i) + data_d = data_i; + if (ndmreset_o) + havereset_d_aligned[NrHarts - 1:0] = {NrHarts {1'sb1}}; + if (sberror_valid_i) + sbcs_d[14-:3] = sberror_i; + if (sbdata_valid_i) + sbdata_d = sv2v_cast_64(sbdata_i); + dmcontrol_d[26] = 1'b0; + dmcontrol_d[29] = 1'b0; + dmcontrol_d[3] = 1'b0; + dmcontrol_d[2] = 1'b0; + dmcontrol_d[27] = 1'sb0; + dmcontrol_d[5-:2] = {2 {1'sb0}}; + dmcontrol_d[28] = 1'b0; + if (!dmcontrol_q[30] && dmcontrol_d[30]) + clear_resumeack_o = 1'b1; + if (dmcontrol_q[30] && resumeack_i) + dmcontrol_d[30] = 1'b0; + sbcs_d[31-:3] = 3'd1; + sbcs_d[21] = sbbusy_i; + sbcs_d[11-:7] = sv2v_cast_7(BusWidth); + sbcs_d[4] = 1'b0; + sbcs_d[3] = sv2v_cast_1(BusWidth == 32'd64); + sbcs_d[2] = sv2v_cast_1(BusWidth == 32'd32); + sbcs_d[1] = 1'b0; + sbcs_d[0] = 1'b0; + sbcs_d[19-:3] = (BusWidth == 32'd64 ? 3'd3 : 3'd2); + end + function automatic [HartSelLen:0] sv2v_cast_7DE8E_unsigned; + input reg [HartSelLen:0] inp; + sv2v_cast_7DE8E_unsigned = inp; + endfunction + always @(*) begin : p_outmux + selected_hart = hartsel_o[HartSelLen - 1:0]; + haltreq_o = {NrHarts {1'sb0}}; + resumereq_o = {NrHarts {1'sb0}}; + if (selected_hart < sv2v_cast_7DE8E_unsigned(NrHarts)) begin + haltreq_o[selected_hart] = dmcontrol_q[31]; + resumereq_o[selected_hart] = dmcontrol_q[30]; + end + end + assign dmactive_o = dmcontrol_q[0]; + assign cmd_o = command_q; + assign cmd_valid_o = cmd_valid_q; + assign progbuf_o = progbuf_q; + assign data_o = data_q; + assign ndmreset_o = dmcontrol_q[1]; + wire unused_testmode; + assign unused_testmode = testmode_i; + prim_fifo_sync #( + .Width(32), + .Pass(1'b0), + .Depth(2) + ) i_fifo( + .clk_i(clk_i), + .rst_ni(dmi_rst_ni), + .clr_i(1'b0), + .wdata_i(resp_queue_data), + .wvalid_i(dmi_req_valid_i), + .wready_o(dmi_req_ready_o), + .rdata_o(dmi_resp_o[33-:32]), + .rvalid_o(dmi_resp_valid_o), + .rready_i(dmi_resp_ready_i), + .depth_o() + ); + always @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + dmcontrol_q <= {32 {1'sb0}}; + cmderr_q <= dm_CmdErrNone; + command_q <= {32 {1'sb0}}; + cmd_valid_q <= 1'sb0; + abstractauto_q <= {32 {1'sb0}}; + progbuf_q <= {dm_ProgBufSize * 32 {1'sb0}}; + data_q <= {dm_DataCount * 32 {1'sb0}}; + sbcs_q <= {32 {1'sb0}}; + sbaddr_q <= {64 {1'sb0}}; + sbdata_q <= {64 {1'sb0}}; + havereset_q <= {NrHarts {1'sb1}}; + end + else begin + havereset_q <= SelectableHarts & havereset_d; + if (!dmcontrol_q[0]) begin + dmcontrol_q[31] <= 1'sb0; + dmcontrol_q[30] <= 1'sb0; + dmcontrol_q[29] <= 1'sb0; + dmcontrol_q[28] <= 1'sb0; + dmcontrol_q[27] <= 1'sb0; + dmcontrol_q[26] <= 1'sb0; + dmcontrol_q[25-:10] <= {10 {1'sb0}}; + dmcontrol_q[15-:10] <= {10 {1'sb0}}; + dmcontrol_q[5-:2] <= {2 {1'sb0}}; + dmcontrol_q[3] <= 1'sb0; + dmcontrol_q[2] <= 1'sb0; + dmcontrol_q[1] <= 1'sb0; + dmcontrol_q[0] <= dmcontrol_d[0]; + cmderr_q <= dm_CmdErrNone; + command_q <= {32 {1'sb0}}; + cmd_valid_q <= 1'sb0; + abstractauto_q <= {32 {1'sb0}}; + progbuf_q <= {dm_ProgBufSize * 32 {1'sb0}}; + data_q <= {dm_DataCount * 32 {1'sb0}}; + sbcs_q <= {32 {1'sb0}}; + sbaddr_q <= {64 {1'sb0}}; + sbdata_q <= {64 {1'sb0}}; + end + else begin + dmcontrol_q <= dmcontrol_d; + cmderr_q <= cmderr_d; + command_q <= command_d; + cmd_valid_q <= cmd_valid_d; + abstractauto_q <= abstractauto_d; + progbuf_q <= progbuf_d; + data_q <= data_d; + sbcs_q <= sbcs_d; + sbaddr_q <= sbaddr_d; + sbdata_q <= sbdata_d; + end + end + end +endmodule +module dm_mem ( + clk_i, + rst_ni, + debug_req_o, + hartsel_i, + haltreq_i, + resumereq_i, + clear_resumeack_i, + halted_o, + resuming_o, + progbuf_i, + data_i, + data_o, + data_valid_o, + cmd_valid_i, + cmd_i, + cmderror_valid_o, + cmderror_o, + cmdbusy_o, + req_i, + we_i, + addr_i, + wdata_i, + be_i, + rdata_o +); + parameter [31:0] NrHarts = 1; + parameter [31:0] BusWidth = 32; + parameter [NrHarts - 1:0] SelectableHarts = {NrHarts {1'b1}}; + parameter [31:0] DmBaseAddress = 1'sb0; + input wire clk_i; + input wire rst_ni; + output wire [NrHarts - 1:0] debug_req_o; + input wire [19:0] hartsel_i; + input wire [NrHarts - 1:0] haltreq_i; + input wire [NrHarts - 1:0] resumereq_i; + input wire clear_resumeack_i; + output wire [NrHarts - 1:0] halted_o; + output wire [NrHarts - 1:0] resuming_o; + localparam [4:0] dm_ProgBufSize = 5'h08; + input wire [(dm_ProgBufSize * 32) - 1:0] progbuf_i; + localparam [3:0] dm_DataCount = 4'h2; + input wire [(dm_DataCount * 32) - 1:0] data_i; + output reg [(dm_DataCount * 32) - 1:0] data_o; + output reg data_valid_o; + input wire cmd_valid_i; + input wire [31:0] cmd_i; + output reg cmderror_valid_o; + output reg [2:0] cmderror_o; + output reg cmdbusy_o; + input wire req_i; + input wire we_i; + input wire [BusWidth - 1:0] addr_i; + input wire [BusWidth - 1:0] wdata_i; + input wire [(BusWidth / 8) - 1:0] be_i; + output wire [BusWidth - 1:0] rdata_o; + localparam [31:0] DbgAddressBits = 12; + localparam [31:0] HartSelLen = (NrHarts == 1 ? 1 : $clog2(NrHarts)); + localparam [31:0] NrHartsAligned = 2 ** HartSelLen; + localparam [31:0] MaxAar = (BusWidth == 64 ? 4 : 3); + localparam [0:0] HasSndScratch = DmBaseAddress != 0; + localparam [4:0] LoadBaseAddr = (DmBaseAddress == 0 ? 5'd0 : 5'd10); + localparam [11:0] dm_DataAddr = 12'h380; + localparam [DbgAddressBits - 1:0] DataBaseAddr = dm_DataAddr; + localparam [DbgAddressBits - 1:0] DataEndAddr = (dm_DataAddr + (4 * dm_DataCount)) - 1; + localparam [DbgAddressBits - 1:0] ProgBufBaseAddr = dm_DataAddr - (4 * dm_ProgBufSize); + localparam [DbgAddressBits - 1:0] ProgBufEndAddr = dm_DataAddr - 1; + localparam [DbgAddressBits - 1:0] AbstractCmdBaseAddr = ProgBufBaseAddr - 40; + localparam [DbgAddressBits - 1:0] AbstractCmdEndAddr = ProgBufBaseAddr - 1; + localparam [DbgAddressBits - 1:0] WhereToAddr = 'h300; + localparam [DbgAddressBits - 1:0] FlagsBaseAddr = 'h400; + localparam [DbgAddressBits - 1:0] FlagsEndAddr = 'h7ff; + localparam [DbgAddressBits - 1:0] HaltedAddr = 'h100; + localparam [DbgAddressBits - 1:0] GoingAddr = 'h104; + localparam [DbgAddressBits - 1:0] ResumingAddr = 'h108; + localparam [DbgAddressBits - 1:0] ExceptionAddr = 'h10c; + wire [((dm_ProgBufSize / 2) * 64) - 1:0] progbuf; + reg [511:0] abstract_cmd; + wire [NrHarts - 1:0] halted_d; + reg [NrHarts - 1:0] halted_q; + wire [NrHarts - 1:0] resuming_d; + reg [NrHarts - 1:0] resuming_q; + reg resume; + reg go; + reg going; + reg exception; + reg unsupported_command; + wire [63:0] rom_rdata; + reg [63:0] rdata_d; + reg [63:0] rdata_q; + reg word_enable32_q; + wire [HartSelLen - 1:0] hartsel; + wire [HartSelLen - 1:0] wdata_hartsel; + assign hartsel = hartsel_i[HartSelLen - 1:0]; + assign wdata_hartsel = wdata_i[HartSelLen - 1:0]; + wire [NrHartsAligned - 1:0] resumereq_aligned; + wire [NrHartsAligned - 1:0] haltreq_aligned; + reg [NrHartsAligned - 1:0] halted_d_aligned; + wire [NrHartsAligned - 1:0] halted_q_aligned; + reg [NrHartsAligned - 1:0] halted_aligned; + wire [NrHartsAligned - 1:0] resumereq_wdata_aligned; + reg [NrHartsAligned - 1:0] resuming_d_aligned; + wire [NrHartsAligned - 1:0] resuming_q_aligned; + function automatic [NrHartsAligned - 1:0] sv2v_cast_8FC1C; + input reg [NrHartsAligned - 1:0] inp; + sv2v_cast_8FC1C = inp; + endfunction + assign resumereq_aligned = sv2v_cast_8FC1C(resumereq_i); + assign haltreq_aligned = sv2v_cast_8FC1C(haltreq_i); + assign resumereq_wdata_aligned = sv2v_cast_8FC1C(resumereq_i); + assign halted_q_aligned = sv2v_cast_8FC1C(halted_q); + function automatic [NrHarts - 1:0] sv2v_cast_50608; + input reg [NrHarts - 1:0] inp; + sv2v_cast_50608 = inp; + endfunction + assign halted_d = sv2v_cast_50608(halted_d_aligned); + assign resuming_q_aligned = sv2v_cast_8FC1C(resuming_q); + assign resuming_d = sv2v_cast_50608(resuming_d_aligned); + wire fwd_rom_d; + reg fwd_rom_q; + wire [23:0] ac_ar; + function automatic [23:0] sv2v_cast_24; + input reg [23:0] inp; + sv2v_cast_24 = inp; + endfunction + assign ac_ar = sv2v_cast_24(cmd_i[23-:24]); + assign debug_req_o = haltreq_i; + assign halted_o = halted_q; + assign resuming_o = resuming_q; + assign progbuf = progbuf_i; + reg [1:0] state_d; + reg [1:0] state_q; + localparam [1:0] CmdExecuting = 3; + localparam [1:0] Go = 1; + localparam [2:0] Idle = 0; + localparam [1:0] Resume = 2; + localparam [2:0] dm_CmdErrNone = 0; + localparam [2:0] dm_CmdErrNotSupported = 2; + localparam [2:0] dm_CmdErrorException = 3; + localparam [2:0] dm_CmdErrorHaltResume = 4; + always @(*) begin : p_hart_ctrl_queue + cmderror_valid_o = 1'b0; + cmderror_o = dm_CmdErrNone; + state_d = state_q; + go = 1'b0; + resume = 1'b0; + cmdbusy_o = 1'b1; + case (state_q) + Idle: begin + cmdbusy_o = 1'b0; + if ((cmd_valid_i && halted_q_aligned[hartsel]) && !unsupported_command) + state_d = Go; + else if (cmd_valid_i) begin + cmderror_valid_o = 1'b1; + cmderror_o = dm_CmdErrorHaltResume; + end + if (((resumereq_aligned[hartsel] && !resuming_q_aligned[hartsel]) && !haltreq_aligned[hartsel]) && halted_q_aligned[hartsel]) + state_d = Resume; + end + Go: begin + cmdbusy_o = 1'b1; + go = 1'b1; + if (going) + state_d = CmdExecuting; + end + Resume: begin + cmdbusy_o = 1'b1; + resume = 1'b1; + if (resuming_q_aligned[hartsel]) + state_d = Idle; + end + CmdExecuting: begin + cmdbusy_o = 1'b1; + go = 1'b0; + if (halted_aligned[hartsel]) + state_d = Idle; + end + default: + ; + endcase + if (unsupported_command && cmd_valid_i) begin + cmderror_valid_o = 1'b1; + cmderror_o = dm_CmdErrNotSupported; + end + if (exception) begin + cmderror_valid_o = 1'b1; + cmderror_o = dm_CmdErrorException; + end + end + wire [63:0] word_mux; + assign word_mux = (fwd_rom_q ? rom_rdata : rdata_q); + generate + if (BusWidth == 64) begin : gen_word_mux64 + assign rdata_o = word_mux; + end + else begin : gen_word_mux32 + assign rdata_o = (word_enable32_q ? word_mux[32+:32] : word_mux[0+:32]); + end + endgenerate + reg [63:0] data_bits; + reg [63:0] rdata; + function automatic [20:0] sv2v_cast_21; + input reg [20:0] inp; + sv2v_cast_21 = inp; + endfunction + function automatic [$clog2(5'h08) - 1:0] sv2v_cast_D971A; + input reg [$clog2(5'h08) - 1:0] inp; + sv2v_cast_D971A = inp; + endfunction + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [11:0] sv2v_cast_12; + input reg [11:0] inp; + sv2v_cast_12 = inp; + endfunction + localparam [7:0] dm_AccessRegister = 8'h00; + localparam [63:0] dm_HaltAddress = 64'h0000000000000800; + localparam [63:0] dm_ResumeAddress = dm_HaltAddress + 4; + function automatic [31:0] dm_jal; + input reg [4:0] rd; + input reg [20:0] imm; + dm_jal = {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f}; + endfunction + always @(*) begin : p_rw_logic + halted_d_aligned = sv2v_cast_8FC1C(halted_q); + resuming_d_aligned = sv2v_cast_8FC1C(resuming_q); + rdata_d = rdata_q; + data_bits = data_i; + rdata = {64 {1'sb0}}; + data_valid_o = 1'b0; + exception = 1'b0; + halted_aligned = {NrHartsAligned {1'sb0}}; + going = 1'b0; + if (clear_resumeack_i) + resuming_d_aligned[hartsel] = 1'b0; + if (req_i) + if (we_i) begin + if (addr_i[DbgAddressBits - 1:0] == HaltedAddr) begin + halted_aligned[wdata_hartsel] = 1'b1; + halted_d_aligned[wdata_hartsel] = 1'b1; + end + else if (addr_i[DbgAddressBits - 1:0] == GoingAddr) + going = 1'b1; + else if (addr_i[DbgAddressBits - 1:0] == ResumingAddr) begin + halted_d_aligned[wdata_hartsel] = 1'b0; + resuming_d_aligned[wdata_hartsel] = 1'b1; + end + else if (addr_i[DbgAddressBits - 1:0] == ExceptionAddr) + exception = 1'b1; + else if ((DataBaseAddr <= addr_i[DbgAddressBits - 1:0]) && (DataEndAddr >= addr_i[DbgAddressBits - 1:0])) begin + data_valid_o = 1'b1; + begin : sv2v_autoblock_78 + reg signed [31:0] i; + for (i = 0; i < (BusWidth / 8); i = i + 1) + if (be_i[i]) + data_bits[i * 8+:8] = wdata_i[i * 8+:8]; + end + end + end + else if (addr_i[DbgAddressBits - 1:0] == WhereToAddr) begin + if (resumereq_wdata_aligned[wdata_hartsel]) + rdata_d = {32'b00000000000000000000000000000000, dm_jal(1'sb0, sv2v_cast_21(dm_ResumeAddress[11:0]) - sv2v_cast_21(WhereToAddr))}; + if (cmdbusy_o) + if (((cmd_i[31-:8] == dm_AccessRegister) && !ac_ar[17]) && ac_ar[18]) + rdata_d = {32'b00000000000000000000000000000000, dm_jal(1'sb0, sv2v_cast_21(ProgBufBaseAddr) - sv2v_cast_21(WhereToAddr))}; + else + rdata_d = {32'b00000000000000000000000000000000, dm_jal(1'sb0, sv2v_cast_21(AbstractCmdBaseAddr) - sv2v_cast_21(WhereToAddr))}; + end + else if ((DataBaseAddr <= addr_i[DbgAddressBits - 1:0]) && (DataEndAddr >= addr_i[DbgAddressBits - 1:0])) + rdata_d = {data_i[sv2v_cast_D971A((addr_i[DbgAddressBits - 1:3] - DataBaseAddr[DbgAddressBits - 1:3]) + 1'b1) * 32+:32], data_i[sv2v_cast_D971A(addr_i[DbgAddressBits - 1:3] - DataBaseAddr[DbgAddressBits - 1:3]) * 32+:32]}; + else if ((ProgBufBaseAddr <= addr_i[DbgAddressBits - 1:0]) && (ProgBufEndAddr >= addr_i[DbgAddressBits - 1:0])) + rdata_d = progbuf[sv2v_cast_D971A(addr_i[DbgAddressBits - 1:3] - ProgBufBaseAddr[DbgAddressBits - 1:3]) * 64+:64]; + else if ((AbstractCmdBaseAddr <= addr_i[DbgAddressBits - 1:0]) && (AbstractCmdEndAddr >= addr_i[DbgAddressBits - 1:0])) + rdata_d = abstract_cmd[sv2v_cast_3(addr_i[DbgAddressBits - 1:3] - AbstractCmdBaseAddr[DbgAddressBits - 1:3]) * 64+:64]; + else if ((FlagsBaseAddr <= addr_i[DbgAddressBits - 1:0]) && (FlagsEndAddr >= addr_i[DbgAddressBits - 1:0])) begin + if (({addr_i[DbgAddressBits - 1:3], 3'b000} - FlagsBaseAddr[DbgAddressBits - 1:0]) == (sv2v_cast_12(hartsel) & {{DbgAddressBits - 3 {1'b1}}, 3'b000})) + rdata[(sv2v_cast_12(hartsel) & sv2v_cast_12(3'b111)) * 8+:8] = {6'b000000, resume, go}; + rdata_d = rdata; + end + data_o = data_bits; + end + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + localparam [11:0] dm_CSR_DSCRATCH0 = 12'h7b2; + localparam [11:0] dm_CSR_DSCRATCH1 = 12'h7b3; + function automatic [31:0] dm_auipc; + input reg [4:0] rd; + input reg [20:0] imm; + dm_auipc = {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17}; + endfunction + function automatic [31:0] dm_csrr; + input reg [11:0] csr; + input reg [4:0] dest; + dm_csrr = {csr, 5'h00, 3'h2, dest, 7'h73}; + endfunction + function automatic [31:0] dm_csrw; + input reg [11:0] csr; + input reg [4:0] rs1; + dm_csrw = {csr, rs1, 3'h1, 5'h00, 7'h73}; + endfunction + function automatic [31:0] dm_ebreak; + input _sv2v_unused; + dm_ebreak = 32'h00100073; + endfunction + function automatic [31:0] dm_float_load; + input reg [2:0] size; + input reg [4:0] dest; + input reg [4:0] base; + input reg [11:0] offset; + dm_float_load = {offset[11:0], base, size, dest, 7'b0000111}; + endfunction + function automatic [31:0] dm_float_store; + input reg [2:0] size; + input reg [4:0] src; + input reg [4:0] base; + input reg [11:0] offset; + dm_float_store = {offset[11:5], src, base, size, offset[4:0], 7'b0100111}; + endfunction + function automatic [31:0] dm_illegal; + input _sv2v_unused; + dm_illegal = 32'h00000000; + endfunction + function automatic [31:0] dm_load; + input reg [2:0] size; + input reg [4:0] dest; + input reg [4:0] base; + input reg [11:0] offset; + dm_load = {offset[11:0], base, size, dest, 7'h03}; + endfunction + function automatic [31:0] dm_nop; + input _sv2v_unused; + dm_nop = 32'h00000013; + endfunction + function automatic [31:0] dm_slli; + input reg [4:0] rd; + input reg [4:0] rs1; + input reg [5:0] shamt; + dm_slli = {6'b000000, shamt[5:0], rs1, 3'h1, rd, 7'h13}; + endfunction + function automatic [31:0] dm_srli; + input reg [4:0] rd; + input reg [4:0] rs1; + input reg [5:0] shamt; + dm_srli = {6'b000000, shamt[5:0], rs1, 3'h5, rd, 7'h13}; + endfunction + function automatic [31:0] dm_store; + input reg [2:0] size; + input reg [4:0] src; + input reg [4:0] base; + input reg [11:0] offset; + dm_store = {offset[11:5], src, base, size, offset[4:0], 7'h23}; + endfunction + always @(*) begin : p_abstract_cmd_rom + unsupported_command = 1'b0; + abstract_cmd[31-:32] = dm_illegal(0); + abstract_cmd[63-:32] = (HasSndScratch ? dm_auipc(5'd10, 1'sb0) : dm_nop(0)); + abstract_cmd[95-:32] = (HasSndScratch ? dm_srli(5'd10, 5'd10, 6'd12) : dm_nop(0)); + abstract_cmd[127-:32] = (HasSndScratch ? dm_slli(5'd10, 5'd10, 6'd12) : dm_nop(0)); + abstract_cmd[159-:32] = dm_nop(0); + abstract_cmd[191-:32] = dm_nop(0); + abstract_cmd[223-:32] = dm_nop(0); + abstract_cmd[255-:32] = dm_nop(0); + abstract_cmd[287-:32] = (HasSndScratch ? dm_csrr(dm_CSR_DSCRATCH1, 5'd10) : dm_nop(0)); + abstract_cmd[319-:32] = dm_ebreak(0); + abstract_cmd[320+:192] = {192 {1'sb0}}; + case (cmd_i[31-:8]) + dm_AccessRegister: begin + if (((sv2v_cast_32(ac_ar[22-:3]) < MaxAar) && ac_ar[17]) && ac_ar[16]) begin + abstract_cmd[31-:32] = (HasSndScratch ? dm_csrr(dm_CSR_DSCRATCH1, 5'd10) : dm_nop(0)); + if (ac_ar[15:14] != {2 {1'sb0}}) begin + abstract_cmd[31-:32] = dm_ebreak(0); + unsupported_command = 1'b1; + end + else if (((HasSndScratch && ac_ar[12]) && !ac_ar[5]) && (ac_ar[4:0] == 5'd10)) begin + abstract_cmd[159-:32] = dm_csrw(dm_CSR_DSCRATCH0, 5'd8); + abstract_cmd[191-:32] = dm_load(ac_ar[22-:3], 5'd8, LoadBaseAddr, dm_DataAddr); + abstract_cmd[223-:32] = dm_csrw(dm_CSR_DSCRATCH1, 5'd8); + abstract_cmd[255-:32] = dm_csrr(dm_CSR_DSCRATCH0, 5'd8); + end + else if (ac_ar[12]) begin + if (ac_ar[5]) + abstract_cmd[159-:32] = dm_float_load(ac_ar[22-:3], ac_ar[4:0], LoadBaseAddr, dm_DataAddr); + else + abstract_cmd[159-:32] = dm_load(ac_ar[22-:3], ac_ar[4:0], LoadBaseAddr, dm_DataAddr); + end + else begin + abstract_cmd[159-:32] = dm_csrw(dm_CSR_DSCRATCH0, 5'd8); + abstract_cmd[191-:32] = dm_load(ac_ar[22-:3], 5'd8, LoadBaseAddr, dm_DataAddr); + abstract_cmd[223-:32] = dm_csrw(sv2v_cast_12(ac_ar[11:0]), 5'd8); + abstract_cmd[255-:32] = dm_csrr(dm_CSR_DSCRATCH0, 5'd8); + end + end + else if (((sv2v_cast_32(ac_ar[22-:3]) < MaxAar) && ac_ar[17]) && !ac_ar[16]) begin + abstract_cmd[31-:32] = (HasSndScratch ? dm_csrr(dm_CSR_DSCRATCH1, LoadBaseAddr) : dm_nop(0)); + if (ac_ar[15:14] != {2 {1'sb0}}) begin + abstract_cmd[31-:32] = dm_ebreak(0); + unsupported_command = 1'b1; + end + else if (((HasSndScratch && ac_ar[12]) && !ac_ar[5]) && (ac_ar[4:0] == 5'd10)) begin + abstract_cmd[159-:32] = dm_csrw(dm_CSR_DSCRATCH0, 5'd8); + abstract_cmd[191-:32] = dm_csrr(dm_CSR_DSCRATCH1, 5'd8); + abstract_cmd[223-:32] = dm_store(ac_ar[22-:3], 5'd8, LoadBaseAddr, dm_DataAddr); + abstract_cmd[255-:32] = dm_csrr(dm_CSR_DSCRATCH0, 5'd8); + end + else if (ac_ar[12]) begin + if (ac_ar[5]) + abstract_cmd[159-:32] = dm_float_store(ac_ar[22-:3], ac_ar[4:0], LoadBaseAddr, dm_DataAddr); + else + abstract_cmd[159-:32] = dm_store(ac_ar[22-:3], ac_ar[4:0], LoadBaseAddr, dm_DataAddr); + end + else begin + abstract_cmd[159-:32] = dm_csrw(dm_CSR_DSCRATCH0, 5'd8); + abstract_cmd[191-:32] = dm_csrr(sv2v_cast_12(ac_ar[11:0]), 5'd8); + abstract_cmd[223-:32] = dm_store(ac_ar[22-:3], 5'd8, LoadBaseAddr, dm_DataAddr); + abstract_cmd[255-:32] = dm_csrr(dm_CSR_DSCRATCH0, 5'd8); + end + end + else if ((sv2v_cast_32(ac_ar[22-:3]) >= MaxAar) || (ac_ar[19] == 1'b1)) begin + abstract_cmd[31-:32] = dm_ebreak(0); + unsupported_command = 1'b1; + end + if (ac_ar[18] && !unsupported_command) + abstract_cmd[319-:32] = dm_nop(0); + end + default: begin + abstract_cmd[31-:32] = dm_ebreak(0); + unsupported_command = 1'b1; + end + endcase + end + wire [63:0] rom_addr; + function automatic [63:0] sv2v_cast_64; + input reg [63:0] inp; + sv2v_cast_64 = inp; + endfunction + assign rom_addr = sv2v_cast_64(addr_i); + generate + if (HasSndScratch) begin : gen_rom_snd_scratch + debug_rom i_debug_rom( + .clk_i(clk_i), + .req_i(req_i), + .addr_i(rom_addr), + .rdata_o(rom_rdata) + ); + end + /*else begin : gen_rom_one_scratch + debug_rom_one_scratch i_debug_rom( + .clk_i(clk_i), + .req_i(req_i), + .addr_i(rom_addr), + .rdata_o(rom_rdata) + ); + end*/ + endgenerate + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + assign fwd_rom_d = sv2v_cast_1(addr_i[DbgAddressBits - 1:0] >= dm_HaltAddress[DbgAddressBits - 1:0]); + always @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) begin + fwd_rom_q <= 1'b0; + rdata_q <= {64 {1'sb0}}; + state_q <= Idle; + word_enable32_q <= 1'b0; + end + else begin + fwd_rom_q <= fwd_rom_d; + rdata_q <= rdata_d; + state_q <= state_d; + word_enable32_q <= addr_i[2]; + end + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + halted_q <= 1'b0; + resuming_q <= 1'b0; + end + else begin + halted_q <= SelectableHarts & halted_d; + resuming_q <= SelectableHarts & resuming_d; + end +endmodule +module dm_sba ( + clk_i, + rst_ni, + dmactive_i, + master_req_o, + master_add_o, + master_we_o, + master_wdata_o, + master_be_o, + master_gnt_i, + master_r_valid_i, + master_r_rdata_i, + sbaddress_i, + sbaddress_write_valid_i, + sbreadonaddr_i, + sbaddress_o, + sbautoincrement_i, + sbaccess_i, + sbreadondata_i, + sbdata_i, + sbdata_read_valid_i, + sbdata_write_valid_i, + sbdata_o, + sbdata_valid_o, + sbbusy_o, + sberror_valid_o, + sberror_o +); + parameter [31:0] BusWidth = 32; + input wire clk_i; + input wire rst_ni; + input wire dmactive_i; + output wire master_req_o; + output wire [BusWidth - 1:0] master_add_o; + output wire master_we_o; + output wire [BusWidth - 1:0] master_wdata_o; + output wire [(BusWidth / 8) - 1:0] master_be_o; + input wire master_gnt_i; + input wire master_r_valid_i; + input wire [BusWidth - 1:0] master_r_rdata_i; + input wire [BusWidth - 1:0] sbaddress_i; + input wire sbaddress_write_valid_i; + input wire sbreadonaddr_i; + output reg [BusWidth - 1:0] sbaddress_o; + input wire sbautoincrement_i; + input wire [2:0] sbaccess_i; + input wire sbreadondata_i; + input wire [BusWidth - 1:0] sbdata_i; + input wire sbdata_read_valid_i; + input wire sbdata_write_valid_i; + output wire [BusWidth - 1:0] sbdata_o; + output wire sbdata_valid_o; + output wire sbbusy_o; + output reg sberror_valid_o; + output reg [2:0] sberror_o; + reg [2:0] state_d; + reg [2:0] state_q; + reg [BusWidth - 1:0] address; + reg req; + wire gnt; + reg we; + reg [(BusWidth / 8) - 1:0] be; + reg [$clog2(BusWidth / 8) - 1:0] be_idx; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + localparam [2:0] Idle = 0; + assign sbbusy_o = sv2v_cast_1(state_q != Idle); + localparam [2:0] Read = 1; + localparam [2:0] WaitRead = 3; + localparam [2:0] WaitWrite = 4; + localparam [2:0] Write = 2; + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + always @(*) begin : p_fsm + req = 1'b0; + address = sbaddress_i; + we = 1'b0; + be = {BusWidth / 8 {1'sb0}}; + be_idx = sbaddress_i[$clog2(BusWidth / 8) - 1:0]; + sberror_o = {3 {1'sb0}}; + sberror_valid_o = 1'b0; + sbaddress_o = sbaddress_i; + state_d = state_q; + case (state_q) + Idle: begin + if (sbaddress_write_valid_i && sbreadonaddr_i) + state_d = Read; + if (sbdata_write_valid_i) + state_d = Write; + if (sbdata_read_valid_i && sbreadondata_i) + state_d = Read; + end + Read: begin + req = 1'b1; + if (gnt) + state_d = WaitRead; + end + Write: begin + req = 1'b1; + we = 1'b1; + case (sbaccess_i) + 3'b000: be[be_idx] = 1'sb1; + 3'b001: be[sv2v_cast_32_signed({be_idx[$clog2(BusWidth / 8) - 1:1], 1'b0})+:2] = {2 {1'sb1}}; + 3'b010: + if (BusWidth == 32'd64) + be[sv2v_cast_32_signed({be_idx[$clog2(BusWidth / 8) - 1], 2'h0})+:4] = {4 {1'sb1}}; + else + be = {BusWidth / 8 {1'sb1}}; + 3'b011: be = {BusWidth / 8 {1'sb1}}; + default: + ; + endcase + if (gnt) + state_d = WaitWrite; + end + WaitRead: + if (sbdata_valid_o) begin + state_d = Idle; + if (sbautoincrement_i) + sbaddress_o = sbaddress_i + (32'h00000001 << sbaccess_i); + end + WaitWrite: + if (sbdata_valid_o) begin + state_d = Idle; + if (sbautoincrement_i) + sbaddress_o = sbaddress_i + (32'h00000001 << sbaccess_i); + end + default: state_d = Idle; + endcase + if ((sbaccess_i > 3) && (state_q != Idle)) begin + req = 1'b0; + state_d = Idle; + sberror_valid_o = 1'b1; + sberror_o = 3'd3; + end + end + always @(posedge clk_i or negedge rst_ni) begin : p_regs + if (!rst_ni) + state_q <= Idle; + else + state_q <= state_d; + end + assign master_req_o = req; + assign master_add_o = address[BusWidth - 1:0]; + assign master_we_o = we; + assign master_wdata_o = sbdata_i[BusWidth - 1:0]; + assign master_be_o = be[(BusWidth / 8) - 1:0]; + assign gnt = master_gnt_i; + assign sbdata_valid_o = master_r_valid_i; + assign sbdata_o = master_r_rdata_i[BusWidth - 1:0]; +endmodule +module dmi_cdc ( + tck_i, + trst_ni, + jtag_dmi_req_i, + jtag_dmi_ready_o, + jtag_dmi_valid_i, + jtag_dmi_resp_o, + jtag_dmi_valid_o, + jtag_dmi_ready_i, + clk_i, + rst_ni, + core_dmi_req_o, + core_dmi_valid_o, + core_dmi_ready_i, + core_dmi_resp_i, + core_dmi_ready_o, + core_dmi_valid_i +); + input wire tck_i; + input wire trst_ni; + input wire [40:0] jtag_dmi_req_i; + output wire jtag_dmi_ready_o; + input wire jtag_dmi_valid_i; + output wire [33:0] jtag_dmi_resp_o; + output wire jtag_dmi_valid_o; + input wire jtag_dmi_ready_i; + input wire clk_i; + input wire rst_ni; + output wire [40:0] core_dmi_req_o; + output wire core_dmi_valid_o; + input wire core_dmi_ready_i; + input wire [33:0] core_dmi_resp_i; + output wire core_dmi_ready_o; + input wire core_dmi_valid_i; + prim_fifo_async #( + .Width(41), + .Depth(4) + ) i_cdc_req( + .clk_wr_i(tck_i), + .rst_wr_ni(trst_ni), + .wvalid_i(jtag_dmi_valid_i), + .wready_o(jtag_dmi_ready_o), + .wdata_i(jtag_dmi_req_i), + .wdepth_o(), + .clk_rd_i(clk_i), + .rst_rd_ni(rst_ni), + .rvalid_o(core_dmi_valid_o), + .rready_i(core_dmi_ready_i), + .rdata_o(core_dmi_req_o), + .rdepth_o() + ); + prim_fifo_async #( + .Width(34), + .Depth(4) + ) i_cdc_resp( + .clk_wr_i(clk_i), + .rst_wr_ni(rst_ni), + .wvalid_i(core_dmi_valid_i), + .wready_o(core_dmi_ready_o), + .wdata_i(core_dmi_resp_i), + .wdepth_o(), + .clk_rd_i(tck_i), + .rst_rd_ni(trst_ni), + .rvalid_o(jtag_dmi_valid_o), + .rready_i(jtag_dmi_ready_i), + .rdata_o(jtag_dmi_resp_o), + .rdepth_o() + ); +endmodule +module dmi_jtag ( + clk_i, + rst_ni, + testmode_i, + dmi_rst_no, + dmi_req_o, + dmi_req_valid_o, + dmi_req_ready_i, + dmi_resp_i, + dmi_resp_ready_o, + dmi_resp_valid_i, + tck_i, + tms_i, + trst_ni, + td_i, + td_o, + tdo_oe_o +); + parameter [31:0] IdcodeValue = 32'h00000001; + input wire clk_i; + input wire rst_ni; + input wire testmode_i; + output wire dmi_rst_no; + output wire [40:0] dmi_req_o; + output wire dmi_req_valid_o; + input wire dmi_req_ready_i; + input wire [33:0] dmi_resp_i; + output wire dmi_resp_ready_o; + input wire dmi_resp_valid_i; + input wire tck_i; + input wire tms_i; + input wire trst_ni; + input wire td_i; + output wire td_o; + output wire tdo_oe_o; + assign dmi_rst_no = rst_ni; + wire test_logic_reset; + wire shift_dr; + wire update_dr; + wire capture_dr; + wire dmi_access; + wire dtmcs_select; + wire dmi_reset; + wire dmi_tdi; + wire dmi_tdo; + wire [40:0] dmi_req; + wire dmi_req_ready; + reg dmi_req_valid; + wire [33:0] dmi_resp; + wire dmi_resp_valid; + wire dmi_resp_ready; + reg [2:0] state_d; + reg [2:0] state_q; + reg [40:0] dr_d; + reg [40:0] dr_q; + reg [6:0] address_d; + reg [6:0] address_q; + reg [31:0] data_d; + reg [31:0] data_q; + wire [40:0] dmi; + function automatic [40:0] sv2v_cast_41; + input reg [40:0] inp; + sv2v_cast_41 = inp; + endfunction + assign dmi = sv2v_cast_41(dr_q); + assign dmi_req[40-:7] = address_q; + assign dmi_req[31-:32] = data_q; + localparam [2:0] Write = 3; + localparam [1:0] dm_DTM_READ = 2'h1; + localparam [1:0] dm_DTM_WRITE = 2'h2; + assign dmi_req[33-:2] = (state_q == Write ? dm_DTM_WRITE : dm_DTM_READ); + assign dmi_resp_ready = 1'b1; + reg error_dmi_busy; + reg [1:0] error_d; + reg [1:0] error_q; + localparam [1:0] DMIBusy = 2'h3; + localparam [1:0] DMINoError = 2'h0; + localparam [2:0] Idle = 0; + localparam [2:0] Read = 1; + localparam [2:0] WaitReadValid = 2; + function automatic [1:0] sv2v_cast_2; + input reg [1:0] inp; + sv2v_cast_2 = inp; + endfunction + always @(*) begin : p_fsm + error_dmi_busy = 1'b0; + state_d = state_q; + address_d = address_q; + data_d = data_q; + error_d = error_q; + dmi_req_valid = 1'b0; + case (state_q) + Idle: + if ((dmi_access && update_dr) && (error_q == DMINoError)) begin + address_d = dmi[40-:7]; + data_d = dmi[33-:32]; + if (sv2v_cast_2(dmi[1-:2]) == dm_DTM_READ) + state_d = Read; + else if (sv2v_cast_2(dmi[1-:2]) == dm_DTM_WRITE) + state_d = Write; + end + Read: begin + dmi_req_valid = 1'b1; + if (dmi_req_ready) + state_d = WaitReadValid; + end + WaitReadValid: + if (dmi_resp_valid) begin + data_d = dmi_resp[33-:32]; + state_d = Idle; + end + Write: begin + dmi_req_valid = 1'b1; + if (dmi_req_ready) + state_d = Idle; + end + default: + if (dmi_resp_valid) + state_d = Idle; + endcase + if (update_dr && (state_q != Idle)) + error_dmi_busy = 1'b1; + if (capture_dr && |{state_q == Read, state_q == WaitReadValid}) + error_dmi_busy = 1'b1; + if (error_dmi_busy) + error_d = DMIBusy; + if (dmi_reset && dtmcs_select) + error_d = DMINoError; + end + assign dmi_tdo = dr_q[0]; + always @(*) begin : p_shift + dr_d = dr_q; + if (capture_dr) + if (dmi_access) + if ((error_q == DMINoError) && !error_dmi_busy) + dr_d = {address_q, data_q, DMINoError}; + else if ((error_q == DMIBusy) || error_dmi_busy) + dr_d = {address_q, data_q, DMIBusy}; + if (shift_dr) + if (dmi_access) + dr_d = {dmi_tdi, dr_q[40:1]}; + if (test_logic_reset) + dr_d = {41 {1'sb0}}; + end + always @(posedge tck_i or negedge trst_ni) begin : p_regs + if (!trst_ni) begin + dr_q <= {41 {1'sb0}}; + state_q <= Idle; + address_q <= {7 {1'sb0}}; + data_q <= {32 {1'sb0}}; + error_q <= DMINoError; + end + else begin + dr_q <= dr_d; + state_q <= state_d; + address_q <= address_d; + data_q <= data_d; + error_q <= error_d; + end + end + dmi_jtag_tap #( + .IrLength(5), + .IdcodeValue(IdcodeValue) + ) i_dmi_jtag_tap( + .tck_i(tck_i), + .tms_i(tms_i), + .trst_ni(trst_ni), + .td_i(td_i), + .td_o(td_o), + .tdo_oe_o(tdo_oe_o), + .testmode_i(testmode_i), + .test_logic_reset_o(test_logic_reset), + .shift_dr_o(shift_dr), + .update_dr_o(update_dr), + .capture_dr_o(capture_dr), + .dmi_access_o(dmi_access), + .dtmcs_select_o(dtmcs_select), + .dmi_reset_o(dmi_reset), + .dmi_error_i(error_q), + .dmi_tdi_o(dmi_tdi), + .dmi_tdo_i(dmi_tdo) + ); + dmi_cdc i_dmi_cdc( + .tck_i(tck_i), + .trst_ni(trst_ni), + .jtag_dmi_req_i(dmi_req), + .jtag_dmi_ready_o(dmi_req_ready), + .jtag_dmi_valid_i(dmi_req_valid), + .jtag_dmi_resp_o(dmi_resp), + .jtag_dmi_valid_o(dmi_resp_valid), + .jtag_dmi_ready_i(dmi_resp_ready), + .clk_i(clk_i), + .rst_ni(rst_ni), + .core_dmi_req_o(dmi_req_o), + .core_dmi_valid_o(dmi_req_valid_o), + .core_dmi_ready_i(dmi_req_ready_i), + .core_dmi_resp_i(dmi_resp_i), + .core_dmi_ready_o(dmi_resp_ready_o), + .core_dmi_valid_i(dmi_resp_valid_i) + ); +endmodule +module dmi_jtag_tap ( + tck_i, + tms_i, + trst_ni, + td_i, + td_o, + tdo_oe_o, + testmode_i, + test_logic_reset_o, + shift_dr_o, + update_dr_o, + capture_dr_o, + dmi_access_o, + dtmcs_select_o, + dmi_reset_o, + dmi_error_i, + dmi_tdi_o, + dmi_tdo_i +); + parameter [31:0] IrLength = 5; + parameter [31:0] IdcodeValue = 32'h00000001; + input wire tck_i; + input wire tms_i; + input wire trst_ni; + input wire td_i; + output reg td_o; + output reg tdo_oe_o; + input wire testmode_i; + output reg test_logic_reset_o; + output reg shift_dr_o; + output reg update_dr_o; + output reg capture_dr_o; + output reg dmi_access_o; + output reg dtmcs_select_o; + output wire dmi_reset_o; + input wire [1:0] dmi_error_i; + output wire dmi_tdi_o; + input wire dmi_tdo_i; + assign dmi_tdi_o = td_i; + reg [3:0] tap_state_q; + reg [3:0] tap_state_d; + reg [IrLength - 1:0] jtag_ir_shift_d; + reg [IrLength - 1:0] jtag_ir_shift_q; + reg [IrLength - 1:0] jtag_ir_d; + reg [IrLength - 1:0] jtag_ir_q; + reg capture_ir; + reg shift_ir; + reg update_ir; + function automatic [IrLength - 1:0] sv2v_cast_AFF3E; + input reg [IrLength - 1:0] inp; + sv2v_cast_AFF3E = inp; + endfunction + function automatic [IrLength - 1:0] sv2v_cast_42A93; + input reg [IrLength - 1:0] inp; + sv2v_cast_42A93 = inp; + endfunction + localparam [IrLength - 1:0] IDCODE = 'h1; + always @(*) begin : p_jtag + jtag_ir_shift_d = jtag_ir_shift_q; + jtag_ir_d = jtag_ir_q; + if (shift_ir) + jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength - 1:1]}; + if (capture_ir) + jtag_ir_shift_d = sv2v_cast_AFF3E(4'b0101); + if (update_ir) + jtag_ir_d = sv2v_cast_42A93(jtag_ir_shift_q); + if (test_logic_reset_o) begin + jtag_ir_shift_d = {IrLength {1'sb0}}; + jtag_ir_d = IDCODE; + end + end + always @(posedge tck_i or negedge trst_ni) begin : p_jtag_ir_reg + if (!trst_ni) begin + jtag_ir_shift_q <= {IrLength {1'sb0}}; + jtag_ir_q <= IDCODE; + end + else begin + jtag_ir_shift_q <= jtag_ir_shift_d; + jtag_ir_q <= jtag_ir_d; + end + end + reg [31:0] idcode_d; + reg [31:0] idcode_q; + reg idcode_select; + reg bypass_select; + reg [31:0] dtmcs_d; + reg [31:0] dtmcs_q; + reg bypass_d; + reg bypass_q; + assign dmi_reset_o = dtmcs_q[16]; + function automatic [1:0] sv2v_cast_2; + input reg [1:0] inp; + sv2v_cast_2 = inp; + endfunction + function automatic [30:0] sv2v_cast_31; + input reg [30:0] inp; + sv2v_cast_31 = inp; + endfunction + always @(*) begin + idcode_d = idcode_q; + bypass_d = bypass_q; + dtmcs_d = dtmcs_q; + if (capture_dr_o) begin + if (idcode_select) + idcode_d = IdcodeValue; + if (bypass_select) + bypass_d = 1'b0; + if (dtmcs_select_o) + dtmcs_d = {14'b00000000000000, 1'b0, 1'b0, 1'sb0, 3'd1, sv2v_cast_2(dmi_error_i), 6'd7, 4'd1}; + end + if (shift_dr_o) begin + if (idcode_select) + idcode_d = {td_i, sv2v_cast_31(idcode_q >> 1)}; + if (bypass_select) + bypass_d = td_i; + if (dtmcs_select_o) + dtmcs_d = {td_i, sv2v_cast_31(dtmcs_q >> 1)}; + end + if (test_logic_reset_o) begin + idcode_d = IdcodeValue; + bypass_d = 1'b0; + end + end + localparam [IrLength - 1:0] BYPASS0 = 'h0; + localparam [IrLength - 1:0] BYPASS1 = 'h1f; + localparam [IrLength - 1:0] DMIACCESS = 'h11; + localparam [IrLength - 1:0] DTMCSR = 'h10; + always @(*) begin : p_data_reg_sel + dmi_access_o = 1'b0; + dtmcs_select_o = 1'b0; + idcode_select = 1'b0; + bypass_select = 1'b0; + case (jtag_ir_q) + BYPASS0: bypass_select = 1'b1; + IDCODE: idcode_select = 1'b1; + DTMCSR: dtmcs_select_o = 1'b1; + DMIACCESS: dmi_access_o = 1'b1; + BYPASS1: bypass_select = 1'b1; + default: bypass_select = 1'b1; + endcase + end + reg tdo_mux; + always @(*) begin : p_out_sel + if (shift_ir) + tdo_mux = jtag_ir_shift_q[0]; + else + case (jtag_ir_q) + IDCODE: tdo_mux = idcode_q[0]; + DTMCSR: tdo_mux = dtmcs_q[0]; + DMIACCESS: tdo_mux = dmi_tdo_i; + default: tdo_mux = bypass_q; + endcase + end + wire tck_n; + prim_generic_clock_inv #(.HasScanMode(1'b1)) i_tck_inv( + .clk_i(tck_i), + .clk_no(tck_n), + .scanmode_i(testmode_i) + ); + always @(posedge tck_n or negedge trst_ni) begin : p_tdo_regs + if (!trst_ni) begin + td_o <= 1'b0; + tdo_oe_o <= 1'b0; + end + else begin + td_o <= tdo_mux; + tdo_oe_o <= shift_ir | shift_dr_o; + end + end + localparam [3:0] CaptureDr = 3; + localparam [3:0] CaptureIr = 10; + localparam [3:0] Exit1Dr = 5; + localparam [3:0] Exit1Ir = 12; + localparam [3:0] Exit2Dr = 7; + localparam [3:0] Exit2Ir = 14; + localparam [3:0] PauseDr = 6; + localparam [3:0] PauseIr = 13; + localparam [3:0] RunTestIdle = 1; + localparam [3:0] SelectDrScan = 2; + localparam [3:0] SelectIrScan = 9; + localparam [3:0] ShiftDr = 4; + localparam [3:0] ShiftIr = 11; + localparam [3:0] TestLogicReset = 0; + localparam [3:0] UpdateDr = 8; + localparam [3:0] UpdateIr = 15; + always @(*) begin : p_tap_fsm + test_logic_reset_o = 1'b0; + capture_dr_o = 1'b0; + shift_dr_o = 1'b0; + update_dr_o = 1'b0; + capture_ir = 1'b0; + shift_ir = 1'b0; + update_ir = 1'b0; + case (tap_state_q) + TestLogicReset: begin + tap_state_d = (tms_i ? TestLogicReset : RunTestIdle); + test_logic_reset_o = 1'b1; + end + RunTestIdle: tap_state_d = (tms_i ? SelectDrScan : RunTestIdle); + SelectDrScan: tap_state_d = (tms_i ? SelectIrScan : CaptureDr); + CaptureDr: begin + capture_dr_o = 1'b1; + tap_state_d = (tms_i ? Exit1Dr : ShiftDr); + end + ShiftDr: begin + shift_dr_o = 1'b1; + tap_state_d = (tms_i ? Exit1Dr : ShiftDr); + end + Exit1Dr: tap_state_d = (tms_i ? UpdateDr : PauseDr); + PauseDr: tap_state_d = (tms_i ? Exit2Dr : PauseDr); + Exit2Dr: tap_state_d = (tms_i ? UpdateDr : ShiftDr); + UpdateDr: begin + update_dr_o = 1'b1; + tap_state_d = (tms_i ? SelectDrScan : RunTestIdle); + end + SelectIrScan: tap_state_d = (tms_i ? TestLogicReset : CaptureIr); + CaptureIr: begin + capture_ir = 1'b1; + tap_state_d = (tms_i ? Exit1Ir : ShiftIr); + end + ShiftIr: begin + shift_ir = 1'b1; + tap_state_d = (tms_i ? Exit1Ir : ShiftIr); + end + Exit1Ir: tap_state_d = (tms_i ? UpdateIr : PauseIr); + PauseIr: tap_state_d = (tms_i ? Exit2Ir : PauseIr); + Exit2Ir: tap_state_d = (tms_i ? UpdateIr : ShiftIr); + UpdateIr: begin + update_ir = 1'b1; + tap_state_d = (tms_i ? SelectDrScan : RunTestIdle); + end + default: + ; + endcase + end + always @(posedge tck_i or negedge trst_ni) begin : p_regs + if (!trst_ni) begin + tap_state_q <= RunTestIdle; + idcode_q <= IdcodeValue; + bypass_q <= 1'b0; + dtmcs_q <= {32 {1'sb0}}; + end + else begin + tap_state_q <= tap_state_d; + idcode_q <= idcode_d; + bypass_q <= bypass_d; + dtmcs_q <= dtmcs_d; + end + end +endmodule +module rv_dm ( + clk_i, + rst_ni, + testmode_i, + ndmreset_o, + dmactive_o, + debug_req_o, + unavailable_i, + tl_d_i, + tl_d_o, + tl_h_o, + tl_h_i, + tck_i, + tms_i, + trst_ni, + td_i, + td_o, + tdo_oe_o +); + parameter signed [31:0] NrHarts = 1; + parameter [31:0] IdcodeValue = 32'h00000001; + input wire clk_i; + input wire rst_ni; + input wire testmode_i; + output wire ndmreset_o; + output wire dmactive_o; + output wire [NrHarts - 1:0] debug_req_o; + input wire [NrHarts - 1:0] unavailable_i; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_d_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_d_o; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_h_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_h_i; + input wire tck_i; + input wire tms_i; + input wire trst_ni; + input wire td_i; + output wire td_o; + output wire tdo_oe_o; + localparam signed [31:0] BusWidth = 32; + localparam [NrHarts - 1:0] SelectableHarts = {NrHarts {1'b1}}; + wire [(NrHarts * 32) - 1:0] hartinfo; + wire [NrHarts - 1:0] halted; + wire [NrHarts - 1:0] resumeack; + wire [NrHarts - 1:0] haltreq; + wire [NrHarts - 1:0] resumereq; + wire clear_resumeack; + wire cmd_valid; + wire [31:0] cmd; + wire cmderror_valid; + wire [2:0] cmderror; + wire cmdbusy; + localparam [4:0] dm_ProgBufSize = 5'h08; + wire [(dm_ProgBufSize * 32) - 1:0] progbuf; + localparam [3:0] dm_DataCount = 4'h2; + wire [(dm_DataCount * 32) - 1:0] data_csrs_mem; + wire [(dm_DataCount * 32) - 1:0] data_mem_csrs; + wire data_valid; + wire [19:0] hartsel; + wire [BusWidth - 1:0] sbaddress_csrs_sba; + wire [BusWidth - 1:0] sbaddress_sba_csrs; + wire sbaddress_write_valid; + wire sbreadonaddr; + wire sbautoincrement; + wire [2:0] sbaccess; + wire sbreadondata; + wire [BusWidth - 1:0] sbdata_write; + wire sbdata_read_valid; + wire sbdata_write_valid; + wire [BusWidth - 1:0] sbdata_read; + wire sbdata_valid; + wire sbbusy; + wire sberror_valid; + wire [2:0] sberror; + wire [40:0] dmi_req; + wire [33:0] dmi_rsp; + wire dmi_req_valid; + wire dmi_req_ready; + wire dmi_rsp_valid; + wire dmi_rsp_ready; + wire dmi_rst_n; + localparam [11:0] dm_DataAddr = 12'h380; + function automatic [3:0] sv2v_cast_4; + input reg [3:0] inp; + sv2v_cast_4 = inp; + endfunction + function automatic [11:0] sv2v_cast_12; + input reg [11:0] inp; + sv2v_cast_12 = inp; + endfunction + localparam [31:0] DebugHartInfo = {8'b00000000, 4'd2, 3'd0, 1'b1, sv2v_cast_4(dm_DataCount), sv2v_cast_12(dm_DataAddr)}; + generate + genvar i; + for (i = 0; i < NrHarts; i = i + 1) begin : gen_dm_hart_ctrl + assign hartinfo[i * 32+:32] = DebugHartInfo; + end + endgenerate + dm_csrs #( + .NrHarts(NrHarts), + .BusWidth(BusWidth), + .SelectableHarts(SelectableHarts) + ) i_dm_csrs( + .clk_i(clk_i), + .rst_ni(rst_ni), + .testmode_i(testmode_i), + .dmi_rst_ni(dmi_rst_n), + .dmi_req_valid_i(dmi_req_valid), + .dmi_req_ready_o(dmi_req_ready), + .dmi_req_i(dmi_req), + .dmi_resp_valid_o(dmi_rsp_valid), + .dmi_resp_ready_i(dmi_rsp_ready), + .dmi_resp_o(dmi_rsp), + .ndmreset_o(ndmreset_o), + .dmactive_o(dmactive_o), + .hartsel_o(hartsel), + .hartinfo_i(hartinfo), + .halted_i(halted), + .unavailable_i(unavailable_i), + .resumeack_i(resumeack), + .haltreq_o(haltreq), + .resumereq_o(resumereq), + .clear_resumeack_o(clear_resumeack), + .cmd_valid_o(cmd_valid), + .cmd_o(cmd), + .cmderror_valid_i(cmderror_valid), + .cmderror_i(cmderror), + .cmdbusy_i(cmdbusy), + .progbuf_o(progbuf), + .data_i(data_mem_csrs), + .data_valid_i(data_valid), + .data_o(data_csrs_mem), + .sbaddress_o(sbaddress_csrs_sba), + .sbaddress_i(sbaddress_sba_csrs), + .sbaddress_write_valid_o(sbaddress_write_valid), + .sbreadonaddr_o(sbreadonaddr), + .sbautoincrement_o(sbautoincrement), + .sbaccess_o(sbaccess), + .sbreadondata_o(sbreadondata), + .sbdata_o(sbdata_write), + .sbdata_read_valid_o(sbdata_read_valid), + .sbdata_write_valid_o(sbdata_write_valid), + .sbdata_i(sbdata_read), + .sbdata_valid_i(sbdata_valid), + .sbbusy_i(sbbusy), + .sberror_valid_i(sberror_valid), + .sberror_i(sberror) + ); + wire host_req; + wire [BusWidth - 1:0] host_add; + wire host_we; + wire [BusWidth - 1:0] host_wdata; + wire [(BusWidth / 8) - 1:0] host_be; + wire host_gnt; + wire host_r_valid; + wire [BusWidth - 1:0] host_r_rdata; + wire host_r_err; + dm_sba #(.BusWidth(BusWidth)) i_dm_sba( + .clk_i(clk_i), + .rst_ni(rst_ni), + .master_req_o(host_req), + .master_add_o(host_add), + .master_we_o(host_we), + .master_wdata_o(host_wdata), + .master_be_o(host_be), + .master_gnt_i(host_gnt), + .master_r_valid_i(host_r_valid), + .master_r_rdata_i(host_r_rdata), + .dmactive_i(dmactive_o), + .sbaddress_i(sbaddress_csrs_sba), + .sbaddress_o(sbaddress_sba_csrs), + .sbaddress_write_valid_i(sbaddress_write_valid), + .sbreadonaddr_i(sbreadonaddr), + .sbautoincrement_i(sbautoincrement), + .sbaccess_i(sbaccess), + .sbreadondata_i(sbreadondata), + .sbdata_i(sbdata_write), + .sbdata_read_valid_i(sbdata_read_valid), + .sbdata_write_valid_i(sbdata_write_valid), + .sbdata_o(sbdata_read), + .sbdata_valid_o(sbdata_valid), + .sbbusy_o(sbbusy), + .sberror_valid_o(sberror_valid), + .sberror_o(sberror) + ); + tlul_adapter_host #(.MAX_REQS(1)) tl_adapter_host_sba( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_i(host_req), + .gnt_o(host_gnt), + .addr_i(host_add), + .we_i(host_we), + .wdata_i(host_wdata), + .be_i(host_be), + .valid_o(host_r_valid), + .rdata_o(host_r_rdata), + .err_o(host_r_err), + .tl_o(tl_h_o), + .tl_i(tl_h_i) + ); + localparam [31:0] AddressWidthWords = BusWidth - 2; + wire req; + wire we; + wire [(BusWidth / 8) - 1:0] be; + wire [BusWidth - 1:0] wdata; + wire [BusWidth - 1:0] rdata; + reg rvalid; + wire [BusWidth - 1:0] addr_b; + wire [AddressWidthWords - 1:0] addr_w; + assign be = {BusWidth / 8 {1'b1}}; + assign addr_b = {addr_w, {2 {1'b0}}}; + dm_mem #( + .NrHarts(NrHarts), + .BusWidth(BusWidth), + .SelectableHarts(SelectableHarts), + .DmBaseAddress(1) + ) i_dm_mem( + .clk_i(clk_i), + .rst_ni(rst_ni), + .debug_req_o(debug_req_o), + .hartsel_i(hartsel), + .haltreq_i(haltreq), + .resumereq_i(resumereq), + .clear_resumeack_i(clear_resumeack), + .halted_o(halted), + .resuming_o(resumeack), + .cmd_valid_i(cmd_valid), + .cmd_i(cmd), + .cmderror_valid_o(cmderror_valid), + .cmderror_o(cmderror), + .cmdbusy_o(cmdbusy), + .progbuf_i(progbuf), + .data_i(data_csrs_mem), + .data_o(data_mem_csrs), + .data_valid_o(data_valid), + .req_i(req), + .we_i(we), + .addr_i(addr_b), + .wdata_i(wdata), + .be_i(be), + .rdata_o(rdata) + ); + dmi_jtag #(.IdcodeValue(IdcodeValue)) dap( + .clk_i(clk_i), + .rst_ni(rst_ni), + .testmode_i(testmode_i), + .dmi_rst_no(dmi_rst_n), + .dmi_req_o(dmi_req), + .dmi_req_valid_o(dmi_req_valid), + .dmi_req_ready_i(dmi_req_ready), + .dmi_resp_i(dmi_rsp), + .dmi_resp_ready_o(dmi_rsp_ready), + .dmi_resp_valid_i(dmi_rsp_valid), + .tck_i(tck_i), + .tms_i(tms_i), + .trst_ni(trst_ni), + .td_i(td_i), + .td_o(td_o), + .tdo_oe_o(tdo_oe_o) + ); + tlul_adapter_sram #( + .SramAw(AddressWidthWords), + .SramDw(BusWidth), + .Outstanding(1), + .ByteAccess(0) + ) tl_adapter_device_mem( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_o(req), + .gnt_i(1'b1), + .we_o(we), + .addr_o(addr_w), + .wdata_o(wdata), + .wmask_o(), + .rdata_i(rdata), + .rvalid_i(rvalid), + .rerror_i(2'b00), + .tl_o(tl_d_o), + .tl_i(tl_d_i) + ); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + rvalid <= 1'sb0; + else + rvalid <= req & ~we; +endmodule +module rv_plic ( + clk_i, + rst_ni, + tl_i, + tl_o, + intr_src_i, + irq_o, + irq_id_o, + msip_o +); + localparam signed [31:0] NumSrc = 41; + localparam signed [31:0] NumTarget = 1; + localparam [8:0] RV_PLIC_IP_OFFSET = 9'h000; + localparam [8:0] RV_PLIC_LE_OFFSET = 9'h004; + localparam [8:0] RV_PLIC_PRIO0_OFFSET = 9'h008; + localparam [8:0] RV_PLIC_PRIO1_OFFSET = 9'h00c; + localparam [8:0] RV_PLIC_PRIO2_OFFSET = 9'h010; + localparam [8:0] RV_PLIC_PRIO3_OFFSET = 9'h014; + localparam [8:0] RV_PLIC_PRIO4_OFFSET = 9'h018; + localparam [8:0] RV_PLIC_PRIO5_OFFSET = 9'h01c; + localparam [8:0] RV_PLIC_PRIO6_OFFSET = 9'h020; + localparam [8:0] RV_PLIC_PRIO7_OFFSET = 9'h024; + localparam [8:0] RV_PLIC_PRIO8_OFFSET = 9'h028; + localparam [8:0] RV_PLIC_PRIO9_OFFSET = 9'h02c; + localparam [8:0] RV_PLIC_PRIO10_OFFSET = 9'h030; + localparam [8:0] RV_PLIC_PRIO11_OFFSET = 9'h034; + localparam [8:0] RV_PLIC_PRIO12_OFFSET = 9'h038; + localparam [8:0] RV_PLIC_PRIO13_OFFSET = 9'h03c; + localparam [8:0] RV_PLIC_PRIO14_OFFSET = 9'h040; + localparam [8:0] RV_PLIC_PRIO15_OFFSET = 9'h044; + localparam [8:0] RV_PLIC_PRIO16_OFFSET = 9'h048; + localparam [8:0] RV_PLIC_PRIO17_OFFSET = 9'h04c; + localparam [8:0] RV_PLIC_PRIO18_OFFSET = 9'h050; + localparam [8:0] RV_PLIC_PRIO19_OFFSET = 9'h054; + localparam [8:0] RV_PLIC_PRIO20_OFFSET = 9'h058; + localparam [8:0] RV_PLIC_PRIO21_OFFSET = 9'h05c; + localparam [8:0] RV_PLIC_PRIO22_OFFSET = 9'h060; + localparam [8:0] RV_PLIC_PRIO23_OFFSET = 9'h064; + localparam [8:0] RV_PLIC_PRIO24_OFFSET = 9'h068; + localparam [8:0] RV_PLIC_PRIO25_OFFSET = 9'h06c; + localparam [8:0] RV_PLIC_PRIO26_OFFSET = 9'h070; + localparam [8:0] RV_PLIC_PRIO27_OFFSET = 9'h074; + localparam [8:0] RV_PLIC_PRIO28_OFFSET = 9'h078; + localparam [8:0] RV_PLIC_PRIO29_OFFSET = 9'h07c; + localparam [8:0] RV_PLIC_PRIO30_OFFSET = 9'h080; + localparam [8:0] RV_PLIC_PRIO31_OFFSET = 9'h084; + localparam [8:0] RV_PLIC_IE0_OFFSET = 9'h100; + localparam [8:0] RV_PLIC_THRESHOLD0_OFFSET = 9'h104; + localparam [8:0] RV_PLIC_CC0_OFFSET = 9'h108; + localparam [8:0] RV_PLIC_MSIP0_OFFSET = 9'h10c; + localparam signed [31:0] RV_PLIC_IP = 0; + localparam signed [31:0] RV_PLIC_LE = 1; + localparam signed [31:0] RV_PLIC_PRIO0 = 2; + localparam signed [31:0] RV_PLIC_PRIO1 = 3; + localparam signed [31:0] RV_PLIC_PRIO2 = 4; + localparam signed [31:0] RV_PLIC_PRIO3 = 5; + localparam signed [31:0] RV_PLIC_PRIO4 = 6; + localparam signed [31:0] RV_PLIC_PRIO5 = 7; + localparam signed [31:0] RV_PLIC_PRIO6 = 8; + localparam signed [31:0] RV_PLIC_PRIO7 = 9; + localparam signed [31:0] RV_PLIC_PRIO8 = 10; + localparam signed [31:0] RV_PLIC_PRIO9 = 11; + localparam signed [31:0] RV_PLIC_PRIO10 = 12; + localparam signed [31:0] RV_PLIC_PRIO11 = 13; + localparam signed [31:0] RV_PLIC_PRIO12 = 14; + localparam signed [31:0] RV_PLIC_PRIO13 = 15; + localparam signed [31:0] RV_PLIC_PRIO14 = 16; + localparam signed [31:0] RV_PLIC_PRIO15 = 17; + localparam signed [31:0] RV_PLIC_PRIO16 = 18; + localparam signed [31:0] RV_PLIC_PRIO17 = 19; + localparam signed [31:0] RV_PLIC_PRIO18 = 20; + localparam signed [31:0] RV_PLIC_PRIO19 = 21; + localparam signed [31:0] RV_PLIC_PRIO20 = 22; + localparam signed [31:0] RV_PLIC_PRIO21 = 23; + localparam signed [31:0] RV_PLIC_PRIO22 = 24; + localparam signed [31:0] RV_PLIC_PRIO23 = 25; + localparam signed [31:0] RV_PLIC_PRIO24 = 26; + localparam signed [31:0] RV_PLIC_PRIO25 = 27; + localparam signed [31:0] RV_PLIC_PRIO26 = 28; + localparam signed [31:0] RV_PLIC_PRIO27 = 29; + localparam signed [31:0] RV_PLIC_PRIO28 = 30; + localparam signed [31:0] RV_PLIC_PRIO29 = 31; + localparam signed [31:0] RV_PLIC_PRIO30 = 32; + localparam signed [31:0] RV_PLIC_PRIO31 = 33; + localparam signed [31:0] RV_PLIC_IE0 = 34; + localparam signed [31:0] RV_PLIC_THRESHOLD0 = 35; + localparam signed [31:0] RV_PLIC_CC0 = 36; + localparam signed [31:0] RV_PLIC_MSIP0 = 37; + localparam [151:0] RV_PLIC_PERMIT = {4'b1111, 4'b1111, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b1111, 4'b0001, 4'b0001, 4'b0001}; + localparam signed [31:0] SRCW = 6; + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + input [NumSrc - 1:0] intr_src_i; + output [NumTarget - 1:0] irq_o; + output [((2 - NumTarget) * SRCW) + (((NumTarget - 1) * SRCW) - 1):(NumTarget - 1) * SRCW] irq_id_o; + output wire [NumTarget - 1:0] msip_o; + wire [171:0] reg2hw; + wire [69:0] hw2reg; + localparam signed [31:0] MAX_PRIO = 7; + localparam signed [31:0] PRIOW = 3; + wire [NumSrc - 1:0] le; + wire [NumSrc - 1:0] ip; + wire [NumSrc - 1:0] ie [0:NumTarget - 1]; + wire [NumTarget - 1:0] claim_re; + wire [SRCW - 1:0] claim_id [0:NumTarget - 1]; + reg [NumSrc - 1:0] claim; + wire [NumTarget - 1:0] complete_we; + wire [SRCW - 1:0] complete_id [0:NumTarget - 1]; + reg [NumSrc - 1:0] complete; + wire [((2 - NumTarget) * SRCW) + (((NumTarget - 1) * SRCW) - 1):(NumTarget - 1) * SRCW] cc_id; + wire [(NumSrc * PRIOW) - 1:0] prio; + wire [PRIOW - 1:0] threshold [0:NumTarget - 1]; + assign cc_id = irq_id_o; + always @(*) begin + claim = {NumSrc {1'sb0}}; + begin : sv2v_autoblock_79 + reg signed [31:0] i; + for (i = 0; i < NumTarget; i = i + 1) + if (claim_re[i]) + claim[claim_id[i]] = 1'b1; + end + end + always @(*) begin + complete = {NumSrc {1'sb0}}; + begin : sv2v_autoblock_80 + reg signed [31:0] i; + for (i = 0; i < NumTarget; i = i + 1) + if (complete_we[i]) + complete[complete_id[i]] = 1'b1; + end + end + assign prio[(NumSrc - 1) * PRIOW+:PRIOW] = reg2hw[139-:3]; + assign prio[(NumSrc - 2) * PRIOW+:PRIOW] = reg2hw[136-:3]; + assign prio[(NumSrc - 3) * PRIOW+:PRIOW] = reg2hw[133-:3]; + assign prio[(NumSrc - 4) * PRIOW+:PRIOW] = reg2hw[130-:3]; + assign prio[(NumSrc - 5) * PRIOW+:PRIOW] = reg2hw[127-:3]; + assign prio[(NumSrc - 6) * PRIOW+:PRIOW] = reg2hw[124-:3]; + assign prio[(NumSrc - 7) * PRIOW+:PRIOW] = reg2hw[121-:3]; + assign prio[(NumSrc - 8) * PRIOW+:PRIOW] = reg2hw[118-:3]; + assign prio[(NumSrc - 9) * PRIOW+:PRIOW] = reg2hw[115-:3]; + assign prio[(NumSrc - 10) * PRIOW+:PRIOW] = reg2hw[112-:3]; + assign prio[(NumSrc - 11) * PRIOW+:PRIOW] = reg2hw[109-:3]; + assign prio[(NumSrc - 12) * PRIOW+:PRIOW] = reg2hw[106-:3]; + assign prio[(NumSrc - 13) * PRIOW+:PRIOW] = reg2hw[103-:3]; + assign prio[(NumSrc - 14) * PRIOW+:PRIOW] = reg2hw[100-:3]; + assign prio[(NumSrc - 15) * PRIOW+:PRIOW] = reg2hw[97-:3]; + assign prio[(NumSrc - 16) * PRIOW+:PRIOW] = reg2hw[94-:3]; + assign prio[(NumSrc - 17) * PRIOW+:PRIOW] = reg2hw[91-:3]; + assign prio[(NumSrc - 18) * PRIOW+:PRIOW] = reg2hw[88-:3]; + assign prio[(NumSrc - 19) * PRIOW+:PRIOW] = reg2hw[85-:3]; + assign prio[(NumSrc - 20) * PRIOW+:PRIOW] = reg2hw[82-:3]; + assign prio[(NumSrc - 21) * PRIOW+:PRIOW] = reg2hw[79-:3]; + assign prio[(NumSrc - 22) * PRIOW+:PRIOW] = reg2hw[76-:3]; + assign prio[(NumSrc - 23) * PRIOW+:PRIOW] = reg2hw[73-:3]; + assign prio[(NumSrc - 24) * PRIOW+:PRIOW] = reg2hw[70-:3]; + assign prio[(NumSrc - 25) * PRIOW+:PRIOW] = reg2hw[67-:3]; + assign prio[(NumSrc - 26) * PRIOW+:PRIOW] = reg2hw[64-:3]; + assign prio[(NumSrc - 27) * PRIOW+:PRIOW] = reg2hw[61-:3]; + assign prio[(NumSrc - 28) * PRIOW+:PRIOW] = reg2hw[58-:3]; + assign prio[(NumSrc - 29) * PRIOW+:PRIOW] = reg2hw[55-:3]; + assign prio[(NumSrc - 30) * PRIOW+:PRIOW] = reg2hw[52-:3]; + assign prio[(NumSrc - 31) * PRIOW+:PRIOW] = reg2hw[49-:3]; + assign prio[(NumSrc - 32) * PRIOW+:PRIOW] = reg2hw[46-:3]; + generate + genvar s; + for (s = 0; s < 32; s = s + 1) begin : gen_ie0 + assign ie[0][s] = reg2hw[12 + s]; + end + endgenerate + assign threshold[0] = reg2hw[11-:3]; + assign claim_re[0] = reg2hw[1]; + assign claim_id[0] = irq_id_o[0+:SRCW]; + assign complete_we[0] = reg2hw[2]; + assign complete_id[0] = reg2hw[8-:6]; + assign hw2reg[5-:6] = cc_id[0+:SRCW]; + assign msip_o[0] = reg2hw[-0]; + generate + for (s = 0; s < 32; s = s + 1) begin : gen_ip + assign hw2reg[6 + (s * 2)] = 1'b1; + assign hw2reg[6 + ((s * 2) + 1)] = ip[s]; + end + endgenerate + generate + for (s = 0; s < 32; s = s + 1) begin : gen_le + assign le[s] = reg2hw[140 + s]; + end + endgenerate + rv_plic_gateway #(.N_SOURCE(NumSrc)) u_gateway( + .clk_i(clk_i), + .rst_ni(rst_ni), + .src_i(intr_src_i), + .le_i(le), + .claim_i(claim), + .complete_i(complete), + .ip_o(ip) + ); + generate + genvar i; + for (i = 0; i < NumTarget; i = i + 1) begin : gen_target + rv_plic_target #( + .N_SOURCE(NumSrc), + .MAX_PRIO(MAX_PRIO) + ) u_target( + .clk_i(clk_i), + .rst_ni(rst_ni), + .ip_i(ip), + .ie_i(ie[i]), + .prio_i(prio), + .threshold_i(threshold[i]), + .irq_o(irq_o[i]), + .irq_id_o(irq_id_o[i * SRCW+:SRCW]) + ); + end + endgenerate + rv_plic_reg_top u_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_i), + .tl_o(tl_o), + .reg2hw(reg2hw), + .hw2reg(hw2reg), + .devmode_i(1'b1) + ); +endmodule +module rv_plic_gateway ( + clk_i, + rst_ni, + src_i, + le_i, + claim_i, + complete_i, + ip_o +); + parameter signed [31:0] N_SOURCE = 32; + input clk_i; + input rst_ni; + input [N_SOURCE - 1:0] src_i; + input [N_SOURCE - 1:0] le_i; + input [N_SOURCE - 1:0] claim_i; + input [N_SOURCE - 1:0] complete_i; + output reg [N_SOURCE - 1:0] ip_o; + reg [N_SOURCE - 1:0] ia; + reg [N_SOURCE - 1:0] set; + reg [N_SOURCE - 1:0] src_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + src_q <= {N_SOURCE {1'sb0}}; + else + src_q <= src_i; + always @(*) begin : sv2v_autoblock_81 + reg signed [31:0] i; + for (i = 0; i < N_SOURCE; i = i + 1) + set[i] = (le_i[i] ? src_i[i] & ~src_q[i] : src_i[i]); + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + ip_o <= {N_SOURCE {1'sb0}}; + else + ip_o <= (ip_o | ((set & ~ia) & ~ip_o)) & ~(ip_o & claim_i); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + ia <= {N_SOURCE {1'sb0}}; + else + ia <= (ia | (set & ~ia)) & ~((ia & complete_i) & ~ip_o); +endmodule +module rv_plic_reg_top ( + clk_i, + rst_ni, + tl_i, + tl_o, + reg2hw, + hw2reg, + devmode_i +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire [171:0] reg2hw; + input wire [69:0] hw2reg; + input devmode_i; + localparam signed [31:0] NumSrc = 41; + localparam signed [31:0] NumTarget = 1; + localparam [8:0] RV_PLIC_IP_OFFSET = 9'h000; + localparam [8:0] RV_PLIC_LE_OFFSET = 9'h004; + localparam [8:0] RV_PLIC_PRIO0_OFFSET = 9'h008; + localparam [8:0] RV_PLIC_PRIO1_OFFSET = 9'h00c; + localparam [8:0] RV_PLIC_PRIO2_OFFSET = 9'h010; + localparam [8:0] RV_PLIC_PRIO3_OFFSET = 9'h014; + localparam [8:0] RV_PLIC_PRIO4_OFFSET = 9'h018; + localparam [8:0] RV_PLIC_PRIO5_OFFSET = 9'h01c; + localparam [8:0] RV_PLIC_PRIO6_OFFSET = 9'h020; + localparam [8:0] RV_PLIC_PRIO7_OFFSET = 9'h024; + localparam [8:0] RV_PLIC_PRIO8_OFFSET = 9'h028; + localparam [8:0] RV_PLIC_PRIO9_OFFSET = 9'h02c; + localparam [8:0] RV_PLIC_PRIO10_OFFSET = 9'h030; + localparam [8:0] RV_PLIC_PRIO11_OFFSET = 9'h034; + localparam [8:0] RV_PLIC_PRIO12_OFFSET = 9'h038; + localparam [8:0] RV_PLIC_PRIO13_OFFSET = 9'h03c; + localparam [8:0] RV_PLIC_PRIO14_OFFSET = 9'h040; + localparam [8:0] RV_PLIC_PRIO15_OFFSET = 9'h044; + localparam [8:0] RV_PLIC_PRIO16_OFFSET = 9'h048; + localparam [8:0] RV_PLIC_PRIO17_OFFSET = 9'h04c; + localparam [8:0] RV_PLIC_PRIO18_OFFSET = 9'h050; + localparam [8:0] RV_PLIC_PRIO19_OFFSET = 9'h054; + localparam [8:0] RV_PLIC_PRIO20_OFFSET = 9'h058; + localparam [8:0] RV_PLIC_PRIO21_OFFSET = 9'h05c; + localparam [8:0] RV_PLIC_PRIO22_OFFSET = 9'h060; + localparam [8:0] RV_PLIC_PRIO23_OFFSET = 9'h064; + localparam [8:0] RV_PLIC_PRIO24_OFFSET = 9'h068; + localparam [8:0] RV_PLIC_PRIO25_OFFSET = 9'h06c; + localparam [8:0] RV_PLIC_PRIO26_OFFSET = 9'h070; + localparam [8:0] RV_PLIC_PRIO27_OFFSET = 9'h074; + localparam [8:0] RV_PLIC_PRIO28_OFFSET = 9'h078; + localparam [8:0] RV_PLIC_PRIO29_OFFSET = 9'h07c; + localparam [8:0] RV_PLIC_PRIO30_OFFSET = 9'h080; + localparam [8:0] RV_PLIC_PRIO31_OFFSET = 9'h084; + localparam [8:0] RV_PLIC_IE0_OFFSET = 9'h100; + localparam [8:0] RV_PLIC_THRESHOLD0_OFFSET = 9'h104; + localparam [8:0] RV_PLIC_CC0_OFFSET = 9'h108; + localparam [8:0] RV_PLIC_MSIP0_OFFSET = 9'h10c; + localparam signed [31:0] RV_PLIC_IP = 0; + localparam signed [31:0] RV_PLIC_LE = 1; + localparam signed [31:0] RV_PLIC_PRIO0 = 2; + localparam signed [31:0] RV_PLIC_PRIO1 = 3; + localparam signed [31:0] RV_PLIC_PRIO2 = 4; + localparam signed [31:0] RV_PLIC_PRIO3 = 5; + localparam signed [31:0] RV_PLIC_PRIO4 = 6; + localparam signed [31:0] RV_PLIC_PRIO5 = 7; + localparam signed [31:0] RV_PLIC_PRIO6 = 8; + localparam signed [31:0] RV_PLIC_PRIO7 = 9; + localparam signed [31:0] RV_PLIC_PRIO8 = 10; + localparam signed [31:0] RV_PLIC_PRIO9 = 11; + localparam signed [31:0] RV_PLIC_PRIO10 = 12; + localparam signed [31:0] RV_PLIC_PRIO11 = 13; + localparam signed [31:0] RV_PLIC_PRIO12 = 14; + localparam signed [31:0] RV_PLIC_PRIO13 = 15; + localparam signed [31:0] RV_PLIC_PRIO14 = 16; + localparam signed [31:0] RV_PLIC_PRIO15 = 17; + localparam signed [31:0] RV_PLIC_PRIO16 = 18; + localparam signed [31:0] RV_PLIC_PRIO17 = 19; + localparam signed [31:0] RV_PLIC_PRIO18 = 20; + localparam signed [31:0] RV_PLIC_PRIO19 = 21; + localparam signed [31:0] RV_PLIC_PRIO20 = 22; + localparam signed [31:0] RV_PLIC_PRIO21 = 23; + localparam signed [31:0] RV_PLIC_PRIO22 = 24; + localparam signed [31:0] RV_PLIC_PRIO23 = 25; + localparam signed [31:0] RV_PLIC_PRIO24 = 26; + localparam signed [31:0] RV_PLIC_PRIO25 = 27; + localparam signed [31:0] RV_PLIC_PRIO26 = 28; + localparam signed [31:0] RV_PLIC_PRIO27 = 29; + localparam signed [31:0] RV_PLIC_PRIO28 = 30; + localparam signed [31:0] RV_PLIC_PRIO29 = 31; + localparam signed [31:0] RV_PLIC_PRIO30 = 32; + localparam signed [31:0] RV_PLIC_PRIO31 = 33; + localparam signed [31:0] RV_PLIC_IE0 = 34; + localparam signed [31:0] RV_PLIC_THRESHOLD0 = 35; + localparam signed [31:0] RV_PLIC_CC0 = 36; + localparam signed [31:0] RV_PLIC_MSIP0 = 37; + localparam [151:0] RV_PLIC_PERMIT = {4'b1111, 4'b1111, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b1111, 4'b0001, 4'b0001, 4'b0001}; + localparam signed [31:0] AW = 9; + localparam signed [31:0] DW = 32; + localparam signed [31:0] DBW = DW / 8; + wire reg_we; + wire reg_re; + wire [AW - 1:0] reg_addr; + wire [DW - 1:0] reg_wdata; + wire [DBW - 1:0] reg_be; + wire [DW - 1:0] reg_rdata; + wire reg_error; + wire addrmiss; + reg wr_err; + reg [DW - 1:0] reg_rdata_next; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_reg_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_reg_d2h; + assign tl_reg_h2d = tl_i; + assign tl_o = tl_reg_d2h; + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW) + ) u_reg_if( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_reg_h2d), + .tl_o(tl_reg_d2h), + .we_o(reg_we), + .re_o(reg_re), + .addr_o(reg_addr), + .wdata_o(reg_wdata), + .be_o(reg_be), + .rdata_i(reg_rdata), + .error_i(reg_error) + ); + assign reg_rdata = reg_rdata_next; + assign reg_error = (devmode_i & addrmiss) | wr_err; + wire ip_p_0_qs; + wire ip_p_1_qs; + wire ip_p_2_qs; + wire ip_p_3_qs; + wire ip_p_4_qs; + wire ip_p_5_qs; + wire ip_p_6_qs; + wire ip_p_7_qs; + wire ip_p_8_qs; + wire ip_p_9_qs; + wire ip_p_10_qs; + wire ip_p_11_qs; + wire ip_p_12_qs; + wire ip_p_13_qs; + wire ip_p_14_qs; + wire ip_p_15_qs; + wire ip_p_16_qs; + wire ip_p_17_qs; + wire ip_p_18_qs; + wire ip_p_19_qs; + wire ip_p_20_qs; + wire ip_p_21_qs; + wire ip_p_22_qs; + wire ip_p_23_qs; + wire ip_p_24_qs; + wire ip_p_25_qs; + wire ip_p_26_qs; + wire ip_p_27_qs; + wire ip_p_28_qs; + wire ip_p_29_qs; + wire ip_p_30_qs; + wire ip_p_31_qs; + wire le_le_0_qs; + wire le_le_0_wd; + wire le_le_0_we; + wire le_le_1_qs; + wire le_le_1_wd; + wire le_le_1_we; + wire le_le_2_qs; + wire le_le_2_wd; + wire le_le_2_we; + wire le_le_3_qs; + wire le_le_3_wd; + wire le_le_3_we; + wire le_le_4_qs; + wire le_le_4_wd; + wire le_le_4_we; + wire le_le_5_qs; + wire le_le_5_wd; + wire le_le_5_we; + wire le_le_6_qs; + wire le_le_6_wd; + wire le_le_6_we; + wire le_le_7_qs; + wire le_le_7_wd; + wire le_le_7_we; + wire le_le_8_qs; + wire le_le_8_wd; + wire le_le_8_we; + wire le_le_9_qs; + wire le_le_9_wd; + wire le_le_9_we; + wire le_le_10_qs; + wire le_le_10_wd; + wire le_le_10_we; + wire le_le_11_qs; + wire le_le_11_wd; + wire le_le_11_we; + wire le_le_12_qs; + wire le_le_12_wd; + wire le_le_12_we; + wire le_le_13_qs; + wire le_le_13_wd; + wire le_le_13_we; + wire le_le_14_qs; + wire le_le_14_wd; + wire le_le_14_we; + wire le_le_15_qs; + wire le_le_15_wd; + wire le_le_15_we; + wire le_le_16_qs; + wire le_le_16_wd; + wire le_le_16_we; + wire le_le_17_qs; + wire le_le_17_wd; + wire le_le_17_we; + wire le_le_18_qs; + wire le_le_18_wd; + wire le_le_18_we; + wire le_le_19_qs; + wire le_le_19_wd; + wire le_le_19_we; + wire le_le_20_qs; + wire le_le_20_wd; + wire le_le_20_we; + wire le_le_21_qs; + wire le_le_21_wd; + wire le_le_21_we; + wire le_le_22_qs; + wire le_le_22_wd; + wire le_le_22_we; + wire le_le_23_qs; + wire le_le_23_wd; + wire le_le_23_we; + wire le_le_24_qs; + wire le_le_24_wd; + wire le_le_24_we; + wire le_le_25_qs; + wire le_le_25_wd; + wire le_le_25_we; + wire le_le_26_qs; + wire le_le_26_wd; + wire le_le_26_we; + wire le_le_27_qs; + wire le_le_27_wd; + wire le_le_27_we; + wire le_le_28_qs; + wire le_le_28_wd; + wire le_le_28_we; + wire le_le_29_qs; + wire le_le_29_wd; + wire le_le_29_we; + wire le_le_30_qs; + wire le_le_30_wd; + wire le_le_30_we; + wire le_le_31_qs; + wire le_le_31_wd; + wire le_le_31_we; + wire [2:0] prio0_qs; + wire [2:0] prio0_wd; + wire prio0_we; + wire [2:0] prio1_qs; + wire [2:0] prio1_wd; + wire prio1_we; + wire [2:0] prio2_qs; + wire [2:0] prio2_wd; + wire prio2_we; + wire [2:0] prio3_qs; + wire [2:0] prio3_wd; + wire prio3_we; + wire [2:0] prio4_qs; + wire [2:0] prio4_wd; + wire prio4_we; + wire [2:0] prio5_qs; + wire [2:0] prio5_wd; + wire prio5_we; + wire [2:0] prio6_qs; + wire [2:0] prio6_wd; + wire prio6_we; + wire [2:0] prio7_qs; + wire [2:0] prio7_wd; + wire prio7_we; + wire [2:0] prio8_qs; + wire [2:0] prio8_wd; + wire prio8_we; + wire [2:0] prio9_qs; + wire [2:0] prio9_wd; + wire prio9_we; + wire [2:0] prio10_qs; + wire [2:0] prio10_wd; + wire prio10_we; + wire [2:0] prio11_qs; + wire [2:0] prio11_wd; + wire prio11_we; + wire [2:0] prio12_qs; + wire [2:0] prio12_wd; + wire prio12_we; + wire [2:0] prio13_qs; + wire [2:0] prio13_wd; + wire prio13_we; + wire [2:0] prio14_qs; + wire [2:0] prio14_wd; + wire prio14_we; + wire [2:0] prio15_qs; + wire [2:0] prio15_wd; + wire prio15_we; + wire [2:0] prio16_qs; + wire [2:0] prio16_wd; + wire prio16_we; + wire [2:0] prio17_qs; + wire [2:0] prio17_wd; + wire prio17_we; + wire [2:0] prio18_qs; + wire [2:0] prio18_wd; + wire prio18_we; + wire [2:0] prio19_qs; + wire [2:0] prio19_wd; + wire prio19_we; + wire [2:0] prio20_qs; + wire [2:0] prio20_wd; + wire prio20_we; + wire [2:0] prio21_qs; + wire [2:0] prio21_wd; + wire prio21_we; + wire [2:0] prio22_qs; + wire [2:0] prio22_wd; + wire prio22_we; + wire [2:0] prio23_qs; + wire [2:0] prio23_wd; + wire prio23_we; + wire [2:0] prio24_qs; + wire [2:0] prio24_wd; + wire prio24_we; + wire [2:0] prio25_qs; + wire [2:0] prio25_wd; + wire prio25_we; + wire [2:0] prio26_qs; + wire [2:0] prio26_wd; + wire prio26_we; + wire [2:0] prio27_qs; + wire [2:0] prio27_wd; + wire prio27_we; + wire [2:0] prio28_qs; + wire [2:0] prio28_wd; + wire prio28_we; + wire [2:0] prio29_qs; + wire [2:0] prio29_wd; + wire prio29_we; + wire [2:0] prio30_qs; + wire [2:0] prio30_wd; + wire prio30_we; + wire [2:0] prio31_qs; + wire [2:0] prio31_wd; + wire prio31_we; + wire ie0_e_0_qs; + wire ie0_e_0_wd; + wire ie0_e_0_we; + wire ie0_e_1_qs; + wire ie0_e_1_wd; + wire ie0_e_1_we; + wire ie0_e_2_qs; + wire ie0_e_2_wd; + wire ie0_e_2_we; + wire ie0_e_3_qs; + wire ie0_e_3_wd; + wire ie0_e_3_we; + wire ie0_e_4_qs; + wire ie0_e_4_wd; + wire ie0_e_4_we; + wire ie0_e_5_qs; + wire ie0_e_5_wd; + wire ie0_e_5_we; + wire ie0_e_6_qs; + wire ie0_e_6_wd; + wire ie0_e_6_we; + wire ie0_e_7_qs; + wire ie0_e_7_wd; + wire ie0_e_7_we; + wire ie0_e_8_qs; + wire ie0_e_8_wd; + wire ie0_e_8_we; + wire ie0_e_9_qs; + wire ie0_e_9_wd; + wire ie0_e_9_we; + wire ie0_e_10_qs; + wire ie0_e_10_wd; + wire ie0_e_10_we; + wire ie0_e_11_qs; + wire ie0_e_11_wd; + wire ie0_e_11_we; + wire ie0_e_12_qs; + wire ie0_e_12_wd; + wire ie0_e_12_we; + wire ie0_e_13_qs; + wire ie0_e_13_wd; + wire ie0_e_13_we; + wire ie0_e_14_qs; + wire ie0_e_14_wd; + wire ie0_e_14_we; + wire ie0_e_15_qs; + wire ie0_e_15_wd; + wire ie0_e_15_we; + wire ie0_e_16_qs; + wire ie0_e_16_wd; + wire ie0_e_16_we; + wire ie0_e_17_qs; + wire ie0_e_17_wd; + wire ie0_e_17_we; + wire ie0_e_18_qs; + wire ie0_e_18_wd; + wire ie0_e_18_we; + wire ie0_e_19_qs; + wire ie0_e_19_wd; + wire ie0_e_19_we; + wire ie0_e_20_qs; + wire ie0_e_20_wd; + wire ie0_e_20_we; + wire ie0_e_21_qs; + wire ie0_e_21_wd; + wire ie0_e_21_we; + wire ie0_e_22_qs; + wire ie0_e_22_wd; + wire ie0_e_22_we; + wire ie0_e_23_qs; + wire ie0_e_23_wd; + wire ie0_e_23_we; + wire ie0_e_24_qs; + wire ie0_e_24_wd; + wire ie0_e_24_we; + wire ie0_e_25_qs; + wire ie0_e_25_wd; + wire ie0_e_25_we; + wire ie0_e_26_qs; + wire ie0_e_26_wd; + wire ie0_e_26_we; + wire ie0_e_27_qs; + wire ie0_e_27_wd; + wire ie0_e_27_we; + wire ie0_e_28_qs; + wire ie0_e_28_wd; + wire ie0_e_28_we; + wire ie0_e_29_qs; + wire ie0_e_29_wd; + wire ie0_e_29_we; + wire ie0_e_30_qs; + wire ie0_e_30_wd; + wire ie0_e_30_we; + wire ie0_e_31_qs; + wire ie0_e_31_wd; + wire ie0_e_31_we; + wire [2:0] threshold0_qs; + wire [2:0] threshold0_wd; + wire threshold0_we; + wire [5:0] cc0_qs; + wire [5:0] cc0_wd; + wire cc0_we; + wire cc0_re; + wire msip0_qs; + wire msip0_wd; + wire msip0_we; + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[6]), + .d(hw2reg[7]), + .qe(), + .q(), + .qs(ip_p_0_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_1( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[8]), + .d(hw2reg[9]), + .qe(), + .q(), + .qs(ip_p_1_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_2( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[10]), + .d(hw2reg[11]), + .qe(), + .q(), + .qs(ip_p_2_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_3( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[12]), + .d(hw2reg[13]), + .qe(), + .q(), + .qs(ip_p_3_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_4( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[14]), + .d(hw2reg[15]), + .qe(), + .q(), + .qs(ip_p_4_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_5( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[16]), + .d(hw2reg[17]), + .qe(), + .q(), + .qs(ip_p_5_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_6( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[18]), + .d(hw2reg[19]), + .qe(), + .q(), + .qs(ip_p_6_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_7( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[20]), + .d(hw2reg[21]), + .qe(), + .q(), + .qs(ip_p_7_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_8( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[22]), + .d(hw2reg[23]), + .qe(), + .q(), + .qs(ip_p_8_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_9( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[24]), + .d(hw2reg[25]), + .qe(), + .q(), + .qs(ip_p_9_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_10( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[26]), + .d(hw2reg[27]), + .qe(), + .q(), + .qs(ip_p_10_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_11( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[28]), + .d(hw2reg[29]), + .qe(), + .q(), + .qs(ip_p_11_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_12( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[30]), + .d(hw2reg[31]), + .qe(), + .q(), + .qs(ip_p_12_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_13( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[32]), + .d(hw2reg[33]), + .qe(), + .q(), + .qs(ip_p_13_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_14( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[34]), + .d(hw2reg[35]), + .qe(), + .q(), + .qs(ip_p_14_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_15( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[36]), + .d(hw2reg[37]), + .qe(), + .q(), + .qs(ip_p_15_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_16( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[38]), + .d(hw2reg[39]), + .qe(), + .q(), + .qs(ip_p_16_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_17( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[40]), + .d(hw2reg[41]), + .qe(), + .q(), + .qs(ip_p_17_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_18( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[42]), + .d(hw2reg[43]), + .qe(), + .q(), + .qs(ip_p_18_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_19( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[44]), + .d(hw2reg[45]), + .qe(), + .q(), + .qs(ip_p_19_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_20( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[46]), + .d(hw2reg[47]), + .qe(), + .q(), + .qs(ip_p_20_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_21( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[48]), + .d(hw2reg[49]), + .qe(), + .q(), + .qs(ip_p_21_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_22( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[50]), + .d(hw2reg[51]), + .qe(), + .q(), + .qs(ip_p_22_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_23( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[52]), + .d(hw2reg[53]), + .qe(), + .q(), + .qs(ip_p_23_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_24( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[54]), + .d(hw2reg[55]), + .qe(), + .q(), + .qs(ip_p_24_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_25( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[56]), + .d(hw2reg[57]), + .qe(), + .q(), + .qs(ip_p_25_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_26( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[58]), + .d(hw2reg[59]), + .qe(), + .q(), + .qs(ip_p_26_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_27( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[60]), + .d(hw2reg[61]), + .qe(), + .q(), + .qs(ip_p_27_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_28( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[62]), + .d(hw2reg[63]), + .qe(), + .q(), + .qs(ip_p_28_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_29( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[64]), + .d(hw2reg[65]), + .qe(), + .q(), + .qs(ip_p_29_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_30( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[66]), + .d(hw2reg[67]), + .qe(), + .q(), + .qs(ip_p_30_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RO"), + .RESVAL(1'h0) + ) u_ip_p_31( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(1'b0), + .wd(1'sb0), + .de(hw2reg[68]), + .d(hw2reg[69]), + .qe(), + .q(), + .qs(ip_p_31_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_0_we), + .wd(le_le_0_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[140]), + .qs(le_le_0_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_1( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_1_we), + .wd(le_le_1_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[141]), + .qs(le_le_1_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_2( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_2_we), + .wd(le_le_2_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[142]), + .qs(le_le_2_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_3( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_3_we), + .wd(le_le_3_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[143]), + .qs(le_le_3_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_4( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_4_we), + .wd(le_le_4_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[144]), + .qs(le_le_4_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_5( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_5_we), + .wd(le_le_5_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[145]), + .qs(le_le_5_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_6( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_6_we), + .wd(le_le_6_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[146]), + .qs(le_le_6_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_7( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_7_we), + .wd(le_le_7_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[147]), + .qs(le_le_7_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_8( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_8_we), + .wd(le_le_8_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[148]), + .qs(le_le_8_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_9( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_9_we), + .wd(le_le_9_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[149]), + .qs(le_le_9_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_10( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_10_we), + .wd(le_le_10_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[150]), + .qs(le_le_10_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_11( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_11_we), + .wd(le_le_11_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[151]), + .qs(le_le_11_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_12( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_12_we), + .wd(le_le_12_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[152]), + .qs(le_le_12_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_13( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_13_we), + .wd(le_le_13_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[153]), + .qs(le_le_13_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_14( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_14_we), + .wd(le_le_14_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[154]), + .qs(le_le_14_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_15( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_15_we), + .wd(le_le_15_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[155]), + .qs(le_le_15_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_16( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_16_we), + .wd(le_le_16_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[156]), + .qs(le_le_16_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_17( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_17_we), + .wd(le_le_17_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[157]), + .qs(le_le_17_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_18( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_18_we), + .wd(le_le_18_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[158]), + .qs(le_le_18_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_19( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_19_we), + .wd(le_le_19_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[159]), + .qs(le_le_19_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_20( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_20_we), + .wd(le_le_20_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[160]), + .qs(le_le_20_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_21( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_21_we), + .wd(le_le_21_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[161]), + .qs(le_le_21_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_22( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_22_we), + .wd(le_le_22_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[162]), + .qs(le_le_22_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_23( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_23_we), + .wd(le_le_23_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[163]), + .qs(le_le_23_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_24( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_24_we), + .wd(le_le_24_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[164]), + .qs(le_le_24_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_25( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_25_we), + .wd(le_le_25_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[165]), + .qs(le_le_25_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_26( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_26_we), + .wd(le_le_26_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[166]), + .qs(le_le_26_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_27( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_27_we), + .wd(le_le_27_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[167]), + .qs(le_le_27_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_28( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_28_we), + .wd(le_le_28_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[168]), + .qs(le_le_28_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_29( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_29_we), + .wd(le_le_29_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[169]), + .qs(le_le_29_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_30( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_30_we), + .wd(le_le_30_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[170]), + .qs(le_le_30_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_le_le_31( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(le_le_31_we), + .wd(le_le_31_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[171]), + .qs(le_le_31_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio0_we), + .wd(prio0_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[139-:3]), + .qs(prio0_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio1( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio1_we), + .wd(prio1_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[136-:3]), + .qs(prio1_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio2( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio2_we), + .wd(prio2_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[133-:3]), + .qs(prio2_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio3( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio3_we), + .wd(prio3_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[130-:3]), + .qs(prio3_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio4( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio4_we), + .wd(prio4_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[127-:3]), + .qs(prio4_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio5( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio5_we), + .wd(prio5_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[124-:3]), + .qs(prio5_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio6( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio6_we), + .wd(prio6_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[121-:3]), + .qs(prio6_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio7( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio7_we), + .wd(prio7_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[118-:3]), + .qs(prio7_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio8( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio8_we), + .wd(prio8_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[115-:3]), + .qs(prio8_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio9( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio9_we), + .wd(prio9_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[112-:3]), + .qs(prio9_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio10( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio10_we), + .wd(prio10_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[109-:3]), + .qs(prio10_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio11( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio11_we), + .wd(prio11_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[106-:3]), + .qs(prio11_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio12( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio12_we), + .wd(prio12_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[103-:3]), + .qs(prio12_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio13( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio13_we), + .wd(prio13_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[100-:3]), + .qs(prio13_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio14( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio14_we), + .wd(prio14_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[97-:3]), + .qs(prio14_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio15( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio15_we), + .wd(prio15_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[94-:3]), + .qs(prio15_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio16( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio16_we), + .wd(prio16_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[91-:3]), + .qs(prio16_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio17( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio17_we), + .wd(prio17_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[88-:3]), + .qs(prio17_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio18( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio18_we), + .wd(prio18_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[85-:3]), + .qs(prio18_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio19( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio19_we), + .wd(prio19_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[82-:3]), + .qs(prio19_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio20( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio20_we), + .wd(prio20_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[79-:3]), + .qs(prio20_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio21( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio21_we), + .wd(prio21_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[76-:3]), + .qs(prio21_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio22( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio22_we), + .wd(prio22_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[73-:3]), + .qs(prio22_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio23( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio23_we), + .wd(prio23_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[70-:3]), + .qs(prio23_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio24( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio24_we), + .wd(prio24_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[67-:3]), + .qs(prio24_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio25( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio25_we), + .wd(prio25_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[64-:3]), + .qs(prio25_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio26( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio26_we), + .wd(prio26_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[61-:3]), + .qs(prio26_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio27( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio27_we), + .wd(prio27_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[58-:3]), + .qs(prio27_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio28( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio28_we), + .wd(prio28_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[55-:3]), + .qs(prio28_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio29( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio29_we), + .wd(prio29_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[52-:3]), + .qs(prio29_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio30( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio30_we), + .wd(prio30_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[49-:3]), + .qs(prio30_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_prio31( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(prio31_we), + .wd(prio31_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[46-:3]), + .qs(prio31_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_0_we), + .wd(ie0_e_0_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[12]), + .qs(ie0_e_0_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_1( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_1_we), + .wd(ie0_e_1_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[13]), + .qs(ie0_e_1_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_2( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_2_we), + .wd(ie0_e_2_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[14]), + .qs(ie0_e_2_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_3( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_3_we), + .wd(ie0_e_3_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[15]), + .qs(ie0_e_3_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_4( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_4_we), + .wd(ie0_e_4_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[16]), + .qs(ie0_e_4_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_5( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_5_we), + .wd(ie0_e_5_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[17]), + .qs(ie0_e_5_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_6( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_6_we), + .wd(ie0_e_6_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[18]), + .qs(ie0_e_6_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_7( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_7_we), + .wd(ie0_e_7_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[19]), + .qs(ie0_e_7_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_8( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_8_we), + .wd(ie0_e_8_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[20]), + .qs(ie0_e_8_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_9( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_9_we), + .wd(ie0_e_9_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[21]), + .qs(ie0_e_9_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_10( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_10_we), + .wd(ie0_e_10_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[22]), + .qs(ie0_e_10_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_11( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_11_we), + .wd(ie0_e_11_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[23]), + .qs(ie0_e_11_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_12( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_12_we), + .wd(ie0_e_12_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[24]), + .qs(ie0_e_12_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_13( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_13_we), + .wd(ie0_e_13_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[25]), + .qs(ie0_e_13_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_14( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_14_we), + .wd(ie0_e_14_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[26]), + .qs(ie0_e_14_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_15( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_15_we), + .wd(ie0_e_15_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[27]), + .qs(ie0_e_15_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_16( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_16_we), + .wd(ie0_e_16_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[28]), + .qs(ie0_e_16_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_17( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_17_we), + .wd(ie0_e_17_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[29]), + .qs(ie0_e_17_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_18( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_18_we), + .wd(ie0_e_18_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[30]), + .qs(ie0_e_18_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_19( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_19_we), + .wd(ie0_e_19_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[31]), + .qs(ie0_e_19_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_20( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_20_we), + .wd(ie0_e_20_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[32]), + .qs(ie0_e_20_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_21( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_21_we), + .wd(ie0_e_21_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[33]), + .qs(ie0_e_21_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_22( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_22_we), + .wd(ie0_e_22_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[34]), + .qs(ie0_e_22_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_23( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_23_we), + .wd(ie0_e_23_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[35]), + .qs(ie0_e_23_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_24( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_24_we), + .wd(ie0_e_24_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[36]), + .qs(ie0_e_24_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_25( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_25_we), + .wd(ie0_e_25_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[37]), + .qs(ie0_e_25_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_26( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_26_we), + .wd(ie0_e_26_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[38]), + .qs(ie0_e_26_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_27( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_27_we), + .wd(ie0_e_27_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[39]), + .qs(ie0_e_27_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_28( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_28_we), + .wd(ie0_e_28_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[40]), + .qs(ie0_e_28_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_29( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_29_we), + .wd(ie0_e_29_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[41]), + .qs(ie0_e_29_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_30( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_30_we), + .wd(ie0_e_30_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[42]), + .qs(ie0_e_30_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ie0_e_31( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ie0_e_31_we), + .wd(ie0_e_31_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[43]), + .qs(ie0_e_31_qs) + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_threshold0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(threshold0_we), + .wd(threshold0_wd), + .de(1'b0), + .d({3 {1'sb0}}), + .qe(), + .q(reg2hw[11-:3]), + .qs(threshold0_qs) + ); + prim_subreg_ext #(.DW(6)) u_cc0( + .re(cc0_re), + .we(cc0_we), + .wd(cc0_wd), + .d(hw2reg[5-:6]), + .qre(reg2hw[1]), + .qe(reg2hw[2]), + .q(reg2hw[8-:6]), + .qs(cc0_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_msip0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(msip0_we), + .wd(msip0_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[-0]), + .qs(msip0_qs) + ); + reg [37:0] addr_hit; + always @(*) begin + addr_hit = {38 {1'sb0}}; + addr_hit[0] = reg_addr == RV_PLIC_IP_OFFSET; + addr_hit[1] = reg_addr == RV_PLIC_LE_OFFSET; + addr_hit[2] = reg_addr == RV_PLIC_PRIO0_OFFSET; + addr_hit[3] = reg_addr == RV_PLIC_PRIO1_OFFSET; + addr_hit[4] = reg_addr == RV_PLIC_PRIO2_OFFSET; + addr_hit[5] = reg_addr == RV_PLIC_PRIO3_OFFSET; + addr_hit[6] = reg_addr == RV_PLIC_PRIO4_OFFSET; + addr_hit[7] = reg_addr == RV_PLIC_PRIO5_OFFSET; + addr_hit[8] = reg_addr == RV_PLIC_PRIO6_OFFSET; + addr_hit[9] = reg_addr == RV_PLIC_PRIO7_OFFSET; + addr_hit[10] = reg_addr == RV_PLIC_PRIO8_OFFSET; + addr_hit[11] = reg_addr == RV_PLIC_PRIO9_OFFSET; + addr_hit[12] = reg_addr == RV_PLIC_PRIO10_OFFSET; + addr_hit[13] = reg_addr == RV_PLIC_PRIO11_OFFSET; + addr_hit[14] = reg_addr == RV_PLIC_PRIO12_OFFSET; + addr_hit[15] = reg_addr == RV_PLIC_PRIO13_OFFSET; + addr_hit[16] = reg_addr == RV_PLIC_PRIO14_OFFSET; + addr_hit[17] = reg_addr == RV_PLIC_PRIO15_OFFSET; + addr_hit[18] = reg_addr == RV_PLIC_PRIO16_OFFSET; + addr_hit[19] = reg_addr == RV_PLIC_PRIO17_OFFSET; + addr_hit[20] = reg_addr == RV_PLIC_PRIO18_OFFSET; + addr_hit[21] = reg_addr == RV_PLIC_PRIO19_OFFSET; + addr_hit[22] = reg_addr == RV_PLIC_PRIO20_OFFSET; + addr_hit[23] = reg_addr == RV_PLIC_PRIO21_OFFSET; + addr_hit[24] = reg_addr == RV_PLIC_PRIO22_OFFSET; + addr_hit[25] = reg_addr == RV_PLIC_PRIO23_OFFSET; + addr_hit[26] = reg_addr == RV_PLIC_PRIO24_OFFSET; + addr_hit[27] = reg_addr == RV_PLIC_PRIO25_OFFSET; + addr_hit[28] = reg_addr == RV_PLIC_PRIO26_OFFSET; + addr_hit[29] = reg_addr == RV_PLIC_PRIO27_OFFSET; + addr_hit[30] = reg_addr == RV_PLIC_PRIO28_OFFSET; + addr_hit[31] = reg_addr == RV_PLIC_PRIO29_OFFSET; + addr_hit[32] = reg_addr == RV_PLIC_PRIO30_OFFSET; + addr_hit[33] = reg_addr == RV_PLIC_PRIO31_OFFSET; + addr_hit[34] = reg_addr == RV_PLIC_IE0_OFFSET; + addr_hit[35] = reg_addr == RV_PLIC_THRESHOLD0_OFFSET; + addr_hit[36] = reg_addr == RV_PLIC_CC0_OFFSET; + addr_hit[37] = reg_addr == RV_PLIC_MSIP0_OFFSET; + end + assign addrmiss = (reg_re || reg_we ? ~|addr_hit : 1'b0); + always @(*) begin + wr_err = 1'b0; + if ((addr_hit[0] && reg_we) && (RV_PLIC_PERMIT[148+:4] != (RV_PLIC_PERMIT[148+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[1] && reg_we) && (RV_PLIC_PERMIT[144+:4] != (RV_PLIC_PERMIT[144+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[2] && reg_we) && (RV_PLIC_PERMIT[140+:4] != (RV_PLIC_PERMIT[140+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[3] && reg_we) && (RV_PLIC_PERMIT[136+:4] != (RV_PLIC_PERMIT[136+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[4] && reg_we) && (RV_PLIC_PERMIT[132+:4] != (RV_PLIC_PERMIT[132+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[5] && reg_we) && (RV_PLIC_PERMIT[128+:4] != (RV_PLIC_PERMIT[128+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[6] && reg_we) && (RV_PLIC_PERMIT[124+:4] != (RV_PLIC_PERMIT[124+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[7] && reg_we) && (RV_PLIC_PERMIT[120+:4] != (RV_PLIC_PERMIT[120+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[8] && reg_we) && (RV_PLIC_PERMIT[116+:4] != (RV_PLIC_PERMIT[116+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[9] && reg_we) && (RV_PLIC_PERMIT[112+:4] != (RV_PLIC_PERMIT[112+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[10] && reg_we) && (RV_PLIC_PERMIT[108+:4] != (RV_PLIC_PERMIT[108+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[11] && reg_we) && (RV_PLIC_PERMIT[104+:4] != (RV_PLIC_PERMIT[104+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[12] && reg_we) && (RV_PLIC_PERMIT[100+:4] != (RV_PLIC_PERMIT[100+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[13] && reg_we) && (RV_PLIC_PERMIT[96+:4] != (RV_PLIC_PERMIT[96+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[14] && reg_we) && (RV_PLIC_PERMIT[92+:4] != (RV_PLIC_PERMIT[92+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[15] && reg_we) && (RV_PLIC_PERMIT[88+:4] != (RV_PLIC_PERMIT[88+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[16] && reg_we) && (RV_PLIC_PERMIT[84+:4] != (RV_PLIC_PERMIT[84+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[17] && reg_we) && (RV_PLIC_PERMIT[80+:4] != (RV_PLIC_PERMIT[80+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[18] && reg_we) && (RV_PLIC_PERMIT[76+:4] != (RV_PLIC_PERMIT[76+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[19] && reg_we) && (RV_PLIC_PERMIT[72+:4] != (RV_PLIC_PERMIT[72+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[20] && reg_we) && (RV_PLIC_PERMIT[68+:4] != (RV_PLIC_PERMIT[68+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[21] && reg_we) && (RV_PLIC_PERMIT[64+:4] != (RV_PLIC_PERMIT[64+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[22] && reg_we) && (RV_PLIC_PERMIT[60+:4] != (RV_PLIC_PERMIT[60+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[23] && reg_we) && (RV_PLIC_PERMIT[56+:4] != (RV_PLIC_PERMIT[56+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[24] && reg_we) && (RV_PLIC_PERMIT[52+:4] != (RV_PLIC_PERMIT[52+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[25] && reg_we) && (RV_PLIC_PERMIT[48+:4] != (RV_PLIC_PERMIT[48+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[26] && reg_we) && (RV_PLIC_PERMIT[44+:4] != (RV_PLIC_PERMIT[44+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[27] && reg_we) && (RV_PLIC_PERMIT[40+:4] != (RV_PLIC_PERMIT[40+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[28] && reg_we) && (RV_PLIC_PERMIT[36+:4] != (RV_PLIC_PERMIT[36+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[29] && reg_we) && (RV_PLIC_PERMIT[32+:4] != (RV_PLIC_PERMIT[32+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[30] && reg_we) && (RV_PLIC_PERMIT[28+:4] != (RV_PLIC_PERMIT[28+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[31] && reg_we) && (RV_PLIC_PERMIT[24+:4] != (RV_PLIC_PERMIT[24+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[32] && reg_we) && (RV_PLIC_PERMIT[20+:4] != (RV_PLIC_PERMIT[20+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[33] && reg_we) && (RV_PLIC_PERMIT[16+:4] != (RV_PLIC_PERMIT[16+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[34] && reg_we) && (RV_PLIC_PERMIT[12+:4] != (RV_PLIC_PERMIT[12+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[35] && reg_we) && (RV_PLIC_PERMIT[8+:4] != (RV_PLIC_PERMIT[8+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[36] && reg_we) && (RV_PLIC_PERMIT[4+:4] != (RV_PLIC_PERMIT[4+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[37] && reg_we) && (RV_PLIC_PERMIT[0+:4] != (RV_PLIC_PERMIT[0+:4] & reg_be))) + wr_err = 1'b1; + end + assign le_le_0_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_0_wd = reg_wdata[0]; + assign le_le_1_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_1_wd = reg_wdata[1]; + assign le_le_2_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_2_wd = reg_wdata[2]; + assign le_le_3_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_3_wd = reg_wdata[3]; + assign le_le_4_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_4_wd = reg_wdata[4]; + assign le_le_5_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_5_wd = reg_wdata[5]; + assign le_le_6_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_6_wd = reg_wdata[6]; + assign le_le_7_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_7_wd = reg_wdata[7]; + assign le_le_8_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_8_wd = reg_wdata[8]; + assign le_le_9_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_9_wd = reg_wdata[9]; + assign le_le_10_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_10_wd = reg_wdata[10]; + assign le_le_11_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_11_wd = reg_wdata[11]; + assign le_le_12_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_12_wd = reg_wdata[12]; + assign le_le_13_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_13_wd = reg_wdata[13]; + assign le_le_14_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_14_wd = reg_wdata[14]; + assign le_le_15_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_15_wd = reg_wdata[15]; + assign le_le_16_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_16_wd = reg_wdata[16]; + assign le_le_17_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_17_wd = reg_wdata[17]; + assign le_le_18_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_18_wd = reg_wdata[18]; + assign le_le_19_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_19_wd = reg_wdata[19]; + assign le_le_20_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_20_wd = reg_wdata[20]; + assign le_le_21_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_21_wd = reg_wdata[21]; + assign le_le_22_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_22_wd = reg_wdata[22]; + assign le_le_23_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_23_wd = reg_wdata[23]; + assign le_le_24_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_24_wd = reg_wdata[24]; + assign le_le_25_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_25_wd = reg_wdata[25]; + assign le_le_26_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_26_wd = reg_wdata[26]; + assign le_le_27_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_27_wd = reg_wdata[27]; + assign le_le_28_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_28_wd = reg_wdata[28]; + assign le_le_29_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_29_wd = reg_wdata[29]; + assign le_le_30_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_30_wd = reg_wdata[30]; + assign le_le_31_we = (addr_hit[1] & reg_we) & ~wr_err; + assign le_le_31_wd = reg_wdata[31]; + assign prio0_we = (addr_hit[2] & reg_we) & ~wr_err; + assign prio0_wd = reg_wdata[2:0]; + assign prio1_we = (addr_hit[3] & reg_we) & ~wr_err; + assign prio1_wd = reg_wdata[2:0]; + assign prio2_we = (addr_hit[4] & reg_we) & ~wr_err; + assign prio2_wd = reg_wdata[2:0]; + assign prio3_we = (addr_hit[5] & reg_we) & ~wr_err; + assign prio3_wd = reg_wdata[2:0]; + assign prio4_we = (addr_hit[6] & reg_we) & ~wr_err; + assign prio4_wd = reg_wdata[2:0]; + assign prio5_we = (addr_hit[7] & reg_we) & ~wr_err; + assign prio5_wd = reg_wdata[2:0]; + assign prio6_we = (addr_hit[8] & reg_we) & ~wr_err; + assign prio6_wd = reg_wdata[2:0]; + assign prio7_we = (addr_hit[9] & reg_we) & ~wr_err; + assign prio7_wd = reg_wdata[2:0]; + assign prio8_we = (addr_hit[10] & reg_we) & ~wr_err; + assign prio8_wd = reg_wdata[2:0]; + assign prio9_we = (addr_hit[11] & reg_we) & ~wr_err; + assign prio9_wd = reg_wdata[2:0]; + assign prio10_we = (addr_hit[12] & reg_we) & ~wr_err; + assign prio10_wd = reg_wdata[2:0]; + assign prio11_we = (addr_hit[13] & reg_we) & ~wr_err; + assign prio11_wd = reg_wdata[2:0]; + assign prio12_we = (addr_hit[14] & reg_we) & ~wr_err; + assign prio12_wd = reg_wdata[2:0]; + assign prio13_we = (addr_hit[15] & reg_we) & ~wr_err; + assign prio13_wd = reg_wdata[2:0]; + assign prio14_we = (addr_hit[16] & reg_we) & ~wr_err; + assign prio14_wd = reg_wdata[2:0]; + assign prio15_we = (addr_hit[17] & reg_we) & ~wr_err; + assign prio15_wd = reg_wdata[2:0]; + assign prio16_we = (addr_hit[18] & reg_we) & ~wr_err; + assign prio16_wd = reg_wdata[2:0]; + assign prio17_we = (addr_hit[19] & reg_we) & ~wr_err; + assign prio17_wd = reg_wdata[2:0]; + assign prio18_we = (addr_hit[20] & reg_we) & ~wr_err; + assign prio18_wd = reg_wdata[2:0]; + assign prio19_we = (addr_hit[21] & reg_we) & ~wr_err; + assign prio19_wd = reg_wdata[2:0]; + assign prio20_we = (addr_hit[22] & reg_we) & ~wr_err; + assign prio20_wd = reg_wdata[2:0]; + assign prio21_we = (addr_hit[23] & reg_we) & ~wr_err; + assign prio21_wd = reg_wdata[2:0]; + assign prio22_we = (addr_hit[24] & reg_we) & ~wr_err; + assign prio22_wd = reg_wdata[2:0]; + assign prio23_we = (addr_hit[25] & reg_we) & ~wr_err; + assign prio23_wd = reg_wdata[2:0]; + assign prio24_we = (addr_hit[26] & reg_we) & ~wr_err; + assign prio24_wd = reg_wdata[2:0]; + assign prio25_we = (addr_hit[27] & reg_we) & ~wr_err; + assign prio25_wd = reg_wdata[2:0]; + assign prio26_we = (addr_hit[28] & reg_we) & ~wr_err; + assign prio26_wd = reg_wdata[2:0]; + assign prio27_we = (addr_hit[29] & reg_we) & ~wr_err; + assign prio27_wd = reg_wdata[2:0]; + assign prio28_we = (addr_hit[30] & reg_we) & ~wr_err; + assign prio28_wd = reg_wdata[2:0]; + assign prio29_we = (addr_hit[31] & reg_we) & ~wr_err; + assign prio29_wd = reg_wdata[2:0]; + assign prio30_we = (addr_hit[32] & reg_we) & ~wr_err; + assign prio30_wd = reg_wdata[2:0]; + assign prio31_we = (addr_hit[33] & reg_we) & ~wr_err; + assign prio31_wd = reg_wdata[2:0]; + assign ie0_e_0_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_0_wd = reg_wdata[0]; + assign ie0_e_1_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_1_wd = reg_wdata[1]; + assign ie0_e_2_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_2_wd = reg_wdata[2]; + assign ie0_e_3_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_3_wd = reg_wdata[3]; + assign ie0_e_4_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_4_wd = reg_wdata[4]; + assign ie0_e_5_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_5_wd = reg_wdata[5]; + assign ie0_e_6_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_6_wd = reg_wdata[6]; + assign ie0_e_7_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_7_wd = reg_wdata[7]; + assign ie0_e_8_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_8_wd = reg_wdata[8]; + assign ie0_e_9_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_9_wd = reg_wdata[9]; + assign ie0_e_10_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_10_wd = reg_wdata[10]; + assign ie0_e_11_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_11_wd = reg_wdata[11]; + assign ie0_e_12_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_12_wd = reg_wdata[12]; + assign ie0_e_13_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_13_wd = reg_wdata[13]; + assign ie0_e_14_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_14_wd = reg_wdata[14]; + assign ie0_e_15_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_15_wd = reg_wdata[15]; + assign ie0_e_16_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_16_wd = reg_wdata[16]; + assign ie0_e_17_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_17_wd = reg_wdata[17]; + assign ie0_e_18_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_18_wd = reg_wdata[18]; + assign ie0_e_19_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_19_wd = reg_wdata[19]; + assign ie0_e_20_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_20_wd = reg_wdata[20]; + assign ie0_e_21_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_21_wd = reg_wdata[21]; + assign ie0_e_22_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_22_wd = reg_wdata[22]; + assign ie0_e_23_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_23_wd = reg_wdata[23]; + assign ie0_e_24_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_24_wd = reg_wdata[24]; + assign ie0_e_25_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_25_wd = reg_wdata[25]; + assign ie0_e_26_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_26_wd = reg_wdata[26]; + assign ie0_e_27_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_27_wd = reg_wdata[27]; + assign ie0_e_28_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_28_wd = reg_wdata[28]; + assign ie0_e_29_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_29_wd = reg_wdata[29]; + assign ie0_e_30_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_30_wd = reg_wdata[30]; + assign ie0_e_31_we = (addr_hit[34] & reg_we) & ~wr_err; + assign ie0_e_31_wd = reg_wdata[31]; + assign threshold0_we = (addr_hit[35] & reg_we) & ~wr_err; + assign threshold0_wd = reg_wdata[2:0]; + assign cc0_we = (addr_hit[36] & reg_we) & ~wr_err; + assign cc0_wd = reg_wdata[5:0]; + assign cc0_re = addr_hit[36] && reg_re; + assign msip0_we = (addr_hit[37] & reg_we) & ~wr_err; + assign msip0_wd = reg_wdata[0]; + always @(*) begin + reg_rdata_next = {DW {1'sb0}}; + case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = ip_p_0_qs; + reg_rdata_next[1] = ip_p_1_qs; + reg_rdata_next[2] = ip_p_2_qs; + reg_rdata_next[3] = ip_p_3_qs; + reg_rdata_next[4] = ip_p_4_qs; + reg_rdata_next[5] = ip_p_5_qs; + reg_rdata_next[6] = ip_p_6_qs; + reg_rdata_next[7] = ip_p_7_qs; + reg_rdata_next[8] = ip_p_8_qs; + reg_rdata_next[9] = ip_p_9_qs; + reg_rdata_next[10] = ip_p_10_qs; + reg_rdata_next[11] = ip_p_11_qs; + reg_rdata_next[12] = ip_p_12_qs; + reg_rdata_next[13] = ip_p_13_qs; + reg_rdata_next[14] = ip_p_14_qs; + reg_rdata_next[15] = ip_p_15_qs; + reg_rdata_next[16] = ip_p_16_qs; + reg_rdata_next[17] = ip_p_17_qs; + reg_rdata_next[18] = ip_p_18_qs; + reg_rdata_next[19] = ip_p_19_qs; + reg_rdata_next[20] = ip_p_20_qs; + reg_rdata_next[21] = ip_p_21_qs; + reg_rdata_next[22] = ip_p_22_qs; + reg_rdata_next[23] = ip_p_23_qs; + reg_rdata_next[24] = ip_p_24_qs; + reg_rdata_next[25] = ip_p_25_qs; + reg_rdata_next[26] = ip_p_26_qs; + reg_rdata_next[27] = ip_p_27_qs; + reg_rdata_next[28] = ip_p_28_qs; + reg_rdata_next[29] = ip_p_29_qs; + reg_rdata_next[30] = ip_p_30_qs; + reg_rdata_next[31] = ip_p_31_qs; + end + addr_hit[1]: begin + reg_rdata_next[0] = le_le_0_qs; + reg_rdata_next[1] = le_le_1_qs; + reg_rdata_next[2] = le_le_2_qs; + reg_rdata_next[3] = le_le_3_qs; + reg_rdata_next[4] = le_le_4_qs; + reg_rdata_next[5] = le_le_5_qs; + reg_rdata_next[6] = le_le_6_qs; + reg_rdata_next[7] = le_le_7_qs; + reg_rdata_next[8] = le_le_8_qs; + reg_rdata_next[9] = le_le_9_qs; + reg_rdata_next[10] = le_le_10_qs; + reg_rdata_next[11] = le_le_11_qs; + reg_rdata_next[12] = le_le_12_qs; + reg_rdata_next[13] = le_le_13_qs; + reg_rdata_next[14] = le_le_14_qs; + reg_rdata_next[15] = le_le_15_qs; + reg_rdata_next[16] = le_le_16_qs; + reg_rdata_next[17] = le_le_17_qs; + reg_rdata_next[18] = le_le_18_qs; + reg_rdata_next[19] = le_le_19_qs; + reg_rdata_next[20] = le_le_20_qs; + reg_rdata_next[21] = le_le_21_qs; + reg_rdata_next[22] = le_le_22_qs; + reg_rdata_next[23] = le_le_23_qs; + reg_rdata_next[24] = le_le_24_qs; + reg_rdata_next[25] = le_le_25_qs; + reg_rdata_next[26] = le_le_26_qs; + reg_rdata_next[27] = le_le_27_qs; + reg_rdata_next[28] = le_le_28_qs; + reg_rdata_next[29] = le_le_29_qs; + reg_rdata_next[30] = le_le_30_qs; + reg_rdata_next[31] = le_le_31_qs; + end + addr_hit[2]: reg_rdata_next[2:0] = prio0_qs; + addr_hit[3]: reg_rdata_next[2:0] = prio1_qs; + addr_hit[4]: reg_rdata_next[2:0] = prio2_qs; + addr_hit[5]: reg_rdata_next[2:0] = prio3_qs; + addr_hit[6]: reg_rdata_next[2:0] = prio4_qs; + addr_hit[7]: reg_rdata_next[2:0] = prio5_qs; + addr_hit[8]: reg_rdata_next[2:0] = prio6_qs; + addr_hit[9]: reg_rdata_next[2:0] = prio7_qs; + addr_hit[10]: reg_rdata_next[2:0] = prio8_qs; + addr_hit[11]: reg_rdata_next[2:0] = prio9_qs; + addr_hit[12]: reg_rdata_next[2:0] = prio10_qs; + addr_hit[13]: reg_rdata_next[2:0] = prio11_qs; + addr_hit[14]: reg_rdata_next[2:0] = prio12_qs; + addr_hit[15]: reg_rdata_next[2:0] = prio13_qs; + addr_hit[16]: reg_rdata_next[2:0] = prio14_qs; + addr_hit[17]: reg_rdata_next[2:0] = prio15_qs; + addr_hit[18]: reg_rdata_next[2:0] = prio16_qs; + addr_hit[19]: reg_rdata_next[2:0] = prio17_qs; + addr_hit[20]: reg_rdata_next[2:0] = prio18_qs; + addr_hit[21]: reg_rdata_next[2:0] = prio19_qs; + addr_hit[22]: reg_rdata_next[2:0] = prio20_qs; + addr_hit[23]: reg_rdata_next[2:0] = prio21_qs; + addr_hit[24]: reg_rdata_next[2:0] = prio22_qs; + addr_hit[25]: reg_rdata_next[2:0] = prio23_qs; + addr_hit[26]: reg_rdata_next[2:0] = prio24_qs; + addr_hit[27]: reg_rdata_next[2:0] = prio25_qs; + addr_hit[28]: reg_rdata_next[2:0] = prio26_qs; + addr_hit[29]: reg_rdata_next[2:0] = prio27_qs; + addr_hit[30]: reg_rdata_next[2:0] = prio28_qs; + addr_hit[31]: reg_rdata_next[2:0] = prio29_qs; + addr_hit[32]: reg_rdata_next[2:0] = prio30_qs; + addr_hit[33]: reg_rdata_next[2:0] = prio31_qs; + addr_hit[34]: begin + reg_rdata_next[0] = ie0_e_0_qs; + reg_rdata_next[1] = ie0_e_1_qs; + reg_rdata_next[2] = ie0_e_2_qs; + reg_rdata_next[3] = ie0_e_3_qs; + reg_rdata_next[4] = ie0_e_4_qs; + reg_rdata_next[5] = ie0_e_5_qs; + reg_rdata_next[6] = ie0_e_6_qs; + reg_rdata_next[7] = ie0_e_7_qs; + reg_rdata_next[8] = ie0_e_8_qs; + reg_rdata_next[9] = ie0_e_9_qs; + reg_rdata_next[10] = ie0_e_10_qs; + reg_rdata_next[11] = ie0_e_11_qs; + reg_rdata_next[12] = ie0_e_12_qs; + reg_rdata_next[13] = ie0_e_13_qs; + reg_rdata_next[14] = ie0_e_14_qs; + reg_rdata_next[15] = ie0_e_15_qs; + reg_rdata_next[16] = ie0_e_16_qs; + reg_rdata_next[17] = ie0_e_17_qs; + reg_rdata_next[18] = ie0_e_18_qs; + reg_rdata_next[19] = ie0_e_19_qs; + reg_rdata_next[20] = ie0_e_20_qs; + reg_rdata_next[21] = ie0_e_21_qs; + reg_rdata_next[22] = ie0_e_22_qs; + reg_rdata_next[23] = ie0_e_23_qs; + reg_rdata_next[24] = ie0_e_24_qs; + reg_rdata_next[25] = ie0_e_25_qs; + reg_rdata_next[26] = ie0_e_26_qs; + reg_rdata_next[27] = ie0_e_27_qs; + reg_rdata_next[28] = ie0_e_28_qs; + reg_rdata_next[29] = ie0_e_29_qs; + reg_rdata_next[30] = ie0_e_30_qs; + reg_rdata_next[31] = ie0_e_31_qs; + end + addr_hit[35]: reg_rdata_next[2:0] = threshold0_qs; + addr_hit[36]: reg_rdata_next[5:0] = cc0_qs; + addr_hit[37]: reg_rdata_next[0] = msip0_qs; + default: reg_rdata_next = {DW {1'sb1}}; + endcase + end +endmodule +module rv_plic_target ( + clk_i, + rst_ni, + ip_i, + ie_i, + prio_i, + threshold_i, + irq_o, + irq_id_o +); + parameter signed [31:0] N_SOURCE = 32; + parameter signed [31:0] MAX_PRIO = 7; + localparam signed [31:0] SrcWidth = $clog2(N_SOURCE + 1); + localparam signed [31:0] PrioWidth = $clog2(MAX_PRIO + 1); + input clk_i; + input rst_ni; + input [N_SOURCE - 1:0] ip_i; + input [N_SOURCE - 1:0] ie_i; + input [(0 >= (N_SOURCE - 1) ? ((2 - N_SOURCE) * PrioWidth) + (((N_SOURCE - 1) * PrioWidth) - 1) : (N_SOURCE * PrioWidth) - 1):(0 >= (N_SOURCE - 1) ? (N_SOURCE - 1) * PrioWidth : 0)] prio_i; + input [PrioWidth - 1:0] threshold_i; + output wire irq_o; + output wire [SrcWidth - 1:0] irq_id_o; + localparam signed [31:0] NumLevels = $clog2(N_SOURCE); + wire [(2 ** (NumLevels + 1)) - 2:0] is_tree; + wire [(((2 ** (NumLevels + 1)) - 2) >= 0 ? (((2 ** (NumLevels + 1)) - 1) * SrcWidth) - 1 : ((3 - (2 ** (NumLevels + 1))) * SrcWidth) + ((((2 ** (NumLevels + 1)) - 2) * SrcWidth) - 1)):(((2 ** (NumLevels + 1)) - 2) >= 0 ? 0 : ((2 ** (NumLevels + 1)) - 2) * SrcWidth)] id_tree; + wire [(((2 ** (NumLevels + 1)) - 2) >= 0 ? (((2 ** (NumLevels + 1)) - 1) * PrioWidth) - 1 : ((3 - (2 ** (NumLevels + 1))) * PrioWidth) + ((((2 ** (NumLevels + 1)) - 2) * PrioWidth) - 1)):(((2 ** (NumLevels + 1)) - 2) >= 0 ? 0 : ((2 ** (NumLevels + 1)) - 2) * PrioWidth)] max_tree; + generate + genvar level; + for (level = 0; level < (NumLevels + 1); level = level + 1) begin : gen_tree + localparam signed [31:0] Base0 = (2 ** level) - 1; + localparam signed [31:0] Base1 = (2 ** (level + 1)) - 1; + genvar offset; + for (offset = 0; offset < (2 ** level); offset = offset + 1) begin : gen_level + localparam signed [31:0] Pa = Base0 + offset; + localparam signed [31:0] C0 = Base1 + (2 * offset); + localparam signed [31:0] C1 = (Base1 + (2 * offset)) + 1; + if (level == NumLevels) begin : gen_leafs + if (offset < N_SOURCE) begin : gen_assign + assign is_tree[Pa] = ip_i[offset] & ie_i[offset]; + assign id_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? Pa : ((2 ** (NumLevels + 1)) - 2) - Pa) * SrcWidth+:SrcWidth] = offset; + assign max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? Pa : ((2 ** (NumLevels + 1)) - 2) - Pa) * PrioWidth+:PrioWidth] = prio_i[(0 >= (N_SOURCE - 1) ? offset : (N_SOURCE - 1) - offset) * PrioWidth+:PrioWidth]; + end + else begin : gen_tie_off + assign is_tree[Pa] = 1'sb0; + assign id_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? Pa : ((2 ** (NumLevels + 1)) - 2) - Pa) * SrcWidth+:SrcWidth] = {SrcWidth {1'sb0}}; + assign max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? Pa : ((2 ** (NumLevels + 1)) - 2) - Pa) * PrioWidth+:PrioWidth] = {PrioWidth {1'sb0}}; + end + end + else begin : gen_nodes + wire sel; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + assign sel = (~is_tree[C0] & is_tree[C1]) | ((is_tree[C0] & is_tree[C1]) & sv2v_cast_1(max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? C1 : ((2 ** (NumLevels + 1)) - 2) - C1) * PrioWidth+:PrioWidth] > max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? C0 : ((2 ** (NumLevels + 1)) - 2) - C0) * PrioWidth+:PrioWidth])); + assign is_tree[Pa] = (sel & is_tree[C1]) | (~sel & is_tree[C0]); + assign id_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? Pa : ((2 ** (NumLevels + 1)) - 2) - Pa) * SrcWidth+:SrcWidth] = ({SrcWidth {sel}} & id_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? C1 : ((2 ** (NumLevels + 1)) - 2) - C1) * SrcWidth+:SrcWidth]) | ({SrcWidth {~sel}} & id_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? C0 : ((2 ** (NumLevels + 1)) - 2) - C0) * SrcWidth+:SrcWidth]); + assign max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? Pa : ((2 ** (NumLevels + 1)) - 2) - Pa) * PrioWidth+:PrioWidth] = ({PrioWidth {sel}} & max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? C1 : ((2 ** (NumLevels + 1)) - 2) - C1) * PrioWidth+:PrioWidth]) | ({PrioWidth {~sel}} & max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? C0 : ((2 ** (NumLevels + 1)) - 2) - C0) * PrioWidth+:PrioWidth]); + end + end + end + endgenerate + wire irq_d; + reg irq_q; + wire [SrcWidth - 1:0] irq_id_d; + reg [SrcWidth - 1:0] irq_id_q; + assign irq_d = (max_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? 0 : (2 ** (NumLevels + 1)) - 2) * PrioWidth+:PrioWidth] > threshold_i ? is_tree[0] : 1'b0); + assign irq_id_d = (is_tree[0] ? id_tree[(((2 ** (NumLevels + 1)) - 2) >= 0 ? 0 : (2 ** (NumLevels + 1)) - 2) * SrcWidth+:SrcWidth] : {SrcWidth {1'sb0}}); + always @(posedge clk_i or negedge rst_ni) begin : gen_regs + if (!rst_ni) begin + irq_q <= 1'b0; + irq_id_q <= {SrcWidth {1'sb0}}; + end + else begin + irq_q <= irq_d; + irq_id_q <= irq_id_d; + end + end + assign irq_o = irq_q; + assign irq_id_o = irq_id_q; +endmodule +module rv_timer ( + clk_i, + rst_ni, + tl_i, + tl_o, + intr_timer_expired_0_0_o +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire intr_timer_expired_0_0_o; + localparam signed [31:0] N_HARTS = 1; + localparam signed [31:0] N_TIMERS = 1; + localparam signed [31:0] rv_timer_reg_pkg_N_HARTS = 1; + localparam signed [31:0] rv_timer_reg_pkg_N_TIMERS = 1; + localparam [8:0] RV_TIMER_CTRL_OFFSET = 9'h000; + localparam [8:0] RV_TIMER_CFG0_OFFSET = 9'h100; + localparam [8:0] RV_TIMER_TIMER_V_LOWER0_OFFSET = 9'h104; + localparam [8:0] RV_TIMER_TIMER_V_UPPER0_OFFSET = 9'h108; + localparam [8:0] RV_TIMER_COMPARE_LOWER0_0_OFFSET = 9'h10c; + localparam [8:0] RV_TIMER_COMPARE_UPPER0_0_OFFSET = 9'h110; + localparam [8:0] RV_TIMER_INTR_ENABLE0_OFFSET = 9'h114; + localparam [8:0] RV_TIMER_INTR_STATE0_OFFSET = 9'h118; + localparam [8:0] RV_TIMER_INTR_TEST0_OFFSET = 9'h11c; + localparam signed [31:0] RV_TIMER_CTRL = 0; + localparam signed [31:0] RV_TIMER_CFG0 = 1; + localparam signed [31:0] RV_TIMER_TIMER_V_LOWER0 = 2; + localparam signed [31:0] RV_TIMER_TIMER_V_UPPER0 = 3; + localparam signed [31:0] RV_TIMER_COMPARE_LOWER0_0 = 4; + localparam signed [31:0] RV_TIMER_COMPARE_UPPER0_0 = 5; + localparam signed [31:0] RV_TIMER_INTR_ENABLE0 = 6; + localparam signed [31:0] RV_TIMER_INTR_STATE0 = 7; + localparam signed [31:0] RV_TIMER_INTR_TEST0 = 8; + localparam [35:0] RV_TIMER_PERMIT = {4'b0001, 4'b0111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b0001, 4'b0001, 4'b0001}; + wire [154:0] reg2hw; + wire [67:0] hw2reg; + wire [N_HARTS - 1:0] active; + wire [((2 - N_HARTS) * 12) + (((N_HARTS - 1) * 12) - 1):(N_HARTS - 1) * 12] prescaler; + wire [((2 - N_HARTS) * 8) + (((N_HARTS - 1) * 8) - 1):(N_HARTS - 1) * 8] step; + wire [N_HARTS - 1:0] tick; + wire [63:0] mtime_d [0:N_HARTS - 1]; + wire [63:0] mtime [0:N_HARTS - 1]; + wire [((((((2 - N_HARTS) * (2 - N_TIMERS)) + (((N_TIMERS - 1) + ((N_HARTS - 1) * (2 - N_TIMERS))) - 1)) - ((N_TIMERS - 1) + ((N_HARTS - 1) * (2 - N_TIMERS)))) + 1) * 64) + ((((N_TIMERS - 1) + ((N_HARTS - 1) * (2 - N_TIMERS))) * 64) - 1):((N_TIMERS - 1) + ((N_HARTS - 1) * (2 - N_TIMERS))) * 64] mtimecmp; + wire mtimecmp_update [0:N_HARTS - 1][0:N_TIMERS - 1]; + wire [(N_HARTS * N_TIMERS) - 1:0] intr_timer_set; + wire [(N_HARTS * N_TIMERS) - 1:0] intr_timer_en; + wire [(N_HARTS * N_TIMERS) - 1:0] intr_timer_test_q; + wire [N_HARTS - 1:0] intr_timer_test_qe; + wire [(N_HARTS * N_TIMERS) - 1:0] intr_timer_state_q; + wire [N_HARTS - 1:0] intr_timer_state_de; + wire [(N_HARTS * N_TIMERS) - 1:0] intr_timer_state_d; + wire [(N_HARTS * N_TIMERS) - 1:0] intr_out; + assign active[0] = reg2hw[154]; + assign prescaler = reg2hw[153-:12]; + assign step = reg2hw[141-:8]; + assign hw2reg[2] = tick[0]; + assign hw2reg[35] = tick[0]; + assign hw2reg[34-:32] = mtime_d[0][63:32]; + assign hw2reg[67-:32] = mtime_d[0][31:0]; + assign mtime[0] = {reg2hw[101-:32], reg2hw[133-:32]}; + assign mtimecmp = {reg2hw[36-:32], reg2hw[69-:32]}; + assign mtimecmp_update[0][0] = reg2hw[4] | reg2hw[37]; + assign intr_timer_expired_0_0_o = intr_out[0]; + assign intr_timer_en = reg2hw[3]; + assign intr_timer_state_q = reg2hw[2]; + assign intr_timer_test_q = reg2hw[1]; + assign intr_timer_test_qe = reg2hw[0]; + assign hw2reg[0] = intr_timer_state_de | mtimecmp_update[0][0]; + assign hw2reg[1] = intr_timer_state_d & ~mtimecmp_update[0][0]; + generate + genvar h; + for (h = 0; h < N_HARTS; h = h + 1) begin : gen_harts + prim_intr_hw #(.Width(N_TIMERS)) u_intr_hw( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(intr_timer_set), + .reg2hw_intr_enable_q_i(intr_timer_en[h * N_TIMERS+:N_TIMERS]), + .reg2hw_intr_test_q_i(intr_timer_test_q[h * N_TIMERS+:N_TIMERS]), + .reg2hw_intr_test_qe_i(intr_timer_test_qe[h]), + .reg2hw_intr_state_q_i(intr_timer_state_q[h * N_TIMERS+:N_TIMERS]), + .hw2reg_intr_state_de_o(intr_timer_state_de), + .hw2reg_intr_state_d_o(intr_timer_state_d[h * N_TIMERS+:N_TIMERS]), + .intr_o(intr_out[h * N_TIMERS+:N_TIMERS]) + ); + timer_core #(.N(N_TIMERS)) u_core( + .clk_i(clk_i), + .rst_ni(rst_ni), + .active(active[h]), + .prescaler(prescaler[h * 12+:12]), + .step(step[h * 8+:8]), + .tick(tick[h]), + .mtime_d(mtime_d[h]), + .mtime(mtime[h]), + .mtimecmp(mtimecmp[64 * ((N_TIMERS - 1) + (h * (2 - N_TIMERS)))+:64 * (2 - N_TIMERS)]), + .intr(intr_timer_set[h * N_TIMERS+:N_TIMERS]) + ); + end + endgenerate + rv_timer_reg_top u_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_i), + .tl_o(tl_o), + .reg2hw(reg2hw), + .hw2reg(hw2reg), + .devmode_i(1'b1) + ); +endmodule +module rv_timer_reg_top ( + clk_i, + rst_ni, + tl_i, + tl_o, + reg2hw, + hw2reg, + devmode_i +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire [154:0] reg2hw; + input wire [67:0] hw2reg; + input devmode_i; + localparam signed [31:0] N_HARTS = 1; + localparam signed [31:0] N_TIMERS = 1; + localparam [8:0] RV_TIMER_CTRL_OFFSET = 9'h000; + localparam [8:0] RV_TIMER_CFG0_OFFSET = 9'h100; + localparam [8:0] RV_TIMER_TIMER_V_LOWER0_OFFSET = 9'h104; + localparam [8:0] RV_TIMER_TIMER_V_UPPER0_OFFSET = 9'h108; + localparam [8:0] RV_TIMER_COMPARE_LOWER0_0_OFFSET = 9'h10c; + localparam [8:0] RV_TIMER_COMPARE_UPPER0_0_OFFSET = 9'h110; + localparam [8:0] RV_TIMER_INTR_ENABLE0_OFFSET = 9'h114; + localparam [8:0] RV_TIMER_INTR_STATE0_OFFSET = 9'h118; + localparam [8:0] RV_TIMER_INTR_TEST0_OFFSET = 9'h11c; + localparam signed [31:0] RV_TIMER_CTRL = 0; + localparam signed [31:0] RV_TIMER_CFG0 = 1; + localparam signed [31:0] RV_TIMER_TIMER_V_LOWER0 = 2; + localparam signed [31:0] RV_TIMER_TIMER_V_UPPER0 = 3; + localparam signed [31:0] RV_TIMER_COMPARE_LOWER0_0 = 4; + localparam signed [31:0] RV_TIMER_COMPARE_UPPER0_0 = 5; + localparam signed [31:0] RV_TIMER_INTR_ENABLE0 = 6; + localparam signed [31:0] RV_TIMER_INTR_STATE0 = 7; + localparam signed [31:0] RV_TIMER_INTR_TEST0 = 8; + localparam [35:0] RV_TIMER_PERMIT = {4'b0001, 4'b0111, 4'b1111, 4'b1111, 4'b1111, 4'b1111, 4'b0001, 4'b0001, 4'b0001}; + localparam signed [31:0] AW = 9; + localparam signed [31:0] DW = 32; + localparam signed [31:0] DBW = DW / 8; + wire reg_we; + wire reg_re; + wire [AW - 1:0] reg_addr; + wire [DW - 1:0] reg_wdata; + wire [DBW - 1:0] reg_be; + wire [DW - 1:0] reg_rdata; + wire reg_error; + wire addrmiss; + reg wr_err; + reg [DW - 1:0] reg_rdata_next; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_reg_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_reg_d2h; + assign tl_reg_h2d = tl_i; + assign tl_o = tl_reg_d2h; + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW) + ) u_reg_if( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_reg_h2d), + .tl_o(tl_reg_d2h), + .we_o(reg_we), + .re_o(reg_re), + .addr_o(reg_addr), + .wdata_o(reg_wdata), + .be_o(reg_be), + .rdata_i(reg_rdata), + .error_i(reg_error) + ); + assign reg_rdata = reg_rdata_next; + assign reg_error = (devmode_i & addrmiss) | wr_err; + wire ctrl_qs; + wire ctrl_wd; + wire ctrl_we; + wire [11:0] cfg0_prescale_qs; + wire [11:0] cfg0_prescale_wd; + wire cfg0_prescale_we; + wire [7:0] cfg0_step_qs; + wire [7:0] cfg0_step_wd; + wire cfg0_step_we; + wire [31:0] timer_v_lower0_qs; + wire [31:0] timer_v_lower0_wd; + wire timer_v_lower0_we; + wire [31:0] timer_v_upper0_qs; + wire [31:0] timer_v_upper0_wd; + wire timer_v_upper0_we; + wire [31:0] compare_lower0_0_qs; + wire [31:0] compare_lower0_0_wd; + wire compare_lower0_0_we; + wire [31:0] compare_upper0_0_qs; + wire [31:0] compare_upper0_0_wd; + wire compare_upper0_0_we; + wire intr_enable0_qs; + wire intr_enable0_wd; + wire intr_enable0_we; + wire intr_state0_qs; + wire intr_state0_wd; + wire intr_state0_we; + wire intr_test0_wd; + wire intr_test0_we; + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_we), + .wd(ctrl_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[154]), + .qs(ctrl_qs) + ); + prim_subreg #( + .DW(12), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(12'h000) + ) u_cfg0_prescale( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(cfg0_prescale_we), + .wd(cfg0_prescale_wd), + .de(1'b0), + .d({12 {1'sb0}}), + .qe(), + .q(reg2hw[153-:12]), + .qs(cfg0_prescale_qs) + ); + prim_subreg #( + .DW(8), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(8'h01) + ) u_cfg0_step( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(cfg0_step_we), + .wd(cfg0_step_wd), + .de(1'b0), + .d({8 {1'sb0}}), + .qe(), + .q(reg2hw[141-:8]), + .qs(cfg0_step_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_timer_v_lower0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(timer_v_lower0_we), + .wd(timer_v_lower0_wd), + .de(hw2reg[35]), + .d(hw2reg[67-:32]), + .qe(), + .q(reg2hw[133-:32]), + .qs(timer_v_lower0_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'h00000000) + ) u_timer_v_upper0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(timer_v_upper0_we), + .wd(timer_v_upper0_wd), + .de(hw2reg[2]), + .d(hw2reg[34-:32]), + .qe(), + .q(reg2hw[101-:32]), + .qs(timer_v_upper0_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'hffffffff) + ) u_compare_lower0_0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(compare_lower0_0_we), + .wd(compare_lower0_0_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(reg2hw[37]), + .q(reg2hw[69-:32]), + .qs(compare_lower0_0_qs) + ); + prim_subreg #( + .DW(32), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(32'hffffffff) + ) u_compare_upper0_0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(compare_upper0_0_we), + .wd(compare_upper0_0_wd), + .de(1'b0), + .d({32 {1'sb0}}), + .qe(reg2hw[4]), + .q(reg2hw[36-:32]), + .qs(compare_upper0_0_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable0_we), + .wd(intr_enable0_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[3]), + .qs(intr_enable0_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state0( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state0_we), + .wd(intr_state0_wd), + .de(hw2reg[0]), + .d(hw2reg[1]), + .qe(), + .q(reg2hw[2]), + .qs(intr_state0_qs) + ); + prim_subreg_ext #(.DW(1)) u_intr_test0( + .re(1'b0), + .we(intr_test0_we), + .wd(intr_test0_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[0]), + .q(reg2hw[1]), + .qs() + ); + reg [8:0] addr_hit; + always @(*) begin + addr_hit = {9 {1'sb0}}; + addr_hit[0] = reg_addr == RV_TIMER_CTRL_OFFSET; + addr_hit[1] = reg_addr == RV_TIMER_CFG0_OFFSET; + addr_hit[2] = reg_addr == RV_TIMER_TIMER_V_LOWER0_OFFSET; + addr_hit[3] = reg_addr == RV_TIMER_TIMER_V_UPPER0_OFFSET; + addr_hit[4] = reg_addr == RV_TIMER_COMPARE_LOWER0_0_OFFSET; + addr_hit[5] = reg_addr == RV_TIMER_COMPARE_UPPER0_0_OFFSET; + addr_hit[6] = reg_addr == RV_TIMER_INTR_ENABLE0_OFFSET; + addr_hit[7] = reg_addr == RV_TIMER_INTR_STATE0_OFFSET; + addr_hit[8] = reg_addr == RV_TIMER_INTR_TEST0_OFFSET; + end + assign addrmiss = (reg_re || reg_we ? ~|addr_hit : 1'b0); + always @(*) begin + wr_err = 1'b0; + if ((addr_hit[0] && reg_we) && (RV_TIMER_PERMIT[32+:4] != (RV_TIMER_PERMIT[32+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[1] && reg_we) && (RV_TIMER_PERMIT[28+:4] != (RV_TIMER_PERMIT[28+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[2] && reg_we) && (RV_TIMER_PERMIT[24+:4] != (RV_TIMER_PERMIT[24+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[3] && reg_we) && (RV_TIMER_PERMIT[20+:4] != (RV_TIMER_PERMIT[20+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[4] && reg_we) && (RV_TIMER_PERMIT[16+:4] != (RV_TIMER_PERMIT[16+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[5] && reg_we) && (RV_TIMER_PERMIT[12+:4] != (RV_TIMER_PERMIT[12+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[6] && reg_we) && (RV_TIMER_PERMIT[8+:4] != (RV_TIMER_PERMIT[8+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[7] && reg_we) && (RV_TIMER_PERMIT[4+:4] != (RV_TIMER_PERMIT[4+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[8] && reg_we) && (RV_TIMER_PERMIT[0+:4] != (RV_TIMER_PERMIT[0+:4] & reg_be))) + wr_err = 1'b1; + end + assign ctrl_we = (addr_hit[0] & reg_we) & ~wr_err; + assign ctrl_wd = reg_wdata[0]; + assign cfg0_prescale_we = (addr_hit[1] & reg_we) & ~wr_err; + assign cfg0_prescale_wd = reg_wdata[11:0]; + assign cfg0_step_we = (addr_hit[1] & reg_we) & ~wr_err; + assign cfg0_step_wd = reg_wdata[23:16]; + assign timer_v_lower0_we = (addr_hit[2] & reg_we) & ~wr_err; + assign timer_v_lower0_wd = reg_wdata[31:0]; + assign timer_v_upper0_we = (addr_hit[3] & reg_we) & ~wr_err; + assign timer_v_upper0_wd = reg_wdata[31:0]; + assign compare_lower0_0_we = (addr_hit[4] & reg_we) & ~wr_err; + assign compare_lower0_0_wd = reg_wdata[31:0]; + assign compare_upper0_0_we = (addr_hit[5] & reg_we) & ~wr_err; + assign compare_upper0_0_wd = reg_wdata[31:0]; + assign intr_enable0_we = (addr_hit[6] & reg_we) & ~wr_err; + assign intr_enable0_wd = reg_wdata[0]; + assign intr_state0_we = (addr_hit[7] & reg_we) & ~wr_err; + assign intr_state0_wd = reg_wdata[0]; + assign intr_test0_we = (addr_hit[8] & reg_we) & ~wr_err; + assign intr_test0_wd = reg_wdata[0]; + always @(*) begin + reg_rdata_next = {DW {1'sb0}}; + case (1'b1) + addr_hit[0]: reg_rdata_next[0] = ctrl_qs; + addr_hit[1]: begin + reg_rdata_next[11:0] = cfg0_prescale_qs; + reg_rdata_next[23:16] = cfg0_step_qs; + end + addr_hit[2]: reg_rdata_next[31:0] = timer_v_lower0_qs; + addr_hit[3]: reg_rdata_next[31:0] = timer_v_upper0_qs; + addr_hit[4]: reg_rdata_next[31:0] = compare_lower0_0_qs; + addr_hit[5]: reg_rdata_next[31:0] = compare_upper0_0_qs; + addr_hit[6]: reg_rdata_next[0] = intr_enable0_qs; + addr_hit[7]: reg_rdata_next[0] = intr_state0_qs; + addr_hit[8]: reg_rdata_next[0] = 1'sb0; + default: reg_rdata_next = {DW {1'sb1}}; + endcase + end +endmodule +module timer_core ( + clk_i, + rst_ni, + active, + prescaler, + step, + tick, + mtime_d, + mtime, + mtimecmp, + intr +); + parameter signed [31:0] N = 1; + input clk_i; + input rst_ni; + input active; + input [11:0] prescaler; + input [7:0] step; + output wire tick; + output wire [63:0] mtime_d; + input [63:0] mtime; + input [(0 >= (N - 1) ? ((2 - N) * 64) + (((N - 1) * 64) - 1) : (N * 64) - 1):(0 >= (N - 1) ? (N - 1) * 64 : 0)] mtimecmp; + output wire [N - 1:0] intr; + reg [11:0] tick_count; + always @(posedge clk_i or negedge rst_ni) begin : generate_tick + if (!rst_ni) + tick_count <= 12'h000; + else if (!active) + tick_count <= 12'h000; + else if (tick_count == prescaler) + tick_count <= 12'h000; + else + tick_count <= tick_count + 1'b1; + end + assign tick = active & (tick_count >= prescaler); + function automatic [63:0] sv2v_cast_64; + input reg [63:0] inp; + sv2v_cast_64 = inp; + endfunction + assign mtime_d = mtime + sv2v_cast_64(step); + generate + genvar t; + for (t = 0; t < N; t = t + 1) begin : gen_intr + assign intr[t] = active & (mtime >= mtimecmp[(0 >= (N - 1) ? t : (N - 1) - t) * 64+:64]); + end + endgenerate +endmodule +module tlul_adapter_host ( + clk_i, + rst_ni, + req_i, + gnt_o, + addr_i, + we_i, + wdata_i, + be_i, + valid_o, + rdata_o, + err_o, + tl_o, + tl_i +); + parameter [31:0] MAX_REQS = 2; + input clk_i; + input rst_ni; + input req_i; + output wire gnt_o; + localparam signed [31:0] top_pkg_TL_AW = 32; + input wire [top_pkg_TL_AW - 1:0] addr_i; + input wire we_i; + localparam signed [31:0] top_pkg_TL_DW = 32; + input wire [top_pkg_TL_DW - 1:0] wdata_i; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + input wire [top_pkg_TL_DBW - 1:0] be_i; + output wire valid_o; + output wire [top_pkg_TL_DW - 1:0] rdata_o; + output wire err_o; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_o; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_i; + localparam signed [31:0] WordSize = $clog2(top_pkg_TL_DBW); + wire [top_pkg_TL_AIW - 1:0] tl_source; + wire [top_pkg_TL_DBW - 1:0] tl_be; + generate + if (MAX_REQS == 1) begin : g_single_req + assign tl_source = {top_pkg_TL_AIW {1'sb0}}; + end + else begin : g_multiple_reqs + localparam signed [31:0] ReqNumW = $clog2(MAX_REQS); + reg [ReqNumW - 1:0] source_d; + reg [ReqNumW - 1:0] source_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + source_q <= {ReqNumW {1'sb0}}; + else + source_q <= source_d; + always @(*) begin + source_d = source_q; + if (req_i && gnt_o) + if (source_q == (MAX_REQS - 1)) + source_d = {ReqNumW {1'sb0}}; + else + source_d = source_q + 1; + end + function automatic [7:0] sv2v_cast_8; + input reg [7:0] inp; + sv2v_cast_8 = inp; + endfunction + assign tl_source = sv2v_cast_8(source_q); + end + endgenerate + assign tl_be = (~we_i ? {top_pkg_TL_DBW {1'b1}} : be_i); + localparam [2:0] tlul_pkg_Get = 3'h4; + localparam [2:0] tlul_pkg_PutFullData = 3'h0; + localparam [2:0] tlul_pkg_PutPartialData = 3'h1; + function automatic signed [top_pkg_TL_SZW - 1:0] sv2v_cast_38DDD_signed; + input reg signed [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_38DDD_signed = inp; + endfunction + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + function automatic [15:0] sv2v_cast_16; + input reg [15:0] inp; + sv2v_cast_16 = inp; + endfunction + assign tl_o = {sv2v_cast_1(req_i), sv2v_cast_3((~we_i ? tlul_pkg_Get : (&be_i ? tlul_pkg_PutFullData : tlul_pkg_PutPartialData))), 3'h0, sv2v_cast_F00AF(sv2v_cast_38DDD_signed(WordSize)), sv2v_cast_F1F18(tl_source), sv2v_cast_4CD75({addr_i[31:WordSize], {WordSize {1'b0}}}), sv2v_cast_37199(tl_be), sv2v_cast_2497D(wdata_i), sv2v_cast_16({7'b0000000, 1'sb0, 8'b00000000}), 1'b1}; + assign gnt_o = tl_i[0]; + assign valid_o = tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))]; + assign rdata_o = tl_i[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1]; + assign err_o = tl_i[1]; +endmodule +module tlul_adapter_reg ( + clk_i, + rst_ni, + tl_i, + tl_o, + re_o, + we_o, + addr_o, + wdata_o, + be_o, + rdata_i, + error_i +); + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + localparam signed [31:0] top_pkg_TL_DIW = 1; + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + localparam signed [31:0] top_pkg_TL_DUW = 16; + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + parameter signed [31:0] RegAw = 8; + parameter signed [31:0] RegDw = 32; + localparam signed [31:0] RegBw = RegDw / 8; + input clk_i; + input rst_ni; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire re_o; + output wire we_o; + output wire [RegAw - 1:0] addr_o; + output wire [RegDw - 1:0] wdata_o; + output wire [RegBw - 1:0] be_o; + input [RegDw - 1:0] rdata_i; + input error_i; + localparam signed [31:0] IW = top_pkg_TL_AIW; + localparam signed [31:0] SZW = top_pkg_TL_SZW; + reg outstanding; + wire a_ack; + wire d_ack; + reg [RegDw - 1:0] rdata; + reg error; + wire err_internal; + reg addr_align_err; + wire malformed_meta_err; + wire tl_err; + reg [IW - 1:0] reqid; + reg [SZW - 1:0] reqsz; + reg [2:0] rspop; + wire rd_req; + wire wr_req; + assign a_ack = tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & tl_o[0]; + assign d_ack = tl_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))] & tl_i[0]; + assign wr_req = a_ack & ((tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutFullData) | (tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutPartialData)); + assign rd_req = a_ack & (tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == Get); + assign we_o = wr_req & ~err_internal; + assign re_o = rd_req & ~err_internal; + assign addr_o = {tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - ((top_pkg_TL_AW - 1) - (RegAw - 1)):(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_AW - 3)], 2'b00}; + assign wdata_o = tl_i[top_pkg_TL_DW + 16-:top_pkg_TL_DW]; + assign be_o = tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + outstanding <= 1'b0; + else if (a_ack) + outstanding <= 1'b1; + else if (d_ack) + outstanding <= 1'b0; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + reqid <= {IW {1'sb0}}; + reqsz <= {SZW {1'sb0}}; + rspop <= AccessAck; + end + else if (a_ack) begin + reqid <= tl_i[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)]; + reqsz <= tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]; + rspop <= (rd_req ? AccessAckData : AccessAck); + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + rdata <= {RegDw {1'sb0}}; + error <= 1'b0; + end + else if (a_ack) begin + rdata <= (err_internal ? {RegDw {1'sb1}} : rdata_i); + error <= error_i | err_internal; + end + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + assign tl_o = {sv2v_cast_1(outstanding), sv2v_cast_3(rspop), 3'b000, sv2v_cast_F00AF(reqsz), sv2v_cast_F1F18(reqid), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(rdata), sv2v_cast_92577(1'sb0), sv2v_cast_1(error), sv2v_cast_1(~outstanding)}; + assign err_internal = (addr_align_err | malformed_meta_err) | tl_err; + assign malformed_meta_err = tl_i[9] == 1'b1; + always @(*) + if (wr_req) + addr_align_err = |tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_AW - 2):(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_AW - 1)]; + else + addr_align_err = 1'b0; + tlul_err u_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_i), + .err_o(tl_err) + ); +endmodule +module tlul_adapter_sram ( + clk_i, + rst_ni, + tl_i, + tl_o, + req_o, + gnt_i, + we_o, + addr_o, + wdata_o, + wmask_o, + rdata_i, + rvalid_i, + rerror_i +); + parameter signed [31:0] SramAw = 12; + parameter signed [31:0] SramDw = 32; + parameter signed [31:0] Outstanding = 1; + parameter [0:0] ByteAccess = 1; + parameter [0:0] ErrOnWrite = 0; + parameter [0:0] ErrOnRead = 0; + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire req_o; + input gnt_i; + output wire we_o; + output wire [SramAw - 1:0] addr_o; + output wire [SramDw - 1:0] wdata_o; + output wire [SramDw - 1:0] wmask_o; + input [SramDw - 1:0] rdata_i; + input rvalid_i; + input [1:0] rerror_i; + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + localparam signed [31:0] SramByte = SramDw / 8; + function automatic integer prim_util_pkg_vbits; + input integer value; + prim_util_pkg_vbits = (value == 1 ? 1 : $clog2(value)); + endfunction + localparam signed [31:0] DataBitWidth = prim_util_pkg_vbits(SramByte); + localparam signed [31:0] WidthMult = SramDw / top_pkg_TL_DW; + localparam signed [31:0] WoffsetWidth = (SramByte == top_pkg_TL_DBW ? 1 : DataBitWidth - prim_util_pkg_vbits(top_pkg_TL_DBW)); + localparam signed [31:0] SramReqFifoWidth = top_pkg_TL_DBW + WoffsetWidth; + localparam signed [31:0] ReqFifoWidth = (3 + top_pkg_TL_SZW) + top_pkg_TL_AIW; + localparam signed [31:0] RspFifoWidth = (SramDw >= 0 ? SramDw + 1 : 1 - SramDw); + wire reqfifo_wvalid; + wire reqfifo_wready; + wire reqfifo_rvalid; + wire reqfifo_rready; + wire [((3 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_wdata; + wire [((3 + top_pkg_TL_SZW) + top_pkg_TL_AIW) - 1:0] reqfifo_rdata; + wire sramreqfifo_wvalid; + wire sramreqfifo_wready; + wire sramreqfifo_rready; + wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_wdata; + wire [(top_pkg_TL_DBW + WoffsetWidth) - 1:0] sramreqfifo_rdata; + wire rspfifo_wvalid; + wire rspfifo_wready; + wire rspfifo_rvalid; + wire rspfifo_rready; + wire [SramDw:0] rspfifo_wdata; + wire [SramDw:0] rspfifo_rdata; + wire error_internal; + wire wr_attr_error; + wire wr_vld_error; + wire rd_vld_error; + wire tlul_error; + wire a_ack; + wire d_ack; + wire sram_ack; + assign a_ack = tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & tl_o[0]; + assign d_ack = tl_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))] & tl_i[0]; + assign sram_ack = req_o & gnt_i; + reg d_valid; + reg d_error; + localparam [1:0] OpRead = 1; + always @(*) begin + d_valid = 1'b0; + if (reqfifo_rvalid) begin + if (reqfifo_rdata[1 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))]) + d_valid = 1'b1; + else if (reqfifo_rdata[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))-:((3 + (top_pkg_TL_SZW + 7)) >= (1 + (top_pkg_TL_SZW + 8)) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))) - (1 + (top_pkg_TL_SZW + top_pkg_TL_AIW))) + 1 : ((1 + (top_pkg_TL_SZW + top_pkg_TL_AIW)) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1)))) + 1)] == OpRead) + d_valid = rspfifo_rvalid; + else + d_valid = 1'b1; + end + else + d_valid = 1'b0; + end + always @(*) begin + d_error = 1'b0; + if (reqfifo_rvalid) begin + if (reqfifo_rdata[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))-:((3 + (top_pkg_TL_SZW + 7)) >= (1 + (top_pkg_TL_SZW + 8)) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))) - (1 + (top_pkg_TL_SZW + top_pkg_TL_AIW))) + 1 : ((1 + (top_pkg_TL_SZW + top_pkg_TL_AIW)) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1)))) + 1)] == OpRead) + d_error = rspfifo_rdata[0] | reqfifo_rdata[1 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))]; + else + d_error = reqfifo_rdata[1 + (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))]; + end + else + d_error = 1'b0; + end + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + assign tl_o = {sv2v_cast_1(d_valid), sv2v_cast_3((d_valid && (reqfifo_rdata[3 + (top_pkg_TL_SZW + 7)-:((3 + (top_pkg_TL_SZW + 7)) >= (1 + (top_pkg_TL_SZW + 8)) ? ((3 + (top_pkg_TL_SZW + 7)) - (1 + (top_pkg_TL_SZW + 8))) + 1 : ((1 + (top_pkg_TL_SZW + 8)) - (3 + (top_pkg_TL_SZW + 7))) + 1)] != 1) ? AccessAck : AccessAckData)), 3'b000, sv2v_cast_F00AF((d_valid ? reqfifo_rdata[top_pkg_TL_SZW + (top_pkg_TL_AIW - 1)-:((top_pkg_TL_SZW + 7) >= 8 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW - 1)) - top_pkg_TL_AIW) + 1 : (top_pkg_TL_AIW - (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))) + 1)] : {((top_pkg_TL_SZW + 7) >= 8 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW - 1)) - top_pkg_TL_AIW) + 1 : (top_pkg_TL_AIW - (top_pkg_TL_SZW + (top_pkg_TL_AIW - 1))) + 1) {1'sb0}})), sv2v_cast_F1F18((d_valid ? reqfifo_rdata[top_pkg_TL_AIW - 1-:top_pkg_TL_AIW] : {top_pkg_TL_AIW {1'sb0}})), sv2v_cast_B5AB2(1'b0), sv2v_cast_2497D(((d_valid && rspfifo_rvalid) && (reqfifo_rdata[3 + (top_pkg_TL_SZW + 7)-:((3 + (top_pkg_TL_SZW + 7)) >= (1 + (top_pkg_TL_SZW + 8)) ? ((3 + (top_pkg_TL_SZW + 7)) - (1 + (top_pkg_TL_SZW + 8))) + 1 : ((1 + (top_pkg_TL_SZW + 8)) - (3 + (top_pkg_TL_SZW + 7))) + 1)] == 1) ? rspfifo_rdata[SramDw-:(SramDw >= 1 ? SramDw : 2 - SramDw)] : {(SramDw >= 1 ? SramDw : 2 - SramDw) {1'sb0}})), sv2v_cast_92577(1'sb0), sv2v_cast_1(d_valid && d_error), sv2v_cast_1(((gnt_i | error_internal) & reqfifo_wready) & sramreqfifo_wready)}; + assign req_o = (tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & reqfifo_wready) & ~error_internal; + assign we_o = tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & sv2v_cast_1(|{tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutFullData, tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutPartialData}); + assign addr_o = (tl_i[7 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))] ? tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - ((top_pkg_TL_AW - 1) - DataBitWidth)+:SramAw] : {SramAw {1'sb0}}); + wire [WoffsetWidth - 1:0] woffset; + generate + if (top_pkg_TL_DW != SramDw) begin : gen_wordwidthadapt + assign woffset = tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - ((top_pkg_TL_AW - 1) - (DataBitWidth - 1)):(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - ((top_pkg_TL_AW - 1) - prim_util_pkg_vbits(top_pkg_TL_DBW))]; + end + else begin : gen_no_wordwidthadapt + assign woffset = {WoffsetWidth {1'sb0}}; + end + endgenerate + reg [(WidthMult * top_pkg_TL_DW) - 1:0] wmask_int; + reg [(WidthMult * top_pkg_TL_DW) - 1:0] wdata_int; + always @(*) begin + wmask_int = {WidthMult * top_pkg_TL_DW {1'sb0}}; + wdata_int = {WidthMult * top_pkg_TL_DW {1'sb0}}; + if (tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))]) begin : sv2v_autoblock_82 + reg signed [31:0] i; + for (i = 0; i < (top_pkg_TL_DW / 8); i = i + 1) + begin + wmask_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = {8 {tl_i[(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - ((top_pkg_TL_DBW - 1) - i)]}}; + wdata_int[(woffset * top_pkg_TL_DW) + (8 * i)+:8] = (tl_i[(top_pkg_TL_DBW + 48) - ((top_pkg_TL_DBW - 1) - i)] && we_o ? tl_i[(top_pkg_TL_DW + 16) - ((top_pkg_TL_DW - 1) - (8 * i))+:8] : {8 {1'sb0}}); + end + end + end + assign wmask_o = wmask_int; + assign wdata_o = wdata_int; + assign wr_attr_error = ((tl_i[6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) - (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))))) + 1 : ((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) - (6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))))) + 1)] == 3'h0) || (tl_i[6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) - (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))))) + 1 : ((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) - (6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))))) + 1)] == 3'h1) ? (ByteAccess == 0 ? (tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] != {top_pkg_TL_DBW {1'sb1}}) || (tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)] != 2'h2) : 1'b0) : 1'b0); + generate + if (ErrOnWrite == 1) begin : gen_no_writes + assign wr_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] != Get; + end + else begin : gen_writes_allowed + assign wr_vld_error = 1'b0; + end + endgenerate + generate + if (ErrOnRead == 1) begin : gen_no_reads + assign rd_vld_error = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == Get; + end + else begin : gen_reads_allowed + assign rd_vld_error = 1'b0; + end + endgenerate + tlul_err u_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_i), + .err_o(tlul_error) + ); + assign error_internal = ((wr_attr_error | wr_vld_error) | rd_vld_error) | tlul_error; + assign reqfifo_wvalid = a_ack; + function automatic [1:0] sv2v_cast_2; + input reg [1:0] inp; + sv2v_cast_2 = inp; + endfunction + localparam [1:0] OpWrite = 0; + assign reqfifo_wdata = {sv2v_cast_2((tl_i[6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) - (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))))) + 1 : ((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) - (6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))))) + 1)] != 3'h4 ? OpWrite : OpRead)), sv2v_cast_1(error_internal), sv2v_cast_F00AF(tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]), sv2v_cast_F1F18(tl_i[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)])}; + assign reqfifo_rready = d_ack; + function automatic [WoffsetWidth - 1:0] sv2v_cast_4AB74; + input reg [WoffsetWidth - 1:0] inp; + sv2v_cast_4AB74 = inp; + endfunction + assign sramreqfifo_wdata = {sv2v_cast_37199(tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)]), sv2v_cast_4AB74(woffset)}; + assign sramreqfifo_wvalid = sram_ack & ~we_o; + assign sramreqfifo_rready = rspfifo_wvalid; + assign rspfifo_wvalid = rvalid_i & reqfifo_rvalid; + wire [(WidthMult * top_pkg_TL_DW) - 1:0] rdata; + reg [(WidthMult * top_pkg_TL_DW) - 1:0] rmask; + wire [top_pkg_TL_DW - 1:0] rdata_tlword; + always @(*) begin + rmask = {WidthMult * top_pkg_TL_DW {1'sb0}}; + begin : sv2v_autoblock_83 + reg signed [31:0] i; + for (i = 0; i < (top_pkg_TL_DW / 8); i = i + 1) + rmask[(sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * top_pkg_TL_DW) + (8 * i)+:8] = {8 {sramreqfifo_rdata[(top_pkg_TL_DBW + (WoffsetWidth - 1)) - ((top_pkg_TL_DBW - 1) - i)]}}; + end + end + assign rdata = rdata_i & rmask; + assign rdata_tlword = rdata[sramreqfifo_rdata[WoffsetWidth - 1-:WoffsetWidth] * top_pkg_TL_DW+:top_pkg_TL_DW]; + function automatic [SramDw - 1:0] sv2v_cast_D11AA; + input reg [SramDw - 1:0] inp; + sv2v_cast_D11AA = inp; + endfunction + assign rspfifo_wdata = {sv2v_cast_D11AA(rdata_tlword), sv2v_cast_1(rerror_i[1])}; + assign rspfifo_rready = ((reqfifo_rdata[3 + (top_pkg_TL_SZW + 7)-:((3 + (top_pkg_TL_SZW + 7)) >= (1 + (top_pkg_TL_SZW + 8)) ? ((3 + (top_pkg_TL_SZW + 7)) - (1 + (top_pkg_TL_SZW + 8))) + 1 : ((1 + (top_pkg_TL_SZW + 8)) - (3 + (top_pkg_TL_SZW + 7))) + 1)] == 1) & ~reqfifo_rdata[1 + (top_pkg_TL_SZW + 7)] ? reqfifo_rready : 1'b0); + wire unused_rerror; + assign unused_rerror = rerror_i[0]; + prim_fifo_sync #( + .Width(ReqFifoWidth), + .Pass(1'b0), + .Depth(Outstanding) + ) u_reqfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(1'b0), + .wvalid_i(reqfifo_wvalid), + .wready_o(reqfifo_wready), + .wdata_i(reqfifo_wdata), + .depth_o(), + .rvalid_o(reqfifo_rvalid), + .rready_i(reqfifo_rready), + .rdata_o(reqfifo_rdata) + ); + prim_fifo_sync #( + .Width(SramReqFifoWidth), + .Pass(1'b0), + .Depth(Outstanding) + ) u_sramreqfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(1'b0), + .wvalid_i(sramreqfifo_wvalid), + .wready_o(sramreqfifo_wready), + .wdata_i(sramreqfifo_wdata), + .depth_o(), + .rvalid_o(), + .rready_i(sramreqfifo_rready), + .rdata_o(sramreqfifo_rdata) + ); + prim_fifo_sync #( + .Width(RspFifoWidth), + .Pass(1'b1), + .Depth(Outstanding) + ) u_rspfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(1'b0), + .wvalid_i(rspfifo_wvalid), + .wready_o(rspfifo_wready), + .wdata_i(rspfifo_wdata), + .depth_o(), + .rvalid_o(rspfifo_rvalid), + .rready_i(rspfifo_rready), + .rdata_o(rspfifo_rdata) + ); +endmodule +module tlul_err ( + clk_i, + rst_ni, + tl_i, + err_o +); + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + localparam signed [31:0] top_pkg_TL_DIW = 1; + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + localparam signed [31:0] top_pkg_TL_DUW = 16; + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + input clk_i; + input rst_ni; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + output wire err_o; + localparam signed [31:0] IW = top_pkg_TL_AIW; + localparam signed [31:0] SZW = top_pkg_TL_SZW; + localparam signed [31:0] DW = top_pkg_TL_DW; + localparam signed [31:0] MW = top_pkg_TL_DBW; + localparam signed [31:0] SubAW = 2; + wire opcode_allowed; + wire a_config_allowed; + wire op_full; + wire op_partial; + wire op_get; + assign op_full = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutFullData; + assign op_partial = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutPartialData; + assign op_get = tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == Get; + assign err_o = ~(opcode_allowed & a_config_allowed); + assign opcode_allowed = ((tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutFullData) | (tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == PutPartialData)) | (tl_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] == Get); + reg addr_sz_chk; + reg mask_chk; + reg fulldata_chk; + wire [MW - 1:0] mask; + assign mask = 1 << tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - ((top_pkg_TL_AW - 1) - (SubAW - 1)):(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_AW - 1)]; + always @(*) begin + addr_sz_chk = 1'b0; + mask_chk = 1'b0; + fulldata_chk = 1'b0; + if (tl_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))]) + case (tl_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]) + 'h0: begin + addr_sz_chk = 1'b1; + mask_chk = ~|(tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] & ~mask); + fulldata_chk = |(tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] & mask); + end + 'h1: begin + addr_sz_chk = ~tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_AW - 1)]; + mask_chk = (tl_i[(32 + (top_pkg_TL_DBW + 48)) - 30] ? ~|(tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] & 4'b0011) : ~|(tl_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] & 4'b1100)); + fulldata_chk = (tl_i[(32 + (top_pkg_TL_DBW + 48)) - 30] ? &tl_i[(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DBW - 4):(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DBW - 3)] : &tl_i[(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DBW - 2):(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DBW - 1)]); + end + 'h2: begin + addr_sz_chk = ~|tl_i[(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - ((top_pkg_TL_AW - 1) - (SubAW - 1)):(top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_AW - 1)]; + mask_chk = 1'b1; + fulldata_chk = &tl_i[(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DBW - 4):(top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DBW - 1)]; + end + default: begin + addr_sz_chk = 1'b0; + mask_chk = 1'b0; + fulldata_chk = 1'b0; + end + endcase + else begin + addr_sz_chk = 1'b0; + mask_chk = 1'b0; + fulldata_chk = 1'b0; + end + end + assign a_config_allowed = (addr_sz_chk & mask_chk) & ((op_get | op_partial) | fulldata_chk); +endmodule +module tlul_err_resp ( + clk_i, + rst_ni, + tl_h_i, + tl_h_o +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_h_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_h_o; + localparam ArbiterImpl = "PPC"; + localparam [31:0] ADDR_SPACE_UART = 32'h40000000; + localparam [31:0] ADDR_SPACE_GPIO = 32'h40010000; + localparam [31:0] ADDR_SPACE_SRAMD = 32'h18000000; + localparam [31:0] ADDR_SPACE_SRAMI = 32'h00080000; + localparam [31:0] ADDR_SPACE_DEBUG_MEM = 32'h1a110000; + localparam [31:0] ADDR_SPACE_RV_PLIC = 32'h40090000; + localparam [31:0] ADDR_SPACE_SPI_DEVICE = 32'h40020000; + localparam [31:0] ADDR_SPACE_RV_TIMER = 32'h40080000; + localparam [31:0] ADDR_MASK_UART = 32'h00000fff; + localparam [31:0] ADDR_MASK_GPIO = 32'h00000fff; + localparam [31:0] ADDR_MASK_SRAMD = 32'h0000ffff; + localparam [31:0] ADDR_MASK_SRAMI = 32'h0000ffff; + localparam [31:0] ADDR_MASK_DEBUG_MEM = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_PLIC = 32'h00000fff; + localparam [31:0] ADDR_MASK_SPI_DEVICE = 32'h00000fff; + localparam [31:0] ADDR_MASK_RV_TIMER = 32'h00000fff; + localparam [2:0] PutFullData = 3'h0; + localparam [2:0] PutPartialData = 3'h1; + localparam [2:0] Get = 3'h4; + localparam [2:0] AccessAck = 3'h0; + localparam [2:0] AccessAckData = 3'h1; + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] TL_H2D_DEFAULT = {1'sb0, 3'b000, 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_4CD75(1'sb0), sv2v_cast_37199(1'sb0), sv2v_cast_2497D(1'sb0), 16'b0000000000000000, 1'b1}; + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + localparam [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] TL_D2H_DEFAULT = {1'sb0, sv2v_cast_3(3'b000), 3'b000, sv2v_cast_F00AF(1'sb0), sv2v_cast_F1F18(1'sb0), sv2v_cast_B5AB2(1'sb0), sv2v_cast_2497D(1'sb0), sv2v_cast_92577(1'sb0), 1'sb0, 1'b1}; + reg [2:0] err_opcode; + reg [top_pkg_TL_AIW - 1:0] err_source; + reg [top_pkg_TL_SZW - 1:0] err_size; + reg err_req_pending; + reg err_rsp_pending; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + err_req_pending <= 1'b0; + err_source <= {top_pkg_TL_AIW {1'b0}}; + err_opcode <= Get; + err_size <= {top_pkg_TL_SZW {1'sb0}}; + end + else if (tl_h_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] && tl_h_o[0]) begin + err_req_pending <= 1'b1; + err_source <= tl_h_i[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)]; + err_opcode <= tl_h_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]; + err_size <= tl_h_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]; + end + else if (!err_rsp_pending) + err_req_pending <= 1'b0; + assign tl_h_o[0] = ~err_rsp_pending & ~(err_req_pending & ~tl_h_i[0]); + assign tl_h_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))] = err_req_pending | err_rsp_pending; + assign tl_h_o[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1] = {((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1)) + 1)) + 1 {1'sb1}}; + assign tl_h_o[top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))-:((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) + 1] = err_source; + assign tl_h_o[top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))-:((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1] = {((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1)) + 1)) + 1 {1'sb0}}; + assign tl_h_o[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)] = {((3 + (top_pkg_TL_SZW + 58)) >= (((3 + (top_pkg_TL_SZW + 58)) - ((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + 58)) - (top_pkg_TL_SZW + 59)) + 1 : ((top_pkg_TL_SZW + 59) - (3 + (top_pkg_TL_SZW + 58))) + 1)) + 1) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - ((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)) + 1)) + 1 : ((((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - ((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)) + 1) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1) {1'sb0}}; + assign tl_h_o[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))-:((top_pkg_TL_SZW + 58) >= 59 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))) - (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) + 1)] = err_size; + assign tl_h_o[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)] = (err_opcode == Get ? AccessAckData : AccessAck); + assign tl_h_o[top_pkg_TL_DUW + 1-:top_pkg_TL_DUW] = {((top_pkg_TL_DUW + 1) - (((top_pkg_TL_DUW + 1) - top_pkg_TL_DUW) + 1)) + 1 {1'sb0}}; + assign tl_h_o[1] = 1'b1; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + err_rsp_pending <= 1'b0; + else if ((err_req_pending || err_rsp_pending) && !tl_h_i[0]) + err_rsp_pending <= 1'b1; + else + err_rsp_pending <= 1'b0; +endmodule +module tlul_fifo_sync ( + clk_i, + rst_ni, + tl_h_i, + tl_h_o, + tl_d_o, + tl_d_i, + spare_req_i, + spare_req_o, + spare_rsp_i, + spare_rsp_o +); + parameter [31:0] ReqPass = 1'b1; + parameter [31:0] RspPass = 1'b1; + parameter [31:0] ReqDepth = 2; + parameter [31:0] RspDepth = 2; + parameter [31:0] SpareReqW = 1; + parameter [31:0] SpareRspW = 1; + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_h_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_h_o; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_d_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_d_i; + input [SpareReqW - 1:0] spare_req_i; + output [SpareReqW - 1:0] spare_req_o; + input [SpareRspW - 1:0] spare_rsp_i; + output [SpareRspW - 1:0] spare_rsp_o; + localparam [31:0] REQFIFO_WIDTH = ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15) + SpareReqW; + prim_fifo_sync #( + .Width(REQFIFO_WIDTH), + .Pass(ReqPass), + .Depth(ReqDepth) + ) reqfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(1'b0), + .wvalid_i(tl_h_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))]), + .wready_o(tl_h_o[0]), + .wdata_i({tl_h_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)], tl_h_i[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)], tl_h_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)], tl_h_i[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)], tl_h_i[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)], tl_h_i[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)], tl_h_i[top_pkg_TL_DW + 16-:top_pkg_TL_DW], tl_h_i[16-:16], spare_req_i}), + .depth_o(), + .rvalid_o(tl_d_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))]), + .rready_i(tl_d_i[0]), + .rdata_o({tl_d_o[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)], tl_d_o[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)], tl_d_o[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)], tl_d_o[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)], tl_d_o[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)], tl_d_o[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)], tl_d_o[top_pkg_TL_DW + 16-:top_pkg_TL_DW], tl_d_o[16-:16], spare_req_o}) + ); + localparam [31:0] RSPFIFO_WIDTH = ((((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)) - 2) + SpareRspW; + localparam [2:0] tlul_pkg_AccessAckData = 3'h1; + prim_fifo_sync #( + .Width(RSPFIFO_WIDTH), + .Pass(RspPass), + .Depth(RspDepth) + ) rspfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(1'b0), + .wvalid_i(tl_d_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))]), + .wready_o(tl_d_o[0]), + .wdata_i({tl_d_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)], tl_d_i[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)], tl_d_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))-:((top_pkg_TL_SZW + 58) >= 59 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))) - (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) + 1)], tl_d_i[top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))-:((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) + 1], tl_d_i[top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))-:((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1], (tl_d_i[6 + (top_pkg_TL_SZW + 58)-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + 58)) - (3 + (top_pkg_TL_SZW + 59))) + 1 : ((3 + (top_pkg_TL_SZW + 59)) - (6 + (top_pkg_TL_SZW + 58))) + 1)] == 3'h1 ? tl_d_i[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1] : {top_pkg_TL_DW {1'b0}}), tl_d_i[top_pkg_TL_DUW + 1-:top_pkg_TL_DUW], tl_d_i[1], spare_rsp_i}), + .depth_o(), + .rvalid_o(tl_h_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))]), + .rready_i(tl_h_i[0]), + .rdata_o({tl_h_o[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)], tl_h_o[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)], tl_h_o[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))-:((top_pkg_TL_SZW + 58) >= 59 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))) - (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) + 1)], tl_h_o[top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))-:((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) + 1], tl_h_o[top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))-:((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1], tl_h_o[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1], tl_h_o[top_pkg_TL_DUW + 1-:top_pkg_TL_DUW], tl_h_o[1], spare_rsp_o}) + ); +endmodule +module tlul_socket_1n ( + clk_i, + rst_ni, + tl_h_i, + tl_h_o, + tl_d_o, + tl_d_i, + dev_select_i +); + parameter [31:0] N = 4; + parameter [0:0] HReqPass = 1'b1; + parameter [0:0] HRspPass = 1'b1; + parameter [N - 1:0] DReqPass = {N {1'b1}}; + parameter [N - 1:0] DRspPass = {N {1'b1}}; + parameter [3:0] HReqDepth = 4'h2; + parameter [3:0] HRspDepth = 4'h2; + parameter [(N * 4) - 1:0] DReqDepth = {N {4'h2}}; + parameter [(N * 4) - 1:0] DRspDepth = {N {4'h2}}; + localparam [31:0] NWD = $clog2(N + 1); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_h_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_h_o; + output wire [(0 >= (N - 1) ? (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((2 - N) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) + (((N - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1) : ((2 - N) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((N - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))) - 1)) : (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (N * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (N * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15))):(0 >= (N - 1) ? (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (N - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((N - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))) : (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] tl_d_o; + input wire [(0 >= (N - 1) ? (((7 + top_pkg_TL_SZW) + 58) >= 0 ? ((2 - N) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) + (((N - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1) : ((2 - N) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + ((((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + ((N - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))) - 1)) : (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (N * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (N * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW))):(0 >= (N - 1) ? (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (N - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + ((N - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))) : (((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] tl_d_i; + input [NWD - 1:0] dev_select_i; + wire [NWD - 1:0] dev_select_t; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_t_o; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_t_i; + tlul_fifo_sync #( + .ReqPass(HReqPass), + .RspPass(HRspPass), + .ReqDepth(HReqDepth), + .RspDepth(HRspDepth), + .SpareReqW(NWD) + ) fifo_h( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_h_i), + .tl_h_o(tl_h_o), + .tl_d_o(tl_t_o), + .tl_d_i(tl_t_i), + .spare_req_i(dev_select_i), + .spare_req_o(dev_select_t), + .spare_rsp_i(1'b0), + .spare_rsp_o() + ); + reg [7:0] num_req_outstanding; + reg [NWD - 1:0] dev_select_outstanding; + wire hold_all_requests; + wire accept_t_req; + wire accept_t_rsp; + assign accept_t_req = tl_t_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & tl_t_i[0]; + assign accept_t_rsp = tl_t_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))] & tl_t_o[0]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + num_req_outstanding <= 8'h00; + dev_select_outstanding <= {NWD {1'sb0}}; + end + else if (accept_t_req) begin + if (!accept_t_rsp) + num_req_outstanding <= num_req_outstanding + 8'h01; + dev_select_outstanding <= dev_select_t; + end + else if (accept_t_rsp) + num_req_outstanding <= num_req_outstanding - 8'h01; + assign hold_all_requests = (num_req_outstanding != 8'h00) & (dev_select_t != dev_select_outstanding); + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_u_o [0:N]; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_u_i [0:N]; + generate + genvar i; + for (i = 0; i < N; i = i + 1) begin : gen_u_o + function automatic signed [NWD - 1:0] sv2v_cast_3B809_signed; + input reg signed [NWD - 1:0] inp; + sv2v_cast_3B809_signed = inp; + endfunction + assign tl_u_o[i][7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] = (tl_t_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & (dev_select_t == sv2v_cast_3B809_signed(i))) & ~hold_all_requests; + assign tl_u_o[i][6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] = tl_t_o[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]; + assign tl_u_o[i][3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] = tl_t_o[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]; + assign tl_u_o[i][top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)] = tl_t_o[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]; + assign tl_u_o[i][top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)] = tl_t_o[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)]; + assign tl_u_o[i][top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] = tl_t_o[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)]; + assign tl_u_o[i][top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] = tl_t_o[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)]; + assign tl_u_o[i][top_pkg_TL_DW + 16-:top_pkg_TL_DW] = tl_t_o[top_pkg_TL_DW + 16-:top_pkg_TL_DW]; + assign tl_u_o[i][16-:16] = tl_t_o[16-:16]; + end + endgenerate + reg [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_t_p; + reg hfifo_reqready; + function automatic signed [NWD - 1:0] sv2v_cast_3B809_signed; + input reg signed [NWD - 1:0] inp; + sv2v_cast_3B809_signed = inp; + endfunction + always @(*) begin + hfifo_reqready = tl_u_i[N][0]; + begin : sv2v_autoblock_84 + reg signed [31:0] idx; + for (idx = 0; idx < N; idx = idx + 1) + if (dev_select_t == sv2v_cast_3B809_signed(idx)) + hfifo_reqready = tl_u_i[idx][0]; + end + if (hold_all_requests) + hfifo_reqready = 1'b0; + end + assign tl_t_i[0] = tl_t_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & hfifo_reqready; + always @(*) begin + tl_t_p = tl_u_i[N]; + begin : sv2v_autoblock_85 + reg signed [31:0] idx; + for (idx = 0; idx < N; idx = idx + 1) + if (dev_select_outstanding == sv2v_cast_3B809_signed(idx)) + tl_t_p = tl_u_i[idx]; + end + end + assign tl_t_i[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))] = tl_t_p[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))]; + assign tl_t_i[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)] = tl_t_p[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)]; + assign tl_t_i[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)] = tl_t_p[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)]; + assign tl_t_i[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))-:((top_pkg_TL_SZW + 58) >= 59 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))) - (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) + 1)] = tl_t_p[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))-:((top_pkg_TL_SZW + 58) >= 59 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))) - (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) + 1)]; + assign tl_t_i[top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))-:((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) + 1] = tl_t_p[top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))-:((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) + 1]; + assign tl_t_i[top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))-:((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1] = tl_t_p[top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))-:((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1]; + assign tl_t_i[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1] = tl_t_p[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1]; + assign tl_t_i[top_pkg_TL_DUW + 1-:top_pkg_TL_DUW] = tl_t_p[top_pkg_TL_DUW + 1-:top_pkg_TL_DUW]; + assign tl_t_i[1] = tl_t_p[1]; + generate + for (i = 0; i < (N + 1); i = i + 1) begin : gen_u_o_d_ready + assign tl_u_o[i][0] = tl_t_o[0]; + end + endgenerate + generate + for (i = 0; i < N; i = i + 1) begin : gen_dfifo + tlul_fifo_sync #( + .ReqPass(DReqPass[i]), + .RspPass(DRspPass[i]), + .ReqDepth(DReqDepth[i * 4+:4]), + .RspDepth(DRspDepth[i * 4+:4]) + ) fifo_d( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_u_o[i]), + .tl_h_o(tl_u_i[i]), + .tl_d_o(tl_d_o[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((0 >= (N - 1) ? i : (N - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]), + .tl_d_i(tl_d_i[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + ((0 >= (N - 1) ? i : (N - 1) - i) * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]), + .spare_req_i(1'b0), + .spare_req_o(), + .spare_rsp_i(1'b0), + .spare_rsp_o() + ); + end + endgenerate + function automatic [NWD - 1:0] sv2v_cast_3B809_unsigned; + input reg [NWD - 1:0] inp; + sv2v_cast_3B809_unsigned = inp; + endfunction + assign tl_u_o[N][7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] = (tl_t_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))] & (dev_select_t == sv2v_cast_3B809_unsigned(N))) & ~hold_all_requests; + assign tl_u_o[N][6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] = tl_t_o[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]; + assign tl_u_o[N][3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)] = tl_t_o[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]; + assign tl_u_o[N][top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)] = tl_t_o[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]; + assign tl_u_o[N][top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)] = tl_t_o[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)]; + assign tl_u_o[N][top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)] = tl_t_o[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)]; + assign tl_u_o[N][top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)] = tl_t_o[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)]; + assign tl_u_o[N][top_pkg_TL_DW + 16-:top_pkg_TL_DW] = tl_t_o[top_pkg_TL_DW + 16-:top_pkg_TL_DW]; + assign tl_u_o[N][16-:16] = tl_t_o[16-:16]; + tlul_err_resp err_resp( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(tl_u_o[N]), + .tl_h_o(tl_u_i[N]) + ); +endmodule +module tlul_socket_m1 ( + clk_i, + rst_ni, + tl_h_i, + tl_h_o, + tl_d_o, + tl_d_i +); + parameter [31:0] M = 4; + parameter [M - 1:0] HReqPass = {M {1'b1}}; + parameter [M - 1:0] HRspPass = {M {1'b1}}; + parameter [(M * 4) - 1:0] HReqDepth = {M {4'h2}}; + parameter [(M * 4) - 1:0] HRspDepth = {M {4'h2}}; + parameter [0:0] DReqPass = 1'b1; + parameter [0:0] DRspPass = 1'b1; + parameter [3:0] DReqDepth = 4'h2; + parameter [3:0] DRspDepth = 4'h2; + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(0 >= (M - 1) ? (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((2 - M) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) + (((M - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1) : ((2 - M) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((M - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))) - 1)) : (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (M * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (M * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15))):(0 >= (M - 1) ? (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (M - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((M - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))) : (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] tl_h_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(0 >= (M - 1) ? (((7 + top_pkg_TL_SZW) + 58) >= 0 ? ((2 - M) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) + (((M - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1) : ((2 - M) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + ((((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + ((M - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))) - 1)) : (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (M * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2)) - 1 : (M * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))) + (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW))):(0 >= (M - 1) ? (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (M - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + ((M - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))) : (((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))] tl_h_o; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_d_o; + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_d_i; + localparam [31:0] IDW = top_pkg_TL_AIW; + localparam [31:0] STIDW = $clog2(M); + wire [(0 >= (M - 1) ? (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((2 - M) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) + (((M - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1) : ((2 - M) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((M - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))) - 1)) : (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (M * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17)) - 1 : (M * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 15))):(0 >= (M - 1) ? (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (M - 1) * ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((M - 1) * (1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))) : (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))] hreq_fifo_o; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] hrsp_fifo_i [0:M - 1]; + wire [M - 1:0] hrequest; + wire [M - 1:0] hgrant; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] dreq_fifo_i; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] drsp_fifo_o; + wire arb_valid; + wire arb_ready; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] arb_data; + generate + genvar i; + for (i = 0; i < M; i = i + 1) begin : gen_host_fifo + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] hreq_fifo_i; + wire [STIDW - 1:0] reqid_sub; + wire [IDW - 1:0] shifted_id; + assign reqid_sub = i; + assign shifted_id = {tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AIW - 1) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AIW - 1))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AIW - 1) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AIW - 1)))) - (IDW - STIDW)) + 1)+:IDW - STIDW], reqid_sub}; + wire [IDW - 1:IDW - STIDW] unused_tl_h_source; + assign unused_tl_h_source = tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - ((top_pkg_TL_AIW - 1) - (IDW - 1)) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - ((top_pkg_TL_AIW - 1) - (IDW - 1)))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - ((top_pkg_TL_AIW - 1) - (IDW - 1)) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - ((top_pkg_TL_AIW - 1) - (IDW - 1))))) + STIDW) - 1)-:STIDW]; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + function automatic [15:0] sv2v_cast_16; + input reg [15:0] inp; + sv2v_cast_16 = inp; + endfunction + assign hreq_fifo_i = {sv2v_cast_1(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))))]), sv2v_cast_3(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))))) + ((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)) - 1)-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]), sv2v_cast_3(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))))) + ((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)) - 1)-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]), sv2v_cast_F00AF(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + ((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)) - 1)-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]), sv2v_cast_F1F18(shifted_id), sv2v_cast_4CD75(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + ((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)) - 1)-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)]), sv2v_cast_37199(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_DBW + (top_pkg_TL_DW + 16) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_DBW + (top_pkg_TL_DW + 16) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + ((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)) - 1)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)]), sv2v_cast_2497D(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_DW + 16 : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_DW + 16)) : ((((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? top_pkg_TL_DW + 16 : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (top_pkg_TL_DW + 16))) + top_pkg_TL_DW) - 1)-:top_pkg_TL_DW]), sv2v_cast_16(tl_h_i[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 16 : ((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) : (((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 16 : ((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW)) + 15)-:16]), sv2v_cast_1(tl_h_i[((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)])}; + tlul_fifo_sync #( + .ReqPass(HReqPass[i]), + .RspPass(HRspPass[i]), + .ReqDepth(HReqDepth[i * 4+:4]), + .RspDepth(HRspDepth[i * 4+:4]), + .SpareReqW(1) + ) u_hostfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(hreq_fifo_i), + .tl_h_o(tl_h_o[(((7 + top_pkg_TL_SZW) + 58) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1) + ((0 >= (M - 1) ? i : (M - 1) - i) * (((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1)))+:(((7 + top_pkg_TL_SZW) + 58) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 2 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1))]), + .tl_d_o(hreq_fifo_o[(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) + ((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)))+:(((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))]), + .tl_d_i(hrsp_fifo_i[i]), + .spare_req_i(1'b0), + .spare_req_o(), + .spare_rsp_i(1'b0), + .spare_rsp_o() + ); + end + endgenerate + tlul_fifo_sync #( + .ReqPass(DReqPass), + .RspPass(DRspPass), + .ReqDepth(DReqDepth), + .RspDepth(DRspDepth), + .SpareReqW(1) + ) u_devicefifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_h_i(dreq_fifo_i), + .tl_h_o(drsp_fifo_o), + .tl_d_o(tl_d_o), + .tl_d_i(tl_d_i), + .spare_req_i(1'b0), + .spare_req_o(), + .spare_rsp_i(1'b0), + .spare_rsp_o() + ); + generate + for (i = 0; i < M; i = i + 1) begin : gen_arbreqgnt + assign hrequest[i] = hreq_fifo_o[((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) : ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16) - (7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))))]; + end + endgenerate + assign arb_ready = drsp_fifo_o[0]; + localparam tlul_pkg_ArbiterImpl = "PPC"; + generate + if (tlul_pkg_ArbiterImpl == "PPC") begin : gen_arb_ppc + prim_arbiter_ppc #( + .N(M), + .DW((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17), + .EnReqStabA(0) + ) u_reqarb( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_i(hrequest), + .data_i(hreq_fifo_o), + .gnt_o(hgrant), + .idx_o(), + .valid_o(arb_valid), + .data_o(arb_data), + .ready_i(arb_ready) + ); + end + else if (tlul_pkg_ArbiterImpl == "BINTREE") begin : gen_tree_arb + prim_arbiter_tree #( + .N(M), + .DW((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17), + .EnReqStabA(0) + ) u_reqarb( + .clk_i(clk_i), + .rst_ni(rst_ni), + .req_i(hrequest), + .data_i(hreq_fifo_o), + .gnt_o(hgrant), + .idx_o(), + .valid_o(arb_valid), + .data_o(arb_data), + .ready_i(arb_ready) + ); + end + endgenerate + wire [M - 1:0] hfifo_rspvalid; + wire [M - 1:0] dfifo_rspready; + wire [IDW - 1:0] hfifo_rspid; + wire dfifo_rspready_merged; + assign dfifo_rspready_merged = |dfifo_rspready; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + function automatic [2:0] sv2v_cast_3; + input reg [2:0] inp; + sv2v_cast_3 = inp; + endfunction + function automatic [top_pkg_TL_SZW - 1:0] sv2v_cast_F00AF; + input reg [top_pkg_TL_SZW - 1:0] inp; + sv2v_cast_F00AF = inp; + endfunction + function automatic [top_pkg_TL_AIW - 1:0] sv2v_cast_F1F18; + input reg [top_pkg_TL_AIW - 1:0] inp; + sv2v_cast_F1F18 = inp; + endfunction + function automatic [top_pkg_TL_AW - 1:0] sv2v_cast_4CD75; + input reg [top_pkg_TL_AW - 1:0] inp; + sv2v_cast_4CD75 = inp; + endfunction + function automatic [top_pkg_TL_DBW - 1:0] sv2v_cast_37199; + input reg [top_pkg_TL_DBW - 1:0] inp; + sv2v_cast_37199 = inp; + endfunction + function automatic [top_pkg_TL_DW - 1:0] sv2v_cast_2497D; + input reg [top_pkg_TL_DW - 1:0] inp; + sv2v_cast_2497D = inp; + endfunction + function automatic [15:0] sv2v_cast_16; + input reg [15:0] inp; + sv2v_cast_16 = inp; + endfunction + assign dreq_fifo_i = {sv2v_cast_1(arb_valid), sv2v_cast_3(arb_data[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((6 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49)))) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]), sv2v_cast_3(arb_data[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))-:((3 + (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48)))) >= (top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 49))) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))))) + 1)]), sv2v_cast_F00AF(arb_data[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))-:((top_pkg_TL_SZW + (40 + (top_pkg_TL_DBW + 48))) >= (40 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))))) + 1)]), sv2v_cast_F1F18(arb_data[top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))-:((40 + (top_pkg_TL_DBW + 48)) >= (32 + (top_pkg_TL_DBW + 49)) ? ((top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17)))) + 1 : ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) - (top_pkg_TL_AIW + (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))))) + 1)]), sv2v_cast_4CD75(arb_data[top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))-:((32 + (top_pkg_TL_DBW + 48)) >= (top_pkg_TL_DBW + 49) ? ((top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 17))) + 1 : ((top_pkg_TL_DBW + (top_pkg_TL_DW + 17)) - (top_pkg_TL_AW + (top_pkg_TL_DBW + (top_pkg_TL_DW + 16)))) + 1)]), sv2v_cast_37199(arb_data[top_pkg_TL_DBW + (top_pkg_TL_DW + 16)-:((top_pkg_TL_DBW + 48) >= 49 ? ((top_pkg_TL_DBW + (top_pkg_TL_DW + 16)) - (top_pkg_TL_DW + 17)) + 1 : ((top_pkg_TL_DW + 17) - (top_pkg_TL_DBW + (top_pkg_TL_DW + 16))) + 1)]), sv2v_cast_2497D(arb_data[top_pkg_TL_DW + 16-:top_pkg_TL_DW]), sv2v_cast_16(arb_data[16-:16]), sv2v_cast_1(dfifo_rspready_merged)}; + assign hfifo_rspid = {{STIDW {1'b0}}, drsp_fifo_o[(top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - ((top_pkg_TL_AIW - 1) - (IDW - 1)):(top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - ((top_pkg_TL_AIW - 1) - STIDW)]}; + generate + for (i = 0; i < M; i = i + 1) begin : gen_idrouting + assign hfifo_rspvalid[i] = drsp_fifo_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))] & (drsp_fifo_o[(top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_AIW - 1)+:STIDW] == i); + assign dfifo_rspready[i] = (hreq_fifo_o[((0 >= (M - 1) ? i : (M - 1) - i) * (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 17 : 1 - ((((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16))) + (((((7 + top_pkg_TL_SZW) + 40) + top_pkg_TL_DBW) + 48) >= 0 ? 0 : (((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16)] & (drsp_fifo_o[(top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))) - (top_pkg_TL_AIW - 1)+:STIDW] == i)) & drsp_fifo_o[7 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))]; + function automatic [top_pkg_TL_DIW - 1:0] sv2v_cast_B5AB2; + input reg [top_pkg_TL_DIW - 1:0] inp; + sv2v_cast_B5AB2 = inp; + endfunction + function automatic [top_pkg_TL_DUW - 1:0] sv2v_cast_92577; + input reg [top_pkg_TL_DUW - 1:0] inp; + sv2v_cast_92577 = inp; + endfunction + assign hrsp_fifo_i[i] = {sv2v_cast_1(hfifo_rspvalid[i]), sv2v_cast_3(drsp_fifo_o[6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((6 + (top_pkg_TL_SZW + 58)) >= (3 + (top_pkg_TL_SZW + 59)) ? ((6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))))) + 1 : ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) - (6 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)]), sv2v_cast_3(drsp_fifo_o[3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))-:((3 + (top_pkg_TL_SZW + 58)) >= (top_pkg_TL_SZW + 59) ? ((3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))))) + 1 : ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) - (3 + (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))))) + 1)]), sv2v_cast_F00AF(drsp_fifo_o[top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))-:((top_pkg_TL_SZW + 58) >= 59 ? ((top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))))) - (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))))) + 1 : ((top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 2)))) - (top_pkg_TL_SZW + (top_pkg_TL_AIW + (top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1)))))) + 1)]), sv2v_cast_F1F18(hfifo_rspid), sv2v_cast_B5AB2(drsp_fifo_o[top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))-:((top_pkg_TL_DIW + (top_pkg_TL_DW + (top_pkg_TL_DUW + 1))) - (top_pkg_TL_DW + (top_pkg_TL_DUW + 2))) + 1]), sv2v_cast_2497D(drsp_fifo_o[top_pkg_TL_DW + (top_pkg_TL_DUW + 1)-:((top_pkg_TL_DW + (top_pkg_TL_DUW + 1)) - (top_pkg_TL_DUW + 2)) + 1]), sv2v_cast_92577(drsp_fifo_o[top_pkg_TL_DUW + 1-:top_pkg_TL_DUW]), sv2v_cast_1(drsp_fifo_o[1]), sv2v_cast_1(hgrant[i])}; + end + endgenerate +endmodule +module uart ( + clk_i, + rst_ni, + tl_i, + tl_o, + cio_rx_i, + cio_tx_o, + cio_tx_en_o, + intr_tx_watermark_o, + intr_rx_watermark_o, + intr_tx_empty_o, + intr_rx_overflow_o, + intr_rx_frame_err_o, + intr_rx_break_err_o, + intr_rx_timeout_o, + intr_rx_parity_err_o +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + input cio_rx_i; + output wire cio_tx_o; + output wire cio_tx_en_o; + output wire intr_tx_watermark_o; + output wire intr_rx_watermark_o; + output wire intr_tx_empty_o; + output wire intr_rx_overflow_o; + output wire intr_rx_frame_err_o; + output wire intr_rx_break_err_o; + output wire intr_rx_timeout_o; + output wire intr_rx_parity_err_o; + localparam [5:0] UART_INTR_STATE_OFFSET = 6'h00; + localparam [5:0] UART_INTR_ENABLE_OFFSET = 6'h04; + localparam [5:0] UART_INTR_TEST_OFFSET = 6'h08; + localparam [5:0] UART_CTRL_OFFSET = 6'h0c; + localparam [5:0] UART_STATUS_OFFSET = 6'h10; + localparam [5:0] UART_RDATA_OFFSET = 6'h14; + localparam [5:0] UART_WDATA_OFFSET = 6'h18; + localparam [5:0] UART_FIFO_CTRL_OFFSET = 6'h1c; + localparam [5:0] UART_FIFO_STATUS_OFFSET = 6'h20; + localparam [5:0] UART_OVRD_OFFSET = 6'h24; + localparam [5:0] UART_VAL_OFFSET = 6'h28; + localparam [5:0] UART_TIMEOUT_CTRL_OFFSET = 6'h2c; + localparam signed [31:0] UART_INTR_STATE = 0; + localparam signed [31:0] UART_INTR_ENABLE = 1; + localparam signed [31:0] UART_INTR_TEST = 2; + localparam signed [31:0] UART_CTRL = 3; + localparam signed [31:0] UART_STATUS = 4; + localparam signed [31:0] UART_RDATA = 5; + localparam signed [31:0] UART_WDATA = 6; + localparam signed [31:0] UART_FIFO_CTRL = 7; + localparam signed [31:0] UART_FIFO_STATUS = 8; + localparam signed [31:0] UART_OVRD = 9; + localparam signed [31:0] UART_VAL = 10; + localparam signed [31:0] UART_TIMEOUT_CTRL = 11; + localparam [47:0] UART_PERMIT = {4'b0001, 4'b0001, 4'b0001, 4'b1111, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0111, 4'b0001, 4'b0011, 4'b1111}; + wire [124:0] reg2hw; + wire [64:0] hw2reg; + uart_reg_top u_reg( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_i), + .tl_o(tl_o), + .reg2hw(reg2hw), + .hw2reg(hw2reg), + .devmode_i(1'b1) + ); + uart_core uart_core( + .clk_i(clk_i), + .rst_ni(rst_ni), + .reg2hw(reg2hw), + .hw2reg(hw2reg), + .rx(cio_rx_i), + .tx(cio_tx_o), + .intr_tx_watermark_o(intr_tx_watermark_o), + .intr_rx_watermark_o(intr_rx_watermark_o), + .intr_tx_empty_o(intr_tx_empty_o), + .intr_rx_overflow_o(intr_rx_overflow_o), + .intr_rx_frame_err_o(intr_rx_frame_err_o), + .intr_rx_break_err_o(intr_rx_break_err_o), + .intr_rx_timeout_o(intr_rx_timeout_o), + .intr_rx_parity_err_o(intr_rx_parity_err_o) + ); + assign cio_tx_en_o = 1'b1; +endmodule +module uart_core ( + clk_i, + rst_ni, + reg2hw, + hw2reg, + rx, + tx, + intr_tx_watermark_o, + intr_rx_watermark_o, + intr_tx_empty_o, + intr_rx_overflow_o, + intr_rx_frame_err_o, + intr_rx_break_err_o, + intr_rx_timeout_o, + intr_rx_parity_err_o +); + input clk_i; + input rst_ni; + input wire [124:0] reg2hw; + output wire [64:0] hw2reg; + input rx; + output wire tx; + output wire intr_tx_watermark_o; + output wire intr_rx_watermark_o; + output wire intr_tx_empty_o; + output wire intr_rx_overflow_o; + output wire intr_rx_frame_err_o; + output wire intr_rx_break_err_o; + output wire intr_rx_timeout_o; + output wire intr_rx_parity_err_o; + localparam [5:0] UART_INTR_STATE_OFFSET = 6'h00; + localparam [5:0] UART_INTR_ENABLE_OFFSET = 6'h04; + localparam [5:0] UART_INTR_TEST_OFFSET = 6'h08; + localparam [5:0] UART_CTRL_OFFSET = 6'h0c; + localparam [5:0] UART_STATUS_OFFSET = 6'h10; + localparam [5:0] UART_RDATA_OFFSET = 6'h14; + localparam [5:0] UART_WDATA_OFFSET = 6'h18; + localparam [5:0] UART_FIFO_CTRL_OFFSET = 6'h1c; + localparam [5:0] UART_FIFO_STATUS_OFFSET = 6'h20; + localparam [5:0] UART_OVRD_OFFSET = 6'h24; + localparam [5:0] UART_VAL_OFFSET = 6'h28; + localparam [5:0] UART_TIMEOUT_CTRL_OFFSET = 6'h2c; + localparam signed [31:0] UART_INTR_STATE = 0; + localparam signed [31:0] UART_INTR_ENABLE = 1; + localparam signed [31:0] UART_INTR_TEST = 2; + localparam signed [31:0] UART_CTRL = 3; + localparam signed [31:0] UART_STATUS = 4; + localparam signed [31:0] UART_RDATA = 5; + localparam signed [31:0] UART_WDATA = 6; + localparam signed [31:0] UART_FIFO_CTRL = 7; + localparam signed [31:0] UART_FIFO_STATUS = 8; + localparam signed [31:0] UART_OVRD = 9; + localparam signed [31:0] UART_VAL = 10; + localparam signed [31:0] UART_TIMEOUT_CTRL = 11; + localparam [47:0] UART_PERMIT = {4'b0001, 4'b0001, 4'b0001, 4'b1111, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0111, 4'b0001, 4'b0011, 4'b1111}; + localparam signed [31:0] NcoWidth = 16; + reg [15:0] rx_val_q; + wire [7:0] uart_rdata; + wire tick_baud_x16; + wire rx_tick_baud; + wire [5:0] tx_fifo_depth; + wire [5:0] rx_fifo_depth; + reg [5:0] rx_fifo_depth_prev_q; + wire [23:0] rx_timeout_count_d; + reg [23:0] rx_timeout_count_q; + wire [23:0] uart_rxto_val; + wire rx_fifo_depth_changed; + wire uart_rxto_en; + wire tx_enable; + wire rx_enable; + wire sys_loopback; + wire line_loopback; + wire rxnf_enable; + wire uart_fifo_rxrst; + wire uart_fifo_txrst; + wire [2:0] uart_fifo_rxilvl; + wire [1:0] uart_fifo_txilvl; + wire ovrd_tx_en; + wire ovrd_tx_val; + wire [7:0] tx_fifo_data; + wire tx_fifo_rready; + wire tx_fifo_rvalid; + wire tx_fifo_wready; + wire tx_uart_idle; + wire tx_out; + reg tx_out_q; + wire [7:0] rx_fifo_data; + wire rx_valid; + wire rx_fifo_wvalid; + wire rx_fifo_rvalid; + wire rx_fifo_wready; + wire rx_uart_idle; + wire rx_sync; + wire rx_in; + reg break_err; + wire [4:0] allzero_cnt_d; + reg [4:0] allzero_cnt_q; + wire allzero_err; + wire not_allzero_char; + wire event_tx_watermark; + wire event_rx_watermark; + wire event_tx_empty; + wire event_rx_overflow; + wire event_rx_frame_err; + wire event_rx_break_err; + wire event_rx_timeout; + wire event_rx_parity_err; + reg tx_watermark_d; + reg tx_watermark_prev_q; + reg rx_watermark_d; + reg rx_watermark_prev_q; + reg tx_uart_idle_q; + assign tx_enable = reg2hw[92]; + assign rx_enable = reg2hw[91]; + assign rxnf_enable = reg2hw[90]; + assign sys_loopback = reg2hw[89]; + assign line_loopback = reg2hw[88]; + assign uart_fifo_rxrst = reg2hw[37] & reg2hw[36]; + assign uart_fifo_txrst = reg2hw[35] & reg2hw[34]; + assign uart_fifo_rxilvl = reg2hw[33-:3]; + assign uart_fifo_txilvl = reg2hw[29-:2]; + assign ovrd_tx_en = reg2hw[26]; + assign ovrd_tx_val = reg2hw[25]; + reg break_st_q; + assign not_allzero_char = rx_valid & (~event_rx_frame_err | (rx_fifo_data != 8'h00)); + assign allzero_err = event_rx_frame_err & (rx_fifo_data == 8'h00); + localparam [0:0] BRK_WAIT = 1; + assign allzero_cnt_d = ((break_st_q == BRK_WAIT) || not_allzero_char ? 5'h00 : (allzero_err ? allzero_cnt_q + 5'd1 : allzero_cnt_q)); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + allzero_cnt_q <= {5 {1'sb0}}; + else if (rx_enable) + allzero_cnt_q <= allzero_cnt_d; + always @(*) + case (reg2hw[85-:2]) + 2'h0: break_err = allzero_cnt_d >= 5'd2; + 2'h1: break_err = allzero_cnt_d >= 5'd4; + 2'h2: break_err = allzero_cnt_d >= 5'd8; + default: break_err = allzero_cnt_d >= 5'd16; + endcase + localparam [0:0] BRK_CHK = 0; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + break_st_q <= BRK_CHK; + else + case (break_st_q) + BRK_CHK: + if (event_rx_break_err) + break_st_q <= BRK_WAIT; + BRK_WAIT: + if (rx_in) + break_st_q <= BRK_CHK; + default: break_st_q <= BRK_CHK; + endcase + assign hw2reg[15-:16] = rx_val_q; + assign hw2reg[42-:8] = uart_rdata; + assign hw2reg[43] = ~rx_fifo_rvalid; + assign hw2reg[44] = rx_uart_idle; + assign hw2reg[45] = tx_uart_idle & ~tx_fifo_rvalid; + assign hw2reg[46] = ~tx_fifo_rvalid; + assign hw2reg[47] = ~rx_fifo_wready; + assign hw2reg[48] = ~tx_fifo_wready; + assign hw2reg[27-:6] = tx_fifo_depth; + assign hw2reg[21-:6] = rx_fifo_depth; + assign hw2reg[31] = 1'b0; + assign hw2reg[34-:3] = 3'h0; + assign hw2reg[28] = 1'b0; + assign hw2reg[30-:2] = 2'h0; + reg [NcoWidth:0] nco_sum_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + nco_sum_q <= 17'h00000; + else if (tx_enable || rx_enable) + nco_sum_q <= {1'b0, nco_sum_q[NcoWidth - 1:0]} + {1'b0, reg2hw[NcoWidth + 67:68]}; + assign tick_baud_x16 = nco_sum_q[16]; + assign tx_fifo_rready = (tx_uart_idle & tx_fifo_rvalid) & tx_enable; + prim_fifo_sync #( + .Width(8), + .Pass(1'b0), + .Depth(32) + ) u_uart_txfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(uart_fifo_txrst), + .wvalid_i(reg2hw[38]), + .wready_o(tx_fifo_wready), + .wdata_i(reg2hw[46-:8]), + .depth_o(tx_fifo_depth), + .rvalid_o(tx_fifo_rvalid), + .rready_i(tx_fifo_rready), + .rdata_o(tx_fifo_data) + ); + uart_tx uart_tx( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tx_enable(tx_enable), + .tick_baud_x16(tick_baud_x16), + .parity_enable(reg2hw[87]), + .wr(tx_fifo_rready), + .wr_parity(^tx_fifo_data ^ reg2hw[86]), + .wr_data(tx_fifo_data), + .idle(tx_uart_idle), + .tx(tx_out) + ); + assign tx = (line_loopback ? rx : tx_out_q); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + tx_out_q <= 1'b1; + else if (ovrd_tx_en) + tx_out_q <= ovrd_tx_val; + else if (sys_loopback) + tx_out_q <= 1'b1; + else + tx_out_q <= tx_out; + prim_generic_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) sync_rx( + .clk_i(clk_i), + .rst_ni(rst_ni), + .d_i(rx), + .q_o(rx_sync) + ); + reg rx_sync_q1; + reg rx_sync_q2; + wire rx_in_mx; + wire rx_in_maj; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + rx_sync_q1 <= 1'b1; + rx_sync_q2 <= 1'b1; + end + else begin + rx_sync_q1 <= rx_sync; + rx_sync_q2 <= rx_sync_q1; + end + assign rx_in_maj = ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2)) | (rx_sync_q1 & rx_sync_q2); + assign rx_in_mx = (rxnf_enable ? rx_in_maj : rx_sync); + assign rx_in = (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx)); + uart_rx uart_rx( + .clk_i(clk_i), + .rst_ni(rst_ni), + .rx_enable(rx_enable), + .tick_baud_x16(tick_baud_x16), + .parity_enable(reg2hw[87]), + .parity_odd(reg2hw[86]), + .tick_baud(rx_tick_baud), + .rx_valid(rx_valid), + .rx_data(rx_fifo_data), + .idle(rx_uart_idle), + .frame_err(event_rx_frame_err), + .rx(rx_in), + .rx_parity_err(event_rx_parity_err) + ); + assign rx_fifo_wvalid = (rx_valid & ~event_rx_frame_err) & ~event_rx_parity_err; + prim_fifo_sync #( + .Width(8), + .Pass(1'b0), + .Depth(32) + ) u_uart_rxfifo( + .clk_i(clk_i), + .rst_ni(rst_ni), + .clr_i(uart_fifo_rxrst), + .wvalid_i(rx_fifo_wvalid), + .wready_o(rx_fifo_wready), + .wdata_i(rx_fifo_data), + .depth_o(rx_fifo_depth), + .rvalid_o(rx_fifo_rvalid), + .rready_i(reg2hw[47]), + .rdata_o(uart_rdata) + ); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + rx_val_q <= 16'h0000; + else if (tick_baud_x16) + rx_val_q <= {rx_val_q[14:0], rx_in}; + always @(*) + case (uart_fifo_txilvl) + 2'h0: tx_watermark_d = tx_fifo_depth < 6'd2; + 2'h1: tx_watermark_d = tx_fifo_depth < 6'd4; + 2'h2: tx_watermark_d = tx_fifo_depth < 6'd8; + default: tx_watermark_d = tx_fifo_depth < 6'd16; + endcase + assign event_tx_watermark = tx_watermark_d & ~tx_watermark_prev_q; + assign event_tx_empty = (~tx_fifo_rvalid & ~tx_uart_idle_q) & tx_uart_idle; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + tx_watermark_prev_q <= 1'b1; + rx_watermark_prev_q <= 1'b0; + tx_uart_idle_q <= 1'b1; + end + else begin + tx_watermark_prev_q <= tx_watermark_d; + rx_watermark_prev_q <= rx_watermark_d; + tx_uart_idle_q <= tx_uart_idle; + end + always @(*) + case (uart_fifo_rxilvl) + 3'h0: rx_watermark_d = rx_fifo_depth >= 6'd1; + 3'h1: rx_watermark_d = rx_fifo_depth >= 6'd4; + 3'h2: rx_watermark_d = rx_fifo_depth >= 6'd8; + 3'h3: rx_watermark_d = rx_fifo_depth >= 6'd16; + 3'h4: rx_watermark_d = rx_fifo_depth >= 6'd30; + default: rx_watermark_d = 1'b0; + endcase + assign event_rx_watermark = rx_watermark_d & ~rx_watermark_prev_q; + assign uart_rxto_en = reg2hw[-0]; + assign uart_rxto_val = reg2hw[24-:24]; + assign rx_fifo_depth_changed = rx_fifo_depth != rx_fifo_depth_prev_q; + assign rx_timeout_count_d = (uart_rxto_en == 1'b0 ? 24'd0 : (event_rx_timeout ? 24'd0 : (rx_fifo_depth_changed ? 24'd0 : (rx_fifo_depth == 5'd0 ? 24'd0 : (rx_tick_baud ? rx_timeout_count_q + 24'd1 : rx_timeout_count_q))))); + assign event_rx_timeout = (rx_timeout_count_q == uart_rxto_val) & uart_rxto_en; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + rx_timeout_count_q <= 24'd0; + rx_fifo_depth_prev_q <= 6'd0; + end + else begin + rx_timeout_count_q <= rx_timeout_count_d; + rx_fifo_depth_prev_q <= rx_fifo_depth; + end + assign event_rx_overflow = rx_fifo_wvalid & ~rx_fifo_wready; + assign event_rx_break_err = break_err & (break_st_q == BRK_CHK); + prim_intr_hw #(.Width(1)) intr_hw_tx_watermark( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_tx_watermark), + .reg2hw_intr_enable_q_i(reg2hw[116]), + .reg2hw_intr_test_q_i(reg2hw[108]), + .reg2hw_intr_test_qe_i(reg2hw[107]), + .reg2hw_intr_state_q_i(reg2hw[124]), + .hw2reg_intr_state_de_o(hw2reg[63]), + .hw2reg_intr_state_d_o(hw2reg[64]), + .intr_o(intr_tx_watermark_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_rx_watermark( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_rx_watermark), + .reg2hw_intr_enable_q_i(reg2hw[115]), + .reg2hw_intr_test_q_i(reg2hw[106]), + .reg2hw_intr_test_qe_i(reg2hw[105]), + .reg2hw_intr_state_q_i(reg2hw[123]), + .hw2reg_intr_state_de_o(hw2reg[61]), + .hw2reg_intr_state_d_o(hw2reg[62]), + .intr_o(intr_rx_watermark_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_tx_empty( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_tx_empty), + .reg2hw_intr_enable_q_i(reg2hw[114]), + .reg2hw_intr_test_q_i(reg2hw[104]), + .reg2hw_intr_test_qe_i(reg2hw[103]), + .reg2hw_intr_state_q_i(reg2hw[122]), + .hw2reg_intr_state_de_o(hw2reg[59]), + .hw2reg_intr_state_d_o(hw2reg[60]), + .intr_o(intr_tx_empty_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_rx_overflow( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_rx_overflow), + .reg2hw_intr_enable_q_i(reg2hw[113]), + .reg2hw_intr_test_q_i(reg2hw[102]), + .reg2hw_intr_test_qe_i(reg2hw[101]), + .reg2hw_intr_state_q_i(reg2hw[121]), + .hw2reg_intr_state_de_o(hw2reg[57]), + .hw2reg_intr_state_d_o(hw2reg[58]), + .intr_o(intr_rx_overflow_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_rx_frame_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_rx_frame_err), + .reg2hw_intr_enable_q_i(reg2hw[112]), + .reg2hw_intr_test_q_i(reg2hw[100]), + .reg2hw_intr_test_qe_i(reg2hw[99]), + .reg2hw_intr_state_q_i(reg2hw[120]), + .hw2reg_intr_state_de_o(hw2reg[55]), + .hw2reg_intr_state_d_o(hw2reg[56]), + .intr_o(intr_rx_frame_err_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_rx_break_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_rx_break_err), + .reg2hw_intr_enable_q_i(reg2hw[111]), + .reg2hw_intr_test_q_i(reg2hw[98]), + .reg2hw_intr_test_qe_i(reg2hw[97]), + .reg2hw_intr_state_q_i(reg2hw[119]), + .hw2reg_intr_state_de_o(hw2reg[53]), + .hw2reg_intr_state_d_o(hw2reg[54]), + .intr_o(intr_rx_break_err_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_rx_timeout( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_rx_timeout), + .reg2hw_intr_enable_q_i(reg2hw[110]), + .reg2hw_intr_test_q_i(reg2hw[96]), + .reg2hw_intr_test_qe_i(reg2hw[95]), + .reg2hw_intr_state_q_i(reg2hw[118]), + .hw2reg_intr_state_de_o(hw2reg[51]), + .hw2reg_intr_state_d_o(hw2reg[52]), + .intr_o(intr_rx_timeout_o) + ); + prim_intr_hw #(.Width(1)) intr_hw_rx_parity_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .event_intr_i(event_rx_parity_err), + .reg2hw_intr_enable_q_i(reg2hw[109]), + .reg2hw_intr_test_q_i(reg2hw[94]), + .reg2hw_intr_test_qe_i(reg2hw[93]), + .reg2hw_intr_state_q_i(reg2hw[117]), + .hw2reg_intr_state_de_o(hw2reg[49]), + .hw2reg_intr_state_d_o(hw2reg[50]), + .intr_o(intr_rx_parity_err_o) + ); +endmodule +module uart_reg_top ( + clk_i, + rst_ni, + tl_i, + tl_o, + reg2hw, + hw2reg, + devmode_i +); + input clk_i; + input rst_ni; + localparam signed [31:0] top_pkg_TL_AIW = 8; + localparam signed [31:0] top_pkg_TL_AW = 32; + localparam signed [31:0] top_pkg_TL_DW = 32; + localparam signed [31:0] top_pkg_TL_DBW = top_pkg_TL_DW >> 3; + localparam signed [31:0] top_pkg_TL_SZW = $clog2($clog2(top_pkg_TL_DBW) + 1); + input wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_i; + localparam signed [31:0] top_pkg_TL_DIW = 1; + localparam signed [31:0] top_pkg_TL_DUW = 16; + output wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_o; + output wire [124:0] reg2hw; + input wire [64:0] hw2reg; + input devmode_i; + localparam [5:0] UART_INTR_STATE_OFFSET = 6'h00; + localparam [5:0] UART_INTR_ENABLE_OFFSET = 6'h04; + localparam [5:0] UART_INTR_TEST_OFFSET = 6'h08; + localparam [5:0] UART_CTRL_OFFSET = 6'h0c; + localparam [5:0] UART_STATUS_OFFSET = 6'h10; + localparam [5:0] UART_RDATA_OFFSET = 6'h14; + localparam [5:0] UART_WDATA_OFFSET = 6'h18; + localparam [5:0] UART_FIFO_CTRL_OFFSET = 6'h1c; + localparam [5:0] UART_FIFO_STATUS_OFFSET = 6'h20; + localparam [5:0] UART_OVRD_OFFSET = 6'h24; + localparam [5:0] UART_VAL_OFFSET = 6'h28; + localparam [5:0] UART_TIMEOUT_CTRL_OFFSET = 6'h2c; + localparam signed [31:0] UART_INTR_STATE = 0; + localparam signed [31:0] UART_INTR_ENABLE = 1; + localparam signed [31:0] UART_INTR_TEST = 2; + localparam signed [31:0] UART_CTRL = 3; + localparam signed [31:0] UART_STATUS = 4; + localparam signed [31:0] UART_RDATA = 5; + localparam signed [31:0] UART_WDATA = 6; + localparam signed [31:0] UART_FIFO_CTRL = 7; + localparam signed [31:0] UART_FIFO_STATUS = 8; + localparam signed [31:0] UART_OVRD = 9; + localparam signed [31:0] UART_VAL = 10; + localparam signed [31:0] UART_TIMEOUT_CTRL = 11; + localparam [47:0] UART_PERMIT = {4'b0001, 4'b0001, 4'b0001, 4'b1111, 4'b0001, 4'b0001, 4'b0001, 4'b0001, 4'b0111, 4'b0001, 4'b0011, 4'b1111}; + localparam signed [31:0] AW = 6; + localparam signed [31:0] DW = 32; + localparam signed [31:0] DBW = DW / 8; + wire reg_we; + wire reg_re; + wire [AW - 1:0] reg_addr; + wire [DW - 1:0] reg_wdata; + wire [DBW - 1:0] reg_be; + wire [DW - 1:0] reg_rdata; + wire reg_error; + wire addrmiss; + reg wr_err; + reg [DW - 1:0] reg_rdata_next; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_AW) + top_pkg_TL_DBW) + top_pkg_TL_DW) + 16:0] tl_reg_h2d; + wire [(((((7 + top_pkg_TL_SZW) + top_pkg_TL_AIW) + top_pkg_TL_DIW) + top_pkg_TL_DW) + top_pkg_TL_DUW) + 1:0] tl_reg_d2h; + assign tl_reg_h2d = tl_i; + assign tl_o = tl_reg_d2h; + tlul_adapter_reg #( + .RegAw(AW), + .RegDw(DW) + ) u_reg_if( + .clk_i(clk_i), + .rst_ni(rst_ni), + .tl_i(tl_reg_h2d), + .tl_o(tl_reg_d2h), + .we_o(reg_we), + .re_o(reg_re), + .addr_o(reg_addr), + .wdata_o(reg_wdata), + .be_o(reg_be), + .rdata_i(reg_rdata), + .error_i(reg_error) + ); + assign reg_rdata = reg_rdata_next; + assign reg_error = (devmode_i & addrmiss) | wr_err; + wire intr_state_tx_watermark_qs; + wire intr_state_tx_watermark_wd; + wire intr_state_tx_watermark_we; + wire intr_state_rx_watermark_qs; + wire intr_state_rx_watermark_wd; + wire intr_state_rx_watermark_we; + wire intr_state_tx_empty_qs; + wire intr_state_tx_empty_wd; + wire intr_state_tx_empty_we; + wire intr_state_rx_overflow_qs; + wire intr_state_rx_overflow_wd; + wire intr_state_rx_overflow_we; + wire intr_state_rx_frame_err_qs; + wire intr_state_rx_frame_err_wd; + wire intr_state_rx_frame_err_we; + wire intr_state_rx_break_err_qs; + wire intr_state_rx_break_err_wd; + wire intr_state_rx_break_err_we; + wire intr_state_rx_timeout_qs; + wire intr_state_rx_timeout_wd; + wire intr_state_rx_timeout_we; + wire intr_state_rx_parity_err_qs; + wire intr_state_rx_parity_err_wd; + wire intr_state_rx_parity_err_we; + wire intr_enable_tx_watermark_qs; + wire intr_enable_tx_watermark_wd; + wire intr_enable_tx_watermark_we; + wire intr_enable_rx_watermark_qs; + wire intr_enable_rx_watermark_wd; + wire intr_enable_rx_watermark_we; + wire intr_enable_tx_empty_qs; + wire intr_enable_tx_empty_wd; + wire intr_enable_tx_empty_we; + wire intr_enable_rx_overflow_qs; + wire intr_enable_rx_overflow_wd; + wire intr_enable_rx_overflow_we; + wire intr_enable_rx_frame_err_qs; + wire intr_enable_rx_frame_err_wd; + wire intr_enable_rx_frame_err_we; + wire intr_enable_rx_break_err_qs; + wire intr_enable_rx_break_err_wd; + wire intr_enable_rx_break_err_we; + wire intr_enable_rx_timeout_qs; + wire intr_enable_rx_timeout_wd; + wire intr_enable_rx_timeout_we; + wire intr_enable_rx_parity_err_qs; + wire intr_enable_rx_parity_err_wd; + wire intr_enable_rx_parity_err_we; + wire intr_test_tx_watermark_wd; + wire intr_test_tx_watermark_we; + wire intr_test_rx_watermark_wd; + wire intr_test_rx_watermark_we; + wire intr_test_tx_empty_wd; + wire intr_test_tx_empty_we; + wire intr_test_rx_overflow_wd; + wire intr_test_rx_overflow_we; + wire intr_test_rx_frame_err_wd; + wire intr_test_rx_frame_err_we; + wire intr_test_rx_break_err_wd; + wire intr_test_rx_break_err_we; + wire intr_test_rx_timeout_wd; + wire intr_test_rx_timeout_we; + wire intr_test_rx_parity_err_wd; + wire intr_test_rx_parity_err_we; + wire ctrl_tx_qs; + wire ctrl_tx_wd; + wire ctrl_tx_we; + wire ctrl_rx_qs; + wire ctrl_rx_wd; + wire ctrl_rx_we; + wire ctrl_nf_qs; + wire ctrl_nf_wd; + wire ctrl_nf_we; + wire ctrl_slpbk_qs; + wire ctrl_slpbk_wd; + wire ctrl_slpbk_we; + wire ctrl_llpbk_qs; + wire ctrl_llpbk_wd; + wire ctrl_llpbk_we; + wire ctrl_parity_en_qs; + wire ctrl_parity_en_wd; + wire ctrl_parity_en_we; + wire ctrl_parity_odd_qs; + wire ctrl_parity_odd_wd; + wire ctrl_parity_odd_we; + wire [1:0] ctrl_rxblvl_qs; + wire [1:0] ctrl_rxblvl_wd; + wire ctrl_rxblvl_we; + wire [15:0] ctrl_nco_qs; + wire [15:0] ctrl_nco_wd; + wire ctrl_nco_we; + wire status_txfull_qs; + wire status_txfull_re; + wire status_rxfull_qs; + wire status_rxfull_re; + wire status_txempty_qs; + wire status_txempty_re; + wire status_txidle_qs; + wire status_txidle_re; + wire status_rxidle_qs; + wire status_rxidle_re; + wire status_rxempty_qs; + wire status_rxempty_re; + wire [7:0] rdata_qs; + wire rdata_re; + wire [7:0] wdata_wd; + wire wdata_we; + wire fifo_ctrl_rxrst_wd; + wire fifo_ctrl_rxrst_we; + wire fifo_ctrl_txrst_wd; + wire fifo_ctrl_txrst_we; + wire [2:0] fifo_ctrl_rxilvl_qs; + wire [2:0] fifo_ctrl_rxilvl_wd; + wire fifo_ctrl_rxilvl_we; + wire [1:0] fifo_ctrl_txilvl_qs; + wire [1:0] fifo_ctrl_txilvl_wd; + wire fifo_ctrl_txilvl_we; + wire [5:0] fifo_status_txlvl_qs; + wire fifo_status_txlvl_re; + wire [5:0] fifo_status_rxlvl_qs; + wire fifo_status_rxlvl_re; + wire ovrd_txen_qs; + wire ovrd_txen_wd; + wire ovrd_txen_we; + wire ovrd_txval_qs; + wire ovrd_txval_wd; + wire ovrd_txval_we; + wire [15:0] val_qs; + wire val_re; + wire [23:0] timeout_ctrl_val_qs; + wire [23:0] timeout_ctrl_val_wd; + wire timeout_ctrl_val_we; + wire timeout_ctrl_en_qs; + wire timeout_ctrl_en_wd; + wire timeout_ctrl_en_we; + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_tx_watermark( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_tx_watermark_we), + .wd(intr_state_tx_watermark_wd), + .de(hw2reg[63]), + .d(hw2reg[64]), + .qe(), + .q(reg2hw[124]), + .qs(intr_state_tx_watermark_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_rx_watermark( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_rx_watermark_we), + .wd(intr_state_rx_watermark_wd), + .de(hw2reg[61]), + .d(hw2reg[62]), + .qe(), + .q(reg2hw[123]), + .qs(intr_state_rx_watermark_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_tx_empty( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_tx_empty_we), + .wd(intr_state_tx_empty_wd), + .de(hw2reg[59]), + .d(hw2reg[60]), + .qe(), + .q(reg2hw[122]), + .qs(intr_state_tx_empty_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_rx_overflow( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_rx_overflow_we), + .wd(intr_state_rx_overflow_wd), + .de(hw2reg[57]), + .d(hw2reg[58]), + .qe(), + .q(reg2hw[121]), + .qs(intr_state_rx_overflow_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_rx_frame_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_rx_frame_err_we), + .wd(intr_state_rx_frame_err_wd), + .de(hw2reg[55]), + .d(hw2reg[56]), + .qe(), + .q(reg2hw[120]), + .qs(intr_state_rx_frame_err_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_rx_break_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_rx_break_err_we), + .wd(intr_state_rx_break_err_wd), + .de(hw2reg[53]), + .d(hw2reg[54]), + .qe(), + .q(reg2hw[119]), + .qs(intr_state_rx_break_err_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_rx_timeout( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_rx_timeout_we), + .wd(intr_state_rx_timeout_wd), + .de(hw2reg[51]), + .d(hw2reg[52]), + .qe(), + .q(reg2hw[118]), + .qs(intr_state_rx_timeout_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(24), + .SWACCESS("W1C"), + .RESVAL(1'h0) + ) u_intr_state_rx_parity_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_state_rx_parity_err_we), + .wd(intr_state_rx_parity_err_wd), + .de(hw2reg[49]), + .d(hw2reg[50]), + .qe(), + .q(reg2hw[117]), + .qs(intr_state_rx_parity_err_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_tx_watermark( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_tx_watermark_we), + .wd(intr_enable_tx_watermark_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[116]), + .qs(intr_enable_tx_watermark_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_rx_watermark( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_rx_watermark_we), + .wd(intr_enable_rx_watermark_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[115]), + .qs(intr_enable_rx_watermark_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_tx_empty( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_tx_empty_we), + .wd(intr_enable_tx_empty_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[114]), + .qs(intr_enable_tx_empty_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_rx_overflow( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_rx_overflow_we), + .wd(intr_enable_rx_overflow_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[113]), + .qs(intr_enable_rx_overflow_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_rx_frame_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_rx_frame_err_we), + .wd(intr_enable_rx_frame_err_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[112]), + .qs(intr_enable_rx_frame_err_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_rx_break_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_rx_break_err_we), + .wd(intr_enable_rx_break_err_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[111]), + .qs(intr_enable_rx_break_err_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_rx_timeout( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_rx_timeout_we), + .wd(intr_enable_rx_timeout_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[110]), + .qs(intr_enable_rx_timeout_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_intr_enable_rx_parity_err( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(intr_enable_rx_parity_err_we), + .wd(intr_enable_rx_parity_err_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[109]), + .qs(intr_enable_rx_parity_err_qs) + ); + prim_subreg_ext #(.DW(1)) u_intr_test_tx_watermark( + .re(1'b0), + .we(intr_test_tx_watermark_we), + .wd(intr_test_tx_watermark_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[107]), + .q(reg2hw[108]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_rx_watermark( + .re(1'b0), + .we(intr_test_rx_watermark_we), + .wd(intr_test_rx_watermark_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[105]), + .q(reg2hw[106]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_tx_empty( + .re(1'b0), + .we(intr_test_tx_empty_we), + .wd(intr_test_tx_empty_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[103]), + .q(reg2hw[104]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_rx_overflow( + .re(1'b0), + .we(intr_test_rx_overflow_we), + .wd(intr_test_rx_overflow_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[101]), + .q(reg2hw[102]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_rx_frame_err( + .re(1'b0), + .we(intr_test_rx_frame_err_we), + .wd(intr_test_rx_frame_err_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[99]), + .q(reg2hw[100]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_rx_break_err( + .re(1'b0), + .we(intr_test_rx_break_err_we), + .wd(intr_test_rx_break_err_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[97]), + .q(reg2hw[98]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_rx_timeout( + .re(1'b0), + .we(intr_test_rx_timeout_we), + .wd(intr_test_rx_timeout_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[95]), + .q(reg2hw[96]), + .qs() + ); + prim_subreg_ext #(.DW(1)) u_intr_test_rx_parity_err( + .re(1'b0), + .we(intr_test_rx_parity_err_we), + .wd(intr_test_rx_parity_err_wd), + .d(1'sb0), + .qre(), + .qe(reg2hw[93]), + .q(reg2hw[94]), + .qs() + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_tx( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_tx_we), + .wd(ctrl_tx_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[92]), + .qs(ctrl_tx_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_rx( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_rx_we), + .wd(ctrl_rx_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[91]), + .qs(ctrl_rx_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_nf( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_nf_we), + .wd(ctrl_nf_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[90]), + .qs(ctrl_nf_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_slpbk( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_slpbk_we), + .wd(ctrl_slpbk_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[89]), + .qs(ctrl_slpbk_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_llpbk( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_llpbk_we), + .wd(ctrl_llpbk_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[88]), + .qs(ctrl_llpbk_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_parity_en( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_parity_en_we), + .wd(ctrl_parity_en_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[87]), + .qs(ctrl_parity_en_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ctrl_parity_odd( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_parity_odd_we), + .wd(ctrl_parity_odd_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[86]), + .qs(ctrl_parity_odd_qs) + ); + prim_subreg #( + .DW(2), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(2'h0) + ) u_ctrl_rxblvl( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_rxblvl_we), + .wd(ctrl_rxblvl_wd), + .de(1'b0), + .d({2 {1'sb0}}), + .qe(), + .q(reg2hw[85-:2]), + .qs(ctrl_rxblvl_qs) + ); + prim_subreg #( + .DW(16), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(16'h0000) + ) u_ctrl_nco( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ctrl_nco_we), + .wd(ctrl_nco_wd), + .de(1'b0), + .d({16 {1'sb0}}), + .qe(), + .q(reg2hw[83-:16]), + .qs(ctrl_nco_qs) + ); + prim_subreg_ext #(.DW(1)) u_status_txfull( + .re(status_txfull_re), + .we(1'b0), + .wd(1'sb0), + .d(hw2reg[48]), + .qre(reg2hw[66]), + .qe(), + .q(reg2hw[67]), + .qs(status_txfull_qs) + ); + prim_subreg_ext #(.DW(1)) u_status_rxfull( + .re(status_rxfull_re), + .we(1'b0), + .wd(1'sb0), + .d(hw2reg[47]), + .qre(reg2hw[64]), + .qe(), + .q(reg2hw[65]), + .qs(status_rxfull_qs) + ); + prim_subreg_ext #(.DW(1)) u_status_txempty( + .re(status_txempty_re), + .we(1'b0), + .wd(1'sb0), + .d(hw2reg[46]), + .qre(reg2hw[62]), + .qe(), + .q(reg2hw[63]), + .qs(status_txempty_qs) + ); + prim_subreg_ext #(.DW(1)) u_status_txidle( + .re(status_txidle_re), + .we(1'b0), + .wd(1'sb0), + .d(hw2reg[45]), + .qre(reg2hw[60]), + .qe(), + .q(reg2hw[61]), + .qs(status_txidle_qs) + ); + prim_subreg_ext #(.DW(1)) u_status_rxidle( + .re(status_rxidle_re), + .we(1'b0), + .wd(1'sb0), + .d(hw2reg[44]), + .qre(reg2hw[58]), + .qe(), + .q(reg2hw[59]), + .qs(status_rxidle_qs) + ); + prim_subreg_ext #(.DW(1)) u_status_rxempty( + .re(status_rxempty_re), + .we(1'b0), + .wd(1'sb0), + .d(hw2reg[43]), + .qre(reg2hw[56]), + .qe(), + .q(reg2hw[57]), + .qs(status_rxempty_qs) + ); + prim_subreg_ext #(.DW(8)) u_rdata( + .re(rdata_re), + .we(1'b0), + .wd({8 {1'sb0}}), + .d(hw2reg[42-:8]), + .qre(reg2hw[47]), + .qe(), + .q(reg2hw[55-:8]), + .qs(rdata_qs) + ); + prim_subreg #( + .DW(8), + ._sv2v_width_SWACCESS(16), + .SWACCESS("WO"), + .RESVAL(8'h00) + ) u_wdata( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(wdata_we), + .wd(wdata_wd), + .de(1'b0), + .d({8 {1'sb0}}), + .qe(reg2hw[38]), + .q(reg2hw[46-:8]), + .qs() + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("WO"), + .RESVAL(1'h0) + ) u_fifo_ctrl_rxrst( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(fifo_ctrl_rxrst_we), + .wd(fifo_ctrl_rxrst_wd), + .de(1'b0), + .d(1'sb0), + .qe(reg2hw[36]), + .q(reg2hw[37]), + .qs() + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("WO"), + .RESVAL(1'h0) + ) u_fifo_ctrl_txrst( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(fifo_ctrl_txrst_we), + .wd(fifo_ctrl_txrst_wd), + .de(1'b0), + .d(1'sb0), + .qe(reg2hw[34]), + .q(reg2hw[35]), + .qs() + ); + prim_subreg #( + .DW(3), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(3'h0) + ) u_fifo_ctrl_rxilvl( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(fifo_ctrl_rxilvl_we), + .wd(fifo_ctrl_rxilvl_wd), + .de(hw2reg[31]), + .d(hw2reg[34-:3]), + .qe(reg2hw[30]), + .q(reg2hw[33-:3]), + .qs(fifo_ctrl_rxilvl_qs) + ); + prim_subreg #( + .DW(2), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(2'h0) + ) u_fifo_ctrl_txilvl( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(fifo_ctrl_txilvl_we), + .wd(fifo_ctrl_txilvl_wd), + .de(hw2reg[28]), + .d(hw2reg[30-:2]), + .qe(reg2hw[27]), + .q(reg2hw[29-:2]), + .qs(fifo_ctrl_txilvl_qs) + ); + prim_subreg_ext #(.DW(6)) u_fifo_status_txlvl( + .re(fifo_status_txlvl_re), + .we(1'b0), + .wd({6 {1'sb0}}), + .d(hw2reg[27-:6]), + .qre(), + .qe(), + .q(), + .qs(fifo_status_txlvl_qs) + ); + prim_subreg_ext #(.DW(6)) u_fifo_status_rxlvl( + .re(fifo_status_rxlvl_re), + .we(1'b0), + .wd({6 {1'sb0}}), + .d(hw2reg[21-:6]), + .qre(), + .qe(), + .q(), + .qs(fifo_status_rxlvl_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ovrd_txen( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ovrd_txen_we), + .wd(ovrd_txen_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[26]), + .qs(ovrd_txen_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_ovrd_txval( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(ovrd_txval_we), + .wd(ovrd_txval_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[25]), + .qs(ovrd_txval_qs) + ); + prim_subreg_ext #(.DW(16)) u_val( + .re(val_re), + .we(1'b0), + .wd({16 {1'sb0}}), + .d(hw2reg[15-:16]), + .qre(), + .qe(), + .q(), + .qs(val_qs) + ); + prim_subreg #( + .DW(24), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(24'h000000) + ) u_timeout_ctrl_val( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(timeout_ctrl_val_we), + .wd(timeout_ctrl_val_wd), + .de(1'b0), + .d({24 {1'sb0}}), + .qe(), + .q(reg2hw[24-:24]), + .qs(timeout_ctrl_val_qs) + ); + prim_subreg #( + .DW(1), + ._sv2v_width_SWACCESS(16), + .SWACCESS("RW"), + .RESVAL(1'h0) + ) u_timeout_ctrl_en( + .clk_i(clk_i), + .rst_ni(rst_ni), + .we(timeout_ctrl_en_we), + .wd(timeout_ctrl_en_wd), + .de(1'b0), + .d(1'sb0), + .qe(), + .q(reg2hw[-0]), + .qs(timeout_ctrl_en_qs) + ); + reg [11:0] addr_hit; + always @(*) begin + addr_hit = {12 {1'sb0}}; + addr_hit[0] = reg_addr == UART_INTR_STATE_OFFSET; + addr_hit[1] = reg_addr == UART_INTR_ENABLE_OFFSET; + addr_hit[2] = reg_addr == UART_INTR_TEST_OFFSET; + addr_hit[3] = reg_addr == UART_CTRL_OFFSET; + addr_hit[4] = reg_addr == UART_STATUS_OFFSET; + addr_hit[5] = reg_addr == UART_RDATA_OFFSET; + addr_hit[6] = reg_addr == UART_WDATA_OFFSET; + addr_hit[7] = reg_addr == UART_FIFO_CTRL_OFFSET; + addr_hit[8] = reg_addr == UART_FIFO_STATUS_OFFSET; + addr_hit[9] = reg_addr == UART_OVRD_OFFSET; + addr_hit[10] = reg_addr == UART_VAL_OFFSET; + addr_hit[11] = reg_addr == UART_TIMEOUT_CTRL_OFFSET; + end + assign addrmiss = (reg_re || reg_we ? ~|addr_hit : 1'b0); + always @(*) begin + wr_err = 1'b0; + if ((addr_hit[0] && reg_we) && (UART_PERMIT[44+:4] != (UART_PERMIT[44+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[1] && reg_we) && (UART_PERMIT[40+:4] != (UART_PERMIT[40+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[2] && reg_we) && (UART_PERMIT[36+:4] != (UART_PERMIT[36+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[3] && reg_we) && (UART_PERMIT[32+:4] != (UART_PERMIT[32+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[4] && reg_we) && (UART_PERMIT[28+:4] != (UART_PERMIT[28+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[5] && reg_we) && (UART_PERMIT[24+:4] != (UART_PERMIT[24+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[6] && reg_we) && (UART_PERMIT[20+:4] != (UART_PERMIT[20+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[7] && reg_we) && (UART_PERMIT[16+:4] != (UART_PERMIT[16+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[8] && reg_we) && (UART_PERMIT[12+:4] != (UART_PERMIT[12+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[9] && reg_we) && (UART_PERMIT[8+:4] != (UART_PERMIT[8+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[10] && reg_we) && (UART_PERMIT[4+:4] != (UART_PERMIT[4+:4] & reg_be))) + wr_err = 1'b1; + if ((addr_hit[11] && reg_we) && (UART_PERMIT[0+:4] != (UART_PERMIT[0+:4] & reg_be))) + wr_err = 1'b1; + end + assign intr_state_tx_watermark_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_tx_watermark_wd = reg_wdata[0]; + assign intr_state_rx_watermark_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_rx_watermark_wd = reg_wdata[1]; + assign intr_state_tx_empty_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_tx_empty_wd = reg_wdata[2]; + assign intr_state_rx_overflow_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_rx_overflow_wd = reg_wdata[3]; + assign intr_state_rx_frame_err_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_rx_frame_err_wd = reg_wdata[4]; + assign intr_state_rx_break_err_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_rx_break_err_wd = reg_wdata[5]; + assign intr_state_rx_timeout_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_rx_timeout_wd = reg_wdata[6]; + assign intr_state_rx_parity_err_we = (addr_hit[0] & reg_we) & ~wr_err; + assign intr_state_rx_parity_err_wd = reg_wdata[7]; + assign intr_enable_tx_watermark_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_tx_watermark_wd = reg_wdata[0]; + assign intr_enable_rx_watermark_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_rx_watermark_wd = reg_wdata[1]; + assign intr_enable_tx_empty_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_tx_empty_wd = reg_wdata[2]; + assign intr_enable_rx_overflow_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_rx_overflow_wd = reg_wdata[3]; + assign intr_enable_rx_frame_err_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_rx_frame_err_wd = reg_wdata[4]; + assign intr_enable_rx_break_err_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_rx_break_err_wd = reg_wdata[5]; + assign intr_enable_rx_timeout_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_rx_timeout_wd = reg_wdata[6]; + assign intr_enable_rx_parity_err_we = (addr_hit[1] & reg_we) & ~wr_err; + assign intr_enable_rx_parity_err_wd = reg_wdata[7]; + assign intr_test_tx_watermark_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_tx_watermark_wd = reg_wdata[0]; + assign intr_test_rx_watermark_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_rx_watermark_wd = reg_wdata[1]; + assign intr_test_tx_empty_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_tx_empty_wd = reg_wdata[2]; + assign intr_test_rx_overflow_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_rx_overflow_wd = reg_wdata[3]; + assign intr_test_rx_frame_err_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_rx_frame_err_wd = reg_wdata[4]; + assign intr_test_rx_break_err_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_rx_break_err_wd = reg_wdata[5]; + assign intr_test_rx_timeout_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_rx_timeout_wd = reg_wdata[6]; + assign intr_test_rx_parity_err_we = (addr_hit[2] & reg_we) & ~wr_err; + assign intr_test_rx_parity_err_wd = reg_wdata[7]; + assign ctrl_tx_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_tx_wd = reg_wdata[0]; + assign ctrl_rx_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_rx_wd = reg_wdata[1]; + assign ctrl_nf_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_nf_wd = reg_wdata[2]; + assign ctrl_slpbk_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_slpbk_wd = reg_wdata[4]; + assign ctrl_llpbk_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_llpbk_wd = reg_wdata[5]; + assign ctrl_parity_en_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_parity_en_wd = reg_wdata[6]; + assign ctrl_parity_odd_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_parity_odd_wd = reg_wdata[7]; + assign ctrl_rxblvl_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_rxblvl_wd = reg_wdata[9:8]; + assign ctrl_nco_we = (addr_hit[3] & reg_we) & ~wr_err; + assign ctrl_nco_wd = reg_wdata[31:16]; + assign status_txfull_re = addr_hit[4] && reg_re; + assign status_rxfull_re = addr_hit[4] && reg_re; + assign status_txempty_re = addr_hit[4] && reg_re; + assign status_txidle_re = addr_hit[4] && reg_re; + assign status_rxidle_re = addr_hit[4] && reg_re; + assign status_rxempty_re = addr_hit[4] && reg_re; + assign rdata_re = addr_hit[5] && reg_re; + assign wdata_we = (addr_hit[6] & reg_we) & ~wr_err; + assign wdata_wd = reg_wdata[7:0]; + assign fifo_ctrl_rxrst_we = (addr_hit[7] & reg_we) & ~wr_err; + assign fifo_ctrl_rxrst_wd = reg_wdata[0]; + assign fifo_ctrl_txrst_we = (addr_hit[7] & reg_we) & ~wr_err; + assign fifo_ctrl_txrst_wd = reg_wdata[1]; + assign fifo_ctrl_rxilvl_we = (addr_hit[7] & reg_we) & ~wr_err; + assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2]; + assign fifo_ctrl_txilvl_we = (addr_hit[7] & reg_we) & ~wr_err; + assign fifo_ctrl_txilvl_wd = reg_wdata[6:5]; + assign fifo_status_txlvl_re = addr_hit[8] && reg_re; + assign fifo_status_rxlvl_re = addr_hit[8] && reg_re; + assign ovrd_txen_we = (addr_hit[9] & reg_we) & ~wr_err; + assign ovrd_txen_wd = reg_wdata[0]; + assign ovrd_txval_we = (addr_hit[9] & reg_we) & ~wr_err; + assign ovrd_txval_wd = reg_wdata[1]; + assign val_re = addr_hit[10] && reg_re; + assign timeout_ctrl_val_we = (addr_hit[11] & reg_we) & ~wr_err; + assign timeout_ctrl_val_wd = reg_wdata[23:0]; + assign timeout_ctrl_en_we = (addr_hit[11] & reg_we) & ~wr_err; + assign timeout_ctrl_en_wd = reg_wdata[31]; + always @(*) begin + reg_rdata_next = {DW {1'sb0}}; + case (1'b1) + addr_hit[0]: begin + reg_rdata_next[0] = intr_state_tx_watermark_qs; + reg_rdata_next[1] = intr_state_rx_watermark_qs; + reg_rdata_next[2] = intr_state_tx_empty_qs; + reg_rdata_next[3] = intr_state_rx_overflow_qs; + reg_rdata_next[4] = intr_state_rx_frame_err_qs; + reg_rdata_next[5] = intr_state_rx_break_err_qs; + reg_rdata_next[6] = intr_state_rx_timeout_qs; + reg_rdata_next[7] = intr_state_rx_parity_err_qs; + end + addr_hit[1]: begin + reg_rdata_next[0] = intr_enable_tx_watermark_qs; + reg_rdata_next[1] = intr_enable_rx_watermark_qs; + reg_rdata_next[2] = intr_enable_tx_empty_qs; + reg_rdata_next[3] = intr_enable_rx_overflow_qs; + reg_rdata_next[4] = intr_enable_rx_frame_err_qs; + reg_rdata_next[5] = intr_enable_rx_break_err_qs; + reg_rdata_next[6] = intr_enable_rx_timeout_qs; + reg_rdata_next[7] = intr_enable_rx_parity_err_qs; + end + addr_hit[2]: begin + reg_rdata_next[0] = 1'sb0; + reg_rdata_next[1] = 1'sb0; + reg_rdata_next[2] = 1'sb0; + reg_rdata_next[3] = 1'sb0; + reg_rdata_next[4] = 1'sb0; + reg_rdata_next[5] = 1'sb0; + reg_rdata_next[6] = 1'sb0; + reg_rdata_next[7] = 1'sb0; + end + addr_hit[3]: begin + reg_rdata_next[0] = ctrl_tx_qs; + reg_rdata_next[1] = ctrl_rx_qs; + reg_rdata_next[2] = ctrl_nf_qs; + reg_rdata_next[4] = ctrl_slpbk_qs; + reg_rdata_next[5] = ctrl_llpbk_qs; + reg_rdata_next[6] = ctrl_parity_en_qs; + reg_rdata_next[7] = ctrl_parity_odd_qs; + reg_rdata_next[9:8] = ctrl_rxblvl_qs; + reg_rdata_next[31:16] = ctrl_nco_qs; + end + addr_hit[4]: begin + reg_rdata_next[0] = status_txfull_qs; + reg_rdata_next[1] = status_rxfull_qs; + reg_rdata_next[2] = status_txempty_qs; + reg_rdata_next[3] = status_txidle_qs; + reg_rdata_next[4] = status_rxidle_qs; + reg_rdata_next[5] = status_rxempty_qs; + end + addr_hit[5]: reg_rdata_next[7:0] = rdata_qs; + addr_hit[6]: reg_rdata_next[7:0] = {8 {1'sb0}}; + addr_hit[7]: begin + reg_rdata_next[0] = 1'sb0; + reg_rdata_next[1] = 1'sb0; + reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs; + reg_rdata_next[6:5] = fifo_ctrl_txilvl_qs; + end + addr_hit[8]: begin + reg_rdata_next[5:0] = fifo_status_txlvl_qs; + reg_rdata_next[21:16] = fifo_status_rxlvl_qs; + end + addr_hit[9]: begin + reg_rdata_next[0] = ovrd_txen_qs; + reg_rdata_next[1] = ovrd_txval_qs; + end + addr_hit[10]: reg_rdata_next[15:0] = val_qs; + addr_hit[11]: begin + reg_rdata_next[23:0] = timeout_ctrl_val_qs; + reg_rdata_next[31] = timeout_ctrl_en_qs; + end + default: reg_rdata_next = {DW {1'sb1}}; + endcase + end +endmodule +module uart_rx ( + clk_i, + rst_ni, + rx_enable, + tick_baud_x16, + parity_enable, + parity_odd, + tick_baud, + rx_valid, + rx_data, + idle, + frame_err, + rx_parity_err, + rx +); + input clk_i; + input rst_ni; + input rx_enable; + input tick_baud_x16; + input parity_enable; + input parity_odd; + output wire tick_baud; + output wire rx_valid; + output [7:0] rx_data; + output wire idle; + output frame_err; + output rx_parity_err; + input rx; + reg rx_valid_q; + reg [10:0] sreg_q; + reg [10:0] sreg_d; + reg [3:0] bit_cnt_q; + reg [3:0] bit_cnt_d; + reg [3:0] baud_div_q; + reg [3:0] baud_div_d; + reg tick_baud_d; + reg tick_baud_q; + reg idle_d; + reg idle_q; + assign tick_baud = tick_baud_q; + assign idle = idle_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + sreg_q <= 11'h000; + bit_cnt_q <= 4'h0; + baud_div_q <= 4'h0; + tick_baud_q <= 1'b0; + idle_q <= 1'b1; + end + else begin + sreg_q <= sreg_d; + bit_cnt_q <= bit_cnt_d; + baud_div_q <= baud_div_d; + tick_baud_q <= tick_baud_d; + idle_q <= idle_d; + end + always @(*) + if (!rx_enable) begin + sreg_d = 11'h000; + bit_cnt_d = 4'h0; + baud_div_d = 4'h0; + tick_baud_d = 1'b0; + idle_d = 1'b1; + end + else begin + tick_baud_d = 1'b0; + sreg_d = sreg_q; + bit_cnt_d = bit_cnt_q; + baud_div_d = baud_div_q; + idle_d = idle_q; + if (tick_baud_x16) + {tick_baud_d, baud_div_d} = {1'b0, baud_div_q} + 5'h01; + if (idle_q && !rx) begin + baud_div_d = 4'd8; + tick_baud_d = 1'b0; + bit_cnt_d = (parity_enable ? 4'd11 : 4'd10); + sreg_d = 11'h000; + idle_d = 1'b0; + end + else if (!idle_q && tick_baud_q) + if ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx) begin + idle_d = 1'b1; + bit_cnt_d = 4'h0; + end + else begin + sreg_d = {rx, sreg_q[10:1]}; + bit_cnt_d = bit_cnt_q - 4'h1; + idle_d = bit_cnt_q == 4'h1; + end + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + rx_valid_q <= 1'b0; + else + rx_valid_q <= tick_baud_q & (bit_cnt_q == 4'h1); + assign rx_valid = rx_valid_q; + assign rx_data = (parity_enable ? sreg_q[8:1] : sreg_q[9:2]); + assign frame_err = rx_valid_q & ~sreg_q[10]; + assign rx_parity_err = (parity_enable & rx_valid_q) & ^{sreg_q[9:1], parity_odd}; +endmodule +module uart_tx ( + clk_i, + rst_ni, + tx_enable, + tick_baud_x16, + parity_enable, + wr, + wr_parity, + wr_data, + idle, + tx +); + input clk_i; + input rst_ni; + input tx_enable; + input tick_baud_x16; + input wire parity_enable; + input wr; + input wire wr_parity; + input [7:0] wr_data; + output idle; + output wire tx; + reg [3:0] baud_div_q; + reg tick_baud_q; + reg [3:0] bit_cnt_q; + reg [3:0] bit_cnt_d; + reg [10:0] sreg_q; + reg [10:0] sreg_d; + reg tx_q; + reg tx_d; + assign tx = tx_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + baud_div_q <= 4'h0; + tick_baud_q <= 1'b0; + end + else if (tick_baud_x16) + {tick_baud_q, baud_div_q} <= {1'b0, baud_div_q} + 5'h01; + else + tick_baud_q <= 1'b0; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + bit_cnt_q <= 4'h0; + sreg_q <= 11'h7ff; + tx_q <= 1'b1; + end + else begin + bit_cnt_q <= bit_cnt_d; + sreg_q <= sreg_d; + tx_q <= tx_d; + end + always @(*) + if (!tx_enable) begin + bit_cnt_d = 4'h0; + sreg_d = 11'h7ff; + tx_d = 1'b1; + end + else begin + bit_cnt_d = bit_cnt_q; + sreg_d = sreg_q; + tx_d = tx_q; + if (wr) begin + sreg_d = {1'b1, (parity_enable ? wr_parity : 1'b1), wr_data, 1'b0}; + bit_cnt_d = (parity_enable ? 4'd11 : 4'd10); + end + else if (tick_baud_q && (bit_cnt_q != 4'h0)) begin + sreg_d = {1'b1, sreg_q[10:1]}; + tx_d = sreg_q[0]; + bit_cnt_d = bit_cnt_q - 4'h1; + end + end + assign idle = (tx_enable ? bit_cnt_q == 4'h0 : 1'b1); +endmodule
diff --git a/verilog/rtl/ghazi/ghazi_top_dffram_csv.v b/verilog/rtl/ghazi/ghazi_top_dffram_csv.v new file mode 100644 index 0000000..5c1130c --- /dev/null +++ b/verilog/rtl/ghazi/ghazi_top_dffram_csv.v
@@ -0,0 +1,195 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module ghazi_top_dffram_csv ( +`ifdef USE_POWER_PINS + inout VPWR, // User area 1 1.8V supply + inout VGND, // User area 1 digital ground +`endif + + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oen, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb +); + + wire RESET_n; + wire rst_ni; + wire rst_lc_ni; + wire ndmreset_req_o; + wire jtag_tck_i; + wire jtag_tms_i; + wire jtag_trst_ni; + wire jtag_tdi_i; + wire jtag_tdo_o; + wire cio_uart_rx_p2d; + wire cio_uart_tx_d2p; + wire cio_uart_tx_en_d2p; + wire [31:0] cio_gpio_gpio_p2d; + wire [31:0] cio_gpio_gpio_d2p; + wire [31:0] cio_gpio_gpio_en_d2p; + wire cio_spi_device_sck_p2d; + wire cio_spi_device_csb_p2d; + wire cio_spi_device_sdi_p2d; + wire cio_spi_device_sdo_d2p; + wire cio_spi_device_sdo_en_d2p; + wire [15:0] CLKS_PER_BIT; + assign CLKS_PER_BIT = la_data_in[47:32]; + assign rst_lc_ni = la_data_in[64]; + assign la_data_out[31:0] = cio_gpio_gpio_en_d2p; + assign la_data_out[32] = cio_uart_tx_en_d2p; + assign la_data_out[33] = ndmreset_req_o; + assign RESET_n = (~la_oen[0]) ? (~la_data_in[0]) : ~wb_rst_i; + // assign RESET_n = ~wb_rst_i; + assign jtag_tck_i = io_in[0]; + assign jtag_tms_i = io_in[1]; + assign jtag_trst_ni = io_in[2]; + assign jtag_tdi_i = io_in[3]; + assign io_out[4] = jtag_tdo_o; + assign cio_uart_rx_p2d = io_in[5]; + assign cio_spi_device_sdi_p2d = io_in[18]; + assign cio_spi_device_csb_p2d = io_in[19]; + assign cio_spi_device_sck_p2d = io_in[20]; + assign cio_gpio_gpio_p2d = io_in[36:5]; + assign io_out[5] = cio_gpio_gpio_d2p[0]; + assign io_out[6] = (cio_uart_tx_en_d2p ? cio_uart_tx_d2p : cio_gpio_gpio_d2p[1]); + assign io_out[16:7] = cio_gpio_gpio_d2p[11:2]; + assign io_out[17] = (cio_spi_device_sdo_en_d2p ? cio_spi_device_sdo_d2p : cio_gpio_gpio_d2p[12]); + assign io_out[28:18] = cio_gpio_gpio_d2p[23:13]; + assign io_out[36:29] = cio_gpio_gpio_d2p[31:24]; + assign io_oeb[36:0] = {~cio_gpio_gpio_en_d2p[31:2], ~cio_gpio_gpio_en_d2p[1] | ~cio_uart_tx_en_d2p, ~cio_gpio_gpio_en_d2p[0], 1'b0, 4'b1111}; + wire ram_main_instr_req; + wire ram_main_instr_we; + wire [13:0] ram_main_instr_addr; + wire [31:0] ram_main_instr_wdata; + wire [31:0] ram_main_instr_wmask; + wire [31:0] ram_main_instr_rdata; + reg ram_main_instr_rvalid; + wire [1:0] ram_main_instr_rerror; + wire ram_main_data_req; + wire ram_main_data_we; + wire [13:0] ram_main_data_addr; + wire [31:0] ram_main_data_wdata; + wire [31:0] ram_main_data_wmask; + wire [31:0] ram_main_data_rdata; + reg ram_main_data_rvalid; + wire [1:0] ram_main_data_rerror; + ghazi_top ghazi_top( + .clk_i(wb_clk_i), + .rst_lc_ni(rst_lc_ni), + .rst_ni(rst_ni), + .ram_main_instr_req(ram_main_instr_req), + .ram_main_instr_we(ram_main_instr_we), + .ram_main_instr_addr(ram_main_instr_addr), + .ram_main_instr_wdata(ram_main_instr_wdata), + .ram_main_instr_wmask(ram_main_instr_wmask), + .ram_main_instr_rdata(ram_main_instr_rdata), + .ram_main_instr_rvalid(ram_main_instr_rvalid), + .ram_main_instr_rerror(2'b00), + .ram_main_data_req(ram_main_data_req), + .ram_main_data_we(ram_main_data_we), + .ram_main_data_addr(ram_main_data_addr), + .ram_main_data_wdata(ram_main_data_wdata), + .ram_main_data_wmask(ram_main_data_wmask), + .ram_main_data_rdata(ram_main_data_rdata), + .ram_main_data_rvalid(ram_main_data_rvalid), + .ram_main_data_rerror(2'b00), + .jtag_tck_i(jtag_tck_i), + .jtag_tms_i(jtag_tms_i), + .jtag_trst_ni(jtag_trst_ni), + .jtag_tdi_i(jtag_tdi_i), + .jtag_tdo_o(jtag_tdo_o), + .cio_gpio_gpio_p2d(cio_gpio_gpio_p2d), + .cio_gpio_gpio_d2p(cio_gpio_gpio_d2p), + .cio_gpio_gpio_en_d2p(cio_gpio_gpio_en_d2p), + .cio_uart_rx_p2d(cio_uart_rx_p2d), + .cio_uart_tx_d2p(cio_uart_tx_d2p), + .cio_uart_tx_en_d2p(cio_uart_tx_en_d2p), + .cio_spi_device_sck_p2d(cio_spi_device_sck_p2d), + .cio_spi_device_csb_p2d(cio_spi_device_csb_p2d), + .cio_spi_device_sdi_p2d(cio_spi_device_sdi_p2d), + .cio_spi_device_sdo_d2p(cio_spi_device_sdo_d2p), + .cio_spi_device_sdo_en_d2p(cio_spi_device_sdo_en_d2p), + .ndmreset_req_o(ndmreset_req_o) + ); + wire [3:0] instr_WE; + wire instr_EN; + wire ram_prog_instr_we; + wire [31:0] instr_Di; + wire [31:0] ram_prog_instr_wdata; + wire [13:0] instr_A; + wire [13:0] ram_prog_instr_addr; + assign instr_A = (rst_ni ? ram_main_instr_addr : ram_prog_instr_addr); + assign instr_Di = (rst_ni ? ram_main_instr_wdata : ram_prog_instr_wdata); + assign instr_WE = {4 {ram_prog_instr_we}} | ({ram_main_instr_wmask[31:24] != 8'b00000000, ram_main_instr_wmask[23:16] != 8'b00000000, ram_main_instr_wmask[15:8] != 8'b00000000, ram_main_instr_wmask[7:0] != 8'b00000000} & {4 {ram_main_instr_we}}); + assign instr_EN = ram_main_instr_req | ram_prog_instr_we; + always @(posedge wb_clk_i) + if (!rst_ni) + ram_main_instr_rvalid <= 1'b0; + else if (ram_main_instr_we || ram_prog_instr_we) + ram_main_instr_rvalid <= 1'b0; + else + ram_main_instr_rvalid <= ram_main_instr_req; + DFFRAM #(1) SRAMI( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(wb_clk_i), + .WE(instr_WE), + .EN(instr_EN), + .Di(instr_Di), + .Do(ram_main_instr_rdata), + .A(instr_A[7:0]) + ); + wire [3:0] data_WE; + assign data_WE = {ram_main_data_wmask[31:24] != 8'b00000000, ram_main_data_wmask[23:16] != 8'b00000000, ram_main_data_wmask[15:8] != 8'b00000000, ram_main_data_wmask[7:0] != 8'b00000000} & {4 {ram_main_data_we}}; + always @(posedge wb_clk_i) + if (!rst_ni) + ram_main_data_rvalid <= 1'b0; + else if (ram_main_data_we) + ram_main_data_rvalid <= 1'b0; + else + ram_main_data_rvalid <= ram_main_data_req; + DFFRAM #(1) SRAMD( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(wb_clk_i), + .WE(data_WE), + .EN(ram_main_data_req), + .Di(ram_main_data_wdata), + .Do(ram_main_data_rdata), + .A(ram_main_data_addr[7:0]) + ); + wire rx_dv_i; + wire [7:0] rx_byte_i; + iccm_controller u_dut( + .clk_i(wb_clk_i), + .rst_ni(RESET_n), + .rx_dv_i(rx_dv_i), + .rx_byte_i(rx_byte_i), + .we_o(ram_prog_instr_we), + .addr_o(ram_prog_instr_addr), + .wdata_o(ram_prog_instr_wdata), + .reset_o(rst_ni) + ); + uart_rx_prog u_uart_rx( + .i_Clock(wb_clk_i), + .rst_ni(RESET_n), + .i_Rx_Serial(cio_uart_rx_p2d), + .CLKS_PER_BIT(CLKS_PER_BIT), + .o_Rx_DV(rx_dv_i), + .o_Rx_Byte(rx_byte_i) + ); +endmodule
diff --git a/verilog/rtl/ghazi/iccm_controller.v b/verilog/rtl/ghazi/iccm_controller.v new file mode 100644 index 0000000..41d95d4 --- /dev/null +++ b/verilog/rtl/ghazi/iccm_controller.v
@@ -0,0 +1,117 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module iccm_controller ( + clk_i, + rst_ni, + rx_dv_i, + rx_byte_i, + we_o, + addr_o, + wdata_o, + reset_o +); + input wire clk_i; + input wire rst_ni; + input wire rx_dv_i; + input wire [7:0] rx_byte_i; + output wire we_o; + output wire [13:0] addr_o; + output wire [31:0] wdata_o; + output wire reset_o; + reg [1:0] ctrl_fsm_cs; + reg [1:0] ctrl_fsm_ns; + wire [7:0] rx_byte_d; + reg [7:0] rx_byte_q0; + reg [7:0] rx_byte_q1; + reg [7:0] rx_byte_q2; + reg [7:0] rx_byte_q3; + reg we_q; + reg we_d; + reg [13:0] addr_q; + reg [13:0] addr_d; + reg reset_q; + reg reset_d; + reg [1:0] byte_count; + localparam [1:0] DONE = 3; + localparam [1:0] LOAD = 1; + localparam [1:0] PROG = 2; + localparam [1:0] RESET = 0; + always @(*) begin + we_d = we_q; + addr_d = addr_q; + reset_d = reset_q; + ctrl_fsm_ns = ctrl_fsm_cs; + case (ctrl_fsm_cs) + RESET: + if (rx_dv_i) + ctrl_fsm_ns = LOAD; + else + ctrl_fsm_ns = RESET; + LOAD: + if (((byte_count == 2'b11) && (rx_byte_q2 != 8'h0f)) && (rx_byte_d != 8'hff)) begin + we_d = 1'b1; + ctrl_fsm_ns = PROG; + end + else + ctrl_fsm_ns = DONE; + PROG: begin + we_d = 1'b0; + ctrl_fsm_ns = DONE; + end + DONE: + if (wdata_o == 32'h00000fff) begin + ctrl_fsm_ns = DONE; + reset_d = 1'b1; + end + else if (rx_dv_i) + ctrl_fsm_ns = LOAD; + else + ctrl_fsm_ns = DONE; + default: ctrl_fsm_ns = RESET; + endcase + end + assign rx_byte_d = rx_byte_i; + assign we_o = we_q; + assign addr_o = addr_q; + assign wdata_o = {rx_byte_q0, rx_byte_q1, rx_byte_q2, rx_byte_q3}; + assign reset_o = reset_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) begin + we_q <= 1'b0; + addr_q <= 14'b00000000000000; + rx_byte_q0 <= 8'b00000000; + rx_byte_q1 <= 8'b00000000; + rx_byte_q2 <= 8'b00000000; + rx_byte_q3 <= 8'b00000000; + reset_q <= 1'b0; + byte_count <= 2'b00; + ctrl_fsm_cs <= RESET; + end + else begin + we_q <= we_d; + if (ctrl_fsm_cs == LOAD) begin + if (byte_count == 2'b00) begin + rx_byte_q0 <= rx_byte_d; + byte_count <= 2'b01; + end + else if (byte_count == 2'b01) begin + rx_byte_q1 <= rx_byte_d; + byte_count <= 2'b10; + end + else if (byte_count == 2'b10) begin + rx_byte_q2 <= rx_byte_d; + byte_count <= 2'b11; + end + else begin + rx_byte_q3 <= rx_byte_d; + byte_count <= 2'b00; + end + addr_q <= addr_d; + end + if (ctrl_fsm_cs == PROG) + addr_q <= addr_d + 1'b1; + reset_q <= reset_d; + ctrl_fsm_cs <= ctrl_fsm_ns; + end +endmodule \ No newline at end of file
diff --git a/verilog/rtl/ghazi/uart_rx_prog.v b/verilog/rtl/ghazi/uart_rx_prog.v new file mode 100644 index 0000000..b7ee5d1 --- /dev/null +++ b/verilog/rtl/ghazi/uart_rx_prog.v
@@ -0,0 +1,142 @@ +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +module uart_rx_prog ( + input i_Clock, + input rst_ni, + input i_Rx_Serial, + input [15:0] CLKS_PER_BIT, + output o_Rx_DV, + output [7:0] o_Rx_Byte + ); + + parameter s_IDLE = 3'b000; + parameter s_RX_START_BIT = 3'b001; + parameter s_RX_DATA_BITS = 3'b010; + parameter s_RX_STOP_BIT = 3'b011; + parameter s_CLEANUP = 3'b100; + + reg r_Rx_Data_R = 1'b1; + reg r_Rx_Data = 1'b1; + + reg [15:0] r_Clock_Count = 0; + reg [2:0] r_Bit_Index = 0; //8 bits total + reg [7:0] r_Rx_Byte = 0; + reg r_Rx_DV = 0; + reg [2:0] r_SM_Main = 0; + + // Purpose: Double-register the incoming data. + // This allows it to be used in the UART RX Clock Domain. + // (It removes problems caused by metastability) + always @(posedge i_Clock) + begin + r_Rx_Data_R <= i_Rx_Serial; + r_Rx_Data <= r_Rx_Data_R; + end + + + // Purpose: Control RX state machine + always @(posedge i_Clock) + begin + if (!rst_ni) begin + r_SM_Main <= s_IDLE; + end else begin + case (r_SM_Main) + s_IDLE : + begin + r_Rx_DV <= 1'b0; + r_Clock_Count <= 0; + r_Bit_Index <= 0; + + if (r_Rx_Data == 1'b0) // Start bit detected + r_SM_Main <= s_RX_START_BIT; + else + r_SM_Main <= s_IDLE; + end + + // Check middle of start bit to make sure it's still low + s_RX_START_BIT : + begin + if (r_Clock_Count == ((CLKS_PER_BIT-1)>>1)) + begin + if (r_Rx_Data == 1'b0) + begin + r_Clock_Count <= 0; // reset counter, found the middle + r_SM_Main <= s_RX_DATA_BITS; + end + else + r_SM_Main <= s_IDLE; + end + else + begin + r_Clock_Count <= r_Clock_Count + 1; + r_SM_Main <= s_RX_START_BIT; + end + end // case: s_RX_START_BIT + + + // Wait CLKS_PER_BIT-1 clock cycles to sample serial data + s_RX_DATA_BITS : + begin + if (r_Clock_Count < CLKS_PER_BIT-1) + begin + r_Clock_Count <= r_Clock_Count + 1; + r_SM_Main <= s_RX_DATA_BITS; + end + else + begin + r_Clock_Count <= 0; + r_Rx_Byte[r_Bit_Index] <= r_Rx_Data; + + // Check if we have received all bits + if (r_Bit_Index < 7) + begin + r_Bit_Index <= r_Bit_Index + 1; + r_SM_Main <= s_RX_DATA_BITS; + end + else + begin + r_Bit_Index <= 0; + r_SM_Main <= s_RX_STOP_BIT; + end + end + end // case: s_RX_DATA_BITS + + + // Receive Stop bit. Stop bit = 1 + s_RX_STOP_BIT : + begin + // Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish + if (r_Clock_Count < CLKS_PER_BIT-1) + begin + r_Clock_Count <= r_Clock_Count + 1; + r_SM_Main <= s_RX_STOP_BIT; + end + else + begin + r_Rx_DV <= 1'b1; + r_Clock_Count <= 0; + r_SM_Main <= s_CLEANUP; + end + end // case: s_RX_STOP_BIT + + + // Stay here 1 clock + s_CLEANUP : + begin + r_SM_Main <= s_IDLE; + r_Rx_DV <= 1'b0; + end + + + default : + r_SM_Main <= s_IDLE; + + endcase + end + end + + assign o_Rx_DV = r_Rx_DV; + assign o_Rx_Byte = r_Rx_Byte; + +endmodule // uart_rx \ No newline at end of file
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 47d92f4..9821cd4 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -79,16 +79,10 @@ /* User project is instantiated here */ /*--------------------------------------*/ - user_proj_example mprj ( + ghazi_top_dffram_csv mprj ( `ifdef USE_POWER_PINS - .vdda1(vdda1), // User area 1 3.3V power - .vdda2(vdda2), // User area 2 3.3V power - .vssa1(vssa1), // User area 1 analog ground - .vssa2(vssa2), // User area 2 analog ground - .vccd1(vccd1), // User area 1 1.8V power - .vccd2(vccd2), // User area 2 1.8V power - .vssd1(vssd1), // User area 1 digital ground - .vssd2(vssd2), // User area 2 digital ground + .VPWR(vccd1), // User area 1 1.8V power + .VGND(vssd1), // User area 1 digital ground `endif // MGMT core clock and reset @@ -96,17 +90,6 @@ .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), - // MGMT SoC Wishbone Slave - - .wbs_cyc_i(wbs_cyc_i), - .wbs_stb_i(wbs_stb_i), - .wbs_we_i(wbs_we_i), - .wbs_sel_i(wbs_sel_i), - .wbs_adr_i(wbs_adr_i), - .wbs_dat_i(wbs_dat_i), - .wbs_ack_o(wbs_ack_o), - .wbs_dat_o(wbs_dat_o), - // Logic Analyzer .la_data_in(la_data_in),
