Add sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped configs

openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl

diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl
new file mode 100644
index 0000000..54e2f73
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/config.tcl
@@ -0,0 +1,28 @@
+# This is an analog design. It will be designed by hand.
+# This is a placeholder to get things going.
+set script_dir [file dirname [file normalize [info script]]]
+# User config
+set ::env(DESIGN_NAME) sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped
+set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hvl
+
+# Change if needed
+set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped.v
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# Fill this
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(CELL_PAD) 0
+
+set ::env(PL_RANDOM_GLB_PLACEMENT) 1
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 25 25"
+set ::env(BOTTOM_MARGIN_MULT) 0
+set ::env(TOP_MARGIN_MULT) 0
+set ::env(LEFT_MARGIN_MULT) 0
+set ::env(RIGHT_MARGIN_MULT) 0
+
+set ::env(PLACE_SITE) "unithvdbl"
+set ::env(PLACE_SITE_WIDTH) 0.480
+set ::env(PLACE_SITE_HEIGHT) 8.14

openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/macro_placement.cfg

diff --git a/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/macro_placement.cfg b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/macro_placement.cfg
new file mode 100644
index 0000000..988134f
--- /dev/null
+++ b/openlane/sky130_fd_sc_hvl__lsbufhv2lv_1_wrapped/macro_placement.cfg
@@ -0,0 +1 @@
+lvlshiftdown  8.825 16.280   N