Corrected an issue with the JTAG and SDO pins that prevented them from
being converted to general purpose digital I/O signals by the management
SoC. This was showing up in the timer testbench which was not seeing
the low two output bits.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index a9caf12..b55ec62 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -488,7 +488,7 @@
gpio_control_block #(
.DM_INIT(3'b110), // Mode = output, strong up/down
- .OENB_INIT(1'b0) // Enable output signaling from wire
+ .OENB_INIT(1'b1) // Enable output signaling from wire
) gpio_control_bidir [1:0] (
`ifdef LVS
inout vccd,
