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agorararmard9c7e7722020-12-11 23:13:01 +02001# SPDX-FileCopyrightText: 2020 Efabless Corporation
2#
3# Licensed under the Apache License, Version 2.0 (the "License");
4# you may not use this file except in compliance with the License.
5# You may obtain a copy of the License at
6#
7# http://www.apache.org/licenses/LICENSE-2.0
8#
9# Unless required by applicable law or agreed to in writing, software
10# distributed under the License is distributed on an "AS IS" BASIS,
11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12# See the License for the specific language governing permissions and
13# limitations under the License.
14# SPDX-License-Identifier: Apache-2.0
15
16# Base Configurations. Don't Touch
17# section begin
18set script_dir [file dirname [file normalize [info script]]]
19set ::env(DESIGN_NAME) user_project_wrapper
20#section end
21
22
23# User Configurations
24set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
25
26set ::env(CLOCK_PORT) "user_clock2"
27set ::env(CLOCK_NET) "mprj.clk"
28
29set ::env(CLOCK_PERIOD) "10"
30
31set ::env(VERILOG_FILES) "\
32 $script_dir/../../verilog/rtl/defines.v \
33 $script_dir/../../verilog/rtl/user_project_wrapper.v"
34
35set ::env(VERILOG_FILES_BLACKBOX) "\
36 $script_dir/../../verilog/rtl/defines.v \
37 $script_dir/../../verilog/rtl/user_proj_example.v"
38
39set ::env(EXTRA_LEFS) "\
40 $script_dir/../../lef/user_proj_example.lef"
41
42set ::env(EXTRA_GDS_FILES) "\
43 $script_dir/../../gds/user_proj_example.gds"
44
45
46# The following is because there are no std cells in the example wrapper project.
47set ::env(SYNTH_TOP_LEVEL) 1
48set ::env(PL_RANDOM_GLB_PLACEMENT) 1
49set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
50set ::env(DIODE_INSERTION_STRATEGY) 0
51set ::env(FILL_INSERTION) 0
52set ::env(TAP_DECAP_INSERTION) 0
53set ::env(CLOCK_TREE_SYNTH) 0
54
55# Area Configurations. DON'T TOUCH.
56set ::env(FP_SIZING) absolute
57set ::env(DIE_AREA) "0 0 2920 3520"
58
59# Power & Pin Configurations. DON'T TOUCH.
60set ::env(FP_PDN_CORE_RING) 1
agorararmardb3e15092020-12-14 20:07:49 +000061set ::env(FP_PDN_CORE_RING_VWIDTH) 3
62set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH)
63set ::env(FP_PDN_CORE_RING_VSPACING) 1.7
64set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING)
65set ::env(FP_PDN_VOFFSET) 14
66set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET)
67set ::env(FP_PDN_VPITCH) 180
68set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH)
69set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)]
70set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)]
71set ::env(FP_PDN_CORE_RING_VOFFSET) 0
72set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET)
73
agorararmard9c7e7722020-12-11 23:13:01 +020074
75set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
76set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
agorararmardb3e15092020-12-14 20:07:49 +000077set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
agorararmard9c7e7722020-12-11 23:13:01 +020078#set ::env(PDN_CFG) $script_dir/pdn.tcl
79
80set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
81set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def
82set ::unit 2.4
83set ::env(FP_IO_VEXTEND) [expr 2*$::unit]
84set ::env(FP_IO_HEXTEND) [expr 2*$::unit]
85set ::env(FP_IO_VLENGTH) $::unit
86set ::env(FP_IO_HLENGTH) $::unit
87
88set ::env(FP_IO_VTHICKNESS_MULT) 4
89set ::env(FP_IO_HTHICKNESS_MULT) 4
90
91
92
93# Need to fix a FastRoute bug for this to work, but it's good
94# for a sense of "isolation"
95set ::env(MAGIC_ZEROIZE_ORIGIN) 0
96set ::env(MAGIC_WRITE_FULL_LEF) 1
97