agorararmard | 9c7e772 | 2020-12-11 23:13:01 +0200 | [diff] [blame] | 1 | # SPDX-FileCopyrightText: 2020 Efabless Corporation |
| 2 | # |
| 3 | # Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | # you may not use this file except in compliance with the License. |
| 5 | # You may obtain a copy of the License at |
| 6 | # |
| 7 | # http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | # |
| 9 | # Unless required by applicable law or agreed to in writing, software |
| 10 | # distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | # See the License for the specific language governing permissions and |
| 13 | # limitations under the License. |
| 14 | # SPDX-License-Identifier: Apache-2.0 |
| 15 | |
| 16 | # Base Configurations. Don't Touch |
| 17 | # section begin |
| 18 | set script_dir [file dirname [file normalize [info script]]] |
| 19 | set ::env(DESIGN_NAME) user_project_wrapper |
| 20 | #section end |
| 21 | |
| 22 | |
| 23 | # User Configurations |
| 24 | set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg |
| 25 | |
| 26 | set ::env(CLOCK_PORT) "user_clock2" |
| 27 | set ::env(CLOCK_NET) "mprj.clk" |
| 28 | |
| 29 | set ::env(CLOCK_PERIOD) "10" |
| 30 | |
| 31 | set ::env(VERILOG_FILES) "\ |
| 32 | $script_dir/../../verilog/rtl/defines.v \ |
| 33 | $script_dir/../../verilog/rtl/user_project_wrapper.v" |
| 34 | |
| 35 | set ::env(VERILOG_FILES_BLACKBOX) "\ |
| 36 | $script_dir/../../verilog/rtl/defines.v \ |
| 37 | $script_dir/../../verilog/rtl/user_proj_example.v" |
| 38 | |
| 39 | set ::env(EXTRA_LEFS) "\ |
| 40 | $script_dir/../../lef/user_proj_example.lef" |
| 41 | |
| 42 | set ::env(EXTRA_GDS_FILES) "\ |
| 43 | $script_dir/../../gds/user_proj_example.gds" |
| 44 | |
| 45 | |
| 46 | # The following is because there are no std cells in the example wrapper project. |
| 47 | set ::env(SYNTH_TOP_LEVEL) 1 |
| 48 | set ::env(PL_RANDOM_GLB_PLACEMENT) 1 |
| 49 | set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 |
| 50 | set ::env(DIODE_INSERTION_STRATEGY) 0 |
| 51 | set ::env(FILL_INSERTION) 0 |
| 52 | set ::env(TAP_DECAP_INSERTION) 0 |
| 53 | set ::env(CLOCK_TREE_SYNTH) 0 |
| 54 | |
| 55 | # Area Configurations. DON'T TOUCH. |
| 56 | set ::env(FP_SIZING) absolute |
| 57 | set ::env(DIE_AREA) "0 0 2920 3520" |
| 58 | |
| 59 | # Power & Pin Configurations. DON'T TOUCH. |
| 60 | set ::env(FP_PDN_CORE_RING) 1 |
agorararmard | b3e1509 | 2020-12-14 20:07:49 +0000 | [diff] [blame^] | 61 | set ::env(FP_PDN_CORE_RING_VWIDTH) 3 |
| 62 | set ::env(FP_PDN_CORE_RING_HWIDTH) $::env(FP_PDN_CORE_RING_VWIDTH) |
| 63 | set ::env(FP_PDN_CORE_RING_VSPACING) 1.7 |
| 64 | set ::env(FP_PDN_CORE_RING_HSPACING) $::env(FP_PDN_CORE_RING_VSPACING) |
| 65 | set ::env(FP_PDN_VOFFSET) 14 |
| 66 | set ::env(FP_PDN_HOFFSET) $::env(FP_PDN_VOFFSET) |
| 67 | set ::env(FP_PDN_VPITCH) 180 |
| 68 | set ::env(FP_PDN_HPITCH) $::env(FP_PDN_VPITCH) |
| 69 | set ::env(FP_PDN_VSPACING) [expr 5*$::env(FP_PDN_CORE_RING_VWIDTH)] |
| 70 | set ::env(FP_PDN_HSPACING) [expr 5*$::env(FP_PDN_CORE_RING_HWIDTH)] |
| 71 | set ::env(FP_PDN_CORE_RING_VOFFSET) 0 |
| 72 | set ::env(FP_PDN_CORE_RING_HOFFSET) $::env(FP_PDN_CORE_RING_VOFFSET) |
| 73 | |
agorararmard | 9c7e772 | 2020-12-11 23:13:01 +0200 | [diff] [blame] | 74 | |
| 75 | set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}] |
| 76 | set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}] |
agorararmard | b3e1509 | 2020-12-14 20:07:49 +0000 | [diff] [blame^] | 77 | set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS" |
agorararmard | 9c7e772 | 2020-12-11 23:13:01 +0200 | [diff] [blame] | 78 | #set ::env(PDN_CFG) $script_dir/pdn.tcl |
| 79 | |
| 80 | set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg |
| 81 | set ::env(FP_DEF_TEMPLATE) $script_dir/../../def/user_project_wrapper_empty.def |
| 82 | set ::unit 2.4 |
| 83 | set ::env(FP_IO_VEXTEND) [expr 2*$::unit] |
| 84 | set ::env(FP_IO_HEXTEND) [expr 2*$::unit] |
| 85 | set ::env(FP_IO_VLENGTH) $::unit |
| 86 | set ::env(FP_IO_HLENGTH) $::unit |
| 87 | |
| 88 | set ::env(FP_IO_VTHICKNESS_MULT) 4 |
| 89 | set ::env(FP_IO_HTHICKNESS_MULT) 4 |
| 90 | |
| 91 | |
| 92 | |
| 93 | # Need to fix a FastRoute bug for this to work, but it's good |
| 94 | # for a sense of "isolation" |
| 95 | set ::env(MAGIC_ZEROIZE_ORIGIN) 0 |
| 96 | set ::env(MAGIC_WRITE_FULL_LEF) 1 |
| 97 | |