| commit | f260b1e858fb70863b79911883d3858168cb4bd3 | [log] [tgz] |
|---|---|---|
| author | Ganesh Gore <goreganesh007@gmail.com> | Thu Dec 17 11:51:48 2020 -0700 |
| committer | Ganesh Gore <goreganesh007@gmail.com> | Thu Dec 17 11:51:48 2020 -0700 |
| tree | 1f7eff8b1d28c025c02dc66641fa887d2ebe64f5 | |
| parent | bcd3eee4c19c5e16fc8388f2709e882468bc96a8 [diff] |
[Check] Updated yaml to pass hierarchy check
diff --git a/info.yaml b/info.yaml index 349f4b4..55f467f 100644 --- a/info.yaml +++ b/info.yaml
@@ -17,6 +17,6 @@ - "OpenSource FPGA IP" category: "Test Harness" top_level_netlist: "verilog/gl/caravel.v" - user_level_netlist: "verilog/gl/caravel_sofa_hd_top.v" + user_level_netlist: "verilog/gl/user_project_wrapper.v" version: "1.00" cover_image: "doc/ciic_harness.png"