commit ea96b3a6c6fa5e4c7236be9292cda5f9774c128f
author manarabdelaty <manarabdelatty@aucegypt.edu> Sat Dec 05 01:00:47 2020 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Sat Dec 05 01:00:47 2020 +0200
tree 6df989f388583997ff74502d1a23a7a614084f4d
parent 1d683db7b9a4c32f4955d625420855b149346c7c

Update mem.c

verilog/dv/caravel/mgmt_soc/mem/mem.c

diff --git a/verilog/dv/caravel/mgmt_soc/mem/mem.c b/verilog/dv/caravel/mgmt_soc/mem/mem.c
index 52b0a12..f4e2ea3 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/mem.c
+++ b/verilog/dv/caravel/mgmt_soc/mem/mem.c
@@ -41,12 +41,11 @@
     // start test
     reg_mprj_datal = 0xA0400000;
 
-    i = 0;
     // Test Word R/W
-    // for (i=0; i<1; i++)
+    for (i=0; i<10; i++)
 	ints[i] = i*5000 + 10000;
 	
-    // for (i=0; i<1; i++)
+    for (i=0; i<10; i++)
 	if ((i*5000+10000) != ints[i])
 	    reg_mprj_datal = 0xAB400000;
 
@@ -54,10 +53,10 @@
 	
     // Test Half Word R/W
     reg_mprj_datal = 0xA0200000;
-    // for (i=0; i<1; i++)
+    for (i=0; i<10; i++)
 	shorts[i] = i*500 + 100;
 	
-    // for(i=0; i<1; i++)
+    for(i=0; i<10; i++)
 	if((i*500+100) != shorts[i])
 	    reg_mprj_datal = 0xAB200000;
 
@@ -65,13 +64,12 @@
 
     // Test byte R/W
     reg_mprj_datal = 0xA0100000;
-    // for(i=0; i<1; i++)
+    for(i=0; i<10; i++)
 	bytes[i] = i*5 + 10;
 	
-    // for(i=0; i<1; i++)
+    for(i=0; i<10; i++)
 	if((i*5+10) != bytes[i])
 	    reg_mprj_datal = 0xAB100000;
 
     reg_mprj_datal = 0xAB110000;
-}
-
+}
\ No newline at end of file