commit	18c630bdf5919b2b2908f81ffda9f63cd03d550e	[log] [tgz]
author	Ganesh Gore <goreganesh007@gmail.com>	Wed Dec 16 16:55:54 2020 -0700
committer	Ganesh Gore <goreganesh007@gmail.com>	Wed Dec 16 16:55:54 2020 -0700
tree	1bf95764615ce02069cf6b4f3a87996d1f40f344
parent	4e8365a1d2977190af024782449d95412195f70f [diff]

[LoaclRun02] df61359

OpenFPGA_task/arch/fabric_key.xml[Added - diff]
OpenFPGA_task/arch/openfpga_arch.xml[Added - diff]
OpenFPGA_task/arch/vpr_arch.xml[Added - diff]
OpenFPGA_task/config/task.conf[Added - diff]
OpenFPGA_task/config/task_generation.conf[Added - diff]
OpenFPGA_task/config/task_simulation.conf[Added - diff]
OpenFPGA_task/design_variables.yml[Added - diff]
OpenFPGA_task/generate_fabric.openfpga[Added - diff]
OpenFPGA_task/generate_testbench.openfpga[Added - diff]
OpenFPGA_task/micro_benchmark/and.act[Added - diff]
OpenFPGA_task/micro_benchmark/and.blif[Added - diff]
OpenFPGA_task/micro_benchmark/and.v[Added - diff]
OpenFPGA_task/process_top_def.sh[Added - diff]
OpenFPGA_task/sc_verilog/digital_io_hd.v[Added - diff]
OpenFPGA_task/sc_verilog/fpga_top.v[Added - diff]
OpenFPGA_task/user_project_wrapper_empty.def[Added - diff]
OpenFPGA_task/user_project_wrapper_template.def[Added - diff]
checks/caravel.magic.drc[diff]
checks/caravel.magic.drc.mag[diff]
checks/caravel.magic.rdb[diff]
checks/full_log.log[diff]
checks/magic_drc.log[diff]
checks/magic_merge_user_project_wrapper.log[diff]
checks/manifest_check.maglef.log[diff]
checks/manifest_check.rtl.log[diff]
checks/spdx_compliance_report.log[diff]
gds/caravel.gds.gz[diff]
gds/user_project_wrapper.gds.gz[diff]
mag/.magicrc[diff]
mag/user_project_wrapper.mag[diff]
source_commit_hash.txt[Added - diff]
user_project_wrapper.mag[Added - diff]
verilog/OpenFPGA_Verilog/InstancesMap.txt[Added - diff]
verilog/OpenFPGA_Verilog/define_simulation.v[Added - diff]
verilog/OpenFPGA_Verilog/fabric_netlists.v[Added - diff]
verilog/OpenFPGA_Verilog/fpga_core.v[Added - diff]
verilog/OpenFPGA_Verilog/fpga_defines.v[Added - diff]
verilog/OpenFPGA_Verilog/fpga_top.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/grid_clb.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_clb_.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_io_mode_io_.v[Added - diff]
verilog/OpenFPGA_Verilog/lb/logical_tile_io_mode_physical__iopad.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cbx_1__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cbx_1__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cbx_1__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cby_0__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cby_1__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/cby_2__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_0__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_0__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_0__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_1__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_1__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_1__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_2__0_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_2__1_.v[Added - diff]
verilog/OpenFPGA_Verilog/routing/sb_2__2_.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/arch_encoder.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/digital_io_hd.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/fpga_top.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/inv_buf_passgate.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/local_encoder.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/luts.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/memories.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/muxes.v[Added - diff]
verilog/OpenFPGA_Verilog/sub_module/wires.v[Added - diff]
verilog/OpenFPGA_Verilog/top_include_netlists.v[Added - diff]
verilog/gl/caravel_sofa_hd_top.v/fpga_top_icv_in_design.pt.v[Added - diff]
verilog/gl/caravel_sofa_hd_top.v/fpga_top_icv_in_design.top_only.pt.v[Added - diff]

74 files changed

tree: 1bf95764615ce02069cf6b4f3a87996d1f40f344

README.md

Caravel-SOFA-HD

Highlights

Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library
Base K4 architecture from VPR with 40 vertical and horizontal channels
No adders (carry-chain) or flipflop reset pins
Designed using commercial PnR tool

Contribution

NOTE

This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check Skywater-OpenFPGA

Caravel design and CIIC Harness

For caravel related updated refer efabless/caravel