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mpw-001
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slot-017
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b5992e67cc7d46f70e703f762d8b8cf9cd17401b
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.
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verilog
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OpenFPGA_Verilog
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define_simulation.v
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//
//
//
//
//
//
//
//
`timescale 1ns / 1ps
`
define INITIAL_SIMULATION
1
`define AUTOCHECKED_SIMULATION 1
`
define ENABLE_FORMAL_VERIFICATION
1
`define FORMAL_SIMULATION 1
