blob: 349f4b4c46e924f74c5a8faaebb18d525781b509 [file] [log] [blame]
---
project:
description: "SOFA-HD (Skywater Opensource FPGAs)"
foundry: "SkyWater"
git_url: "https://github.com/lnis-uofu/Caravel-SOFA-HD.git"
organization: "lnis"
organization_url: "https://sites.google.com/site/pegaillardon/home"
owner: "LNIS"
process: "SKY130"
project_name: "Caravel"
tags:
- "Open MPW"
- "Test Harness"
- "VPR"
- "SOFA"
- "Homogeneous FPGA Design"
- "OpenSource FPGA IP"
category: "Test Harness"
top_level_netlist: "verilog/gl/caravel.v"
user_level_netlist: "verilog/gl/caravel_sofa_hd_top.v"
version: "1.00"
cover_image: "doc/ciic_harness.png"