Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 1 | A quick documentation of the Caravel memory map and operation |
| 2 | --------------------------------------------------------------- |
| 3 | |
| 4 | Caravel pinout: |
| 5 | --------------- |
| 6 | |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 7 | vddio 3.3V supply for all I/O and ESD |
| 8 | vssio Ground for all I/O and ESD |
| 9 | vdda 3.3V supply for management area |
| 10 | vssa Ground for management area |
| 11 | vccd 1.8V supply for management area |
| 12 | vssd Digital ground for management area |
| 13 | |
| 14 | vdda1 3.3V supply for user area 1 |
| 15 | vdda2 3.3V supply for user area 2 |
| 16 | vssa1 Ground for user area 1 |
| 17 | vssa2 Ground for user area 2 |
| 18 | vccd1 1.8 supply for user area 1 |
| 19 | vccd2 1.8 supply for user area 2 |
| 20 | vssd1 Digital ground for user area 1 |
| 21 | vssd2 Digital ground for user area 2 |
| 22 | |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 23 | clock Master clock input |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 24 | gpio 1 bit, mainly used for external LDO control of user power supply |
| 25 | mprj_io 32 bits general purpose programmable digital or analog I/O |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 26 | resetb Master reset (sense inverted) input |
| 27 | flash_csb SPI flash controller chip select (sense inverted) |
| 28 | flash_clk SPI flash controller clock |
| 29 | flash_io0 SPI flash controller data out |
| 30 | flash_io1 SPI flash controller data in |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 31 | |
| 32 | Special-use pins for the management SoC: |
| 33 | ---------------------------------------- |
| 34 | |
| 35 | On power-up, the "mprj_io" GPIO are under complete control of the managment |
| 36 | SoC. The first 8 user GPIO are special-purpose pads with dedicated functions |
| 37 | for the management SoC: |
| 38 | |
| 39 | mprj_io[0] JTAG I/O |
| 40 | mprj_io[1] SDO, housekeeping SPI |
| 41 | mprj_io[2] SDI, housekeeping SPI |
| 42 | mprj_io[3] CSB, housekeeping SPI |
| 43 | mprj_io[4] SCK, housekeeping SPI |
| 44 | mprj_io[5] Rx, UART |
| 45 | mprj_io[6] Tx, UART |
Tim Edwards | 6d9739d | 2020-10-19 11:00:49 -0400 | [diff] [blame] | 46 | mprj_io[7] IRQ |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 47 | |
| 48 | The next 4 user GPIO are designed to be used with an SPI flash controller in |
| 49 | the user space. They allow the four pins to be overridden by the housekeeping |
| 50 | SPI to access the SPI flash in pass-through mode. |
| 51 | |
| 52 | mprj_io[8] user flash CSB |
| 53 | mprj_io[9] user flash SCK |
| 54 | mprj_io[10] user flash IO0 |
| 55 | mprj_io[11] user flash IO1 |
| 56 | |
| 57 | The user may additionally use any available GPIO for the SPI flash IO2 and IO3 |
| 58 | lines; the pass-through mode only uses the basic 4-pin SPI mode. |
| 59 | |
| 60 | All of the special-use pins are configured through a memory-mapped region. But |
| 61 | to avoid a large number of wires in the user space to reach all of the GPIO |
| 62 | pad controls, each user GPIO pad has a corresponding local control block. The |
| 63 | control block holds the configuration data for the corresponding pad. This |
| 64 | configuration data is a mirror of the data in the memory-mapped region, and is |
| 65 | loaded by a "transfer" bit in another memory-mapped register. In addition to |
| 66 | all of the static control bits for the GPIO, each block contains a single bit |
| 67 | that specifies whether that pad is under the control of the user or the management |
| 68 | area. All pins are configured from the management area. However, the configuration |
| 69 | of static control bits leaves three dynamic signals: input, output, and output |
| 70 | enable. One set of these three signals is available to the user when the pad is |
| 71 | under user control. The other set of these three signals is available to the |
| 72 | management SoC. Again, to reduce wiring, only the two pads for JTAG and the |
| 73 | housekeeping SDO have all three pins under control of the SoC; the remaining |
| 74 | pads have a single wire to the management SoC which is either an input wire |
| 75 | or an output wire, depending on how the control signals for the pad are set. |
| 76 | |
| 77 | This setup gives a simplified view of the pad to the user: For digital |
| 78 | applications, the user can treat the pad as a simple bidirectional digital |
| 79 | pad with an output enable to switch between output and input functions. |
| 80 | The user can set the output enable line high or low for a static input or |
| 81 | output function. The user will also have access to the ESD-protected |
| 82 | pad connections for analog signals, and can connect to the VDDA domain |
| 83 | input digital signal if needed. |
| 84 | |
| 85 | Memory map: |
| 86 | ----------- |
| 87 | |
| 88 | The Caravel memory map is as follows: |
| 89 | |
| 90 | SRAM: 0000 0000 |
| 91 | |
| 92 | Flash: Config: 1000 0000 |
| 93 | |
| 94 | UART: Clock divider: 2000 0000 |
| 95 | Data: 2000 0004 |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 96 | Enable 2000 0008 |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 97 | |
| 98 | GPIO: Data: 2100 0000 |
| 99 | Output enable: 2100 0004 |
| 100 | Pullup 2100 0008 |
| 101 | Pulldown 2100 000c |
| 102 | |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 103 | Counter 1: Config: 2200 0000 |
| 104 | Value: 2200 0004 |
| 105 | Data: 2200 0008 |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 106 | |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 107 | Counter 2: Config: 2300 0000 |
| 108 | Value: 2300 0004 |
| 109 | Data: 2300 0008 |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 110 | |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 111 | SPI master: Config: 2400 0000 |
| 112 | Data: 2400 0004 |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 113 | |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 114 | Logic analyzer: Data 0: 2500 0000 |
| 115 | Data 1: 2500 0004 |
| 116 | Data 2: 2500 0008 |
| 117 | Data 3: 2500 000c |
| 118 | Enable 0: 2500 0010 |
| 119 | Enable 1: 2500 0014 |
| 120 | Enable 2: 2500 0018 |
| 121 | Enable 3: 2500 001c |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 122 | |
Tim Edwards | b86fc84 | 2020-10-13 17:11:54 -0400 | [diff] [blame] | 123 | Project ctrl: Data (L): 2600 0000 |
| 124 | Data (H): 2600 0004 |
| 125 | Transfer: 2600 0008 |
| 126 | I/O Config: 2600 000c |
| 127 | to 2600 009c |
| 128 | Power Config: 2600 00a0 |
| 129 | to 2600 0130 |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 130 | |
| 131 | Flash ctrl: Config: 2D00 0000 |
| 132 | |
| 133 | System: PLL out: 2F00 0000 |
| 134 | Trap out: 2F00 0004 |
| 135 | IRQ7 source: 2F00 0008 |
| 136 | |
| 137 | User area base: 3000 0000 |
| 138 | |
| 139 | Crossbar: QSPI control 8000 0000 |
| 140 | Storage area 9000 0000 |
| 141 | Any slave 1 a000 0000 |
| 142 | Any slave 2 b000 0000 |
| 143 | |
| 144 | Project I/O Control: |
| 145 | --------------------- |
| 146 | |
| 147 | Configuration bits per I/O (13 bits for each GPIO pad): |
| 148 | Global Default |
| 149 | Bits 12-10: digital mode (3 bits) 001 |
| 150 | Bit 9: voltage trip point select 0 |
| 151 | Bit 8: slow slew select 0 |
| 152 | Bit 7: analog bus polarity 0 |
| 153 | Bit 6: analog bus select 0 |
| 154 | Bit 5: analog bus enable 0 |
| 155 | Bit 4: IB mode select 0 |
| 156 | Bit 3: input disable 0 |
| 157 | Bit 2: holdover value 0 |
| 158 | Bit 1: output disable 1 |
| 159 | Bit 0: management control enable 1 |
| 160 | |
| 161 | Default I/O modes: |
| 162 | ------------------ |
| 163 | mprj_io[0] JTAG I/O 110 0 0 0 0 0 0 0 0 0 1 |
| 164 | mprj_io[1] SDO, housekeeping SPI 110 0 0 0 0 0 0 0 0 0 1 |
| 165 | all others: 001 0 0 0 0 0 0 0 0 1 1 |
| 166 | |
| 167 | |
| 168 | Standard GPIO output configuration: |
Tim Edwards | 89f0924 | 2020-10-05 15:17:34 -0400 | [diff] [blame] | 169 | mprj_io[6] Tx, UART 110 0 0 0 0 0 0 1 0 0 1 |
Tim Edwards | 44bab47 | 2020-10-04 22:09:54 -0400 | [diff] [blame] | 170 | |
| 171 | Standard GPIO input configuration: |
| 172 | mprj_io[*] 001 0 0 0 0 0 0 0 0 1 1 |
| 173 | |
| 174 | Standard GPIO input configuration with pullup: |
| 175 | mprj_io[*] 010 0 0 0 0 0 0 0 0 1 1 |
| 176 | |
| 177 | Standard GPIO input configuration with pulldown: |
| 178 | mprj_io[*] 011 0 0 0 0 0 0 0 0 1 1 |
| 179 | |
| 180 | Specifically: |
| 181 | JTAG and SDO are set to output. The output enable configure bit |
| 182 | is a don't-care, since the output enable line is directly controlled |
| 183 | by the module (JTAG or housekeeping SPI, respectively). |
| 184 | |
| 185 | All other I/O are set as input mode only, with output disabled. |
| 186 | |
| 187 | Tx is set to input like the others; before enabling the UART |
| 188 | from a program in flash, the I/O must be set to an output configuration. |
| 189 | |
| 190 | Note that the standard input configurations with pull-up and pull-down |
| 191 | require that "out" be set 1 or 0, respectively; since the I/O are |
| 192 | designed with minimal wiring, there is only one wire for input and |
| 193 | output, so the wire is used for input in these cases, and special |
| 194 | signal handling is done locally to set the value of "out" equal to |
| 195 | ~dm[0]. This is a (minor) restriction on the available I/O modes. |
| 196 | |
| 197 | Other possible modes are open-drain (for I2C), weak drive strength |
| 198 | output (5k up + down), and analog mode (digital disabled) |