| v {xschem version=2.9.7 file_version=1.1} |
| G {} |
| V {} |
| S {} |
| E {} |
| N -2340 -90 -2340 60 {lab=input_frequency} |
| N -2340 -90 -150 -90 {lab=input_frequency} |
| N -2250 -70 -150 -70 {lab=data_in[25:0]} |
| N -580 -60 -580 170 {lab=data_in[1]} |
| N -510 -60 -510 170 {lab=data_in[0]} |
| N -440 -40 -440 170 {lab=dither_select[1]} |
| N -370 -40 -370 170 {lab=dither_select[0]} |
| N 470 -90 470 90 {lab=output_frequency} |
| N 150 -90 470 -90 {lab=output_frequency} |
| N -2340 120 -2340 280 {lab=0} |
| N 360 280 470 280 {lab=0} |
| N 470 150 470 280 {lab=0} |
| N -580 230 -580 280 {lab=0} |
| N -510 230 -510 280 {lab=0} |
| N -440 230 -440 280 {lab=0} |
| N -370 230 -370 280 {lab=0} |
| N 150 -70 360 -70 {lab=dither_output} |
| N 360 -70 360 90 {lab=dither_output} |
| N 360 150 360 280 {lab=0} |
| N -430 -50 -150 -50 {lab=dither_select[1:0]} |
| N -720 -60 -720 170 {lab=data_in[3]} |
| N -650 -60 -650 170 {lab=data_in[2]} |
| N -720 230 -720 280 {lab=0} |
| N -650 230 -650 280 {lab=0} |
| N -860 -60 -860 170 {lab=data_in[5]} |
| N -790 -60 -790 170 {lab=data_in[4]} |
| N -860 230 -860 280 {lab=0} |
| N -790 230 -790 280 {lab=0} |
| N -1000 -60 -1000 170 {lab=data_in[7]} |
| N -930 -60 -930 170 {lab=data_in[6]} |
| N -1000 230 -1000 280 {lab=0} |
| N -930 230 -930 280 {lab=0} |
| N -1140 -60 -1140 170 {lab=data_in[9]} |
| N -1070 -60 -1070 170 {lab=data_in[8]} |
| N -1140 230 -1140 280 {lab=0} |
| N -1070 230 -1070 280 {lab=0} |
| N -1280 -60 -1280 170 {lab=data_in[11]} |
| N -1210 -60 -1210 170 {lab=data_in[10]} |
| N -1280 230 -1280 280 {lab=0} |
| N -1210 230 -1210 280 {lab=0} |
| N -1420 -60 -1420 170 {lab=data_in[13]} |
| N -1350 -60 -1350 170 {lab=data_in[12]} |
| N -1420 230 -1420 280 {lab=0} |
| N -1350 230 -1350 280 {lab=0} |
| N -1560 -60 -1560 170 {lab=data_in[15]} |
| N -1490 -60 -1490 170 {lab=data_in[14]} |
| N -1560 230 -1560 280 {lab=0} |
| N -1490 230 -1490 280 {lab=0} |
| N -1700 -60 -1700 170 {lab=data_in[17]} |
| N -1630 -60 -1630 170 {lab=data_in[16]} |
| N -1700 230 -1700 280 {lab=0} |
| N -1630 230 -1630 280 {lab=0} |
| N -1840 -60 -1840 170 {lab=data_in[19]} |
| N -1770 -60 -1770 170 {lab=data_in[18]} |
| N -1840 230 -1840 280 {lab=0} |
| N -1770 230 -1770 280 {lab=0} |
| N -1980 -60 -1980 170 {lab=data_in[21]} |
| N -1910 -60 -1910 170 {lab=data_in[20]} |
| N -1980 230 -1980 280 {lab=0} |
| N -1910 230 -1910 280 {lab=0} |
| N -2120 -60 -2120 170 {lab=data_in[23]} |
| N -2050 -60 -2050 170 {lab=data_in[22]} |
| N -2120 230 -2120 280 {lab=0} |
| N -2050 230 -2050 280 {lab=0} |
| N -2260 -60 -2260 170 {lab=data_in[25]} |
| N -2190 -60 -2190 170 {lab=data_in[24]} |
| N -2260 230 -2260 280 {lab=0} |
| N -2190 230 -2190 280 {lab=0} |
| N -650 280 -580 280 {lab=0} |
| N -580 280 -510 280 {lab=0} |
| N -510 280 -440 280 {lab=0} |
| N -440 280 -370 280 {lab=0} |
| N -370 280 360 280 {lab=0} |
| N -790 280 -720 280 {lab=0} |
| N -720 280 -650 280 {lab=0} |
| N -930 280 -860 280 {lab=0} |
| N -860 280 -790 280 {lab=0} |
| N -1070 280 -1000 280 {lab=0} |
| N -1000 280 -930 280 {lab=0} |
| N -1210 280 -1140 280 {lab=0} |
| N -1140 280 -1070 280 {lab=0} |
| N -1350 280 -1280 280 {lab=0} |
| N -1280 280 -1210 280 {lab=0} |
| N -1490 280 -1420 280 {lab=0} |
| N -1420 280 -1350 280 {lab=0} |
| N -1630 280 -1560 280 {lab=0} |
| N -1560 280 -1490 280 {lab=0} |
| N -1770 280 -1700 280 {lab=0} |
| N -1700 280 -1630 280 {lab=0} |
| N -1910 280 -1840 280 {lab=0} |
| N -1840 280 -1770 280 {lab=0} |
| N -2050 280 -1980 280 {lab=0} |
| N -1980 280 -1910 280 {lab=0} |
| N -2190 280 -2120 280 {lab=0} |
| N -2120 280 -2050 280 {lab=0} |
| N -2340 280 -2260 280 {lab=0} |
| N -2260 280 -2190 280 {lab=0} |
| N -190 -110 -150 -110 {lab=0} |
| N -190 -110 -190 280 {lab=0} |
| C {fractional_n_divider/fractional_n_divider.sym} 0 -80 0 0 {name=x1} |
| C {vsource.sym} -2340 90 0 0 {name=V1 value=3} |
| C {bus_connect_nolab.sym} -580 -60 0 0 {name=r1} |
| C {lab_wire.sym} -430 -70 0 1 {name=l1 sig_type=std_logic lab=data_in[25:0]} |
| C {vsource.sym} -370 200 0 0 {name=V2 value=dither_select_0} |
| C {vsource.sym} -440 200 0 0 {name=V3 value=1.8} |
| C {vsource.sym} -510 200 0 0 {name=V4 value=1.8} |
| C {vsource.sym} -580 200 0 0 {name=V5 value=1.8} |
| C {lab_wire.sym} -580 150 3 1 {name=l2 sig_type=std_logic lab=data_in[1]} |
| C {bus_connect_nolab.sym} -510 -60 0 0 {name=r2} |
| C {lab_wire.sym} -510 150 3 1 {name=l3 sig_type=std_logic lab=data_in[0]} |
| C {bus_connect_nolab.sym} -440 -40 0 0 {name=r3} |
| C {lab_wire.sym} -440 150 3 1 {name=l4 sig_type=std_logic lab=dither_select[1]} |
| C {bus_connect_nolab.sym} -370 -40 0 0 {name=r4} |
| C {lab_wire.sym} -370 150 3 1 {name=l5 sig_type=std_logic lab=dither_select[0]} |
| C {bus_connect_nolab.sym} -370 -40 0 0 {name=r5} |
| C {res.sym} 470 120 0 0 {name=R1 |
| value=1k |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {lab_wire.sym} 150 -90 0 1 {name=l6 sig_type=std_logic lab=output_frequency} |
| C {lab_wire.sym} -430 -90 0 1 {name=l7 sig_type=std_logic lab=input_frequency} |
| C {gnd.sym} -2340 280 0 0 {name=l8 lab=0} |
| C {code.sym} 350 -310 0 0 {name=STIMULI |
| tclcommand="xschem edit_vi_prop" |
| value=" |
| *.option PARHIER=LOCAL RUNLVL=6 post MODMONTE=1 warn maxwarns=400 |
| *.option ITL4=20000 ITL5=0 |
| * .option sampling_method = SRS |
| * .option method=gear |
| |
| * simple transistor model |
| .MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 |
| .MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 |
| |
| * load design and library |
| .include /home/tom/repositories/amsat_txrx_ic/design/fractional_n_divider/yosys/prim_cells_cmos.mod |
| |
| .temp 30 |
| .tran 1e-9 1e-6 uic |
| "} |
| C {res.sym} 360 120 0 0 {name=R2 |
| value=1k |
| footprint=1206 |
| device=resistor |
| m=1} |
| C {lab_wire.sym} -430 -50 0 1 {name=l9 sig_type=std_logic lab=dither_select[1:0]} |
| C {lab_wire.sym} 150 -70 0 1 {name=l10 sig_type=std_logic lab=dither_output} |
| C {bus_connect_nolab.sym} -720 -60 0 0 {name=r6} |
| C {vsource.sym} -650 200 0 0 {name=V6 value=1.8} |
| C {vsource.sym} -720 200 0 0 {name=V7 value=1.8} |
| C {lab_wire.sym} -720 150 3 1 {name=l12 sig_type=std_logic lab=data_in[3]} |
| C {bus_connect_nolab.sym} -650 -60 0 0 {name=r7} |
| C {lab_wire.sym} -650 150 3 1 {name=l13 sig_type=std_logic lab=data_in[2]} |
| C {bus_connect_nolab.sym} -860 -60 0 0 {name=r8} |
| C {vsource.sym} -790 200 0 0 {name=V8 value=1.8} |
| C {vsource.sym} -860 200 0 0 {name=V9 value=1.8} |
| C {lab_wire.sym} -860 150 3 1 {name=l15 sig_type=std_logic lab=data_in[5]} |
| C {bus_connect_nolab.sym} -790 -60 0 0 {name=r9} |
| C {lab_wire.sym} -790 150 3 1 {name=l16 sig_type=std_logic lab=data_in[4]} |
| C {bus_connect_nolab.sym} -1000 -60 0 0 {name=r10} |
| C {vsource.sym} -930 200 0 0 {name=V10 value=1.8} |
| C {vsource.sym} -1000 200 0 0 {name=V11 value=1.8} |
| C {lab_wire.sym} -1000 150 3 1 {name=l18 sig_type=std_logic lab=data_in[7]} |
| C {bus_connect_nolab.sym} -930 -60 0 0 {name=r11} |
| C {lab_wire.sym} -930 150 3 1 {name=l19 sig_type=std_logic lab=data_in[6]} |
| C {bus_connect_nolab.sym} -1140 -60 0 0 {name=r12} |
| C {vsource.sym} -1070 200 0 0 {name=V12 value=1.8} |
| C {vsource.sym} -1140 200 0 0 {name=V13 value=1.8} |
| C {lab_wire.sym} -1140 150 3 1 {name=l11 sig_type=std_logic lab=data_in[9]} |
| C {bus_connect_nolab.sym} -1070 -60 0 0 {name=r13} |
| C {lab_wire.sym} -1070 150 3 1 {name=l14 sig_type=std_logic lab=data_in[8]} |
| C {bus_connect_nolab.sym} -1280 -60 0 0 {name=r14} |
| C {vsource.sym} -1210 200 0 0 {name=V14 value=1.8} |
| C {vsource.sym} -1280 200 0 0 {name=V15 value=1.8} |
| C {lab_wire.sym} -1280 150 3 1 {name=l17 sig_type=std_logic lab=data_in[11]} |
| C {bus_connect_nolab.sym} -1210 -60 0 0 {name=r15} |
| C {lab_wire.sym} -1210 150 3 1 {name=l20 sig_type=std_logic lab=data_in[10]} |
| C {bus_connect_nolab.sym} -1420 -60 0 0 {name=r16} |
| C {vsource.sym} -1350 200 0 0 {name=V16 value=1.8} |
| C {vsource.sym} -1420 200 0 0 {name=V17 value=1.8} |
| C {lab_wire.sym} -1420 150 3 1 {name=l21 sig_type=std_logic lab=data_in[13]} |
| C {bus_connect_nolab.sym} -1350 -60 0 0 {name=r17} |
| C {lab_wire.sym} -1350 150 3 1 {name=l22 sig_type=std_logic lab=data_in[12]} |
| C {bus_connect_nolab.sym} -1560 -60 0 0 {name=r18} |
| C {vsource.sym} -1490 200 0 0 {name=V18 value=1.8} |
| C {vsource.sym} -1560 200 0 0 {name=V19 value=1.8} |
| C {lab_wire.sym} -1560 150 3 1 {name=l23 sig_type=std_logic lab=data_in[15]} |
| C {bus_connect_nolab.sym} -1490 -60 0 0 {name=r19} |
| C {lab_wire.sym} -1490 150 3 1 {name=l24 sig_type=std_logic lab=data_in[14]} |
| C {bus_connect_nolab.sym} -1700 -60 0 0 {name=r20} |
| C {vsource.sym} -1630 200 0 0 {name=V20 value=1.8} |
| C {vsource.sym} -1700 200 0 0 {name=V21 value=1.8} |
| C {lab_wire.sym} -1700 150 3 1 {name=l25 sig_type=std_logic lab=data_in[17]} |
| C {bus_connect_nolab.sym} -1630 -60 0 0 {name=r21} |
| C {lab_wire.sym} -1630 150 3 1 {name=l26 sig_type=std_logic lab=data_in[16]} |
| C {bus_connect_nolab.sym} -1840 -60 0 0 {name=r22} |
| C {vsource.sym} -1770 200 0 0 {name=V22 value=1.8} |
| C {vsource.sym} -1840 200 0 0 {name=V23 value=1.8} |
| C {lab_wire.sym} -1840 150 3 1 {name=l27 sig_type=std_logic lab=data_in[19]} |
| C {bus_connect_nolab.sym} -1770 -60 0 0 {name=r23} |
| C {lab_wire.sym} -1770 150 3 1 {name=l28 sig_type=std_logic lab=data_in[18]} |
| C {bus_connect_nolab.sym} -1980 -60 0 0 {name=r24} |
| C {vsource.sym} -1910 200 0 0 {name=V24 value=1.8} |
| C {vsource.sym} -1980 200 0 0 {name=V25 value=1.8} |
| C {lab_wire.sym} -1980 150 3 1 {name=l29 sig_type=std_logic lab=data_in[21]} |
| C {bus_connect_nolab.sym} -1910 -60 0 0 {name=r25} |
| C {lab_wire.sym} -1910 150 3 1 {name=l30 sig_type=std_logic lab=data_in[20]} |
| C {bus_connect_nolab.sym} -2120 -60 0 0 {name=r26} |
| C {vsource.sym} -2050 200 0 0 {name=V26 value=1.8} |
| C {vsource.sym} -2120 200 0 0 {name=V27 value=1.8} |
| C {lab_wire.sym} -2120 150 3 1 {name=l31 sig_type=std_logic lab=data_in[23]} |
| C {bus_connect_nolab.sym} -2050 -60 0 0 {name=r27} |
| C {lab_wire.sym} -2050 150 3 1 {name=l32 sig_type=std_logic lab=data_in[22]} |
| C {bus_connect_nolab.sym} -2260 -60 0 0 {name=r28} |
| C {vsource.sym} -2190 200 0 0 {name=V28 value=1.8} |
| C {vsource.sym} -2260 200 0 0 {name=V29 value=1.8} |
| C {lab_wire.sym} -2260 150 3 1 {name=l33 sig_type=std_logic lab=data_in[25]} |
| C {bus_connect_nolab.sym} -2190 -60 0 0 {name=r29} |
| C {lab_wire.sym} -2190 150 3 1 {name=l34 sig_type=std_logic lab=data_in[24]} |
