verilog/gl/user_project_wrapper.v

module user_project_wrapper(
            inout     vssd2,
            inout     vccd2,
            in        la_data_in[95],
            in        la_data_in[94],
            in        la_data_in[93],
            in        la_data_in[92],
            in        la_data_in[91],
            in        la_data_in[90],
            in        la_data_in[89],
            in        la_data_in[88],
            in        la_data_in[87],
            in        la_data_in[86],
            in        la_data_in[85],
            in        la_data_in[84],
            in        la_data_in[83],
            in        la_data_in[82],
            in        la_data_in[81],
            in        la_data_in[80],
            in        la_data_in[79],
            in        la_data_in[78],
            inout     analog_io[0],
            inout     analog_io[1],
            inout     analog_io[2],
            inout     analog_io[3],
            inout     analog_io[4],
            inout     analog_io[5],
            inout     analog_io[6],
            inout     analog_io[7],
            inout     analog_io[8],
            inout     analog_io[9],
            inout     analog_io[10],
            inout     analog_io[11],
            inout     analog_io[12],
            inout     analog_io[13],
            inout     analog_io[14],
            inout     analog_io[15],
            inout     analog_io[16],
            inout     analog_io[17],
            inout     analog_io[18],
            inout     analog_io[19],
            inout     analog_io[20],
            inout     analog_io[21]
    );

endmodule