| v { version=2.9.8 file_version=1.2} |
| G {} |
| K {} |
| V {} |
| S {} |
| E {} |
| N 640 -210 700 -210 { lab=#net1} |
| N 640 -190 700 -190 { lab=#net2} |
| N 900 -210 960 -210 { lab=#net3} |
| N 900 -190 960 -190 { lab=#net4} |
| N 1160 -210 1220 -210 { lab=#net5} |
| N 1160 -190 1220 -190 { lab=#net6} |
| N 1420 -210 1480 -210 { lab=#net7} |
| N 1420 -190 1480 -190 { lab=#net8} |
| N 1680 -210 1740 -210 { lab=#net9} |
| N 1680 -190 1740 -190 { lab=#net10} |
| N 1840 -550 1840 -260 { lab=vdd} |
| N 1580 -550 1840 -550 { lab=vdd} |
| N 210 -100 210 0 { lab=vss} |
| N 1580 0 1840 0 { lab=vss} |
| N 1840 -140 1840 0 { lab=vss} |
| N 210 -430 210 -350 { lab=#net11} |
| N 210 -550 210 -490 { lab=vdd} |
| N 540 -550 540 -430 { lab=vdd} |
| N 540 -320 540 -260 { lab=#net12} |
| N 540 -320 800 -320 { lab=#net12} |
| N 800 -320 800 -260 { lab=#net12} |
| N 540 -400 560 -400 { lab=vdd} |
| N 560 -550 560 -400 { lab=vdd} |
| N 210 -460 230 -460 { lab=vdd} |
| N 230 -550 230 -460 { lab=vdd} |
| N 100 -400 500 -400 { lab=en_n} |
| N 100 -460 100 -400 { lab=en_n} |
| N 100 -460 170 -460 { lab=en_n} |
| N 1060 -550 1060 -260 { lab=vdd} |
| N 1320 -550 1320 -260 { lab=vdd} |
| N 1580 -550 1580 -260 { lab=vdd} |
| N 1580 -140 1580 0 { lab=vss} |
| N 1320 -140 1320 0 { lab=vss} |
| N 1060 -140 1060 0 { lab=vss} |
| N 800 -140 800 0 { lab=vss} |
| N 540 -140 540 0 { lab=vss} |
| N 0 -550 210 -550 { lab=vdd} |
| N 0 0 210 0 { lab=vss} |
| N 0 -220 80 -220 { lab=ctl} |
| N 1940 -210 2100 -210 { lab=#net13} |
| N 0 -460 100 -460 { lab=en_n} |
| N 2080 -190 2100 -190 { lab=#net14} |
| N 2080 -190 2080 -140 { lab=#net14} |
| N 2080 -140 2300 -140 { lab=#net14} |
| N 2300 -190 2300 -140 { lab=#net14} |
| N 2280 -190 2300 -190 { lab=#net14} |
| N 2280 -210 2360 -210 { lab=#net15} |
| N 2340 -190 2360 -190 { lab=#net16} |
| N 2340 -190 2340 -140 { lab=#net16} |
| N 2340 -140 2560 -140 { lab=#net16} |
| N 2560 -190 2560 -140 { lab=#net16} |
| N 2540 -190 2560 -190 { lab=#net16} |
| N 360 -550 540 -550 { lab=vdd} |
| N 540 -370 540 -320 { lab=#net12} |
| N 540 -550 560 -550 { lab=vdd} |
| N 210 -550 230 -550 { lab=vdd} |
| N 560 -550 1060 -550 { lab=vdd} |
| N 1060 -550 1320 -550 { lab=vdd} |
| N 1320 -550 1580 -550 { lab=vdd} |
| N 1320 0 1580 0 { lab=vss} |
| N 1060 0 1320 0 { lab=vss} |
| N 800 0 1060 0 { lab=vss} |
| N 540 0 800 0 { lab=vss} |
| N 210 0 540 0 { lab=vss} |
| N 340 -210 440 -210 { lab=#net17} |
| N 340 -190 440 -190 { lab=#net18} |
| N 2020 -310 2040 -310 { lab=vss} |
| N 2040 -370 2040 -340 { lab=bias_cp} |
| N 2040 -370 2110 -370 { lab=bias_cp} |
| N 2110 -370 2110 -310 { lab=bias_cp} |
| N 2080 -310 2110 -310 { lab=bias_cp} |
| N 2040 -280 2040 -0 { lab=vss} |
| N 2020 0 2040 -0 { lab=vss} |
| N 2020 -310 2020 0 { lab=vss} |
| N 1850 -630 2040 -630 { lab=bias_cp} |
| N 2040 -630 2040 -370 { lab=bias_cp} |
| N 2580 -510 2580 -210 { lab=#net19} |
| N 940 -650 940 -580 { lab=vss} |
| N 640 -580 940 -580 { lab=vss} |
| N 640 -770 640 -580 { lab=vss} |
| N 940 -920 940 -750 { lab=vdd} |
| N 640 -920 940 -920 { lab=vdd} |
| N 360 -920 360 -550 { lab=vdd} |
| N 640 -920 640 -870 { lab=vdd} |
| N 790 -820 1170 -820 { lab=rf_p} |
| N 1090 -700 1170 -700 { lab=rf_n} |
| N 1840 -550 3070 -550 { lab=vdd} |
| N 3070 -550 3070 -280 { lab=vdd} |
| N 3070 0 3390 0 { lab=vss} |
| N 3390 -120 3390 0 { lab=vss} |
| N 3070 -160 3070 0 { lab=vss} |
| N 3500 -220 3570 -220 { lab=cp_out} |
| N 3390 -550 3390 -320 { lab=vdd} |
| N 3070 -550 3390 -550 { lab=vdd} |
| N 2540 -210 2580 -210 { lab=#net19} |
| N 2560 -230 2990 -230 { lab=ref_freq} |
| N 2560 -630 2560 -230 { lab=ref_freq} |
| N 2360 -630 2560 -630 { lab=ref_freq} |
| N 2960 -510 3570 -510 { lab=div_out} |
| N 2960 -430 3570 -430 { lab=dither_output} |
| N 2960 -360 3570 -360 { lab=output_frequency} |
| N 2750 -210 2990 -210 { lab=#net20} |
| N 2750 -360 2750 -210 { lab=#net20} |
| N 1840 -0 2020 0 { lab=vss} |
| N 230 -550 360 -550 { lab=vdd} |
| N 360 -920 640 -920 { lab=vdd} |
| N 2040 0 3070 0 { lab=vss} |
| N 1300 -900 1320 -900 { lab=vss} |
| N 1320 -960 1320 -930 { lab=bias_rf} |
| N 1320 -960 1390 -960 { lab=bias_rf} |
| N 1390 -960 1390 -900 { lab=bias_rf} |
| N 1360 -900 1390 -900 { lab=bias_rf} |
| N 1130 -1220 1320 -1220 { lab=bias_rf} |
| N 1320 -1220 1320 -960 { lab=bias_rf} |
| N 940 -580 1310 -580 { lab=vss} |
| N 1310 -580 1320 -580 { lab=vss} |
| N 1320 -870 1320 -580 { lab=vss} |
| N 1300 -900 1300 -580 { lab=vss} |
| N 2750 -360 2800 -360 { lab=#net20} |
| N 2750 -510 2800 -510 { lab=#net21} |
| N 2580 -510 2670 -510 { lab=#net19} |
| C {vco_2-4GHz/vco_2-4GHz.sym} 210 -220 0 0 {name=xvco} |
| C {divider_cml/divider_cml.sym} 540 -200 0 0 {name=x1} |
| C {divider_cml/divider_cml.sym} 800 -200 0 0 {name=x2} |
| C {divider_ff/divider_ff.sym} 1060 -200 0 0 {name=x3} |
| C {divider_ff/divider_ff.sym} 1320 -200 0 0 {name=x4} |
| C {divider_ff/divider_ff.sym} 1580 -200 0 0 {name=x5} |
| C {divider_ff/divider_ff.sym} 1840 -200 0 0 {name=x6} |
| C {sky130_fd_pr/pfet_01v8_lvt.sym} 190 -460 0 0 {name=M1 |
| L=0.35 |
| W=7 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=128 |
| model=pfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/pfet_01v8_lvt.sym} 520 -400 0 0 {name=M2 |
| L=0.35 |
| W=7 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=128 |
| model=pfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {iopin.sym} 0 -550 0 1 {name=p1 lab=vdd} |
| C {iopin.sym} 0 0 0 1 {name=p2 lab=vss} |
| C {ipin.sym} 0 -220 0 0 {name=p3 lab=ctl} |
| C {opin.sym} 3570 -510 0 0 {name=p4 lab=div_out} |
| C {ipin.sym} 0 -460 0 0 {name=p6 lab=en_n} |
| C {sky130_stdcells/dfxbp_1.sym} 2190 -200 0 0 {name=x7 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/dfxbp_1.sym} 2450 -200 0 0 {name=x8 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/bufinv_16.sym} 2840 -510 0 0 {name=x9 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {lab_pin.sym} 340 -310 0 1 {name=l2 sig_type=std_logic lab=ph1_p} |
| C {lab_pin.sym} 340 -290 0 1 {name=l3 sig_type=std_logic lab=ph1_n} |
| C {lab_pin.sym} 340 -160 0 1 {name=l6 sig_type=std_logic lab=ph4_p} |
| C {lab_pin.sym} 340 -140 0 1 {name=l7 sig_type=std_logic lab=ph4_n} |
| C {lab_pin.sym} 1940 -190 0 1 {name=l8 sig_type=std_logic lab=ff_nc} |
| C {sky130_stdcells/tapvpwrvgnd_1.sym} 1640 -900 0 0 {name=x10[2:1] VGND=vss VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {lab_pin.sym} 340 -260 0 1 {name=l1 sig_type=std_logic lab=ph2_p} |
| C {lab_pin.sym} 340 -240 0 1 {name=l4 sig_type=std_logic lab=ph2_n} |
| C {lab_wire.sym} 3150 -210 0 1 {name=l5 sig_type=std_logic lab=DOWN} |
| C {chargepump/chargepump.sym} 3390 -220 0 0 {name=x10[81:1] w_invp=3u l_invp=0.18u w_invn=1u l_invn=0.18u w_currn=1u l_currn=4u w_currp=3u l_currp=4u m_curr=20 w_swn=1u l_swn=0.18u w_swp=3u l_swp=0.18u m_sw=4} |
| C {lab_wire.sym} 3150 -230 0 1 {name=l10 sig_type=std_logic lab=UP} |
| C {phase_frequency_detector/phase_frequency_detector.sym} 3070 -220 0 0 {name=x11} |
| C {lab_wire.sym} 3280 -210 0 0 {name=l11 sig_type=std_logic lab=UP} |
| C {lab_wire.sym} 3280 -230 0 0 {name=l12 sig_type=std_logic lab=DOWN} |
| C {rf_driver/rf_driver.sym} 640 -820 0 0 {name=x12} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 2060 -310 0 1 {name=M3 |
| L=1 |
| W=1 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=200 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 2110 -310 0 1 {name=l13 sig_type=std_logic lab=bias_cp |
| } |
| C {ipin.sym} 1850 -630 0 0 {name=p5 lab=bias_cp} |
| C {rf_driver/rf_driver.sym} 940 -700 0 0 {name=x13} |
| C {lab_pin.sym} 490 -830 0 0 {name=l14 sig_type=std_logic lab=ph2_p} |
| C {lab_pin.sym} 490 -810 0 0 {name=l15 sig_type=std_logic lab=bias_rf} |
| C {lab_pin.sym} 790 -710 0 0 {name=l16 sig_type=std_logic lab=ph2_n} |
| C {lab_pin.sym} 790 -690 0 0 {name=l17 sig_type=std_logic lab=bias_rf} |
| C {lab_wire.sym} 640 -580 0 1 {name=l18 sig_type=std_logic lab=vss} |
| C {opin.sym} 1170 -820 0 0 {name=p7 lab=rf_p} |
| C {opin.sym} 1170 -700 0 0 {name=p8 lab=rf_n} |
| C {lab_wire.sym} 3330 -320 0 0 {name=l19 sig_type=std_logic lab=bias_cp |
| } |
| C {opin.sym} 3570 -220 0 0 {name=p9 lab=cp_out} |
| C {ipin.sym} 2360 -630 0 0 {name=p10 lab=ref_freq} |
| C {sky130_stdcells/bufinv_16.sym} 2920 -510 0 0 {name=x10[16:1] VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {opin.sym} 3570 -430 0 0 {name=p11 lab=dither_output} |
| C {sky130_stdcells/bufinv_16.sym} 2840 -430 0 0 {name=x10 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/bufinv_16.sym} 2920 -430 0 0 {name=x11[16:1] VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {opin.sym} 3570 -360 0 0 {name=p12 lab=output_frequency} |
| C {sky130_stdcells/bufinv_16.sym} 2840 -360 0 0 {name=x14 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {sky130_stdcells/bufinv_16.sym} 2920 -360 0 0 {name=x15[16:1] VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
| C {ipin.sym} 0 -740 0 0 {name=p13 lab=input_frequeny} |
| C {noconn.sym} 2800 -430 0 0 {name=l9} |
| C {noconn.sym} 0 -740 0 1 {name=l21} |
| C {sky130_fd_pr/nfet_01v8_lvt.sym} 1340 -900 0 1 {name=M4 |
| L=1 |
| W=1 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=200 |
| model=nfet_01v8_lvt |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 1390 -900 0 1 {name=l20 sig_type=std_logic lab=bias_rf |
| } |
| C {ipin.sym} 1130 -1220 0 0 {name=p14 lab=bias_rf} |
| C {sky130_stdcells/bufinv_16.sym} 2710 -510 0 0 {name=x15 VGND=vss VNB=vss VPB=vdd VPWR=vdd prefix=sky130_fd_sc_hd__ } |
