| v { version=2.9.8 file_version=1.2} |
| G {} |
| K {} |
| V {} |
| S {} |
| E {} |
| N 460 -260 480 -260 { lab=gnd} |
| N 480 -60 480 0 { lab=gnd} |
| N 460 0 480 0 { lab=gnd} |
| N 460 -30 460 0 { lab=gnd} |
| N 460 -60 480 -60 { lab=gnd} |
| N 460 -230 460 -90 { lab=#net1} |
| N 620 -260 640 -260 { lab=gnd} |
| N 640 -60 640 0 { lab=gnd} |
| N 620 0 640 0 { lab=gnd} |
| N 620 -30 620 0 { lab=gnd} |
| N 620 -60 640 -60 { lab=gnd} |
| N 620 -230 620 -90 { lab=#net2} |
| N 780 -260 800 -260 { lab=gnd} |
| N 800 -60 800 0 { lab=gnd} |
| N 780 0 800 0 { lab=gnd} |
| N 780 -30 780 0 { lab=gnd} |
| N 780 -60 800 -60 { lab=gnd} |
| N 780 -230 780 -90 { lab=#net3} |
| N 940 -260 960 -260 { lab=gnd} |
| N 960 -60 960 0 { lab=gnd} |
| N 940 0 960 0 { lab=gnd} |
| N 940 -30 940 0 { lab=gnd} |
| N 940 -60 960 -60 { lab=gnd} |
| N 940 -230 940 -90 { lab=#net4} |
| N 1100 -260 1120 -260 { lab=gnd} |
| N 1120 -60 1120 0 { lab=gnd} |
| N 1100 0 1120 0 { lab=gnd} |
| N 1100 -30 1100 0 { lab=gnd} |
| N 1100 -60 1120 -60 { lab=gnd} |
| N 1100 -230 1100 -90 { lab=#net5} |
| N 1040 -260 1060 -260 { lab=ctl[1]} |
| N 1040 -320 1040 -260 { lab=ctl[1]} |
| N 1000 -320 1040 -320 { lab=ctl[1]} |
| N 1040 -60 1060 -60 { lab=#net6} |
| N 1040 -120 1040 -60 { lab=#net6} |
| N 880 -120 1040 -120 { lab=#net6} |
| N 880 -260 900 -260 { lab=ctl[2]} |
| N 880 -320 880 -260 { lab=ctl[2]} |
| N 840 -320 880 -320 { lab=ctl[2]} |
| N 880 -60 900 -60 { lab=#net6} |
| N 880 -120 880 -60 { lab=#net6} |
| N 720 -120 880 -120 { lab=#net6} |
| N 720 -260 740 -260 { lab=ctl[3]} |
| N 720 -320 720 -260 { lab=ctl[3]} |
| N 680 -320 720 -320 { lab=ctl[3]} |
| N 720 -60 740 -60 { lab=#net6} |
| N 720 -120 720 -60 { lab=#net6} |
| N 560 -120 720 -120 { lab=#net6} |
| N 560 -260 580 -260 { lab=ctl[4]} |
| N 560 -320 560 -260 { lab=ctl[4]} |
| N 520 -320 560 -320 { lab=ctl[4]} |
| N 560 -60 580 -60 { lab=#net6} |
| N 560 -120 560 -60 { lab=#net6} |
| N 400 -120 560 -120 { lab=#net6} |
| N 400 -260 420 -260 { lab=ctl[5]} |
| N 400 -320 400 -260 { lab=ctl[5]} |
| N 360 -320 400 -320 { lab=ctl[5]} |
| N 400 -60 420 -60 { lab=#net6} |
| N 400 -120 400 -60 { lab=#net6} |
| N 180 -120 400 -120 { lab=#net6} |
| N 480 0 620 0 { lab=gnd} |
| N 640 0 780 0 { lab=gnd} |
| N 800 0 940 0 { lab=gnd} |
| N 960 0 1100 0 { lab=gnd} |
| N 30 -60 50 -60 { lab=gnd} |
| N 30 -60 30 0 { lab=gnd} |
| N 330 0 460 0 { lab=gnd} |
| N 50 -30 50 0 { lab=gnd} |
| N 50 -120 50 -90 { lab=#net6} |
| N 480 -260 480 -60 { lab=gnd} |
| N 640 -260 640 -60 { lab=gnd} |
| N 800 -260 800 -60 { lab=gnd} |
| N 960 -260 960 -60 { lab=gnd} |
| N 1120 -260 1120 -60 { lab=gnd} |
| N 30 0 50 0 { lab=gnd} |
| N 460 -380 460 -290 { lab=out} |
| N 1100 -380 1260 -380 { lab=out} |
| N 620 -380 620 -290 { lab=out} |
| N 780 -380 780 -290 { lab=out} |
| N 940 -380 940 -290 { lab=out} |
| N 1100 -380 1100 -290 { lab=out} |
| N 30 -380 50 -380 { lab=in} |
| N 330 -60 330 0 { lab=gnd} |
| N 310 0 330 0 { lab=gnd} |
| N 310 -30 310 0 { lab=gnd} |
| N 310 -60 330 -60 { lab=gnd} |
| N 180 -60 270 -60 { lab=#net6} |
| N 180 -120 180 -60 { lab=#net6} |
| N 50 -120 180 -120 { lab=#net6} |
| N 90 -60 180 -60 { lab=#net6} |
| N 50 0 310 0 { lab=gnd} |
| N 310 -380 460 -380 { lab=out} |
| N 460 -380 620 -380 { lab=out} |
| N 620 -380 780 -380 { lab=out} |
| N 780 -380 940 -380 { lab=out} |
| N 940 -380 1100 -380 { lab=out} |
| N 1260 -260 1280 -260 { lab=gnd} |
| N 1280 -60 1280 0 { lab=gnd} |
| N 1260 0 1280 0 { lab=gnd} |
| N 1260 -30 1260 0 { lab=gnd} |
| N 1260 -60 1280 -60 { lab=gnd} |
| N 1200 -260 1220 -260 { lab=ctl[0]} |
| N 1200 -320 1200 -260 { lab=ctl[0]} |
| N 1160 -320 1200 -320 { lab=ctl[0]} |
| N 1200 -60 1220 -60 { lab=#net6} |
| N 1200 -120 1200 -60 { lab=#net6} |
| N 1040 -120 1200 -120 { lab=#net6} |
| N 1280 -170 1280 -60 { lab=gnd} |
| N 1260 -380 1260 -290 { lab=out} |
| N 1120 0 1260 0 { lab=gnd} |
| N 1260 -230 1260 -200 { lab=#net7} |
| N 1260 -140 1260 -90 { lab=#net8} |
| N 1260 -170 1280 -170 { lab=gnd} |
| N 1200 -170 1200 -120 { lab=#net6} |
| N 1200 -170 1220 -170 { lab=#net6} |
| N 1260 -460 1260 -380 { lab=out} |
| N 1260 -460 1280 -460 { lab=out} |
| N 50 -240 50 -120 { lab=#net6} |
| N 50 -380 50 -300 { lab=in} |
| N 310 -240 310 -90 { lab=#net9} |
| N 310 -380 310 -300 { lab=out} |
| N 250 -270 270 -270 { lab=vdd} |
| N 250 -330 250 -270 { lab=vdd} |
| N 210 -330 250 -330 { lab=vdd} |
| N 150 -330 150 -270 { lab=vdd} |
| N 110 -330 150 -330 { lab=vdd} |
| N 90 -270 150 -270 { lab=vdd} |
| N 1280 -260 1280 -170 { lab=gnd} |
| N 30 -270 50 -270 { lab=gnd} |
| N 30 -270 30 -60 { lab=gnd} |
| N 0 0 30 0 { lab=gnd} |
| N 0 -380 30 -380 { lab=in} |
| N 310 -270 330 -270 { lab=gnd} |
| N 330 -270 330 -60 { lab=gnd} |
| C {sky130_fd_pr/nfet_01v8.sym} 600 -60 0 0 {name=Mcurr_4[2:1] |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=4 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 760 -60 0 0 {name=Mcurr_3[2:1] |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=2 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 920 -60 0 0 {name=Mcurr_2[2:1] |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 1080 -60 0 0 {name=Mcurr_1 |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 600 -260 0 0 {name=Msw_4[2:1] |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=4 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 760 -260 0 0 {name=Msw_3[2:1] |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=2 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 920 -260 0 0 {name=Msw_2[2:1] |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 1080 -260 0 0 {name=Msw_1 |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 440 -60 0 0 {name=Mcurr_5[2:1] |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=8 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 440 -260 0 0 {name=Msw_5[2:1] |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=8 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 70 -60 0 1 {name=Mcurr_ref |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=16 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {ipin.sym} 0 -440 0 0 {name=p1 lab=ctl[5:0]} |
| C {ipin.sym} 0 0 0 0 {name=p2 lab=gnd} |
| C {ipin.sym} 0 -380 0 0 {name=p3 lab=in} |
| C {opin.sym} 1280 -460 0 0 {name=p4 lab=out} |
| C {lab_wire.sym} 360 -320 0 1 {name=l1 sig_type=std_logic lab=ctl[5]} |
| C {lab_wire.sym} 520 -320 0 1 {name=l2 sig_type=std_logic lab=ctl[4]} |
| C {lab_wire.sym} 680 -320 0 1 {name=l3 sig_type=std_logic lab=ctl[3]} |
| C {lab_wire.sym} 840 -320 0 1 {name=l4 sig_type=std_logic lab=ctl[2]} |
| C {lab_wire.sym} 1000 -320 0 1 {name=l5 sig_type=std_logic lab=ctl[1]} |
| C {sky130_fd_pr/nfet_01v8.sym} 290 -60 0 0 {name=Mcurr_base[2:1] |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=24 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 1240 -60 0 0 {name=Mcurr_0a |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 1240 -260 0 0 {name=Msw_0 |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 1160 -320 0 1 {name=l6 sig_type=std_logic lab=ctl[0]} |
| C {sky130_fd_pr/nfet_01v8.sym} 1240 -170 0 0 {name=Mcurr_0b |
| L=20 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=1 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 290 -270 0 0 {name=Msw_base[2:1] |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=24 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {sky130_fd_pr/nfet_01v8.sym} 70 -270 0 1 {name=Msw_ref |
| L=0.15 |
| W=0.42 |
| ad="'W * 0.29'" pd="'2 * (W + 0.29)'" |
| as="'W * 0.29'" ps="'2 * (W + 0.29)'" |
| nrd="'0.29 / W'" nrs="'0.29 / W'" |
| sa=0 sb=0 sd=0 |
| nf=1 mult=16 |
| model=nfet_01v8 |
| spiceprefix=X |
| } |
| C {lab_wire.sym} 210 -330 0 1 {name=l7 sig_type=std_logic lab=vdd} |
| C {iopin.sym} 0 -480 0 1 {name=p5 lab=vdd} |
| C {lab_wire.sym} 110 -330 0 1 {name=l8 sig_type=std_logic lab=vdd} |