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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-016 / 7a8cbb17d982936bcf08ac4faabe7cbe6eda46be
commit7a8cbb17d982936bcf08ac4faabe7cbe6eda46be[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Mon Oct 12 11:32:11 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Mon Oct 12 11:32:11 2020 -0400
treeaa0db5554e024223e07a063b304b52251d6f2514
parent53d9218c9e1613c4616ca9d4f71195778520e66d [diff]
Added a secondary clock output, going to the user area, that is derived
from the 90-degree phase PLL clock and run on an independent divider.
The use of the 90-degree phase clock is mostly to balance the output
loads.
5 files changed
tree: aa0db5554e024223e07a063b304b52251d6f2514
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.