Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index f0505a7..fd94d2c 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -117,6 +117,7 @@
wire [31:0] value_cur_plus; // Next value, on up-count
wire [31:0] value_cur_minus; // Next value, on down-count
wire is_offset;
+wire loc_enable;
reg enable; // Enable (start) the counter/timer
reg lastenable; // Previous state of enable (catch rising/falling edge)
@@ -307,3 +308,4 @@
end
endmodule
+`default_nettype wire
