Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 42ecf45..95ca327 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1,4 +1,4 @@
-`default_nettype none
+// `default_nettype none
/*--------------------------------------------------------------*/
/* caravel, a project harness for the Google/SkyWater sky130 */
/* fabrication process and open source PDK */
@@ -157,6 +157,7 @@
wire [`MPRJ_IO_PADS-1:0] user_io_oeb;
wire [`MPRJ_IO_PADS-1:0] user_io_in;
wire [`MPRJ_IO_PADS-1:0] user_io_out;
+ wire [`MPRJ_IO_PADS-8:0] user_analog_io;
/* Padframe control signals */
wire [`MPRJ_IO_PADS-1:0] gpio_serial_link;
@@ -186,16 +187,31 @@
wire [`MPRJ_IO_PADS-3:0] mgmt_io_nc3; /* no-connects */
wire [1:0] mgmt_io_nc2; /* no-connects */
+ wire clock_core;
+
// Power-on-reset signal. The reset pad generates the sense-inverted
// reset at 3.3V. The 1.8V signal and the inverted 1.8V signal are
// derived.
wire porb_h;
wire porb_l;
+ wire por_l;
wire rstb_h;
wire rstb_l;
+ wire flash_clk_core, flash_csb_core;
+ wire flash_clk_oeb_core, flash_csb_oeb_core;
+ wire flash_clk_ieb_core, flash_csb_ieb_core;
+ wire flash_io0_oeb_core, flash_io1_oeb_core;
+ wire flash_io2_oeb_core, flash_io3_oeb_core;
+ wire flash_io0_ieb_core, flash_io1_ieb_core;
+ wire flash_io2_ieb_core, flash_io3_ieb_core;
+ wire flash_io0_do_core, flash_io1_do_core;
+ wire flash_io2_do_core, flash_io3_do_core;
+ wire flash_io0_di_core, flash_io1_di_core;
+ wire flash_io2_di_core, flash_io3_di_core;
+
// To be considered: Master hold signal on all user pads (?)
// For now, set holdh_n to 1 (NOTE: This is in the 3.3V domain)
// and setting enh to porb_h.
@@ -229,6 +245,7 @@
.flash_io1(flash_io1),
// SoC Core Interface
.porb_h(porb_h),
+ .por(por_l),
.resetb_core_h(rstb_h),
.clock_core(clock_core),
.gpio_out_core(gpio_out_core),
@@ -251,7 +268,6 @@
.flash_io1_do_core(flash_io1_do_core),
.flash_io0_di_core(flash_io0_di_core),
.flash_io1_di_core(flash_io1_di_core),
- .por(por_l),
.mprj_io_in(mprj_io_in),
.mprj_io_out(mprj_io_out),
.mprj_io_oeb(mprj_io_oeb),
@@ -265,7 +281,8 @@
.mprj_io_analog_en(mprj_io_analog_en),
.mprj_io_analog_sel(mprj_io_analog_sel),
.mprj_io_analog_pol(mprj_io_analog_pol),
- .mprj_io_dm(mprj_io_dm)
+ .mprj_io_dm(mprj_io_dm),
+ .mprj_analog_io(user_analog_io)
);
// SoC core
@@ -489,6 +506,7 @@
.io_in (user_io_in),
.io_out(user_io_out),
.io_oeb(user_io_oeb),
+ .analog_io(user_analog_io),
// Independent clock
.user_clock2(mprj_clock2)
);
@@ -607,8 +625,11 @@
// Power-on-reset circuit
simple_por por (
.vdd3v3(vddio),
+ .vdd1v8(vccd),
.vss(vssio),
- .porb_h(porb_h)
+ .porb_h(porb_h),
+ .porb_l(porb_l),
+ .por_l(por_l)
);
// XRES (chip input pin reset) reset level converter
@@ -640,3 +661,4 @@
);
endmodule
+// `default_nettype wire
diff --git a/verilog/rtl/caravel_clocking.v b/verilog/rtl/caravel_clocking.v
index aa49d6f..4abdae9 100644
--- a/verilog/rtl/caravel_clocking.v
+++ b/verilog/rtl/caravel_clocking.v
@@ -20,6 +20,9 @@
);
wire pll_clk_sel;
+ wire pll_clk_divided;
+ wire pll_clk90_divided;
+ wire core_ext_clk;
reg use_pll_first;
reg use_pll_second;
reg ext_clk_syncd_pre;
@@ -90,3 +93,4 @@
assign resetb_sync = ~(reset_delay[0] | ext_reset);
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 2a2bea7..b8ba7f1 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -1,4 +1,4 @@
-`default_nettype none
+// `default_nettype none
module chip_io(
// Package Pins
inout vddio, // Common padframe/ESD supply
@@ -25,6 +25,7 @@
inout flash_io1,
// Chip Core Interface
input porb_h,
+ input por,
output resetb_core_h,
output clock_core,
input gpio_out_core,
@@ -47,8 +48,6 @@
input flash_io1_do_core,
output flash_io0_di_core,
output flash_io1_di_core,
- // porbh, returned to the I/O level shifted down and inverted
- input por,
// User project IOs
inout [`MPRJ_IO_PADS-1:0] mprj_io,
input [`MPRJ_IO_PADS-1:0] mprj_io_out,
@@ -64,7 +63,10 @@
input [`MPRJ_IO_PADS-1:0] mprj_io_analog_sel,
input [`MPRJ_IO_PADS-1:0] mprj_io_analog_pol,
input [`MPRJ_IO_PADS*3-1:0] mprj_io_dm,
- output [`MPRJ_IO_PADS-1:0] mprj_io_in
+ output [`MPRJ_IO_PADS-1:0] mprj_io_in,
+ // User project direct access to gpio pad connections for analog
+ // (all but the lowest-numbered 7 pads)
+ inout [`MPRJ_IO_PADS-8:0] mprj_analog_io
);
wire analog_a, analog_b;
@@ -271,7 +273,6 @@
.analog_a(analog_a),
.analog_b(analog_b),
.porb_h(porb_h),
- .por(por),
.io(mprj_io),
.io_out(mprj_io_out),
.oeb(mprj_io_oeb),
@@ -286,7 +287,9 @@
.analog_sel(mprj_io_analog_sel),
.analog_pol(mprj_io_analog_pol),
.dm(mprj_io_dm),
- .io_in(mprj_io_in)
+ .io_in(mprj_io_in),
+ .analog_io(mprj_analog_io)
);
endmodule
+// `default_nettype wire
diff --git a/verilog/rtl/clock_div.v b/verilog/rtl/clock_div.v
index 54bf194..4b698a4 100644
--- a/verilog/rtl/clock_div.v
+++ b/verilog/rtl/clock_div.v
@@ -1,5 +1,5 @@
-`default_nettype none
/* Integer-N clock divider */
+`default_nettype none
module clock_div #(
parameter SIZE = 3 // Number of bits for the divider value
@@ -194,3 +194,4 @@
end
endmodule //even
+`default_nettype wire
diff --git a/verilog/rtl/convert_gpio_sigs.v b/verilog/rtl/convert_gpio_sigs.v
index c7d53f3..89ee8b5 100644
--- a/verilog/rtl/convert_gpio_sigs.v
+++ b/verilog/rtl/convert_gpio_sigs.v
@@ -33,4 +33,4 @@
assign gpio_mode0_pad = gpio_outenb;
endmodule
-
+`default_nettype wire
diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v
index b66ee6b..2f1ea58 100755
--- a/verilog/rtl/counter_timer_high.v
+++ b/verilog/rtl/counter_timer_high.v
@@ -276,3 +276,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index f0505a7..fd94d2c 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -117,6 +117,7 @@
wire [31:0] value_cur_plus; // Next value, on up-count
wire [31:0] value_cur_minus; // Next value, on down-count
wire is_offset;
+wire loc_enable;
reg enable; // Enable (start) the counter/timer
reg lastenable; // Previous state of enable (catch rising/falling edge)
@@ -307,3 +308,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index dac708a..2f3fc2a 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -53,3 +53,4 @@
);
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index 1437c93..0cd59b0 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -118,3 +118,4 @@
end
endmodule // digital_pll_controller
+`default_nettype wire
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index f9764ed..8ccdfdd 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -125,6 +125,7 @@
wire user_gpio_in;
wire gpio_in_unbuf;
+ wire gpio_logic1;
/* Serial shift for the above (latched) values */
reg [PAD_CTRL_BITS-1:0] shift_register;
@@ -232,3 +233,4 @@
);
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 77d1f3a..70bf65e 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -138,3 +138,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/housekeeping_spi.v b/verilog/rtl/housekeeping_spi.v
index bd09dcb..7931d38 100644
--- a/verilog/rtl/housekeeping_spi.v
+++ b/verilog/rtl/housekeeping_spi.v
@@ -476,3 +476,4 @@
end // always @ SCK
endmodule // housekeeping_spi_slave
+`default_nettype wire
diff --git a/verilog/rtl/la_wb.v b/verilog/rtl/la_wb.v
index 9b963af..07dfc90 100644
--- a/verilog/rtl/la_wb.v
+++ b/verilog/rtl/la_wb.v
@@ -202,4 +202,5 @@
end
end
-endmodule
\ No newline at end of file
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 55f9eef..67e1f44 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -123,3 +123,4 @@
`endif
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index 21e36dc..2f8b45d 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -85,15 +85,19 @@
wire pll_clk, pll_clk90;
wire ext_reset;
wire hk_connect;
+ wire trap;
+ wire irq_spi;
// JTAG (to be implemented)
wire jtag_out;
wire jtag_out_pre = 1'b0;
wire jtag_outenb = 1'b1;
+ wire jtag_oenb_state;
// SDO
wire sdo_out;
wire sdo_out_pre;
+ wire sdo_oenb_state;
// Housekeeping SPI vectors
wire [4:0] spi_pll_div;
@@ -124,6 +128,18 @@
.resetb_sync(core_rstn)
);
+ // These wires are defined in the SoC but are not being used because
+ // the SoC flash is reduced to a 2-pin I/O
+ wire flash_io2_oeb, flash_io3_oeb;
+ wire flash_io2_ieb, flash_io3_ieb;
+ wire flash_io2_di, flash_io3_di;
+ wire flash_io2_do, flash_io3_do;
+
+ wire pass_thru_mgmt_sdo, pass_thru_mgmt_csb;
+ wire pass_thru_mgmt_sck, pass_thru_mgmt_sdi;
+ wire pass_thru_reset;
+ wire spi_pll_ena, spi_pll_dco_ena;
+
// The following functions are connected to specific user project
// area pins, when under control of the management area (during
// startup, and when not otherwise programmed for the user project).
@@ -289,3 +305,4 @@
);
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index c5c79f3..ad25704 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -302,7 +302,7 @@
.VNB(vssd),
`endif
.A(mprj_vdd_logic1),
- .X(user_vdd_powergood)
+ .X(user1_vdd_powergood)
);
sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
@@ -316,3 +316,4 @@
.X(user2_vdd_powergood)
);
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 8d3e1f7..17a73f4 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -321,6 +321,10 @@
wire irq_spi_master;
wire irq_counter_timer0;
wire irq_counter_timer1;
+ wire ser_tx;
+
+ wire wb_clk_i;
+ wire wb_rst_i;
assign irq_stall = 0;
assign irq_7 = (irq_7_inputsrc == 1'b1) ? mgmt_in_data[7] : 1'b0;
@@ -352,6 +356,7 @@
wire cpu_stb_o;
wire [31:0] cpu_dat_o;
wire cpu_ack_i;
+ wire mem_instr;
picorv32_wb #(
.STACKADDR(STACKADDR),
@@ -845,3 +850,4 @@
assign rdata1 = regs[raddr1[4:0]];
assign rdata2 = regs[raddr2[4:0]];
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 6b17fe2..b31c23a 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -124,6 +124,7 @@
wire pwr_data_sel;
wire xfer_sel;
wire busy;
+ wire selected;
wire [`MPRJ_IO_PADS-1:0] io_ctrl_sel;
reg [31:0] iomem_rdata_pre;
@@ -365,3 +366,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/mprj_io.v b/verilog/rtl/mprj_io.v
index 11a7dc3..d8cb449 100644
--- a/verilog/rtl/mprj_io.v
+++ b/verilog/rtl/mprj_io.v
@@ -1,4 +1,4 @@
-`default_nettype none
+// `default_nettype none
module mprj_io #(
parameter AREA1PADS = 18 // Highest numbered pad in area 1
) (
@@ -23,7 +23,6 @@
input analog_a,
input analog_b,
input porb_h,
- input por,
inout [`MPRJ_IO_PADS-1:0] io,
input [`MPRJ_IO_PADS-1:0] io_out,
input [`MPRJ_IO_PADS-1:0] oeb,
@@ -38,10 +37,12 @@
input [`MPRJ_IO_PADS-1:0] analog_sel,
input [`MPRJ_IO_PADS-1:0] analog_pol,
input [`MPRJ_IO_PADS*3-1:0] dm,
- output [`MPRJ_IO_PADS-1:0] io_in
+ output [`MPRJ_IO_PADS-1:0] io_in,
+ inout [`MPRJ_IO_PADS-8:0] analog_io
);
wire [`MPRJ_IO_PADS-1:0] loop1_io;
+ wire [6:0] no_connect;
sky130_ef_io__gpiov2_pad area1_io_pad [AREA1PADS - 1:0] (
`USER1_ABUTMENT_PINS
@@ -66,7 +67,7 @@
.ANALOG_POL(analog_pol[AREA1PADS - 1:0]),
.DM(dm[AREA1PADS*3 - 1:0]),
.PAD_A_NOESD_H(),
- .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_0_H({analog_io[AREA1PADS - 8:0], no_connect}),
.PAD_A_ESD_1_H(),
.IN(io_in[AREA1PADS - 1:0]),
.IN_H(),
@@ -97,7 +98,7 @@
.ANALOG_POL(analog_pol[`MPRJ_IO_PADS - 1:AREA1PADS]),
.DM(dm[`MPRJ_IO_PADS*3 - 1:AREA1PADS*3]),
.PAD_A_NOESD_H(),
- .PAD_A_ESD_0_H(),
+ .PAD_A_ESD_0_H(analog_io[`MPRJ_IO_PADS - 8:AREA1PADS - 7]),
.PAD_A_ESD_1_H(),
.IN(io_in[`MPRJ_IO_PADS - 1:AREA1PADS]),
.IN_H(),
@@ -106,3 +107,4 @@
);
endmodule
+// `default_nettype wire
diff --git a/verilog/rtl/pads.v b/verilog/rtl/pads.v
index a423124..d56999a 100644
--- a/verilog/rtl/pads.v
+++ b/verilog/rtl/pads.v
@@ -1,4 +1,4 @@
-`default_nettype none
+// `default_nettype none
`ifndef TOP_ROUTING
`define USER1_ABUTMENT_PINS \
.AMUXBUS_A(analog_a),\
@@ -153,3 +153,4 @@
.TIE_HI_ESD(), \
.TIE_LO_ESD(loop_``X) )
+// `default_nettype wire
diff --git a/verilog/rtl/picorv32.v b/verilog/rtl/picorv32.v
index 60dea84..f6e9203 100644
--- a/verilog/rtl/picorv32.v
+++ b/verilog/rtl/picorv32.v
@@ -24,7 +24,6 @@
/* verilator lint_off CASEINCOMPLETE */
`timescale 1 ns / 1 ps
-// `default_nettype none
// `define DEBUGNETS
// `define DEBUGREGS
// `define DEBUGASM
@@ -3043,3 +3042,4 @@
end
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 719da6e..324c2c7 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -9,7 +9,7 @@
input [1:0] trim;
output out;
- wire d0, d1, d2;
+ wire d0, d1, d2, ts;
sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
.A(in),
@@ -232,3 +232,4 @@
`endif // !FUNCTIONAL
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/simple_por.v b/verilog/rtl/simple_por.v
index f6bda39..6307e79 100644
--- a/verilog/rtl/simple_por.v
+++ b/verilog/rtl/simple_por.v
@@ -69,5 +69,6 @@
// since this is behavioral anyway, but this should be
// replaced by a proper inverter
- assign por_l = porb_l;
+ assign por_l = ~porb_l;
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index 8a81954..4576925 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -102,6 +102,7 @@
wire [1:0] reg_cfg_we = (simple_spi_master_reg_cfg_sel) ?
(wb_sel_i[1:0] & {2{wb_we_i}}): 2'b00;
wire reg_dat_we = (simple_spi_master_reg_dat_sel) ? (wb_sel_i[0] & wb_we_i): 1'b0;
+ wire reg_dat_wait;
wire [31:0] mem_wdata = wb_dat_i;
wire reg_dat_re = simple_spi_master_reg_dat_sel && !wb_sel_i && ~wb_we_i;
@@ -388,3 +389,4 @@
end // always
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 66e1915..4fe9f0c 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -220,3 +220,4 @@
end
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/spimemio.v b/verilog/rtl/spimemio.v
index a982981..dc37126 100644
--- a/verilog/rtl/spimemio.v
+++ b/verilog/rtl/spimemio.v
@@ -740,3 +740,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index cf0489d..afbfa12 100644
--- a/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -115,3 +115,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/storage.v b/verilog/rtl/storage.v
index fe0eae7..a290525 100644
--- a/verilog/rtl/storage.v
+++ b/verilog/rtl/storage.v
@@ -42,4 +42,5 @@
.dout0(mgmt_rdata[63:32])
);
-endmodule
\ No newline at end of file
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/storage_bridge_wb.v b/verilog/rtl/storage_bridge_wb.v
index ddce210..bf70052 100644
--- a/verilog/rtl/storage_bridge_wb.v
+++ b/verilog/rtl/storage_bridge_wb.v
@@ -93,4 +93,5 @@
assign mgmt_addr_ro = wb_adr_i[9:2];
assign wb_ro_dat_o = mgmt_rdata_ro;
-endmodule
\ No newline at end of file
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/sysctrl.v b/verilog/rtl/sysctrl.v
index 8a0ac42..7f11f75 100644
--- a/verilog/rtl/sysctrl.v
+++ b/verilog/rtl/sysctrl.v
@@ -111,6 +111,11 @@
wire usr1_vdd_pwrgood;
wire usr2_vdd_pwrgood;
+ wire pwrgood_sel;
+ wire clk_out_sel;
+ wire trap_out_sel;
+ wire irq_sel;
+
assign pwrgood_sel = (iomem_addr[7:0] == PWRGOOD);
assign clk_out_sel = (iomem_addr[7:0] == CLK_OUT);
assign trap_out_sel = (iomem_addr[7:0] == TRAP_OUT);
@@ -157,3 +162,4 @@
end
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/user_id_programming.v b/verilog/rtl/user_id_programming.v
index 421e663..526a802 100644
--- a/verilog/rtl/user_id_programming.v
+++ b/verilog/rtl/user_id_programming.v
@@ -37,3 +37,4 @@
endgenerate
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 6c1c117..5546130 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -152,3 +152,4 @@
endgenerate
endmodule
+`default_nettype wire
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 549353e..b5460f5 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -48,6 +48,12 @@
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
+ // Analog (direct connection to GPIO pad---use with caution)
+ // Note that analog I/O is not available on the 7 lowest-numbered
+ // GPIO pads, and so the analog_io indexing is offset from the
+ // GPIO indexing by 7.
+ inout [`MPRJ_IO_PADS-8:0] analog_io,
+
// Independent clock (on independent integer divider)
input user_clock2
);
@@ -96,3 +102,4 @@
);
endmodule // user_project_wrapper
+`default_nettype wire
diff --git a/verilog/rtl/wb_intercon.v b/verilog/rtl/wb_intercon.v
index 7d9ddb1..6c3ab52 100644
--- a/verilog/rtl/wb_intercon.v
+++ b/verilog/rtl/wb_intercon.v
@@ -56,3 +56,4 @@
end
endmodule
+`default_nettype wire
