commit 2c852fbf5984316620f6089a78845e8926188886
author R. Timothy Edwards <tim@opencircuitdesign.com> Wed Nov 04 12:10:35 2020 -0500
committer GitHub <noreply@github.com> Wed Nov 04 12:10:35 2020 -0500
tree 70af1e4519d7c573bec2bda2732ddac736220e7d
parent db745b7977732da03851fcd7612d2e4ec9f63a50
parent cd4cff7247745cbfba442ae715685276b68c45a8

Merge pull request #30 from Manarabdelaty/wb_mprj_port

Connect WB MI A port outputs to the wb bus

verilog/rtl/mgmt_soc.v

diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 8235436..cf0793d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -681,6 +681,13 @@
         .la_oen(la_oen)
     );
     
+    // User project WB MI A port
+    assign mprj_cyc_o = cpu_cyc_o;
+    assign mprj_we_o  = cpu_we_o;
+    assign mprj_sel_o = cpu_sel_o;
+    assign mprj_adr_o = cpu_adr_o;
+    assign mprj_dat_o = cpu_dat_o;
+
     // WB Slave User Project Control
     wire mprj_ctrl_stb_i;
     wire mprj_ctrl_ack_o;