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Tim Edwards44bab472020-10-04 22:09:54 -040019A quick documentation of the Caravel memory map and operation
20---------------------------------------------------------------
21
22Caravel pinout:
23---------------
24
Tim Edwardsb86fc842020-10-13 17:11:54 -040025 vddio 3.3V supply for all I/O and ESD
26 vssio Ground for all I/O and ESD
27 vdda 3.3V supply for management area
28 vssa Ground for management area
29 vccd 1.8V supply for management area
30 vssd Digital ground for management area
31
32 vdda1 3.3V supply for user area 1
33 vdda2 3.3V supply for user area 2
34 vssa1 Ground for user area 1
35 vssa2 Ground for user area 2
36 vccd1 1.8 supply for user area 1
37 vccd2 1.8 supply for user area 2
38 vssd1 Digital ground for user area 1
39 vssd2 Digital ground for user area 2
40
Tim Edwards44bab472020-10-04 22:09:54 -040041 clock Master clock input
Tim Edwardsb86fc842020-10-13 17:11:54 -040042 gpio 1 bit, mainly used for external LDO control of user power supply
43 mprj_io 32 bits general purpose programmable digital or analog I/O
Tim Edwards44bab472020-10-04 22:09:54 -040044 resetb Master reset (sense inverted) input
45 flash_csb SPI flash controller chip select (sense inverted)
46 flash_clk SPI flash controller clock
47 flash_io0 SPI flash controller data out
48 flash_io1 SPI flash controller data in
Tim Edwards44bab472020-10-04 22:09:54 -040049
50Special-use pins for the management SoC:
51----------------------------------------
52
53 On power-up, the "mprj_io" GPIO are under complete control of the managment
54 SoC. The first 8 user GPIO are special-purpose pads with dedicated functions
55 for the management SoC:
56
57 mprj_io[0] JTAG I/O
58 mprj_io[1] SDO, housekeeping SPI
59 mprj_io[2] SDI, housekeeping SPI
60 mprj_io[3] CSB, housekeeping SPI
61 mprj_io[4] SCK, housekeeping SPI
62 mprj_io[5] Rx, UART
63 mprj_io[6] Tx, UART
Tim Edwards6d9739d2020-10-19 11:00:49 -040064 mprj_io[7] IRQ
Tim Edwards44bab472020-10-04 22:09:54 -040065
66 The next 4 user GPIO are designed to be used with an SPI flash controller in
67 the user space. They allow the four pins to be overridden by the housekeeping
68 SPI to access the SPI flash in pass-through mode.
69
70 mprj_io[8] user flash CSB
71 mprj_io[9] user flash SCK
72 mprj_io[10] user flash IO0
73 mprj_io[11] user flash IO1
74
75 The user may additionally use any available GPIO for the SPI flash IO2 and IO3
76 lines; the pass-through mode only uses the basic 4-pin SPI mode.
77
78 All of the special-use pins are configured through a memory-mapped region. But
79 to avoid a large number of wires in the user space to reach all of the GPIO
80 pad controls, each user GPIO pad has a corresponding local control block. The
81 control block holds the configuration data for the corresponding pad. This
82 configuration data is a mirror of the data in the memory-mapped region, and is
83 loaded by a "transfer" bit in another memory-mapped register. In addition to
84 all of the static control bits for the GPIO, each block contains a single bit
85 that specifies whether that pad is under the control of the user or the management
86 area. All pins are configured from the management area. However, the configuration
87 of static control bits leaves three dynamic signals: input, output, and output
88 enable. One set of these three signals is available to the user when the pad is
89 under user control. The other set of these three signals is available to the
90 management SoC. Again, to reduce wiring, only the two pads for JTAG and the
91 housekeeping SDO have all three pins under control of the SoC; the remaining
92 pads have a single wire to the management SoC which is either an input wire
93 or an output wire, depending on how the control signals for the pad are set.
94
95 This setup gives a simplified view of the pad to the user: For digital
96 applications, the user can treat the pad as a simple bidirectional digital
97 pad with an output enable to switch between output and input functions.
98 The user can set the output enable line high or low for a static input or
99 output function. The user will also have access to the ESD-protected
100 pad connections for analog signals, and can connect to the VDDA domain
101 input digital signal if needed.
102
103Memory map:
104-----------
105
106 The Caravel memory map is as follows:
107
108 SRAM: 0000 0000
109
110 Flash: Config: 1000 0000
111
112 UART: Clock divider: 2000 0000
113 Data: 2000 0004
Tim Edwardsb86fc842020-10-13 17:11:54 -0400114 Enable 2000 0008
Tim Edwards44bab472020-10-04 22:09:54 -0400115
116 GPIO: Data: 2100 0000
117 Output enable: 2100 0004
118 Pullup 2100 0008
119 Pulldown 2100 000c
120
Tim Edwardsb86fc842020-10-13 17:11:54 -0400121 Counter 1: Config: 2200 0000
122 Value: 2200 0004
123 Data: 2200 0008
Tim Edwards44bab472020-10-04 22:09:54 -0400124
Tim Edwardsb86fc842020-10-13 17:11:54 -0400125 Counter 2: Config: 2300 0000
126 Value: 2300 0004
127 Data: 2300 0008
Tim Edwards44bab472020-10-04 22:09:54 -0400128
Tim Edwardsb86fc842020-10-13 17:11:54 -0400129 SPI master: Config: 2400 0000
130 Data: 2400 0004
Tim Edwards44bab472020-10-04 22:09:54 -0400131
Tim Edwardsb86fc842020-10-13 17:11:54 -0400132 Logic analyzer: Data 0: 2500 0000
133 Data 1: 2500 0004
134 Data 2: 2500 0008
135 Data 3: 2500 000c
136 Enable 0: 2500 0010
137 Enable 1: 2500 0014
138 Enable 2: 2500 0018
139 Enable 3: 2500 001c
Tim Edwards44bab472020-10-04 22:09:54 -0400140
Tim Edwardsb86fc842020-10-13 17:11:54 -0400141 Project ctrl: Data (L): 2600 0000
142 Data (H): 2600 0004
143 Transfer: 2600 0008
144 I/O Config: 2600 000c
145 to 2600 009c
146 Power Config: 2600 00a0
147 to 2600 0130
Tim Edwards44bab472020-10-04 22:09:54 -0400148
149 Flash ctrl: Config: 2D00 0000
150
151 System: PLL out: 2F00 0000
152 Trap out: 2F00 0004
153 IRQ7 source: 2F00 0008
154
155 User area base: 3000 0000
156
157 Crossbar: QSPI control 8000 0000
158 Storage area 9000 0000
159 Any slave 1 a000 0000
160 Any slave 2 b000 0000
161
162Project I/O Control:
163---------------------
164
165 Configuration bits per I/O (13 bits for each GPIO pad):
166 Global Default
167 Bits 12-10: digital mode (3 bits) 001
168 Bit 9: voltage trip point select 0
169 Bit 8: slow slew select 0
170 Bit 7: analog bus polarity 0
171 Bit 6: analog bus select 0
172 Bit 5: analog bus enable 0
173 Bit 4: IB mode select 0
174 Bit 3: input disable 0
175 Bit 2: holdover value 0
176 Bit 1: output disable 1
177 Bit 0: management control enable 1
178
179Default I/O modes:
180------------------
181 mprj_io[0] JTAG I/O 110 0 0 0 0 0 0 0 0 0 1
182 mprj_io[1] SDO, housekeeping SPI 110 0 0 0 0 0 0 0 0 0 1
183 all others: 001 0 0 0 0 0 0 0 0 1 1
184
185
186 Standard GPIO output configuration:
Tim Edwards89f09242020-10-05 15:17:34 -0400187 mprj_io[6] Tx, UART 110 0 0 0 0 0 0 1 0 0 1
Tim Edwards44bab472020-10-04 22:09:54 -0400188
189 Standard GPIO input configuration:
190 mprj_io[*] 001 0 0 0 0 0 0 0 0 1 1
191
192 Standard GPIO input configuration with pullup:
193 mprj_io[*] 010 0 0 0 0 0 0 0 0 1 1
194
195 Standard GPIO input configuration with pulldown:
196 mprj_io[*] 011 0 0 0 0 0 0 0 0 1 1
197
198 Specifically:
199 JTAG and SDO are set to output. The output enable configure bit
200 is a don't-care, since the output enable line is directly controlled
201 by the module (JTAG or housekeeping SPI, respectively).
202
203 All other I/O are set as input mode only, with output disabled.
204
205 Tx is set to input like the others; before enabling the UART
206 from a program in flash, the I/O must be set to an output configuration.
207
208 Note that the standard input configurations with pull-up and pull-down
209 require that "out" be set 1 or 0, respectively; since the I/O are
210 designed with minimal wiring, there is only one wire for input and
211 output, so the wire is used for input in these cases, and special
212 signal handling is done locally to set the value of "out" equal to
213 ~dm[0]. This is a (minor) restriction on the available I/O modes.
214
215 Other possible modes are open-drain (for I2C), weak drive strength
216 output (5k up + down), and analog mode (digital disabled)