| commit | e5ac00f49d9b6bc2062e18b42d6907274f641551 | [log] [tgz] |
|---|---|---|
| author | R. Timothy Edwards <tim@opencircuitdesign.com> | Mon Nov 09 09:43:04 2020 -0500 |
| committer | GitHub <noreply@github.com> | Mon Nov 09 09:43:04 2020 -0500 |
| tree | 81726c3a9b9cc02a56fdf148c8982a0bcf266884 | |
| parent | 50b0ea0cf5cf4a8516da661947bbc69881c02039 [diff] | |
| parent | c3b9da4da67f50475e77248f5ce35c52b6257e64 [diff] |
Merge pull request #33 from Manarabdelaty/custom_mem Added power pins to the custom memory cells
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index a72d99e..f1feed5 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -91,7 +91,7 @@ ) counter( .clk(clk), .reset(rst), - .ready(wbs_ack_i), + .ready(wbs_ack_o), .valid(valid), .rdata(rdata), .wdata(wbs_dat_i),