RTL updates to fix gl sim

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 51d6529..08a6241 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -550,8 +550,8 @@
     // SDO).  The rest are configured to be default (input).
 
     gpio_control_block #(
-	.DM_INIT(3'b110),	// Mode = output, strong up/down
-	.OENB_INIT(1'b1)	// Enable output signaling from wire
+	.DM_INIT(`DM_INIT),	// Mode = output, strong up/down
+	.OENB_INIT(`OENB_INIT)	// Enable output signaling from wire
     ) gpio_control_bidir [1:0] (
     	`ifdef USE_POWER_PINS
 			.vccd(vccd),

verilog/rtl/defines.v

diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index a72f0c8..b9df2bd 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -21,4 +21,8 @@
 `define RAM_BLOCKS 2
 
 // Clock divisor default value
-`define CLK_DIV 3'b010
\ No newline at end of file
+`define CLK_DIV 3'b010
+
+// GPIO conrol default mode and enable
+`define DM_INIT 3'b110
+`define OENB_INIT 1'b1
\ No newline at end of file

verilog/rtl/gpio_control_block.v

diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 8ccdfdd..9f9ac7a 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -38,8 +38,8 @@
     parameter TRIP_INIT = 1'b0,
     parameter IB_INIT = 1'b0,
     parameter IENB_INIT = 1'b0,
-    parameter OENB_INIT = 1'b1,
-    parameter DM_INIT = 3'b001,
+    parameter OENB_INIT = `OENB_INIT,
+    parameter DM_INIT = `DM_INIT,
     parameter AENA_INIT = 1'b0,
     parameter ASEL_INIT = 1'b0,
     parameter APOL_INIT = 1'b0

verilog/rtl/picorv32.v

diff --git a/verilog/rtl/picorv32.v b/verilog/rtl/picorv32.v
index f6e9203..17969b5 100644
--- a/verilog/rtl/picorv32.v
+++ b/verilog/rtl/picorv32.v
@@ -2269,6 +2269,7 @@
 		mul_finish <= 0;
 		if (!resetn) begin
 			mul_waiting <= 1;
+			mul_counter <= 0;
 		end else
 		if (mul_waiting) begin
 			if (instr_rs1_signed)