Corrected an issue with the JTAG and SDO pins that prevented them from
being converted to general purpose digital I/O signals by the management
SoC.  This was showing up in the timer testbench which was not seeing
the low two output bits.

verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v

diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
index 85f0c48..ed06c6d 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/mprj_ctrl_tb.v
@@ -14,7 +14,7 @@
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire [36:0] user_io;
+	wire [37:0] user_io;
 	wire SDO;
 
 	wire [3:0] checkbits;

verilog/dv/caravel/mgmt_soc/timer/timer_tb.v

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 5218ee3..9d04404 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -69,26 +69,26 @@
 
 		/* Add checks here */
 		wait(checkbits == 6'h01);
-		$display("   countbits = 0x%x (should be 0xdcba7eb0)", countbits);
-		if(countbits !== 32'hdcba7eb0) begin
+		$display("   countbits = 0x%x (should be 0xdcba7eb3)", countbits);
+		if(countbits !== 32'hdcba7eb3) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h02);
-		$display("   countbits = 0x%x (should be 0x10)", countbits);
-		if(countbits !== 32'h10) begin
+		$display("   countbits = 0x%x (should be 0x11)", countbits);
+		if(countbits !== 32'h11) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h03);
-		$display("   countbits = %x (should be 0x0c)", countbits);
-		if(countbits !== 32'h0c) begin
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== 32'h0f) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h04);
-		$display("   countbits = %x (should be 0x0c)", countbits);
-		if(countbits !== 32'h0c) begin
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== 32'h0f) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end

verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index 30b54f1..b6db4b8 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -69,26 +69,26 @@
 
 		/* Add checks here */
 		wait(checkbits == 6'h01);
-		$display("   countbits = 0x%x (should be 0xdcba7eb0)", countbits);
-		if(countbits !== 32'hdcba7eb0) begin
+		$display("   countbits = 0x%x (should be 0xdcba7eb3)", countbits);
+		if(countbits !== 32'hdcba7eb3) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h02);
-		$display("   countbits = 0x%x (should be 0x10)", countbits);
-		if(countbits !== 32'h10) begin
+		$display("   countbits = 0x%x (should be 0x11)", countbits);
+		if(countbits !== 32'h11) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h03);
-		$display("   countbits = %x (should be 0x0c)", countbits);
-		if(countbits !== 32'h0c) begin
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== 32'h0f) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
 		wait(checkbits == 6'h04);
-		$display("   countbits = %x (should be 0x0c)", countbits);
-		if(countbits !== 32'h0c) begin
+		$display("   countbits = %x (should be 0x0f)", countbits);
+		if(countbits !== 32'h0f) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
@@ -100,8 +100,8 @@
 		end
 
 		wait(checkbits == 6'h06);
-		$display("   countbits = %x (should be 0x0054)", countbits);
-		if(countbits !== 32'h0054) begin
+		$display("   countbits = %x (should be 0x0055)", countbits);
+		if(countbits !== 32'h0055) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
@@ -114,8 +114,8 @@
 		end
 
 		wait(checkbits == 6'h08);
-		$display("   countbits = %x (should be 0x0218)", countbits);
-		if(countbits !== 32'h0218) begin
+		$display("   countbits = %x (should be 0x0219)", countbits);
+		if(countbits !== 32'h0219) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index a9caf12..b55ec62 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -488,7 +488,7 @@
 
     gpio_control_block #(
 	.DM_INIT(3'b110),	// Mode = output, strong up/down
-	.OENB_INIT(1'b0)	// Enable output signaling from wire
+	.OENB_INIT(1'b1)	// Enable output signaling from wire
     ) gpio_control_bidir [1:0] (
     	`ifdef LVS
              inout vccd,

verilog/rtl/counter_timer_low.v

diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v
index 66989d2..b9e1191 100755
--- a/verilog/rtl/counter_timer_low.v
+++ b/verilog/rtl/counter_timer_low.v
@@ -168,7 +168,6 @@
 assign value_cur_plus = value_cur + 1;
 assign value_cur_minus = value_cur - 1;
 
-assign loc_enable = enable_in && enable;
 assign loc_enable = (chain == 1'b1) ? (enable && enable_in) : enable;
 assign enable_out = enable;
 

verilog/rtl/mgmt_core.v

diff --git a/verilog/rtl/mgmt_core.v b/verilog/rtl/mgmt_core.v
index e7511c6..4db3ada 100644
--- a/verilog/rtl/mgmt_core.v
+++ b/verilog/rtl/mgmt_core.v
@@ -75,15 +75,25 @@
 	wire hk_connect;
 
 	// JTAG (to be implemented)
-	wire jtag_out = 1'b0;
+	wire jtag_out;
+	wire jtag_out_pre = 1'b0;
 	wire jtag_outenb = 1'b1;
 
+	// SDO
+	wire sdo_out;
+	wire sdo_out_pre;
+
 	// Housekeeping SPI vectors
 	wire [4:0]  spi_pll_div;
 	wire [2:0]  spi_pll_sel;
 	wire [2:0]  spi_pll90_sel;
 	wire [25:0] spi_pll_trim;
 
+	// Override default function for SDO and JTAG outputs if purposely
+	// set for override by the management SoC.
+	assign sdo_out = (sdo_oenb_state == 1'b0) ? mgmt_out_data[1] : sdo_out_pre;
+	assign jtag_out = (jtag_oenb_state == 1'b0) ? mgmt_out_data[0] : jtag_out_pre;
+
 	caravel_clocking clocking(
 	`ifdef LVS
 		.vdd1v8(vdd1v8),
@@ -177,6 +187,9 @@
 		.pass_thru_mgmt_sck(pass_thru_mgmt_sck),
 		.pass_thru_mgmt_sdi(pass_thru_mgmt_sdi),
 		.pass_thru_mgmt_sdo(pass_thru_mgmt_sdo),
+		// SDO and JTAG state for output override
+		.sdo_oenb_state(sdo_oenb_state),
+		.jtag_oenb_state(jtag_oenb_state),
 		// SPI master->slave direct connection
 		.hk_connect(hk_connect),
 		// Secondary clock (for monitoring)
@@ -231,7 +244,7 @@
 	    .SCK((hk_connect) ? mgmt_out_data[4] : mgmt_in_data[4]),
 	    .SDI((hk_connect) ? mgmt_out_data[2] : mgmt_in_data[2]),
 	    .CSB((hk_connect) ? mgmt_out_data[3] : mgmt_in_data[3]),
-	    .SDO(sdo_out),
+	    .SDO(sdo_out_pre),
 	    .sdo_enb(sdo_outenb),
 	    .pll_dco_ena(spi_pll_dco_ena),
 	    .pll_sel(spi_pll_sel),

verilog/rtl/mgmt_soc.v

diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 67a2c17..f92fa36 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -124,6 +124,9 @@
     input  pass_thru_mgmt_sdi,
     output pass_thru_mgmt_sdo,
 
+    // State of JTAG and SDO pins (override for management output use)
+    output sdo_oenb_state,
+    output jtag_oenb_state,
     // SPI master->slave direct link
     output hk_connect,
     // User clock monitoring
@@ -693,6 +696,8 @@
 	.serial_clock(mprj_io_loader_clock),
 	.serial_resetn(mprj_io_loader_resetn),
 	.serial_data_out(mprj_io_loader_data),
+	.sdo_oenb_state(sdo_oenb_state),
+	.jtag_oenb_state(jtag_oenb_state),
 	.mgmt_gpio_out(mgmt_out_pre),
 	.mgmt_gpio_in(mgmt_in_data)
     );

verilog/rtl/mprj_ctrl.v

diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index ff04158..d7b8ec3 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -24,6 +24,11 @@
     output serial_resetn,
     output serial_data_out,
 
+    // Pass state of OEB bit on SDO and JTAG back to the core
+    // so that the function can be overridden for management output
+    output sdo_oenb_state,
+    output jtag_oenb_state,
+
     // Read/write data to each GPIO pad from management SoC
     input [IO_PADS-1:0] mgmt_gpio_in,
     output [IO_PADS-1:0] mgmt_gpio_out
@@ -59,6 +64,8 @@
 	.serial_clock(serial_clock),
 	.serial_resetn(serial_resetn),
 	.serial_data_out(serial_data_out),
+	.sdo_oenb_state(sdo_oenb_state),
+	.jtag_oenb_state(jtag_oenb_state),
 	// .mgmt_gpio_io(mgmt_gpio_io)
 	.mgmt_gpio_in(mgmt_gpio_in),
 	.mgmt_gpio_out(mgmt_gpio_out)
@@ -89,6 +96,8 @@
     output serial_clock,
     output serial_resetn,
     output serial_data_out,
+    output sdo_oenb_state,
+    output jtag_oenb_state,
     input  [IO_PADS-1:0] mgmt_gpio_in,
     output [IO_PADS-1:0] mgmt_gpio_out
 );
@@ -119,6 +128,16 @@
     wire [PWR_PADS-1:0] pwr_ctrl_sel;
     wire [IO_PADS-1:0] mgmt_gpio_in;
 
+    wire sdo_oenb_state, jtag_oenb_state;
+
+    // JTAG and housekeeping SDO are normally controlled by their respective
+    // modules with OEB set to the default 1 value.  If configured for an
+    // additional output by setting the OEB bit low, then pass this information
+    // back to the core so that the default signals can be overridden.
+
+    assign jtag_oenb_state = io_ctrl[0][OEB];
+    assign sdo_oenb_state = io_ctrl[1][OEB];
+
     assign xfer_sel = (iomem_addr[7:0] == XFER_ADJ);
 
     genvar i;
@@ -195,10 +214,10 @@
              always @(posedge clk) begin
                 if (!resetn) begin
 		    // NOTE:  This initialization must match the defaults passed
-		    // to the control blocks.  Specifically, 0x1801 is for a
+		    // to the control blocks.  Specifically, 0x1803 is for a
 		    // bidirectional pad, and 0x0403 is for a simple input pad
 		    if (i < 2) begin
-                    	io_ctrl[i] <= 'h1801;
+                    	io_ctrl[i] <= 'h1803;
 		    end else begin
                     	io_ctrl[i] <= 'h0403;
 		    end