Added synthesized memory (4kb)
diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index abfcd44..20a426c 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h
@@ -12,6 +12,9 @@
extern uint32_t flashio_worker_begin;
extern uint32_t flashio_worker_end;
+// SYNTH_MEM (0x0100_0000)
+#define reg_synth_mem (*(volatile uint32_t*)0x01000000)
+
// UART (0x2000_0000)
#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
#define reg_uart_data (*(volatile uint32_t*)0x20000004)
diff --git a/verilog/dv/caravel/sections.lds b/verilog/dv/caravel/sections.lds
index 8482887..0e80064 100644
--- a/verilog/dv/caravel/sections.lds
+++ b/verilog/dv/caravel/sections.lds
@@ -1,6 +1,6 @@
MEMORY {
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
- RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x8000 /* 8192 words ( 32 KB) */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x1400 /* 1280 words (5 KB) */
}
SECTIONS {
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index fffee90..a9caf12 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -51,7 +51,7 @@
`include "user_proj_example.v"
`ifdef USE_OPENRAM
- `include "sram_1rw1r_32_8192_8_sky130.v"
+ `include "sram_1rw1r_32_256_8_sky130.v"
`endif
module caravel (
@@ -251,17 +251,17 @@
.mprj_io_in(mprj_io_in),
.mprj_io_out(mprj_io_out),
.mprj_io_oeb(mprj_io_oeb),
- .mprj_io_hldh_n(mprj_io_hldh_n),
+ .mprj_io_hldh_n(mprj_io_hldh_n),
.mprj_io_enh(mprj_io_enh),
- .mprj_io_inp_dis(mprj_io_inp_dis),
- .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
- .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
- .mprj_io_slow_sel(mprj_io_slow_sel),
- .mprj_io_holdover(mprj_io_holdover),
- .mprj_io_analog_en(mprj_io_analog_en),
- .mprj_io_analog_sel(mprj_io_analog_sel),
- .mprj_io_analog_pol(mprj_io_analog_pol),
- .mprj_io_dm(mprj_io_dm)
+ .mprj_io_inp_dis(mprj_io_inp_dis),
+ .mprj_io_ib_mode_sel(mprj_io_ib_mode_sel),
+ .mprj_io_vtrip_sel(mprj_io_vtrip_sel),
+ .mprj_io_slow_sel(mprj_io_slow_sel),
+ .mprj_io_holdover(mprj_io_holdover),
+ .mprj_io_analog_en(mprj_io_analog_en),
+ .mprj_io_analog_sel(mprj_io_analog_sel),
+ .mprj_io_analog_pol(mprj_io_analog_pol),
+ .mprj_io_dm(mprj_io_dm)
);
// SoC core
@@ -301,6 +301,20 @@
// Mask revision
wire [31:0] mask_rev;
+ wire mprj_clock;
+ wire mprj_clock2;
+ wire mprj_resetn;
+ wire mprj_cyc_o_user;
+ wire mprj_stb_o_user;
+ wire mprj_we_o_user;
+ wire [3:0] mprj_sel_o_user;
+ wire [31:0] mprj_adr_o_user;
+ wire [31:0] mprj_dat_o_user;
+ wire mprj_vcc_pwrgood;
+ wire mprj2_vcc_pwrgood;
+ wire mprj_vdd_pwrgood;
+ wire mprj2_vdd_pwrgood;
+
mgmt_core #(
.MPRJ_IO_PADS(`MPRJ_IO_PADS),
.MPRJ_PWR_PADS(`MPRJ_PWR_PADS)
@@ -375,20 +389,6 @@
/* always active, connect the enable to the logic-1 output from */
/* the vccd1 domain. */
- wire mprj_clock;
- wire mprj_clock2;
- wire mprj_resetn;
- wire mprj_cyc_o_user;
- wire mprj_stb_o_user;
- wire mprj_we_o_user;
- wire [3:0] mprj_sel_o_user;
- wire [31:0] mprj_adr_o_user;
- wire [31:0] mprj_dat_o_user;
- wire mprj_vcc_pwrgood;
- wire mprj2_vcc_pwrgood;
- wire mprj_vdd_pwrgood;
- wire mprj2_vdd_pwrgood;
-
mgmt_protect mgmt_buffers (
.vccd(vccd),
.vssd(vssd),
diff --git a/verilog/rtl/mem_synth_wb.v b/verilog/rtl/mem_synth_wb.v
new file mode 100644
index 0000000..d54ddf6
--- /dev/null
+++ b/verilog/rtl/mem_synth_wb.v
@@ -0,0 +1,77 @@
+module mem_synth_wb #(
+ parameter integer MEM_WORDS = 1024
+)(
+ input wb_clk_i,
+ input wb_rst_i,
+
+ input [31:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ input [3:0] wb_sel_i,
+ input wb_we_i,
+ input wb_cyc_i,
+ input wb_stb_i,
+
+ output wb_ack_o,
+ output [31:0] wb_dat_o
+);
+
+ wire valid;
+ wire ram_wen;
+ wire [3:0] wen; // write enable
+
+ assign valid = wb_cyc_i & wb_stb_i;
+ assign ram_wen = wb_we_i && valid;
+
+ assign wen = wb_sel_i & {4{ram_wen}} ;
+
+ reg wb_ack_read;
+ reg wb_ack_o;
+
+ always @(posedge wb_clk_i) begin
+ if (wb_rst_i == 1'b 1) begin
+ wb_ack_read <= 1'b0;
+ wb_ack_o <= 1'b0;
+ end else begin
+ wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
+ wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
+ end
+ end
+
+ soc_mem_synth # (
+ .MEM_WORDS(MEM_WORDS)
+ ) mem (
+ .clk(wb_clk_i),
+ .ena(valid),
+ .wen(wen),
+ .addr(wb_adr_i[12:2]),
+ .wdata(wb_dat_i),
+ .rdata(wb_dat_o)
+ );
+
+endmodule
+
+module soc_mem_synth #(
+ parameter integer MEM_WORDS = 2048
+)(
+ input clk,
+ input ena,
+ input [3:0] wen,
+ input [10:0] addr,
+ input [31:0] wdata,
+ output[31:0] rdata
+);
+
+ reg [31:0] rdata;
+ reg [31:0] mem [0:MEM_WORDS-1];
+
+ always @(posedge clk) begin
+ if (ena == 1'b1) begin
+ rdata <= mem[addr];
+ if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
+ if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
+ if (wen[2]) mem[addr][23:16] <= wdata[23:16];
+ if (wen[3]) mem[addr][31:24] <= wdata[31:24];
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index bacf52c..882f1c7 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -93,12 +93,12 @@
/* Using Port 0 Only - Size: 1KB, 256x32 bits */
//sram_1rw1r_32_256_8_scn4m_subm
- sram_1rw1r_32_8192_8_sky130 SRAM(
+ sram_1rw1r_32_256_8_sky130 SRAM(
.clk0(clk),
.csb0(~ena),
.web0(~|wen),
.wmask0(wen),
- .addr0(addr[12:0]),
+ .addr0(addr[7:0]),
.din0(wdata),
.dout0(rdata)
);
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index ac4fdf5..3a8825e 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -41,6 +41,7 @@
`include "la_wb.v"
`include "mprj_ctrl.v"
`include "convert_gpio_sigs.v"
+`include "mem_synth_wb.v"
module mgmt_soc #(
parameter MPRJ_IO_PADS = 32,
@@ -138,13 +139,15 @@
output [31:0] mprj_dat_o
);
/* Memory reverted back to 256 words while memory has to be synthesized */
- parameter integer MEM_WORDS = 8192;
- parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
+ parameter integer MEM_WORDS = 256;
+ parameter integer MEM_SYNTH_WORDS = 1024;
+ parameter [31:0] STACKADDR = (4*(MEM_WORDS + MEM_SYNTH_WORDS)); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 1000_0000;
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
// Slaves Base Addresses
parameter RAM_BASE_ADR = 32'h 0000_0000;
+ parameter RAM_SYNTH_BASE_ADR = 32'h 0100_0000;
parameter FLASH_BASE_ADR = 32'h 1000_0000;
parameter UART_BASE_ADR = 32'h 2000_0000;
parameter GPIO_BASE_ADR = 32'h 2100_0000;
@@ -200,7 +203,7 @@
// Wishbone Interconnect
localparam ADR_WIDTH = 32;
localparam DAT_WIDTH = 32;
- localparam NUM_SLAVES = 12;
+ localparam NUM_SLAVES = 13;
parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
{8'hFF, {ADR_WIDTH-8{1'b0}}},
@@ -214,6 +217,7 @@
{8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}},
+ {8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}}
};
@@ -229,6 +233,7 @@
{GPIO_BASE_ADR},
{UART_BASE_ADR},
{FLASH_BASE_ADR},
+ {RAM_SYNTH_BASE_ADR},
{RAM_BASE_ADR}
};
@@ -701,6 +706,26 @@
.wb_dat_o(mem_dat_o)
);
+ // Wishbone Slave Synthesized RAM
+ wire mem_synth_stb_i;
+ wire mem_synth_ack_o;
+ wire [31:0] mem_synth_dat_o;
+
+ mem_synth_wb #(
+ .MEM_WORDS(MEM_SYNTH_WORDS)
+ ) soc_mem_synth (
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_adr_i(cpu_adr_o),
+ .wb_dat_i(cpu_dat_o),
+ .wb_sel_i(cpu_sel_o),
+ .wb_we_i(cpu_we_o),
+ .wb_cyc_i(cpu_cyc_o),
+ .wb_stb_i(mem_synth_stb_i),
+ .wb_ack_o(mem_synth_ack_o),
+ .wb_dat_o(mem_synth_dat_o)
+ );
+
// Wishbone intercon logic
wb_intercon #(
.AW(ADR_WIDTH),
@@ -720,17 +745,17 @@
mprj_stb_o, mprj_ctrl_stb_i, la_stb_i,
spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
gpio_stb_i, uart_stb_i,
- spimemio_flash_stb_i, mem_stb_i }),
+ spimemio_flash_stb_i, mem_synth_stb_i, mem_stb_i }),
.wbs_dat_i({ sys_dat_o, spimemio_cfg_dat_o,
mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
gpio_dat_o, uart_dat_o,
- spimemio_flash_dat_o, mem_dat_o }),
+ spimemio_flash_dat_o,mem_synth_dat_o, mem_dat_o }),
.wbs_ack_i({ sys_ack_o, spimemio_cfg_ack_o,
mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
gpio_ack_o, uart_ack_o,
- spimemio_flash_ack_o, mem_ack_o })
+ spimemio_flash_ack_o, mem_synth_ack_o, mem_ack_o })
);
endmodule
diff --git a/verilog/rtl/sram_1rw1r_32_8192_8_sky130.v b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
similarity index 93%
rename from verilog/rtl/sram_1rw1r_32_8192_8_sky130.v
rename to verilog/rtl/sram_1rw1r_32_256_8_sky130.v
index dfd9a45..72864b1 100644
--- a/verilog/rtl/sram_1rw1r_32_8192_8_sky130.v
+++ b/verilog/rtl/sram_1rw1r_32_256_8_sky130.v
@@ -1,9 +1,13 @@
// OpenRAM SRAM model
-// Words: 8192
+// Words: 256
// Word size: 32
// Write size: 8
-module sram_1rw1r_32_8192_8_sky130(
+module sram_1rw1r_32_256_8_sky130(
+`ifdef LVS
+ vdd,
+ gnd,
+`endif
// Port 0: RW
clk0,csb0,web0,wmask0,addr0,din0,dout0,
// Port 1: R
@@ -12,11 +16,15 @@
parameter NUM_WMASKS = 4 ;
parameter DATA_WIDTH = 32 ;
- parameter ADDR_WIDTH = 13 ;
+ parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
- parameter DELAY = 1 ;
+ parameter DELAY = 3 ;
+`ifdef LVS
+ inout vdd;
+ inout gnd;
+`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
