- 0893d01 [DOC] Add more information on tooling for MPW #1 by Ahmed Ghazy · 3 years, 5 months ago
- 7f70d6f Clean-up lvs-X targets by Ahmed Ghazy · 3 years, 5 months ago
- ba523c3 Add maglef views for the 3 remaining blocks by Ahmed Ghazy · 3 years, 5 months ago
- 079d4cd clean user_proj_example directory before filling it in by Jecel Assumpcao Jr · 3 years, 5 months ago
- 9e1dddb Updated mgmt_core gate level netlist by manarabdelaty · 3 years, 5 months ago
- 589a528 RTL updates to fix gl sim by manarabdelaty · 3 years, 5 months ago
- ea96b3a Update mem.c by manarabdelaty · 3 years, 5 months ago
- 1d683db Merge branch 'develop' of https://github.com/efabless/caravel into develop by manarabdelaty · 3 years, 5 months ago
- fc7ff68 Testbench updates to force csb to 1 by manarabdelaty · 3 years, 5 months ago
- 8e2f670 [CI] re-enable DRC checks in the precheck by agorararmard · 3 years, 5 months ago
- 065a942 [DOC] README reference update by agorararmard · 3 years, 5 months ago
- da92aef [Doc] update references and openlane docs by agorararmard · 3 years, 5 months ago
- c804333 [PDK] update the open_pdks pointer to opencircuitdesign by agorararmard · 3 years, 5 months ago
- 56b853b a few large files remained by Jecel Assumpcao Jr · 3 years, 5 months ago
- 4f05733 caravel_out was messed up, we will regenerate it anyway by Jecel Assumpcao Jr · 3 years, 5 months ago
- a927d3e compressed to send to github by Jecel Assumpcao Jr · 3 years, 5 months ago
- df720a2 small clean ups and track stuff in runs by Jecel Assumpcao Jr · 3 years, 5 months ago
- 8c604ca Save the full netlist of chip_io by Ahmed Ghazy · 3 years, 5 months ago
- fdda2cb Add lvs-X targets to run LVS independently by Ahmed Ghazy · 3 years, 5 months ago
- 5272bba small reorganization by Jecel Assumpcao Jr · 3 years, 5 months ago
- 86a3e88 Changed the GDS_FILE pointers in the maglef/ files to add "../gds/" by Tim Edwards · 3 years, 5 months ago
- a30068c [CI]: a solution for the long CI log. by agorararmard · 3 years, 5 months ago
- c4d4aed Merge branch 'develop' of github.com:efabless/caravel into develop by Tim Edwards · 3 years, 5 months ago
- 5c6afe7 Corrected the GPIO testbench to force CSB high during startup, to by Tim Edwards · 3 years, 5 months ago
- e5bdef0 [CI] update CI scripts to reflect the recent precheck changes by agorararmard · 3 years, 5 months ago
- 18caae7 missed a few files by Jecel Assumpcao Jr · 3 years, 5 months ago
- 93974e8 merged with caravel master branch by Jecel Assumpcao Jr · 3 years, 5 months ago
- 08dd483 Added global default value for the clock divisor by manarabdelaty · 3 years, 5 months ago
- 57c50fa Added DSIM to the simulation makefiles by manarabdelaty · 3 years, 5 months ago
- b52d3b9 Merge pull request #20 from Manarabdelaty/fix_gl_testbenches by Manar · 3 years, 5 months ago
- 83598e3 extra pins to make routing easier by Jecel Assumpcao Jr · 3 years, 5 months ago
- 88f00e6 nicer pinout for yellow cell by Jecel Assumpcao Jr · 3 years, 5 months ago
- f36f4dd Merge branch 'develop' into master by Ahmed Ghazy · 3 years, 5 months ago
- 1824244 Merge branch 'develop' into master by Ahmed Ghazy · 3 years, 5 months ago
- 25db7b1 Remove GDS_* properties from mag/ files by Ahmed Ghazy · 3 years, 5 months ago
- f264b7f Remove GDS_* properties from mag/ files by Ahmed Ghazy · 3 years, 5 months ago
- f87daf5 Update caravel top-level views by Ahmed Ghazy · 3 years, 5 months ago
- 3db3127 Update caravel top-level views by Ahmed Ghazy · 3 years, 5 months ago
- 8717024 Update chip_io by Ahmed Ghazy · 3 years, 5 months ago
- 959a3fd Update chip_io by Ahmed Ghazy · 3 years, 5 months ago
- f0c9466 Make user_project_wrapper empty by default by Ahmed Ghazy · 3 years, 5 months ago
- 2d5a7bf Make user_project_wrapper empty by default by Ahmed Ghazy · 3 years, 5 months ago
- 0011f61 Avoid compressing files in openlane/ by Ahmed Ghazy · 3 years, 5 months ago
- 983f406 Avoid compressing files in openlane/ by Ahmed Ghazy · 3 years, 5 months ago
- 378f124 Follow-up on 6aea300d: increase ring spacings by Ahmed Ghazy · 3 years, 5 months ago
- ccd2a26 Follow-up on 6aea300d: increase ring spacings by Ahmed Ghazy · 3 years, 5 months ago
- 8016827 [DATA] regenerate mgmt_core.gds from source by Ahmed Ghazy · 3 years, 5 months ago
- c0aa3ab [DATA] regenerate mgmt_core.gds from source by Ahmed Ghazy · 3 years, 5 months ago
- c73c7ca [Makefile] update open_pdks commit to include the lef read fix by agorararmard · 3 years, 5 months ago
- 1248310 [Makefile] update open_pdks commit to include the lef read fix by agorararmard · 3 years, 5 months ago
- c5aa79b generated individual ycell to be used as a building block by Jecel Assumpcao Jr · 3 years, 5 months ago
- 148e1c1 Ignore openlane runs directory by Ahmed Ghazy · 3 years, 5 months ago
- 1e2e954 Ignore openlane runs directory by Ahmed Ghazy · 3 years, 5 months ago
- a8cacb6 Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 3 years, 5 months ago
- f980a2f Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 3 years, 5 months ago
- 91ada92 added maglef files by mkk · 3 years, 5 months ago
- ebc5978 added maglef files by mkk · 3 years, 5 months ago
- acdf29d Removed duplicate GL testbenches by manarabdelaty · 3 years, 5 months ago
- ec0584c Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 3 years, 5 months ago
- e214257 Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 3 years, 5 months ago
- 8e065f2 Update README.md by Mohamed Kassem · 3 years, 5 months ago
- ba06326 Update README.md by Mohamed Kassem · 3 years, 5 months ago
- 08d9a76 Update README.md by Mohamed Kassem · 3 years, 5 months ago
- 27dc8ce Update README.md by Mohamed Kassem · 3 years, 5 months ago
- 8f79732 Updated mgmt_core gl netlist by manarabdelaty · 3 years, 5 months ago
- 08006ba Updated mgmt_core gl netlist by manarabdelaty · 3 years, 5 months ago
- f595b81 add tests for user_proj_block.v by Jecel Assumpcao Jr · 3 years, 5 months ago
- 36de0c8 both yosys and iverilog seem to support signal arrays, so yblock can be much simpler by Jecel Assumpcao Jr · 3 years, 5 months ago
- 7fd5105 change from Verilog 1995 style to 2001 style by Jecel Assumpcao Jr · 3 years, 5 months ago
- 4b261d3 Merge branch 'main' of https://github.com/fiberhood/MorphleLogic into main by Jecel Assumpcao Jr · 3 years, 5 months ago
- 3e19045 change Morphle Logic ASCII representation to use period instead of space for blank cells by Jecel Assumpcao Jr · 3 years, 5 months ago
- 31c3465 First pruned version of the repo (~470MB w/o .git) by Ahmed Ghazy · 3 years, 5 months ago
- 1c688fd First pruned version of the repo (~470MB w/o .git) by Ahmed Ghazy · 3 years, 5 months ago
- d4a2d6f [DOC] add open_pdks prerequisite by agorararmard · 3 years, 5 months ago
- 73fea9c [DOC] add open_pdks prerequisite by agorararmard · 3 years, 5 months ago
- 9e230f8 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 3 years, 5 months ago
- d180822 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 3 years, 5 months ago
- 8839d6a Correct instance names that iverilog doesn't like by Ahmed Ghazy · 3 years, 5 months ago
- 16a6403 Correct instance names that iverilog doesn't like by Ahmed Ghazy · 3 years, 5 months ago
- 3741dfc [DOC] add documentation on how to use the magic embedded within the openlane docker. This waives the magic installation requirement. by agorararmard · 3 years, 5 months ago
- da83f74 [DOC] add documentation on how to use the magic embedded within the openlane docker. This waives the magic installation requirement. by agorararmard · 3 years, 5 months ago
- fed74ec update the PDK commits by agorararmard · 3 years, 5 months ago
- b4156d9 update the PDK commits by agorararmard · 3 years, 5 months ago
- fc4cabe [CI]: No need to use travis wait since we already skip the DRC checks. by agorararmard · 3 years, 5 months ago
- 22a8294 [CI]: No need to use travis wait since we already skip the DRC checks. by agorararmard · 3 years, 5 months ago
- 19ffc21 Overwrote mgmt_core.v.gz from the source by Ahmed Ghazy · 3 years, 5 months ago
- b7ba3aa Overwrote mgmt_core.v.gz from the source by Ahmed Ghazy · 3 years, 5 months ago
- 65065c6 Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 3 years, 5 months ago
- 32f18ac Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 3 years, 5 months ago
- 2e9f7b3 Merge pull request #18 from Manarabdelaty/develop by Manar · 3 years, 5 months ago
- 1472e66 Merge pull request #18 from Manarabdelaty/develop by Manar · 3 years, 5 months ago
- a115bdd Added GL simulations by manarabdelaty · 3 years, 5 months ago
- 9ba3e59 Added GL simulations by manarabdelaty · 3 years, 5 months ago
- b868eec Delete Fiberhood-logo.png by fiberhood · 3 years, 5 months ago
- 9925c36 Delete morphle shirt 2.1.pdf by fiberhood · 3 years, 5 months ago
- 45fdf35 Delete morphle-logic-logo.png by fiberhood · 3 years, 5 months ago
- 6cd4173 first step to build from smaller blocks by Jecel Assumpcao Jr · 3 years, 5 months ago
- 408e3c6 added 'make help' and cleaned up logic analyzer pinout by Jecel Assumpcao Jr · 3 years, 5 months ago
- c941188 [DATA] updated caravel.synthesis.v under verilog/gl and update info.yaml by agorararmard · 3 years, 5 months ago
- 8b02148 [DATA] updated caravel.synthesis.v under verilog/gl and update info.yaml by agorararmard · 3 years, 5 months ago
