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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / HEAD
  1. 0893d01 [DOC] Add more information on tooling for MPW #1 by Ahmed Ghazy · 4 years ago
  2. 7f70d6f Clean-up lvs-X targets by Ahmed Ghazy · 4 years ago
  3. ba523c3 Add maglef views for the 3 remaining blocks by Ahmed Ghazy · 4 years ago
  4. 079d4cd clean user_proj_example directory before filling it in by Jecel Assumpcao Jr · 4 years ago
  5. 9e1dddb Updated mgmt_core gate level netlist by manarabdelaty · 4 years ago
  6. 589a528 RTL updates to fix gl sim by manarabdelaty · 4 years ago
  7. ea96b3a Update mem.c by manarabdelaty · 4 years ago
  8. 1d683db Merge branch 'develop' of https://github.com/efabless/caravel into develop by manarabdelaty · 4 years ago
  9. fc7ff68 Testbench updates to force csb to 1 by manarabdelaty · 4 years ago
  10. 8e2f670 [CI] re-enable DRC checks in the precheck by agorararmard · 4 years ago
  11. 065a942 [DOC] README reference update by agorararmard · 4 years ago
  12. da92aef [Doc] update references and openlane docs by agorararmard · 4 years ago
  13. c804333 [PDK] update the open_pdks pointer to opencircuitdesign by agorararmard · 4 years ago
  14. 56b853b a few large files remained by Jecel Assumpcao Jr · 4 years ago
  15. 4f05733 caravel_out was messed up, we will regenerate it anyway by Jecel Assumpcao Jr · 4 years ago
  16. a927d3e compressed to send to github by Jecel Assumpcao Jr · 4 years ago
  17. df720a2 small clean ups and track stuff in runs by Jecel Assumpcao Jr · 4 years ago
  18. 8c604ca Save the full netlist of chip_io by Ahmed Ghazy · 4 years ago
  19. fdda2cb Add lvs-X targets to run LVS independently by Ahmed Ghazy · 4 years ago
  20. 5272bba small reorganization by Jecel Assumpcao Jr · 4 years ago
  21. 86a3e88 Changed the GDS_FILE pointers in the maglef/ files to add "../gds/" by Tim Edwards · 4 years ago
  22. a30068c [CI]: a solution for the long CI log. by agorararmard · 4 years ago
  23. c4d4aed Merge branch 'develop' of github.com:efabless/caravel into develop by Tim Edwards · 4 years ago
  24. 5c6afe7 Corrected the GPIO testbench to force CSB high during startup, to by Tim Edwards · 4 years ago
  25. e5bdef0 [CI] update CI scripts to reflect the recent precheck changes by agorararmard · 4 years ago
  26. 18caae7 missed a few files by Jecel Assumpcao Jr · 4 years ago
  27. 93974e8 merged with caravel master branch by Jecel Assumpcao Jr · 4 years ago
  28. 08dd483 Added global default value for the clock divisor by manarabdelaty · 4 years ago
  29. 57c50fa Added DSIM to the simulation makefiles by manarabdelaty · 4 years ago
  30. b52d3b9 Merge pull request #20 from Manarabdelaty/fix_gl_testbenches by Manar · 4 years ago
  31. 83598e3 extra pins to make routing easier by Jecel Assumpcao Jr · 4 years ago
  32. 88f00e6 nicer pinout for yellow cell by Jecel Assumpcao Jr · 4 years ago
  33. f36f4dd Merge branch 'develop' into master by Ahmed Ghazy · 4 years ago
  34. 1824244 Merge branch 'develop' into master by Ahmed Ghazy · 4 years ago
  35. 25db7b1 Remove GDS_* properties from mag/ files by Ahmed Ghazy · 4 years ago
  36. f264b7f Remove GDS_* properties from mag/ files by Ahmed Ghazy · 4 years ago
  37. f87daf5 Update caravel top-level views by Ahmed Ghazy · 4 years ago
  38. 3db3127 Update caravel top-level views by Ahmed Ghazy · 4 years ago
  39. 8717024 Update chip_io by Ahmed Ghazy · 4 years ago
  40. 959a3fd Update chip_io by Ahmed Ghazy · 4 years ago
  41. f0c9466 Make user_project_wrapper empty by default by Ahmed Ghazy · 4 years ago
  42. 2d5a7bf Make user_project_wrapper empty by default by Ahmed Ghazy · 4 years ago
  43. 0011f61 Avoid compressing files in openlane/ by Ahmed Ghazy · 4 years ago
  44. 983f406 Avoid compressing files in openlane/ by Ahmed Ghazy · 4 years ago
  45. 378f124 Follow-up on 6aea300d: increase ring spacings by Ahmed Ghazy · 4 years ago
  46. ccd2a26 Follow-up on 6aea300d: increase ring spacings by Ahmed Ghazy · 4 years ago
  47. 8016827 [DATA] regenerate mgmt_core.gds from source by Ahmed Ghazy · 4 years ago
  48. c0aa3ab [DATA] regenerate mgmt_core.gds from source by Ahmed Ghazy · 4 years ago
  49. c73c7ca [Makefile] update open_pdks commit to include the lef read fix by agorararmard · 4 years ago
  50. 1248310 [Makefile] update open_pdks commit to include the lef read fix by agorararmard · 4 years ago
  51. c5aa79b generated individual ycell to be used as a building block by Jecel Assumpcao Jr · 4 years ago
  52. 148e1c1 Ignore openlane runs directory by Ahmed Ghazy · 4 years ago
  53. 1e2e954 Ignore openlane runs directory by Ahmed Ghazy · 4 years ago
  54. a8cacb6 Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 4 years ago
  55. f980a2f Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 4 years ago
  56. 91ada92 added maglef files by mkk · 4 years ago
  57. ebc5978 added maglef files by mkk · 4 years ago
  58. acdf29d Removed duplicate GL testbenches by manarabdelaty · 4 years ago
  59. ec0584c Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 4 years ago
  60. e214257 Merge branch 'develop' into develop-pruned by Ahmed Ghazy · 4 years ago
  61. 8e065f2 Update README.md by Mohamed Kassem · 4 years ago
  62. ba06326 Update README.md by Mohamed Kassem · 4 years ago
  63. 08d9a76 Update README.md by Mohamed Kassem · 4 years ago
  64. 27dc8ce Update README.md by Mohamed Kassem · 4 years ago
  65. 8f79732 Updated mgmt_core gl netlist by manarabdelaty · 4 years ago
  66. 08006ba Updated mgmt_core gl netlist by manarabdelaty · 4 years ago
  67. f595b81 add tests for user_proj_block.v by Jecel Assumpcao Jr · 4 years ago
  68. 36de0c8 both yosys and iverilog seem to support signal arrays, so yblock can be much simpler by Jecel Assumpcao Jr · 4 years ago
  69. 7fd5105 change from Verilog 1995 style to 2001 style by Jecel Assumpcao Jr · 4 years ago
  70. 4b261d3 Merge branch 'main' of https://github.com/fiberhood/MorphleLogic into main by Jecel Assumpcao Jr · 4 years ago
  71. 3e19045 change Morphle Logic ASCII representation to use period instead of space for blank cells by Jecel Assumpcao Jr · 4 years ago
  72. 31c3465 First pruned version of the repo (~470MB w/o .git) by Ahmed Ghazy · 4 years ago
  73. 1c688fd First pruned version of the repo (~470MB w/o .git) by Ahmed Ghazy · 4 years ago
  74. d4a2d6f [DOC] add open_pdks prerequisite by agorararmard · 4 years ago
  75. 73fea9c [DOC] add open_pdks prerequisite by agorararmard · 4 years ago
  76. 9e230f8 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 4 years ago
  77. d180822 Updated power net name in mgmt_core to match the one in the GL by manarabdelaty · 4 years ago
  78. 8839d6a Correct instance names that iverilog doesn't like by Ahmed Ghazy · 4 years ago
  79. 16a6403 Correct instance names that iverilog doesn't like by Ahmed Ghazy · 4 years ago
  80. 3741dfc [DOC] add documentation on how to use the magic embedded within the openlane docker. This waives the magic installation requirement. by agorararmard · 4 years ago
  81. da83f74 [DOC] add documentation on how to use the magic embedded within the openlane docker. This waives the magic installation requirement. by agorararmard · 4 years ago
  82. fed74ec update the PDK commits by agorararmard · 4 years ago
  83. b4156d9 update the PDK commits by agorararmard · 4 years ago
  84. fc4cabe [CI]: No need to use travis wait since we already skip the DRC checks. by agorararmard · 4 years ago
  85. 22a8294 [CI]: No need to use travis wait since we already skip the DRC checks. by agorararmard · 4 years ago
  86. 19ffc21 Overwrote mgmt_core.v.gz from the source by Ahmed Ghazy · 4 years ago
  87. b7ba3aa Overwrote mgmt_core.v.gz from the source by Ahmed Ghazy · 4 years ago
  88. 65065c6 Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 4 years ago
  89. 32f18ac Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 4 years ago
  90. 2e9f7b3 Merge pull request #18 from Manarabdelaty/develop by Manar · 4 years ago
  91. 1472e66 Merge pull request #18 from Manarabdelaty/develop by Manar · 4 years ago
  92. a115bdd Added GL simulations by manarabdelaty · 4 years ago
  93. 9ba3e59 Added GL simulations by manarabdelaty · 4 years ago
  94. b868eec Delete Fiberhood-logo.png by fiberhood · 4 years ago
  95. 9925c36 Delete morphle shirt 2.1.pdf by fiberhood · 4 years ago
  96. 45fdf35 Delete morphle-logic-logo.png by fiberhood · 4 years ago
  97. 6cd4173 first step to build from smaller blocks by Jecel Assumpcao Jr · 4 years ago
  98. 408e3c6 added 'make help' and cleaned up logic analyzer pinout by Jecel Assumpcao Jr · 4 years ago
  99. c941188 [DATA] updated caravel.synthesis.v under verilog/gl and update info.yaml by agorararmard · 4 years ago
  100. 8b02148 [DATA] updated caravel.synthesis.v under verilog/gl and update info.yaml by agorararmard · 4 years ago