| commit | b868eecd016d0419ddff11adf01cfd04b399ead3 | [log] [tgz] |
|---|---|---|
| author | fiberhood <morphle@ziggo.nl> | Tue Dec 01 08:26:12 2020 +0100 |
| committer | GitHub <noreply@github.com> | Tue Dec 01 08:26:12 2020 +0100 |
| tree | ec0e57287990e2172342d45439f109a91fb1a1e2 | |
| parent | 9925c36a8c4f06be072caf600a4854ddf4428ba7 [diff] |
Delete Fiberhood-logo.png
This is a combination of the Morphle Logic asynchronous runtime reconfigurable array with the Caravel project to design a chip for the Skywater 130 nm technology.
README for Morphle Logic gives more details about that part of the project.
This version of the chip uses a single block of “yellow cells” from Morphle Logic connected to the logic analyzer pins inside Caravel. The processor in the management frame can inject a configuration into the block (a reset, configuration clock and 16 configuration bits interface with the capability of reading back 16 configuration bits coming out of the bottom of the block) and then inject a value into the top interface of the block (16 pairs of bits) and read back the value coming out the top of the block. The left, down and right interfaces are hardwired to loop back into themselves (which shouldn't matter as their missing neighbors always assert that they are “empty”).
Note that the project includes many intermediate files that were generated separately. Using the tools to generate new versions of them is not a good idea. Only the “user_proj_example” and “user_project_wrappers” should be touched and then magic is used to combine this result with previously generated files of the remaining subprojects into the final .gds file with the chip masks.
OpenLane runs inside Docker so that should be installed and able to run as the current user and not just as root.
To build the modified Caravel chip that includes Morphle Logic instead of the supplied user_proj_example, the following steps should be taken starting from the root of the MorphleLogic project:
export PDK_ROOT=<path where the various PDK projects will be placed>
If the supplied user_proj_example is still present in the openlane subdirectory, then this will patch it to use Morphle Logic verilog files instead by replacing only the config.tcl file:
make copy_config_block
If the various PDK packages have been installed with the correct versions then this step can be skipped:
make pdk
If the large files in MorphleLogic are still compressed then you can:
make uncompress export OPENLANE_ROOT=<path where the right version of OpenLane has been installed> cd openlane
If OpenLane has not yet been installed in the indicated place you can:
make openlane
Be sure that you have the latest version of the magic tool, otherwise you will get some very hard to understand errors.
The first actual step is to generate all the files for the example project:
make user_proj_example
Note that this uses files generated in the user_project_wrapper subproject (definition files that help the included subproject know where the pins will go) even though that uses this one. It is not bad as circular dependencies go.
make user_project_wrapper
Now we have the gds/user_project_wrapper.gds file that the main script needs.
cd .. make ship
If there were no errors in any step then the file gds/caravel.gds has the final design. The files needed for error checking should also all be available at this point.
It is possible to “make compress” to make it easier to move the repository around (only files larger than 10MB, by default, will be affected).
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The Caravel README is below for reference only since the instructions above are better for this fork:
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Start by cloning the repo and uncompressing the files.
git clone https://github.com/efabless/caravel.git cd caravel make uncompress
Install the required version of the PDK by running the following commands:
export PDK_ROOT=<The place where you want to install the pdk> make pdk
Then, you can learn more about the caravel chip by watching these video:
Your area is the full user_project_wrapper, so feel free to add your project there or create a differnt macro and harden it seperately then insert it into the user_project_wrapper. For example, if your design is analog or you're using a different tool other than OpenLANE.
If you will use OpenLANE to harden your design, go through the instructions in this README.md.
Then, you will need to put your design aboard the Caravel chip. Make sure you have the following:
./gds/ in the Caravel directory.Run the following command:
export PDK_ROOT=<The place where the installed pdk resides. The same PDK_ROOT used in the pdk installation step> make
This should merge the GDSes using magic and you'll end up with your version of ./gds/caravel.gds. You should expect hundred of thousands of magic DRC violations with the current “development” state of caravel.
The managment SoC runs firmware that can be used to:
The memory map of the management SoC can be found here
This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample user project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: