- 32f18ac Correct path of sky130_ef_io__gpiov2_pad_wrapped.v by Ahmed Ghazy · 4 years, 4 months ago
- 9ba3e59 Added GL simulations by manarabdelaty · 4 years, 4 months ago
- 4d0d957 Wrap lsbufhv2lv to eliminate li1 pins at the top by Ahmed Ghazy · 4 years, 4 months ago
- e87140d Merge branch 'develop' into new_wrapper by ax3ghazy · 4 years, 4 months ago
- 2d313b4 Merge pull request #9 from ax3ghazy/develop-fork by ax3ghazy · 4 years, 4 months ago
- d19e86d Add two more missing USE_POWER_PINS guards by Ahmed Ghazy · 4 years, 4 months ago
- b3eca4c Add more missing USE_POWER_PINS by Ahmed Ghazy · 4 years, 4 months ago
- 02b06a9 Minor RTL fixes, switching to wrapped GPIOV2 by Ahmed Ghazy · 4 years, 4 months ago
- 1b349ac Split the high voltage part of the mgmt_protect.v module into its own by Tim Edwards · 4 years, 4 months ago
- 5b7e875 Corrections to the management protection buffer block, and a couple of corrections by Tim Edwards · 4 years, 4 months ago
- aa491d4 Corrected the mess caused by introducing default_nettype none into the design by Tim Edwards · 4 years, 4 months ago
- 910bdc7 Eliminate the two inverters at the top level by Ahmed Ghazy · 4 years, 4 months ago
- 86ec7cd add default nettype none by Matt Venn · 4 years, 4 months ago
- afb08a3 Renamed lvs guard to use_power_pins by Manar · 4 years, 5 months ago
- 8f81142 Updated storage area by Manar · 4 years, 5 months ago
- 2a12630 Added power pins to the custom memory cells by Manar · 4 years, 5 months ago
- a5a2b0a Add USE_CUSTOM_DFFRAM guard by Ahmed Ghazy · 4 years, 5 months ago
- b3e8dca Connected storage area to mgmt_core by Manar · 4 years, 5 months ago
- 7e67b42 Add a global defines.v and rely less on parameters by Ahmed Ghazy · 4 years, 5 months ago
- f1eb121 Revised the mprj_ctrl to treat the power control as a single bit by Tim Edwards · 4 years, 5 months ago
- b9d1e7d Corrected an issue with the JTAG and SDO pins that prevented them from by Tim Edwards · 4 years, 5 months ago
- c5bf3ec Added synthesized memory (4kb) by Manar · 4 years, 5 months ago
- d92863b Added two additional signals for monitoring the user areas 1 and 2 by Tim Edwards · 4 years, 5 months ago
- 5169896 Merge pull request #19 from Manarabdelaty/rm_xbar by R. Timothy Edwards · 4 years, 5 months ago
- 4814a40 Added two additional features: (1) Timer chaining, which allows one by Tim Edwards · 4 years, 5 months ago
- c6ccc4e Removed cross bar switch port from mgmt core by Manar · 4 years, 5 months ago
- 7828bfe Updated testbenches to declare 38 bits for the user project GPIO pins. by Tim Edwards · 4 years, 5 months ago
- 1deae09 Removed references to "Mega-Project" and replaced them with "User Project". by Tim Edwards · 4 years, 5 months ago
- fb6eaee (1) Added a wrapper interface between the top level verilog and the user project by Tim Edwards · 4 years, 6 months ago
- 47ff6e7 Testbench simulations are now all working correctly with the pre-release by Tim Edwards · 4 years, 6 months ago
- 16ae382 Additional corrections to the pads and connections for sky130_fd_io. by Tim Edwards · 4 years, 6 months ago
- c2258f0 Modified I/O references to match the sky130_fd_io release. Mostly by Tim Edwards · 4 years, 6 months ago
- 4236bdc Added a secondary clock output, going to the user area, that is derived by Tim Edwards · 4 years, 6 months ago
- 6bee2ad Added additional protection for all the signals output to the user by Tim Edwards · 4 years, 6 months ago
- 2101031 Made a few testbench corrections and added the missing OEB lines from the by Tim Edwards · 4 years, 6 months ago
- 53bee22 Made a change to all of the testbench Makefiles to define PDK_PATH as the by Tim Edwards · 4 years, 6 months ago
- 66322fd Revised the clocking scheme in several ways: (1) Removed the output by Tim Edwards · 4 years, 6 months ago
- a239c56 Split the main power supply into managment and two user areas. Mostly by Tim Edwards · 4 years, 6 months ago
- 65f571d Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example" by Tim Edwards · 4 years, 6 months ago
- 22a7435 Various corrections to simplify the user project I/O wiring by Tim Edwards · 4 years, 6 months ago
- e8fb9ff Added a simple power-on-reset circuit with schmitt trigger output, and by Tim Edwards · 4 years, 6 months ago
- 46f5025 Made corrections; GPIO testbench now passes. by Tim Edwards · 4 years, 6 months ago
- 68338d5 Serial chain loading of the I/O configurations is now working. by Tim Edwards · 4 years, 6 months ago
- 19ddfd0 In spite of many errors that still need fixing, this is a major advance by Tim Edwards · 4 years, 6 months ago
- c1b1895 Fixed the syntactical loose ends from yesterday. There are by Tim Edwards · 4 years, 6 months ago
- b5d5b27 Vast and substantial changes: Removed the old GPIO control with the new one by Tim Edwards · 4 years, 6 months ago
- dcf18eb Corrected some things from the initial pass of removing unused GPIO by Tim Edwards · 4 years, 6 months ago
- 9f38569 Caravel 2nd phase (branch phase2): First pass at removing the analog by Tim Edwards · 4 years, 6 months ago
- 114091e initial commit by shalan · 4 years, 7 months ago
- b19394a Started adding RTL for the Caravel project by Tim Edwards · 4 years, 8 months ago
