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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / a239c5674bd55a57f5562c96955b83e2c51cfcd4 / . / verilog / dv / caravel / defs.h
blob: f777c39f1442eb837ac1b246058bff999124252f [file] [log] [blame]
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]1#ifndef _STRIVE_H_
2#define _STRIVE_H_
3
4#include <stdint.h>
5#include <stdbool.h>
6
7// a pointer to this is a null pointer, but the compiler does not
8// know that because "sram" is a linker symbol from sections.lds.
9extern uint32_t sram;
10
11// Pointer to firmware flash routines
12extern uint32_t flashio_worker_begin;
13extern uint32_t flashio_worker_end;
14
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]15// UART (0x2000_0000)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]16#define reg_uart_clkdiv (*(volatile uint32_t*)0x20000000)
17#define reg_uart_data (*(volatile uint32_t*)0x20000004)
Tim Edwards22a74352020-10-06 10:05:11 -0400[diff] [blame]18#define reg_uart_enable (*(volatile uint32_t*)0x20000008)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]19
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]20// GPIO (0x2100_0000)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]21#define reg_gpio_data (*(volatile uint32_t*)0x21000000)
22#define reg_gpio_ena (*(volatile uint32_t*)0x21000004)
23#define reg_gpio_pu (*(volatile uint32_t*)0x21000008)
24#define reg_gpio_pd (*(volatile uint32_t*)0x2100000c)
25
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]26// Logic Analyzer (0x2200_0000)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]27#define reg_la0_data (*(volatile uint32_t*)0x22000000)
28#define reg_la1_data (*(volatile uint32_t*)0x22000004)
29#define reg_la2_data (*(volatile uint32_t*)0x22000008)
30#define reg_la3_data (*(volatile uint32_t*)0x2200000c)
31
32#define reg_la0_ena (*(volatile uint32_t*)0x22000010)
33#define reg_la1_ena (*(volatile uint32_t*)0x22000014)
34#define reg_la2_ena (*(volatile uint32_t*)0x22000018)
35#define reg_la3_ena (*(volatile uint32_t*)0x2200001c)
36
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]37// Mega Project Control (0x2300_0000)
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]38#define reg_mprj_datal (*(volatile uint32_t*)0x23000000)
39#define reg_mprj_datah (*(volatile uint32_t*)0x23000004)
40#define reg_mprj_xfer (*(volatile uint32_t*)0x23000008)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]41
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]42#define reg_mprj_io_0 (*(volatile uint32_t*)0x2300000c)
43#define reg_mprj_io_1 (*(volatile uint32_t*)0x23000010)
44#define reg_mprj_io_2 (*(volatile uint32_t*)0x23000014)
45#define reg_mprj_io_3 (*(volatile uint32_t*)0x23000018)
46#define reg_mprj_io_4 (*(volatile uint32_t*)0x2300001c)
47#define reg_mprj_io_5 (*(volatile uint32_t*)0x23000020)
48#define reg_mprj_io_6 (*(volatile uint32_t*)0x23000024)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]49
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]50#define reg_mprj_io_7 (*(volatile uint32_t*)0x23000028)
51#define reg_mprj_io_8 (*(volatile uint32_t*)0x2300002c)
52#define reg_mprj_io_9 (*(volatile uint32_t*)0x23000030)
53#define reg_mprj_io_10 (*(volatile uint32_t*)0x23000034)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]54
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]55#define reg_mprj_io_11 (*(volatile uint32_t*)0x23000038)
56#define reg_mprj_io_12 (*(volatile uint32_t*)0x2300003c)
57#define reg_mprj_io_13 (*(volatile uint32_t*)0x23000040)
58#define reg_mprj_io_14 (*(volatile uint32_t*)0x23000044)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]59
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]60#define reg_mprj_io_15 (*(volatile uint32_t*)0x23000048)
61#define reg_mprj_io_16 (*(volatile uint32_t*)0x2300004c)
62#define reg_mprj_io_17 (*(volatile uint32_t*)0x23000050)
63#define reg_mprj_io_18 (*(volatile uint32_t*)0x23000054)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]64
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]65#define reg_mprj_io_19 (*(volatile uint32_t*)0x23000058)
66#define reg_mprj_io_20 (*(volatile uint32_t*)0x2300005c)
67#define reg_mprj_io_21 (*(volatile uint32_t*)0x23000060)
68#define reg_mprj_io_22 (*(volatile uint32_t*)0x23000064)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]69
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]70#define reg_mprj_io_23 (*(volatile uint32_t*)0x23000068)
71#define reg_mprj_io_24 (*(volatile uint32_t*)0x2300006c)
72#define reg_mprj_io_25 (*(volatile uint32_t*)0x23000070)
73#define reg_mprj_io_26 (*(volatile uint32_t*)0x23000074)
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]74
Tim Edwardsa239c562020-10-08 21:36:44 -0400[diff] [blame^]75#define reg_mprj_io_27 (*(volatile uint32_t*)0x23000078)
76#define reg_mprj_io_28 (*(volatile uint32_t*)0x2300007c)
77#define reg_mprj_io_29 (*(volatile uint32_t*)0x23000080)
78#define reg_mprj_io_30 (*(volatile uint32_t*)0x23000084)
79#define reg_mprj_io_31 (*(volatile uint32_t*)0x23000088)
shalanb25102e2020-08-31 16:50:48 +0200[diff] [blame]80
81// Mega Project Slaves (0x3000_0000)
82#define reg_mprj_slave (*(volatile uint32_t*)0x30000000)
83
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]84// Flash Control SPI Configuration (2D00_0000)
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]85#define reg_spictrl (*(volatile uint32_t*)0x2d000000)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]86
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]87// Counter-Timer 0 Configuration
88#define reg_timer0_config (*(volatile uint32_t*)0x21100000)
89#define reg_timer0_value (*(volatile uint32_t*)0x21100004)
90#define reg_timer0_data (*(volatile uint32_t*)0x21100008)
91
92// Counter-Timer 1 Configuration
93#define reg_timer1_config (*(volatile uint32_t*)0x21200000)
94#define reg_timer1_value (*(volatile uint32_t*)0x21200004)
95#define reg_timer1_data (*(volatile uint32_t*)0x21200008)
96
97// SPI Master Configuration
98#define reg_spimaster_config (*(volatile uint32_t*)0x21300000)
99#define reg_spimaster_data (*(volatile uint32_t*)0x21300004)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]100
101// System Area (0x2F00_0000)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]102#define reg_pll_out_dest (*(volatile uint32_t*)0x2F00000c)
103#define reg_trap_out_dest (*(volatile uint32_t*)0x2F000010)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]104#define reg_irq7_source (*(volatile uint32_t*)0x2F000014)
105#define reg_irq8_source (*(volatile uint32_t*)0x2F000018)
106
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]107// Crossbar Slave Addresses (0x8000_0000 - 0xB000_0000)
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]108#define qspi_ctrl_slave (*(volatile uint32_t*)0x80000000)
109#define storage_area_slave (*(volatile uint32_t*)0x90000000)
110#define mega_any_slave1 (*(volatile uint32_t*)0xA0000000)
111#define mega_any_slave2 (*(volatile uint32_t*)0xB0000000)
112
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]113// Useful GPIO mode values
114#define GPIO_MODE_MGMT_STD_INPUT_NOPULL 0x0403
115#define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 0x0803
116#define GPIO_MODE_MGMT_STD_INPUT_PULLUP 0x0c03
Tim Edwardse8fb9ff2020-10-05 16:30:24 -0400[diff] [blame]117#define GPIO_MODE_MGMT_STD_OUTPUT 0x1809
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]118
119#define GPIO_MODE_USER_STD_INPUT_NOPULL 0x0402
120#define GPIO_MODE_USER_STD_INPUT_PULLDOWN 0x0802
121#define GPIO_MODE_USER_STD_INPUT_PULLUP 0x0c02
Tim Edwardse8fb9ff2020-10-05 16:30:24 -0400[diff] [blame]122#define GPIO_MODE_USER_STD_OUTPUT 0x1808
Tim Edwards19ddfd02020-10-04 22:09:54 -0400[diff] [blame]123
shalan114091e2020-08-21 16:48:07 +0200[diff] [blame]124// --------------------------------------------------------
125#endif