add tests for user_proj_block.v
diff --git a/verilog/morphle/config_block.tcl b/verilog/morphle/config_block.tcl
index 5e9cd61..7801ce8 100755
--- a/verilog/morphle/config_block.tcl
+++ b/verilog/morphle/config_block.tcl
@@ -9,15 +9,14 @@
$script_dir/../../verilog/morphle/user_proj_block.v"
set ::env(CLOCK_PORT) "wb_clk_i"
-set ::env(CLOCK_NET) "blk.confclk"
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "200"
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def
set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 700 700"
+set ::env(DIE_AREA) "0 0 1000 1000"
set ::env(PL_BASIC_PLACEMENT) 1
set ::env(PL_TARGET_DENSITY) 0.65
diff --git a/verilog/morphle/test005.tv b/verilog/morphle/test005.tv
new file mode 100644
index 0000000..abe41de
--- /dev/null
+++ b/verilog/morphle/test005.tv
@@ -0,0 +1,166 @@
+// SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// test vectors for user_proj_block 16x16 ycell block connected to
+// the rest of the Caravel chip using the logic analyzer pins.
+// The verilog test bench that reads this file is test005upblock.v
+//
+// each vector in the the format of 1+4+8+4+8 = 25 hex digits
+//
+// The first three groups are the values to be sent from Caravel's
+// logic analyzer to the block while the last two groups are the
+// results that the block is expected to send to the logic analyzer.
+//
+// The first digit only controls two bits, so only 0 to 3 are valid
+// values. Bit 0 is the configuration clock and bit 1 is reset. The
+// top two bits of the digit disable comparisons with the fourth
+// and fifth group respectively, which has to be done for the first
+// few vectors while the circuit under test is outputting unknowns
+//
+// The second group is the configuration bits for the 16 columns of
+// ycells
+//
+// The third group is the uin data to be injected into the 16 columns
+// with two bits each. The two bits can be 0 (empty), 1 (value 0) or
+// 2 (value 1). While 3 is not supposed to be used, it might be a good
+// idea to see what happens
+//
+// The fourth group is the expected value from the configuration bits
+// coming out of the bottom of the 16 columns. They should be the same
+// value as 3*BLOCKHEIGHT (48 in the default case of 16 rows) bits ago
+// for the configuration in
+//
+// The fifth (and last) group is the expected value from uout coming
+// from the 16 columns with two bits each
+//
+// example configuration:
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+// ................
+
+C_0000_00000000_0000_00000000 // first three vectors have the output ignored to settle down
+E_0000_00000000_0000_00000000 // reset everything
+E_0000_00000000_0000_00000000 // msb bit 15: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 14: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 13: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 12: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 11: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 10: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 09: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 08: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 07: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 06: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 05: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 04: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 03: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 0A: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 01: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // msb bit 00: ................
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // middle bit
+B_0000_00000000_0000_00000000
+A_0000_00000000_0000_00000000 // lsb bit
+B_0000_00000000_0000_00000000
+0_0000_00000000_0000_00000000 // normal operation!
+
diff --git a/verilog/morphle/test005upblock.v b/verilog/morphle/test005upblock.v
new file mode 100644
index 0000000..8b0361c
--- /dev/null
+++ b/verilog/morphle/test005upblock.v
@@ -0,0 +1,151 @@
+// SPDX-FileCopyrightText: Copyright 2020 Jecel Mattos de Assumpcao Jr
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// https://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// This tests the user_proj_example in Caravel with the version that has
+// a single 16x16 yblock attached to the logic analyzer pins.
+// This reads a file with test vectors and it applies it to the device under
+// test (DUT) and checks that the output is expected. Only the wires and
+// outputs of the device are used, not the internal signals. This allows
+// these to be regression tests that do not depend on internal changes to
+// the DUT.
+
+// this circuit was derived from the one described in
+// https://syssec.ethz.ch/content/dam/ethz/special-interest/infk/inst-infsec/system-security-group-dam/education/Digitaltechnik_14/14_Verilog_Testbenches.pdf
+
+`timescale 1ns/1ps
+`include "../rtl/defines.v"
+`include "ycell.v"
+`include "yblock.v"
+`include "user_proj_block.v"
+
+module test005upblock;
+
+ reg [51:0] tvout;
+ reg [47:0] xtvin;
+
+
+ reg[31:0] vectornum, errors; // bookkeeping variables
+ reg[99:0] testvectors[10000:0];// array of testvectors/
+ reg clk; // DUT is asynchronous, but the test circuit can't be
+ // generate clock
+ always // no sensitivity list, so it always executes
+ begin
+ clk= 0; #5; clk= 1; #5;// 10ns period
+ end
+
+ wire vdda1 = 1'b1; // User area 1 3.3V supply
+ wire vdda2 = 1'b1; // User area 2 3.3V supply
+ wire vssa1 = 1'b0; // User area 1 analog ground
+ wire vssa2 = 1'b0; // User area 2 analog ground
+ wire vccd1 = 1'b1; // User area 1 1.8V supply
+ wire vccd2 = 1'b1; // User area 2 1.8v supply
+ wire vssd1 = 1'b0; // User area 1 digital ground
+ wire vssd2 = 1'b0; // User area 2 digital ground
+
+ // Wishbone Slave ports (WB MI A)
+ wire wb_clk_i = clk;
+ wire wb_rst_i = tvout[97];
+ wire wbs_stb_i = 1'b0;
+ wire wbs_cyc_i = 1'b0;
+ wire wbs_we_i = 1'b0;
+ wire [3:0] wbs_sel_i = {4{1'b0}};
+ wire [31:0] wbs_dat_i = {32{1'b0}};
+ wire [31:0] wbs_adr_i = {32{1'b0}};
+ wire wbs_ack_o;
+ wire [31:0] wbs_dat_o;
+
+ // Logic Analyzer Signals
+ wire [127:0] la_data_in = {{12{1'b0}},tvout,{64{1'b0}}};
+ wire [127:0] la_data_out;
+ wire [127:0] la_oen;
+
+ // IOs
+ wire [37:0] io_in = {38{1'b0}};
+ wire [37:0] io_out;
+ wire [37:0] io_oeb;
+
+
+ user_proj_example DUT (
+ .vdda1(vdda1), // User area 1 3.3V supply
+ .vdda2(vdda2), // User area 2 3.3V supply
+ .vssa1(vssa1), // User area 1 analog ground
+ .vssa2(vssa2), // User area 2 analog ground
+ .vccd1(vccd1), // User area 1 1.8V supply
+ .vccd2(vccd2), // User area 2 1.8v supply
+ .vssd1(vssd1), // User area 1 digital ground
+ .vssd2(vssd2), // User area 2 digital ground
+
+ // Wishbone Slave ports (WB MI A)
+ .wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wbs_stb_i(wbs_stb_i),
+ .wbs_cyc_i(wbs_cyc_i),
+ .wbs_we_i(wbs_we_i),
+ .wbs_sel_i(wbs_sel_i),
+ .wbs_dat_i(wbs_dat_i),
+ .wbs_adr_i(wbs_adr_i),
+ .wbs_ack_o(wbs_ack_o),
+ .wbs_dat_o(wbs_dat_o),
+
+ // Logic Analyzer Signals
+ .la_data_in(la_data_in),
+ .la_data_out(la_data_out),
+ .la_oen(la_oen),
+
+ // IOs
+ .io_in(io_in),
+ .io_out(io_out),
+ .io_oeb(io_oeb)
+);
+
+ initial
+ begin
+ $readmemh("test005.tv", testvectors); // Read vectors
+ vectornum= 0; errors = 0; // Initialize
+ end
+
+ // apply test vectors on rising edge of clk
+ always @(posedge clk)
+ begin
+ #1; {tvout,xtvin} = testvectors[vectornum][99:0];
+ end
+
+ wire reset = la_data_in[113];
+
+ // check results on falling edge of clk
+ always @(negedge clk)
+ begin
+ if (xtvin === 48'bx)
+ begin
+ $display("%d tests completed with %d errors", vectornum, errors);
+ $finish; // End simulation
+ end
+ $display("testing vector %d", vectornum);
+ if ((!tvout[51] & la_data_out[47:32] !== xtvin[47:32]) |
+ (!tvout[50] & la_data_out[31:0] !== xtvin[31:0]))
+ begin
+ $display("Error: sent = %b %b %h %h",
+ la_data_in[113], la_data_in[112], la_data_in[111:96], la_data_in[95:64]);
+ $display(" outputs = %h %h (%h %h exp)",
+ la_data_out[47:32], la_data_out[31:0],
+ xtvin[47:32], xtvin[31:0]);
+ errors = errors + 1;
+ end
+ // increment array index and read next testvector
+ vectornum= vectornum+ 1;
+ end
+
+endmodule
diff --git a/verilog/morphle/user_proj_block.v b/verilog/morphle/user_proj_block.v
index 96eb3bc..6bc54fe 100644
--- a/verilog/morphle/user_proj_block.v
+++ b/verilog/morphle/user_proj_block.v
@@ -81,7 +81,7 @@
if (wbs_sel_i[3]) store[31:24] <= wbs_dat_i[31:24];
end
wbs_dat_o <= store;
- wbs_ack_o <= valid & !wb_ack_o;
+ wbs_ack_o <= valid & !wbs_ack_o;
end
end
@@ -126,7 +126,7 @@
yblock #(.BLOCKWIDTH(BLOCKWIDTH), .BLOCKHEIGHT(BLOCKHEIGHT))
blk (.reset(reset), .confclk(confclk), .cbitin(cbitin), .cbitout(cbitout),
.lhempty(lhempty), .uvempty(uvempty),
- .rempty(rhempty), .dvempty(dvempty),
+ .rhempty(rhempty), .dvempty(dvempty),
.uempty(uempty), .uin(uin), .uout(uout),
.dempty(dempty), .din(din), .dout(dout),
.lempty(lempty), .lin(lin), .lout(lout),
diff --git a/verilog/morphle/ycell.v b/verilog/morphle/ycell.v
index bed1fa0..fcb196d 100644
--- a/verilog/morphle/ycell.v
+++ b/verilog/morphle/ycell.v
@@ -91,7 +91,7 @@
always @*
case(cnfg)
- 3'b000: r = 9'b110001000; // space is empty and blocked
+ default: r = 9'b110001000; // space is empty and blocked
3'b001: r = 9'b000110011; // + sync with don't cares
3'b010: r = 9'b001001000; // - horizontal short circuit
3'b011: r = 9'b010000100; // | vertical short circuit
@@ -154,18 +154,17 @@
.vblock(vblock), .vbypass(vbypass), .vmatch0(vmatch0), .vmatch1(vmatch1));
assign hempty = empty | hblock;
- assign vempty = empty | vblock;
wire hreset = reset | hblock; // perhaps "| hbypass" to save energy?
- wire vreset = reset | vblock;
-
- // internal wiring
- wire [1:0] vin;
- wire [1:0] vout;
- wire [1:0] vback;
wire [1:0] hin;
wire [1:0] hout;
wire [1:0] hback;
-
+
+ assign vempty = empty | vblock;
+ wire vreset = reset | vblock;
+ wire [1:0] vin;
+ wire [1:0] vout;
+ wire [1:0] vback;
+
wire [1:0] hmatch = {vback[1]&hmatch1,vback[0]&hmatch0};
ycfsm hfsm (.reset(hreset), .in(hin), .match(hmatch), .out(hout));
wire [1:0] bhout = hbypass ? hin : hout;
