Add a conb cell in gpio_control_block
- this is to be able to enable/disable output without needed extra cells
on an upper level
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index d58aa9b..fa85ee2 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -590,6 +590,9 @@
.mgmt_gpio_out({sdo_out, jtag_out}),
.mgmt_gpio_oeb({sdo_outenb, jtag_outenb}),
+ .one(),
+ .zero(),
+
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_shifted[1:0]),
.serial_data_out(gpio_serial_link[1:0]),
@@ -614,6 +617,7 @@
.pad_gpio_in(mprj_io_in[1:0])
);
+ wire [`MPRJ_IO_PADS-1:2] one_loop;
gpio_control_block gpio_control_in [`MPRJ_IO_PADS-1:2] (
`ifdef USE_POWER_PINS
.vccd(vccd),
@@ -629,7 +633,10 @@
.mgmt_gpio_in(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
.mgmt_gpio_out(mgmt_io_in[(`MPRJ_IO_PADS-1):2]),
- .mgmt_gpio_oeb(1'b1),
+ .mgmt_gpio_oeb(one_loop),
+
+ .one(one_loop),
+ .zero(),
// Serial data chain for pad configuration
.serial_data_in(gpio_serial_link_shifted[(`MPRJ_IO_PADS-1):2]),
diff --git a/verilog/rtl/gpio_control_block.v b/verilog/rtl/gpio_control_block.v
index 6faaeff..f011e38 100644
--- a/verilog/rtl/gpio_control_block.v
+++ b/verilog/rtl/gpio_control_block.v
@@ -95,7 +95,12 @@
output [2:0] pad_gpio_dm,
output pad_gpio_outenb,
output pad_gpio_out,
- input pad_gpio_in
+ input pad_gpio_in,
+
+ // to provide a way to automatically disable/enable output
+ // from the outside with needing a conb cell
+ output one,
+ output zero
);
/* Parameters defining the bit offset of each function in the chain */
@@ -137,6 +142,8 @@
wire pad_gpio_outenb;
wire pad_gpio_out;
wire pad_gpio_in;
+ wire one;
+ wire zero;
wire user_gpio_in;
wire gpio_in_unbuf;
@@ -250,5 +257,16 @@
.TE(gpio_logic1)
);
+ sky130_fd_sc_hd__conb_1 const_source (
+`ifdef USE_POWER_PINS
+ .VPWR(vccd),
+ .VGND(vssd),
+ .VPB(vccd),
+ .VNB(vssd),
+`endif
+ .HI(one),
+ .LO(zero)
+ );
+
endmodule
`default_nettype wire
