Update and add the rest of design configs - Some are placeholders for macros that will be hand-designed
diff --git a/openlane/caravel/config.tcl b/openlane/caravel/config.tcl new file mode 100755 index 0000000..650a2e3 --- /dev/null +++ b/openlane/caravel/config.tcl
@@ -0,0 +1,77 @@ +# User config +set script_dir [file dirname [file normalize [info script]]] + +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hvl" + + +set ::env(DESIGN_NAME) caravel + +set verilog_root $script_dir/../../verilog/ +set lef_root $script_dir/../../lef/ +set gds_root $script_dir/../../gds/ +# Change if needed +set ::env(VERILOG_FILES) "\ + $verilog_root/rtl/caravel.v" + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +set ::env(VERILOG_FILES_BLACKBOX) "\ + $verilog_root/rtl/defines.v \ + $verilog_root/rtl/pads.v \ + $verilog_root/rtl/chip_io.v \ + $verilog_root/rtl/mgmt_core.v \ + $verilog_root/rtl/storage.v \ + $verilog_root/rtl/user_project_wrapper.v \ + $verilog_root/rtl/mgmt_protect.v \ + $verilog_root/rtl/gpio_control_block.v \ + $verilog_root/rtl/user_id_programming.v \ + $verilog_root/rtl/simple_por.v" + +set ::env(EXTRA_LEFS) "\ + $lef_root/chip_io.lef \ + $lef_root/mgmt_core.lef \ + $lef_root/storage.lef \ + $lef_root/user_project_wrapper.lef \ + $lef_root/mgmt_protect.lef \ + $lef_root/gpio_control_block.lef \ + $lef_root/user_id_programming.lef \ + $lef_root/simple_por.lef" + +set ::env(EXTRA_GDS_FILES) "\ + $gds_root/chip_io.gds \ + $gds_root/mgmt_core.gds \ + $gds_root/storage.gds \ + $gds_root/user_project_wrapper.gds \ + $gds_root/mgmt_protect.gds \ + $gds_root/gpio_control_block.gds \ + $gds_root/user_id_programming.gds \ + $gds_root/simple_por.gds" + +# # !!! +# if { [info exists ::env(LVS_RUN_DIR)] || [info exists ::env(CONNECTIVITY_RUN)] } { +# # if running to get a full floorplan, need the original pads due to +# # missing pins in the abstracted version +# set ::env(GPIO_PADS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/s8iom0s8/*.lef"] +# } + +set ::env(SYNTH_TOP_LEVEL) 1 +set ::env(SYNTH_FLAT_TOP) 1 +set ::env(LEC_ENABLE) 0 + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 3200 5300" + +set ::env(CELL_PAD) 0 +set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 + +set ::env(DIODE_INSERTION_STRATEGY) 0 + +set ::env(GLB_RT_ALLOW_CONGESTION) 1 +set ::env(GLB_RT_OVERFLOW_ITERS) 150 +set ::env(GLB_RT_TILES) 19 + +set ::env(FILL_INSERTION) 0 + +# DON'T PUT CELLS ON THE TOP LEVEL +set ::env(LVS_INSERT_POWER_PINS) 0
diff --git a/openlane/caravel/interactive.lvs.tcl b/openlane/caravel/interactive.lvs.tcl new file mode 100755 index 0000000..8bd3335 --- /dev/null +++ b/openlane/caravel/interactive.lvs.tcl
@@ -0,0 +1,22 @@ +package require openlane +set script_dir [file dirname [file normalize [info script]]] +## ORIGINAL FLOORPLAN FOR CONNECTIVITY INFO +set ::env(CONNECTIVITY_RUN) 1 + +prep -design $script_dir -tag caravel_lvs -overwrite +set top_rtl $script_dir/../../verilog/rtl/caravel.v + +set ::env(SYNTH_DEFINES) "USE_POWER_PINS" +verilog_elaborate + +logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v + +init_floorplan + +if { [info exists ::env(LVS_RUN_DIR)] } { + file copy -force $::env(CURRENT_DEF) $::env(LVS_RUN_DIR)/lvs.def + file copy -force $::env(CURRENT_NETLIST) $::env(LVS_RUN_DIR)/lvs.v + file copy -force $::env(MERGED_LEF_UNPADDED) $::env(LVS_RUN_DIR)/lvs.lef +} else { + puts "Warning: LVS_RUN_DIR not defined" +}
diff --git a/openlane/caravel/interactive.tcl b/openlane/caravel/interactive.tcl new file mode 100755 index 0000000..7d3e72c --- /dev/null +++ b/openlane/caravel/interactive.tcl
@@ -0,0 +1,93 @@ +package require openlane +set script_dir [file dirname [file normalize [info script]]] +prep -design $script_dir -tag caravel -overwrite +set save_path $script_dir/../.. + +set ::env(SYNTH_DEFINES) "TOP_ROUTING" +verilog_elaborate +#logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v + +init_floorplan + +add_macro_placement padframe 0 0 N +add_macro_placement storage 279.960 219.360 N +add_macro_placement soc 813.755 226.905 N +add_macro_placement mprj 251.520 1279.800 N +add_macro_placement mgmt_buffers 887.200 1158.940 N +add_macro_placement porb_level 778.715 1099.725 N +add_macro_placement rstb_level 826.125 1099.725 N +add_macro_placement user_id_value 778.715 1158.940 N +add_macro_placement por 2903.225 2184.205 N + +# west +# gpio_control_blocks: 37 ... 32 +set x 38.560 +set y 1119.130 +set pitch 227 +set orient N +for {set i 37} {$i >= 32} {incr i -1} { + add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient + set y [expr {$y + $pitch}] +} + +# gpio_control_in: 31 ... 25 +set y [expr {$y + 2 * $pitch}] +for {set i 31} {$i >= 25} {incr i -1} { + add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient + set y [expr {$y + $pitch}] +} + +# gpio_control_in: 24 +set y [expr {$y + $pitch}] +add_macro_placement "gpio_control_in\\\[24\\\]" $x $y $orient + +# east +# gpio_control_bidir: 0 ... 1 +set x 3111.080 +set y 696.300 +set pitch 238 +set orient N; # mirror +for {set i 0} {$i <= 1} {incr i} { + add_macro_placement "gpio_control_bidir\\\[$i\\\]" $x $y $orient + set y [expr {$y + $pitch}] +} + +# gpio_control_in: 2 ... 6 +for {set i 2} {$i <= 6} {incr i} { + add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient + set y [expr {$y + $pitch}] +} + +set y [expr {$y + $pitch}] +# gpio_control_in: 7 ... 13 +for {set i 7} {$i <= 13} {incr i} { + add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient + set y [expr {$y + $pitch}] +} + +# gpio_control_in: 14 +set y [expr {$y + 2 * $pitch - 7}] +add_macro_placement "gpio_control_in\\\[14\\\]" $x $y $orient + +# north +# gpio_control_in: 23 ... 15 +set x 468.460 +set y 5207.760 +set pitch 241 +set orient R270 +for {set i 23} {$i >= 15} {incr i -1} { + add_macro_placement "gpio_control_in\\\[$i\\\]" $x $y $orient + set x [expr {$x + $pitch}] +} + + +manual_macro_placement f + +run_magic + +save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(tritonRoute_result_file_tag).def \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -save_path $save_path \ + -tag $::env(RUN_TAG)
diff --git a/openlane/mgmt_protect/config.tcl b/openlane/mgmt_protect/config.tcl new file mode 100755 index 0000000..a588e9b --- /dev/null +++ b/openlane/mgmt_protect/config.tcl
@@ -0,0 +1,19 @@ +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) mgmt_protect + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v\ + $script_dir/../../verilog/rtl/mgmt_protect.v" + +set ::env(EXTRA_LIBS) "\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib\ + $::env(PDK_ROOT)/$::env(PDK)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib" + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +# set ::env(SYNTH_TOP_LEVEL) 1 + +set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 2000 50"
diff --git a/openlane/mgmt_protect/interactive.tcl b/openlane/mgmt_protect/interactive.tcl new file mode 100644 index 0000000..7f6b302 --- /dev/null +++ b/openlane/mgmt_protect/interactive.tcl
@@ -0,0 +1,26 @@ +# This design fails because it mixes HD and HVL cells +# It will be designed by hand. This is just a placeholder to get things going. +package require openlane +set script_dir [file dirname [file normalize [info script]]] + +prep -design $script_dir -tag mgmt_protect -overwrite +set save_path $script_dir/../.. + +run_synthesis + +set exit_code [catch {init_floorplan} error_msg] +if { $exit_code } { + puts_err "Floorplanning fails, but will generate a blackbox." + set_def $::env(verilog2def_tmp_file_tag)_openroad.def +} + +place_io_ol -cfg $::env(FP_PIN_ORDER_CFG) + +run_magic + +save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(CURRENT_DEF) \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -save_path $save_path \ + -tag $::env(RUN_TAG)
diff --git a/openlane/mgmt_protect/pin_order.cfg b/openlane/mgmt_protect/pin_order.cfg new file mode 100644 index 0000000..85719e7 --- /dev/null +++ b/openlane/mgmt_protect/pin_order.cfg
@@ -0,0 +1,11 @@ +#N +.*_user.* +.*_mprj.* +la_.* + +#S +.*_core.* +.*power.* + +#E +caravel_.*
diff --git a/openlane/simple_por/config.tcl b/openlane/simple_por/config.tcl new file mode 100755 index 0000000..5a5d854 --- /dev/null +++ b/openlane/simple_por/config.tcl
@@ -0,0 +1,18 @@ +# This is an analog design. It will be designed by hand. +# This is a placeholder to get things going. +set script_dir [file dirname [file normalize [info script]]] +# User config +set ::env(DESIGN_NAME) simple_por +set ::env(STD_CELL_LIBRARY) sky130_fd_sc_hvl + +# Change if needed +set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/simple_por.v +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +# Fill this +set ::env(CLOCK_TREE_SYNTH) 0 + +set ::env(CELL_PAD) 8 + +set ::env(FP_CORE_UTIL) 30 +set ::env(PL_TARGET_DENSITY) 0.5
diff --git a/openlane/storage/pin_order.cfg b/openlane/storage/pin_order.cfg new file mode 100644 index 0000000..d24d58a --- /dev/null +++ b/openlane/storage/pin_order.cfg
@@ -0,0 +1,2 @@ +#E +mgmt_.*
diff --git a/openlane/user_id_programming/config.tcl b/openlane/user_id_programming/config.tcl new file mode 100755 index 0000000..84aba1c --- /dev/null +++ b/openlane/user_id_programming/config.tcl
@@ -0,0 +1,15 @@ +set script_dir [file dirname [file normalize [info script]]] +# User config +set ::env(DESIGN_NAME) user_id_programming + +# Change if needed +set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/user_id_programming.v +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +# Fill this +set ::env(CLOCK_TREE_SYNTH) 0 + +set ::env(CELL_PAD) 0 + +set ::env(FP_CORE_UTIL) 20 +set ::env(PL_RANDOM_GLB_PLACEMENT) 1
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl new file mode 100644 index 0000000..5528fc9 --- /dev/null +++ b/openlane/user_proj_example/config.tcl
@@ -0,0 +1,15 @@ +set script_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) user_proj_example + +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/user_proj_example.v" + +set ::env(CLOCK_NET) "counter.clk" +set ::env(CLOCK_PERIOD) "10" + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 250 250" +set ::env(PL_BASIC_PLACEMENT) 1 +set ::env(PL_TARGET_DENSITY) 0.15
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 7f63031..e026680 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -3,17 +3,26 @@ set ::env(DESIGN_NAME) user_project_wrapper set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_project_wrapper.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" - set ::env(CLOCK_PORT) "user_clock2" set ::env(CLOCK_NET) "mprj.clk" set ::env(CLOCK_PERIOD) "10" set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 2700 2700" +set ::env(DIE_AREA) "0 0 2700 3700" set ::env(PL_TARGET_DENSITY) 0.001 +set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0 +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/user_project_wrapper.v" + +set ::env(VERILOG_FILES_BLACKBOX) "\ + $script_dir/../../verilog/rtl/defines.v \ + $script_dir/../../verilog/rtl/user_proj_example.v" + +set ::env(EXTRA_LEFS) "\ + $script_dir/../../lef/user_proj_example.lef" + +set ::env(EXTRA_GDS_FILES) "\ + $script_dir/../../gds/user_proj_example.gds"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl new file mode 100644 index 0000000..1f554c1 --- /dev/null +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -0,0 +1,34 @@ +package require openlane +set script_dir [file dirname [file normalize [info script]]] + +prep -design $script_dir -tag user_project_wrapper -overwrite +set save_path $script_dir/../.. + +verilog_elaborate + +init_floorplan + +place_io + +add_macro_placement mprj 1355 3000 N + +manual_macro_placement f + +global_routing_or +detailed_routing + +run_magic +run_magic_spice_export + +save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(tritonRoute_result_file_tag).def \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -save_path $save_path \ + -tag $::env(RUN_TAG) + +run_magic_drc + +run_lvs; # requires run_magic_spice_export + +run_antenna_check