| Notice 0: Reading LEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/merged.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 437 library cells |
| Notice 0: Finished LEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/merged.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/floorplan/verilog2def_openroad.def |
| Notice 0: Design: ycell |
| Notice 0: Created 30 pins. |
| Notice 0: Created 110 components and 781 component-terminals. |
| Notice 0: Created 125 nets and 341 connections. |
| Notice 0: Finished DEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/floorplan/verilog2def_openroad.def |
| Top-level design name: ycell |
| Block boundaries: 0 0 63845 74565 |
| Writing /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/floorplan/ioPlacer.def |
