Split the high voltage part of the mgmt_protect.v module into its own
module called mgmt_protect_hv.v so that it can be synthesized separately
into a hard macro, then included into the mgmt_protect.v block.
diff --git a/ngspice/.simple_por.spice.swp b/ngspice/.simple_por.spice.swp
deleted file mode 100644
index d42a22f..0000000
--- a/ngspice/.simple_por.spice.swp
+++ /dev/null
Binary files differ
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3832f67..130a35c 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -35,6 +35,7 @@
`include "caravel_clocking.v"
`include "mgmt_core.v"
`include "mgmt_protect.v"
+`include "mgmt_protect_hv.v"
`include "mprj_io.v"
`include "chip_io.v"
`include "user_id_programming.v"
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index 6368ae4..d285a91 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -102,53 +102,19 @@
// Logic high in the VDDA (3.3V) domains
- sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
+ mgmt_protect_hv powergood_check (
`ifdef USE_POWER_PINS
- .VPWR(vdda1),
- .VGND(vssa1),
- .VPB(vdda1),
- .VNB(vssa1),
+ .vccd(vccd),
+ .vssd(vssd),
+ .vdda1(vdda1),
+ .vssa1(vssa1),
+ .vdda2(vdda2),
+ .vssa2(vssa2),
`endif
- .HI(mprj_vdd_logic1_h),
- .LO()
- );
-
- sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
-`ifdef USE_POWER_PINS
- .VPWR(vdda2),
- .VGND(vssa2),
- .VPB(vdda2),
- .VNB(vssa2),
-`endif
- .HI(mprj2_vdd_logic1_h),
- .LO()
- );
-
- // Level shift the logic high signals into the 1.8V domain
-
- sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
-`ifdef USE_POWER_PINS
- .VPWR(vdda1),
- .VGND(vssd),
- .LVPWR(vccd),
- .VPB(vdda1),
- .VNB(vssd),
-`endif
- .X(mprj_vdd_logic1),
- .A(mprj_vdd_logic1_h)
+ .mprj_vdd_logic1(mprj_vdd_logic1),
+ .mprj2_vdd_logic1(mprj2_vdd_logic1)
);
- sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
-`ifdef USE_POWER_PINS
- .VPWR(vdda2),
- .VGND(vssd),
- .LVPWR(vccd),
- .VPB(vdda2),
- .VNB(vssd),
-`endif
- .X(mprj2_vdd_logic1),
- .A(mprj2_vdd_logic1_h)
- );
// Buffering from the user side to the management side.
// NOTE: This is intended to be better protected, by a full
diff --git a/verilog/rtl/mgmt_protect_hv.v b/verilog/rtl/mgmt_protect_hv.v
new file mode 100644
index 0000000..9c8cabe
--- /dev/null
+++ b/verilog/rtl/mgmt_protect_hv.v
@@ -0,0 +1,79 @@
+`default_nettype none
+/*----------------------------------------------------------------------*/
+/* mgmt_protect_hv: */
+/* */
+/* High voltage (3.3V) part of the mgmt_protect module. Split out into */
+/* a separate module and file so that the synthesis tools can handle it */
+/* separately from the rest, since it uses a different standard cell */
+/* library. See the file mgmt_protect.v for a full description of the */
+/* whole management protection method. */
+/*----------------------------------------------------------------------*/
+
+module mgmt_protect_hv (
+ inout vccd,
+ inout vssd,
+ inout vdda1,
+ inout vssa1,
+ inout vdda2,
+ inout vssa2,
+
+ output mprj_vdd_logic1,
+ output mprj2_vdd_logic1
+
+);
+
+ wire mprj_vdd_logic1_h;
+ wire mprj2_vdd_logic1_h;
+
+ // Logic high in the VDDA (3.3V) domains
+
+ sky130_fd_sc_hvl__conb_1 mprj_logic_high_hvl (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda1),
+ .VGND(vssa1),
+ .VPB(vdda1),
+ .VNB(vssa1),
+`endif
+ .HI(mprj_vdd_logic1_h),
+ .LO()
+ );
+
+ sky130_fd_sc_hvl__conb_1 mprj2_logic_high_hvl (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda2),
+ .VGND(vssa2),
+ .VPB(vdda2),
+ .VNB(vssa2),
+`endif
+ .HI(mprj2_vdd_logic1_h),
+ .LO()
+ );
+
+ // Level shift the logic high signals into the 1.8V domain
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj_logic_high_lv (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda1),
+ .VGND(vssd),
+ .LVPWR(vccd),
+ .VPB(vdda1),
+ .VNB(vssd),
+`endif
+ .X(mprj_vdd_logic1),
+ .A(mprj_vdd_logic1_h)
+ );
+
+ sky130_fd_sc_hvl__lsbufhv2lv_1 mprj2_logic_high_lv (
+`ifdef USE_POWER_PINS
+ .VPWR(vdda2),
+ .VGND(vssd),
+ .LVPWR(vccd),
+ .VPB(vdda2),
+ .VNB(vssd),
+`endif
+ .X(mprj2_vdd_logic1),
+ .A(mprj2_vdd_logic1_h)
+ );
+
+endmodule
+`default_nettype wire
