blob: bc579858b166c9d3920ee407f7e6a541a03edb6c [file] [log] [blame]
* Simple testbench mainly to check SPICE model conversion from CDL
* Plots the transient response of the smallest inverter in the HD standard cell library
.lib "/home/tim/projects/efabless/tech/SW/sky130A/" tt
.include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
* .option TEMP=27
X0 in vss vss vdd vdd out sky130_fd_sc_hd__inv_1
V0 vdd vss PWL(0n 0.0 30n 1.8)
V1 vss 0 0.0
Vin in vss PWL(0n 0.0 100n 0.0 500n 1.8)
* Transient analysis
tran 1n 1u
plot V(in) V(out)