blob: 6307e7950104c455bc2ce56bf7518a7e0a98f113 [file] [log] [blame]
`default_nettype none
`timescale 1 ns / 1 ps
module simple_por(
inout vdd3v3,
inout vdd1v8,
inout vss,
output porb_h,
output porb_l,
output por_l
);
wire mid, porb_h;
reg inode;
// This is a behavioral model! Actual circuit is a resitor dumping
// current (slowly) from vdd3v3 onto a capacitor, and this fed into
// two schmitt triggers for strong hysteresis/glitch tolerance.
initial begin
inode <= 1'b0;
end
// Emulate current source on capacitor as a 500ns delay either up or
// down.
always @(posedge vdd3v3) begin
#500 inode <= 1'b1;
end
always @(negedge vdd3v3) begin
#500 inode <= 1'b0;
end
// Instantiate two shmitt trigger buffers in series
sky130_fd_sc_hvl__schmittbuf_1 hystbuf1 (
`ifdef USE_POWER_PINS
.VPWR(vdd3v3),
.VGND(vss),
.VPB(vdd3v3),
.VNB(vss),
`endif
.A(inode),
.X(mid)
);
sky130_fd_sc_hvl__schmittbuf_1 hystbuf2 (
`ifdef USE_POWER_PINS
.VPWR(vdd3v3),
.VGND(vss),
.VPB(vdd3v3),
.VNB(vss),
`endif
.A(mid),
.X(porb_h)
);
sky130_fd_sc_hvl__lsbufhv2lv_1 porb_level (
`ifdef USE_POWER_PINS
.VPWR(vdd3v3),
.VPB(vdd3v3),
.LVPWR(vdd1v8),
.VNB(vss),
.VGND(vss),
`endif
.A(porb_h),
.X(porb_l)
);
// since this is behavioral anyway, but this should be
// replaced by a proper inverter
assign por_l = ~porb_l;
endmodule
`default_nettype wire