Merge pull request #6 from dan-rodrigues/tb-fixes
Various testbench fixes (missing power nets, iverilog params, prefixes)
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index 8b011ee..3ab6272 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -18,7 +18,7 @@
%.vvp: %_tb.v %.hex
iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -o $@ $<
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 85d2d17..63b7c93 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -86,22 +86,16 @@
#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
end
- wire flash_csb;
+ wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
- wire USER_VDD1V8;
- wire USER_VDD3V3;
- wire VDD1V8;
- wire VDD3V3;
- wire VSS;
-
- assign VDD3V3 = power1;
- assign VDD1V8 = power2;
- assign USER_VDD3V3 = power3;
- assign USER_VDD1V8 = power4;
- assign VSS = 1'b0;
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
index 8a277e4..19fd4a1 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/Makefile
+++ b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
@@ -18,7 +18,7 @@
%.vvp: %_tb.v %.hex
iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -o $@ $<
%.vcd: %.vvp
vvp $<
diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
index 0b848c6..d9d9a0d 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile
+++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
@@ -18,7 +18,7 @@
%.vvp: %_tb.v %.hex
iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
- $< -o $@
+ -o $@ $<
%.vcd: %.vvp
vvp $<
