change from Verilog 1995 style to 2001 style
diff --git a/verilog/morphle/test001ycfsm.v b/verilog/morphle/test001ycfsm.v
index 585320d..db4e19a 100644
--- a/verilog/morphle/test001ycfsm.v
+++ b/verilog/morphle/test001ycfsm.v
@@ -29,7 +29,7 @@
reg reset;
reg [1:0] match;
- ycfsm DUT (reset, in, match, out);
+ ycfsm DUT (.reset(reset), .in(in), .match(match), .out(out));
initial
begin
diff --git a/verilog/morphle/test002ycfsm.v b/verilog/morphle/test002ycfsm.v
index 45ed561..34cc06b 100644
--- a/verilog/morphle/test002ycfsm.v
+++ b/verilog/morphle/test002ycfsm.v
@@ -44,7 +44,7 @@
clk= 1; #5; clk= 0; #5;// 10ns period
end
- ycfsm DUT (reset, in, match, out);
+ ycfsm DUT (.reset(reset), .in(in), .match(match), .out(out));
initial
begin
diff --git a/verilog/morphle/test003ycconfig.v b/verilog/morphle/test003ycconfig.v
index 623415f..0838060 100644
--- a/verilog/morphle/test003ycconfig.v
+++ b/verilog/morphle/test003ycconfig.v
@@ -29,10 +29,10 @@
wire hblock, hbypass, hmatch0, hmatch1;
wire vblock, vbypass, vmatch0, vmatch1;
- ycconfig DUT (confclk, cbitin, cbitout,
- empty,
- hblock, hbypass, hmatch0, hmatch1,
- vblock, vbypass, vmatch0, vmatch1);
+ ycconfig DUT (.confclk(confclk), .cbitin(cbitin), .cbitout(cbitout),
+ .empty(empty),
+ .hblock(hblock), .hbypass(hbypass), .hmatch0(hmatch0), .hmatch1(hmatch1),
+ .vblock(vblock), .vbypass(vbypass), .vmatch0(vmatch0), .vmatch1(vmatch1));
// adds a second device cascade with the main one being tested to
// see if the expected timing (always holds the previous configuration
diff --git a/verilog/morphle/test004ycell.v b/verilog/morphle/test004ycell.v
index 2066c7b..85419b3 100644
--- a/verilog/morphle/test004ycell.v
+++ b/verilog/morphle/test004ycell.v
@@ -71,12 +71,12 @@
clk= 0; #5; clk= 1; #5;// 10ns period
end
- ycell DUT (reset, confclk, cbitin, cbitout,
- hempty, vempty,
- uempty, uin, uout,
- dempty, din, dout,
- lempty, lin, lout,
- rempty, rin, rout);
+ ycell DUT (.reset(reset), .confclk(confclk), .cbitin(cbitin), .cbitout(cbitout),
+ .hempty(hempty), .vempty(vempty),
+ .uempty(uempty), .uin(uin), .uout(uout),
+ .dempty(dempty), .din(din), .dout(dout),
+ .lempty(lempty), .lin(lin), .lout(lout),
+ .rempty(rempty), .rin(rin), .rout(rout));
initial
begin
diff --git a/verilog/morphle/user_proj_block.v b/verilog/morphle/user_proj_block.v
index 68240b5..90d5049 100644
--- a/verilog/morphle/user_proj_block.v
+++ b/verilog/morphle/user_proj_block.v
@@ -56,7 +56,7 @@
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb
);
- parameter BLOCKWIDTH = 16;
+ parameter BLOCKWIDTH = 16; // this should not be changed
parameter BLOCKHEIGHT = 16;
parameter HMSB = BLOCKWIDTH-1;
parameter HMSB2 = (2*BLOCKWIDTH)-1;
@@ -91,15 +91,6 @@
// 127 to 64 as outputs to the circuit under test
// 63 to 0 as inputs observing points in the circuit
- assign la_data_out[127:48] = {48{1'b0}}; // don't leave it dangling
- // 127:64 is output, 63:48 is unused input
- wire reset = la_data_in[113]; // freezes the cell operations and clears everything
- // 127:114 is unused output
- wire confclk = la_data_in[112]; // a strobe to enter one configuration bit
- wire [HMSB:0] cbitin = la_data_in[111:96]; // new configuration bit from previous cell (U)
- wire [HMSB:0] cbitout; // configuration bit to next cell (D)
- assign la_data_out[47:32] = cbitout;
-
// these are all left hanging
wire [HMSB:0] lhempty; // this cell interrupts horizontal signals to left
wire [HMSB:0] uvempty; // this cell interrupts vertical signals to up
@@ -108,30 +99,38 @@
// UP
wire [HMSB:0] uempty = {HMSB{1'b0}}; // cell U is not empty, so the LA is above us
- wire [HMSB2:0] uin = la_data_in[95:64];
wire [HMSB2:0] uout;
- assign la_data_out[31:0] = uout;
+ wire [HMSB:0] cbitout; // configuration bit to next cell (D)
+ assign la_data_out = {{80{1'b0}},cbitout,uout};
+ // la_data_in[127:114] are unused output
+ wire reset = la_data_in[113]; // freezes the cell operations and clears everything
+ wire confclk = la_data_in[112]; // a strobe to enter one configuration bit
+ wire [HMSB:0] cbitin = la_data_in[111:96]; // new configuration bit from previous cell (U)
+ wire [HMSB2:0] uin = la_data_in[95:64];
+
// DOWN
wire [HMSB:0] dempty = {HMSB{1'b1}}; // cell D is empty, so we are the bottommost of a signal
wire [HMSB2:0] dout; // left dangling to avoid loops that confuse the tools
wire [HMSB2:0] din = {HMSB2{1'b0}};
+
// LEFT
wire [VMSB:0] lempty = {VMSB{1'b1}}; // cell L is empty, so we are the leftmost of a signal
wire [VMSB2:0] lout;
wire [VMSB2:0] lin = {VMSB2{1'b0}};
+
// RIGHT
wire [VMSB:0] rempty = {VMSB{1'b1}}; // cell D is empty, so we are the rightmost of a signal
wire [VMSB2:0] rout;
wire [VMSB2:0] rin = {VMSB2{1'b0}};
yblock #(.BLOCKWIDTH(BLOCKWIDTH), .BLOCKHEIGHT(BLOCKHEIGHT))
- blk (reset, confclk, cbitin, cbitout,
- lhempty, uvempty,
- rhempty, dvempty,
- uempty, uin, uout,
- dempty, din, dout,
- lempty, lin, lout,
- rempty, rin, rout);
+ blk (.reset(reset), .confclk(confclk), .cbitin(cbitin), .cbitout(cbitout),
+ .lhempty(lhempty), .uvempty(uvempty),
+ .rempty(rhempty), .dvempty(dvempty),
+ .uempty(uempty), .uin(uin), .uout(uout),
+ .dempty(dempty), .din(din), .dout(dout),
+ .lempty(lempty), .lin(lin), .lout(lout),
+ .rempty(rempty), .rin(rin), .rout(rout));
endmodule
diff --git a/verilog/morphle/yblock.v b/verilog/morphle/yblock.v
index 7b9c5d5..e4f256f 100644
--- a/verilog/morphle/yblock.v
+++ b/verilog/morphle/yblock.v
@@ -27,44 +27,39 @@
// the combination 3 is not defined
-module yblock(reset, confclk, cbitin, cbitout,
- lhempty, uvempty,
- rhempty, dvempty,
- uempty, uin, uout,
- dempty, din, dout,
- lempty, lin, lout,
- rempty, rin, rout);
- parameter BLOCKWIDTH = 8;
- parameter BLOCKHEIGHT = 8;
- parameter HMSB = BLOCKWIDTH-1;
- parameter HMSB2 = (2*BLOCKWIDTH)-1;
- parameter VMSB = BLOCKHEIGHT-1;
- parameter VMSB2 = (2*BLOCKHEIGHT)-1;
+module yblock #(parameter
+ BLOCKWIDTH = 8,
+ BLOCKHEIGHT = 8,
+ HMSB = BLOCKWIDTH-1,
+ HMSB2 = (2*BLOCKWIDTH)-1,
+ VMSB = BLOCKHEIGHT-1,
+ VMSB2 = (2*BLOCKHEIGHT)-1)
+ (
// control
- input reset; // freezes the cell operations and clears everything
- input confclk; // a strobe to enter one configuration bit
- input [HMSB:0] cbitin; // new configuration bit from previous cell (U)
- output [HMSB:0] cbitout; // configuration bit to next cell (D)
- output [HMSB:0] lhempty; // this cell interrupts horizontal signals to left
- output [HMSB:0] uvempty; // this cell interrupts vertical signals to up
- output [HMSB:0] rhempty; // this cell interrupts horizontal signals to right
- output [HMSB:0] dvempty; // this cell interrupts vertical signals to down
+ input reset, // freezes the cell operations and clears everything
+ input confclk, // a strobe to enter one configuration bit
+ input [HMSB:0] cbitin, // new configuration bit from previous cell (U)
+ output [HMSB:0] cbitout, // configuration bit to next cell (D)
+ output [HMSB:0] lhempty, // this cell interrupts horizontal signals to left
+ output [HMSB:0] uvempty, // this cell interrupts vertical signals to up
+ output [HMSB:0] rhempty, // this cell interrupts horizontal signals to right
+ output [HMSB:0] dvempty, // this cell interrupts vertical signals to down
// UP
- input [HMSB:0] uempty; // cell U is empty, so we are the topmost of a signal
- input [HMSB2:0] uin;
- output [HMSB2:0] uout;
+ input [HMSB:0] uempty, // cells U is empty, so we are the topmost of a signal
+ input [HMSB2:0] uin,
+ output [HMSB2:0] uout,
// DOWN
- input [HMSB:0] dempty; // cell D is empty, so we are the bottommost of a signal
- input [HMSB2:0] din;
- output [HMSB2:0] dout;
+ input [HMSB:0] dempty, // cells D is empty, so we are the bottommost of a signal
+ input [HMSB2:0] din,
+ output [HMSB2:0] dout,
// LEFT
- input [VMSB:0] lempty; // cell L is empty, so we are the leftmost of a signal
- input [VMSB2:0] lin;
- output [VMSB2:0] lout;
+ input [VMSB:0] lempty, // cells L is empty, so we are the leftmost of a signal
+ input [VMSB2:0] lin,
+ output [VMSB2:0] lout,
// RIGHT
- input [VMSB:0] rempty; // cell D is empty, so we are the rightmost of a signal
- input [VMSB2:0] rin;
- output [VMSB2:0] rout;
+ input [VMSB:0] rempty, // cells D is empty, so we are the rightmost of a signal
+ input [VMSB2:0] rin,
+ output [VMSB2:0] rout);
// vertical lines are row order, horizontal lines are column order
// this makes assigning chunks much simpler
@@ -93,27 +88,27 @@
generate
for (x = 0 ; x < BLOCKWIDTH ; x = x + 1) begin : generate_columns
for (y = 0 ; y < BLOCKHEIGHT ; y = y + 1) begin : generate_rows
- ycell gencell (reset, confclk,
+ ycell gencell (.reset(reset), .confclk(confclk),
// cbitin, cbitout,
- vcbit[x+(y*BLOCKWIDTH)], vcbit[x+((y+1)*BLOCKWIDTH)],
+ .cbitin(vcbit[x+(y*BLOCKWIDTH)]), .cbitout(vcbit[x+((y+1)*BLOCKWIDTH)]),
// hempty, vempty,
- he[y+((x+1)*BLOCKHEIGHT)], ve[x+((y+1)*BLOCKWIDTH)],
+ .hempty(he[y+((x+1)*BLOCKHEIGHT)]), .vempty(ve[x+((y+1)*BLOCKWIDTH)]),
// uempty, uin, uout,
- ve[x+(y*BLOCKWIDTH)],
- vs[(2*x)+1+(y*2*BLOCKWIDTH):(2*x)+(y*2*BLOCKWIDTH)],
- vb[(2*x)+1+(y*2*BLOCKWIDTH):(2*x)+(y*2*BLOCKWIDTH)],
+ .uempty(ve[x+(y*BLOCKWIDTH)]),
+ .uin(vs[(2*x)+1+(y*2*BLOCKWIDTH):(2*x)+(y*2*BLOCKWIDTH)]),
+ .uout(vb[(2*x)+1+(y*2*BLOCKWIDTH):(2*x)+(y*2*BLOCKWIDTH)]),
// dempty, din, dout,
- ve[x+((y+2)*BLOCKWIDTH)],
- vb[(2*x)+1+((y+1)*2*BLOCKWIDTH):(2*x)+((y+1)*2*BLOCKWIDTH)],
- vs[(2*x)+1+((y+1)*2*BLOCKWIDTH):(2*x)+((y+1)*2*BLOCKWIDTH)],
+ .dempty(ve[x+((y+2)*BLOCKWIDTH)]),
+ .din(vb[(2*x)+1+((y+1)*2*BLOCKWIDTH):(2*x)+((y+1)*2*BLOCKWIDTH)]),
+ .dout(vs[(2*x)+1+((y+1)*2*BLOCKWIDTH):(2*x)+((y+1)*2*BLOCKWIDTH)]),
// lempty, lin, lout,
- he[y+(x*BLOCKHEIGHT)],
- hs[(2*y)+1+(x*2*BLOCKHEIGHT):(2*y)+(x*2*BLOCKHEIGHT)],
- hb[(2*y)+1+(x*2*BLOCKHEIGHT):(2*y)+(x*2*BLOCKHEIGHT)],
+ .lempty(he[y+(x*BLOCKHEIGHT)]),
+ .lin(hs[(2*y)+1+(x*2*BLOCKHEIGHT):(2*y)+(x*2*BLOCKHEIGHT)]),
+ .lout(hb[(2*y)+1+(x*2*BLOCKHEIGHT):(2*y)+(x*2*BLOCKHEIGHT)]),
// rempty, rin, rout
- he[y+((x+2)*BLOCKHEIGHT)],
- hb[(2*y)+1+((x+1)*2*BLOCKHEIGHT):(2*y)+((x+1)*2*BLOCKHEIGHT)],
- hs[(2*y)+1+((x+1)*2*BLOCKHEIGHT):(2*y)+((x+1)*2*BLOCKHEIGHT)]
+ .rempty(he[y+((x+2)*BLOCKHEIGHT)]),
+ .rin(hb[(2*y)+1+((x+1)*2*BLOCKHEIGHT):(2*y)+((x+1)*2*BLOCKHEIGHT)]),
+ .rout(hs[(2*y)+1+((x+1)*2*BLOCKHEIGHT):(2*y)+((x+1)*2*BLOCKHEIGHT)])
);
end
end
diff --git a/verilog/morphle/ycell.v b/verilog/morphle/ycell.v
index 7ea24ff..bed1fa0 100644
--- a/verilog/morphle/ycell.v
+++ b/verilog/morphle/ycell.v
@@ -28,11 +28,11 @@
// of Morphle Logic. It explicitly defines 5 simple latches that
// directly change when their inputs do, so there is no clock anywhere
-module ycfsm (reset, in, match, out);
- input reset;
- input [1:0] in;
- input [1:0] match;
- output [1:0] out;
+module ycfsm (
+ input reset,
+ input [1:0] in,
+ input [1:0] match,
+ output [1:0] out);
wire [1:0] lin;
wire [1:0] nlin;
@@ -74,15 +74,13 @@
// defined and is the only thing that needs to change (not counting software)
// if the meaning needs to be changed
-module ycconfig (confclk, cbitin, cbitout,
- empty,
- hblock, hbypass, hmatch0, hmatch1,
- vblock, vbypass, vmatch0, vmatch1);
- input confclk, cbitin;
- output cbitout;
- output empty;
- output hblock, hbypass, hmatch0, hmatch1;
- output vblock, vbypass, vmatch0, vmatch1;
+module ycconfig (
+ input confclk, cbitin,
+ output cbitout,
+ output empty,
+ output hblock, hbypass, hmatch0, hmatch1,
+ output vblock, vbypass, vmatch0, vmatch1);
+
reg [8:0] r; // case needs REG even though we want a combinational circuit
assign {empty,hblock,hbypass, hmatch0, hmatch1,
vblock, vbypass, vmatch0, vmatch1} = r;
@@ -121,44 +119,39 @@
// Horizontal signals also have a L to R pair for partial results and a R to L
// pair for final results
-module ycell(reset, confclk, cbitin, cbitout,
- hempty, vempty,
- uempty, uin, uout,
- dempty, din, dout,
- lempty, lin, lout,
- rempty, rin, rout);
+module ycell(
// control
- input reset; // freezes the cell operations and clears everything
- input confclk; // a strobe to enter one configuration bit
- input cbitin; // new configuration bit from previous cell (U)
- output cbitout; // configuration bit to next cell (D)
- output hempty; // this cell interrupts horizontal signals
- output vempty; // this cell interrupts vertical signals
+ input reset, // freezes the cell operations and clears everything
+ input confclk, // a strobe to enter one configuration bit
+ input cbitin, // new configuration bit from previous cell (U)
+ output cbitout, // configuration bit to next cell (D)
+ output hempty, // this cell interrupts horizontal signals
+ output vempty, // this cell interrupts vertical signals
// UP
- input uempty; // cell U is empty, so we are the topmost of a signal
- input [1:0] uin;
- output [1:0] uout;
+ input uempty, // cell U is empty, so we are the topmost of a signal
+ input [1:0] uin,
+ output [1:0] uout,
// DOWN
- input dempty; // cell D is empty, so we are the bottommost of a signal
- input [1:0] din;
- output [1:0] dout;
+ input dempty, // cell D is empty, so we are the bottommost of a signal
+ input [1:0] din,
+ output [1:0] dout,
// LEFT
- input lempty; // cell L is empty, so we are the leftmost of a signal
- input [1:0] lin;
- output [1:0] lout;
+ input lempty, // cell L is empty, so we are the leftmost of a signal
+ input [1:0] lin,
+ output [1:0] lout,
// RIGHT
- input rempty; // cell D is empty, so we are the rightmost of a signal
- input [1:0] rin;
- output [1:0] rout;
+ input rempty, // cell D is empty, so we are the rightmost of a signal
+ input [1:0] rin,
+ output [1:0] rout);
// configuration signals decoded
wire empty;
wire hblock, hbypass, hmatch0, hmatch1;
wire vblock, vbypass, vmatch0, vmatch1;
- ycconfig cfg (confclk, cbitin, cbitout,
- empty,
- hblock, hbypass, hmatch0, hmatch1,
- vblock, vbypass, vmatch0, vmatch1);
+ ycconfig cfg (.confclk(confclk), .cbitin(cbitin), .cbitout(cbitout),
+ .empty(empty),
+ .hblock(hblock), .hbypass(hbypass), .hmatch0(hmatch0), .hmatch1(hmatch1),
+ .vblock(vblock), .vbypass(vbypass), .vmatch0(vmatch0), .vmatch1(vmatch1));
assign hempty = empty | hblock;
assign vempty = empty | vblock;
@@ -174,7 +167,7 @@
wire [1:0] hback;
wire [1:0] hmatch = {vback[1]&hmatch1,vback[0]&hmatch0};
- ycfsm hfsm (hreset, hin, hmatch, hout);
+ ycfsm hfsm (.reset(hreset), .in(hin), .match(hmatch), .out(hout));
wire [1:0] bhout = hbypass ? hin : hout;
assign rout = bhout;
assign hin = lempty ? {~(hback[1]|hback[1'b0]),1'b0} : lin;
@@ -182,7 +175,7 @@
assign lout = hback;
wire [1:0] vmatch = {hback[1]&vmatch1,hback[0]&vmatch0};
- ycfsm vfsm (vreset, vin, vmatch, vout);
+ ycfsm vfsm (.reset(vreset), .in(vin), .match(vmatch), .out(vout));
wire [1:0] bvout = vbypass ? vin : vout;
assign dout = bvout;
assign vin = uempty ? {~(vback[1]|vback[1'b0]),1'b0} : uin;
