pretty print the block and add delay in ycell to stop inifinite oscillation in simulation
diff --git a/ol_templates/config_block.tcl b/ol_templates/config_block.tcl index 8b58a5c..081de92 100755 --- a/ol_templates/config_block.tcl +++ b/ol_templates/config_block.tcl
@@ -8,17 +8,17 @@ $script_dir/../../verilog/morphle/yblock.v \ $script_dir/../../verilog/morphle/user_proj_block.v" -set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_PORT) "la_out\[112i\]" set ::env(CLOCK_PERIOD) "2000" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(CLOCK_TREE_SYNTH) 0 set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef -#set ::env(FP_SIZING) absolute -#set ::env(DIE_AREA) "0 0 2200 2200" -set ::env(FP_SIZING) relative -set ::env(FP_CORE_UTIL) 35 +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 1200 1200" +#set ::env(FP_SIZING) relative +#set ::env(FP_CORE_UTIL) 35 set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.15 +set ::env(PL_TARGET_DENSITY) 0.35
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl index 8b58a5c..081de92 100755 --- a/openlane/user_proj_example/config.tcl +++ b/openlane/user_proj_example/config.tcl
@@ -8,17 +8,17 @@ $script_dir/../../verilog/morphle/yblock.v \ $script_dir/../../verilog/morphle/user_proj_block.v" -set ::env(CLOCK_PORT) "wb_clk_i" +set ::env(CLOCK_PORT) "la_out\[112i\]" set ::env(CLOCK_PERIOD) "2000" set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg set ::env(CLOCK_TREE_SYNTH) 0 set ::env(FP_CONTEXT_DEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/floorplan/ioPlacer.def.macro_placement.def set ::env(FP_CONTEXT_LEF) $script_dir/../user_project_wrapper/runs/user_project_wrapper/tmp/merged_unpadded.lef -#set ::env(FP_SIZING) absolute -#set ::env(DIE_AREA) "0 0 2200 2200" -set ::env(FP_SIZING) relative -set ::env(FP_CORE_UTIL) 35 +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 1200 1200" +#set ::env(FP_SIZING) relative +#set ::env(FP_CORE_UTIL) 35 set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.15 +set ::env(PL_TARGET_DENSITY) 0.35
diff --git a/verilog/morphle/yblock.v b/verilog/morphle/yblock.v index a0edf07..7b7c465 100644 --- a/verilog/morphle/yblock.v +++ b/verilog/morphle/yblock.v
@@ -64,6 +64,8 @@ // vertical lines are row order, horizontal lines are column order // this makes assigning chunks much simpler + // top,right bottom,left + // \/ \/ // ----[]----[]----[]---- // 0 1 2 3 BLOCKHEIGHT+1 vcbit, he, he2, ve, ve2, rst, cclk // @@ -85,16 +87,19 @@ genvar x; genvar y; + // column BLOCKWIDTH is leftmost, 0 is rightmost + // row 0 is the topmost, BLOCKHEIGHT is bottommost + generate - for (x = 0 ; x < BLOCKWIDTH ; x = x + 1) begin : generate_columns - for (y = 0 ; y < BLOCKHEIGHT ; y = y + 1) begin : generate_rows - ycell gencell (.reset(rst[y][x]), .reseto(rst[y+1][x]), + for (x = 0 ; x < BLOCKWIDTH ; x = x + 1) begin : column + for (y = 0 ; y < BLOCKHEIGHT ; y = y + 1) begin : row + ycell yc (.reset(rst[y][x]), .reseto(rst[y+1][x]), .confclk(cclk[y][x]), .confclko(cclk[y+1][x]), // cbitin, cbitout, .cbitin(vcbit[y][x]), .cbitout(vcbit[y+1][x]), - // hempty, vempty, (L, U) + // hempty, vempty, (R, U) .hempty(he2[x][y]), .vempty(ve2[y][x]), - // hempty2, vempty2, (R, D) + // hempty2, vempty2, (L, D) .hempty2(he[x+1][y]), .vempty2(ve[y+1][x]), // uempty, uin, uout, .uempty(ve[y][x]), @@ -105,20 +110,20 @@ .din(vb[y+1][2*x+1:2*x]), .dout(vs[y+1][2*x+1:2*x]), // lempty, lin, lout, - .lempty(he[x][y]), - .lin(hs[x][2*y+1:2*y]), - .lout(hb[x][2*y+1:2*y]), + .lempty(he2[x+1][y]), + .lin(hs[x+1][2*y+1:2*y]), + .lout(hb[x+1][2*y+1:2*y]), // rempty, rin, rout - .rempty(he2[x+1][y]), - .rin(hb[x+1][2*y+1:2*y]), - .rout(hs[x+1][2*y+1:2*y]) + .rempty(he[x][y]), + .rin(hb[x][2*y+1:2*y]), + .rout(hs[x][2*y+1:2*y]) ); end end endgenerate -// he[0]---l[0]h2--he[1]----l[1]h2---he[2] -// he2[0]--h[0]r---he2[1]---h[1]r----he2[2] +// he[2]---l[1]h2--he[1]----l[0]h2---he[0] +// he2[2]--h[1]r---he2[1]---h[0]r----he2[0] // the ends of the arrays of wire go to the outside assign rst[0] = {BLOCKWIDTH{reset}}; @@ -136,16 +141,16 @@ assign dvempty = ve[BLOCKHEIGHT]; assign vb[BLOCKHEIGHT] = din; assign dout = vs[BLOCKHEIGHT]; - // LEFT - assign he[0] = lempty; - assign lhempty = he2[0]; - assign hs[0] = lin; - assign lout = hb[0]; // RIGHT - assign he2[BLOCKWIDTH] = rempty; - assign rhempty = he[BLOCKWIDTH]; - assign hb[BLOCKWIDTH] = rin; - assign rout = hs[BLOCKWIDTH]; + assign he[0] = rempty; + assign rhempty = he2[0]; + assign hb[0] = rin; + assign rout = hs[0]; + // LEFT + assign he2[BLOCKWIDTH] = lempty; + assign lhempty = he[BLOCKWIDTH]; + assign hs[BLOCKWIDTH] = lin; + assign lout = hb[BLOCKWIDTH]; endmodule
diff --git a/verilog/morphle/ycell.v b/verilog/morphle/ycell.v index dccbfcc..e10f099 100644 --- a/verilog/morphle/ycell.v +++ b/verilog/morphle/ycell.v
@@ -181,7 +181,7 @@ ycfsm hfsm (.reset(hreset), .in(hin), .match(hmatch), .out(hout)); wire [1:0] bhout = hbypass ? hin : hout; assign rout = bhout; - assign hin = lempty ? {hosc&(~(hback[1]|hback[1'b0])),1'b0} : lin; // no oscillation on reset + assign #1 hin = lempty ? {hosc&(~(hback[1]|hback[1'b0])),1'b0} : lin; // no oscillation on reset assign hback = (rempty | hempty) ? bhout : rin; // don't propagate when rightmost or empty assign lout = hback; @@ -189,7 +189,7 @@ ycfsm vfsm (.reset(vreset), .in(vin), .match(vmatch), .out(vout)); wire [1:0] bvout = vbypass ? vin : vout; assign dout = bvout; - assign vin = uempty ? {vosc&(~(vback[1]|vback[1'b0])),1'b0} : uin; // no oscillation on reset + assign #1 vin = uempty ? {vosc&(~(vback[1]|vback[1'b0])),1'b0} : uin; // no oscillation on reset assign vback = (dempty | vempty) ? bvout : din; // don't propagate when bottommost or empty assign uout = vback;
diff --git a/verilog/mtests/test005.tv b/verilog/mtests/test005.tv index b83e486..195030f 100644 --- a/verilog/mtests/test005.tv +++ b/verilog/mtests/test005.tv
@@ -69,9 +69,9 @@ // 0 0 1 1 0 0 1 1 // lsb 0 1 0 1 0 1 0 1 -C_0000_00000000_0000_00000000 // first three vectors have the output ignored to settle down -E_0000_00000000_0000_00000000 // reset everything -E_0000_00000000_0000_00000000 // msb bit 15: ................ +8_0000_00000000_0000_00000000 // ignore outputs until first configuration is in +A_0000_00000000_0000_00000000 // reset everything +A_0000_00000000_0000_00000000 // msb bit 15: ................ B_0000_00000000_0000_00000000 A_0000_00000000_0000_00000000 // middle bit B_0000_00000000_0000_00000000 @@ -168,4 +168,5 @@ A_2600_00000000_0000_00000000 // lsb bit B_2600_00000000_0000_00000000 0_0000_00000000_0000_00000000 // normal operation! -0_0000_15A80000_0000_15000000 // inject E0 00 11 1E EE EE EE EE +4_0000_15A80000_0000_15000000 // inject E0 00 11 1E EE EE EE EE and print +4_0000_00000000_0000_00000000 // normal operation and print
diff --git a/verilog/mtests/test005upblock.v b/verilog/mtests/test005upblock.v index 90e010b..93f4619 100644 --- a/verilog/mtests/test005upblock.v +++ b/verilog/mtests/test005upblock.v
@@ -36,6 +36,7 @@ reg [51:0] tvout; reg [47:0] xtvin; + integer r, c; // for printing rows and columns reg[31:0] vectornum, errors; // bookkeeping variables reg[99:0] testvectors[10000:0];// array of testvectors/ @@ -121,7 +122,6 @@ always @(posedge clk) begin #1; {tvout,xtvin} = testvectors[vectornum][99:0]; - $display("just read vector %d %h %h", vectornum, tvout, xtvin); if (xtvin === 48'bx) begin $display("%d tests completed with %d errors", vectornum-1, errors); @@ -130,13 +130,23 @@ end wire reset = la_data_in[113]; - + + wire [2:0] cfg [0:15][0:15]; + + genvar row, col; + generate + for (row = 0; row < 16; row = row + 1) begin : vertical + for (col = 0; col < 16; col = col + 1) begin : horizontal + assign cfg[row][col] = DUT.blk.column[col].row[row].yc.cfg.cnfg; + end + end + endgenerate + // check results on falling edge of clk always @(negedge clk) begin - $display("testing vector %d %h %h", vectornum, tvout, xtvin); - if ((!tvout[51] & la_data_out[47:32] !== xtvin[47:32]) | - (!tvout[50] & la_data_out[31:0] !== xtvin[31:0])) + $display("testing vector %d", vectornum); + if ((!tvout[51] & la_data_out[47:0] !== xtvin[47:0])) begin $display("Error: sent = %b %b %h %h", la_data_in[113], la_data_in[112], la_data_in[111:96], la_data_in[95:64]); @@ -145,35 +155,48 @@ xtvin[47:32], xtvin[31:0]); errors = errors + 1; end - $display(" u0 = %b %b", DUT.blk.vs[0], DUT.blk.vb[0]); - $display(" u1 = %b %b", DUT.blk.vs[1], DUT.blk.vb[1]); - $display(" u2 = %b %b", DUT.blk.vs[2], DUT.blk.vb[2]); - $display(" u3 = %b %b", DUT.blk.vs[3], DUT.blk.vb[3]); - $display(" l8 = %b %b", DUT.blk.hs[8], DUT.blk.hb[8]); - $display(" l9 = %b %b", DUT.blk.hs[9], DUT.blk.hb[9]); - $display(" l10 = %b %b", DUT.blk.hs[10], DUT.blk.hb[10]); - $display(" l11 = %b %b", DUT.blk.hs[11], DUT.blk.hb[11]); - $display(" l12 = %b %b", DUT.blk.hs[12], DUT.blk.hb[12]); - $display(" l13 = %b %b", DUT.blk.hs[13], DUT.blk.hb[13]); - $display(" l14 = %b %b", DUT.blk.hs[14], DUT.blk.hb[14]); - $display(" l15 = %b %b", DUT.blk.hs[15], DUT.blk.hb[15]); - $display(" r15 = %b %b", DUT.blk.hs[16], DUT.blk.hb[16]); - $display(" ve0 = %b", DUT.blk.ve[0]); - $display(" ve1 = %b", DUT.blk.ve[1]); - $display(" ve2 = %b", DUT.blk.ve[2]); - $display(" ve3 = %b", DUT.blk.ve[3]); - $display(" he8 = %b", DUT.blk.he[8]); - $display(" he9 = %b", DUT.blk.he[9]); - $display(" he10 = %b", DUT.blk.he[10]); - $display(" he11 = %b", DUT.blk.he[11]); - $display(" he12 = %b", DUT.blk.he[12]); - $display(" he13 = %b", DUT.blk.he[13]); - $display(" he14 = %b", DUT.blk.he[14]); - $display(" he15 = %b", DUT.blk.he[15]); - $display(" he16 = %b", DUT.blk.he[16]); + if (tvout[50]) // set this bit to pretty print cells + begin + for (r = 0; r < 6; r = r + 1) begin // top to bottom + for (c = 15; c > 1; c = c - 1) begin // left to right + $write(" %b%b %b%b ", DUT.blk.vs[r][1+2*c], DUT.blk.vs[r][2*c], + DUT.blk.vb[r][1+2*c], DUT.blk.vb[r][2*c]); + end + $display(" "); + for (c = 15; c > 1; c = c - 1) begin // left to right + $write(" +--%b--+", DUT.blk.ve2[r][c]); + end + $display(" "); + for (c = 15; c > 1; c = c - 1) begin // left to right + $write("%b%b| |", DUT.blk.hb[c+1][1+2*r], DUT.blk.hb[c+1][2*r]); + end + $display(" "); + for (c = 15; c > 1; c = c - 1) begin // left to right + $write(" %b ", DUT.blk.he2[c][r]); + if (cfg[r][c] == 3'b000) $write("."); + else if (cfg[r][c] == 3'b001) $write("+"); + else if (cfg[r][c] == 3'b010) $write("-"); + else if (cfg[r][c] == 3'b011) $write("|"); + else if (cfg[r][c] == 3'b100) $write("1"); + else if (cfg[r][c] == 3'b101) $write("0"); + else if (cfg[r][c] == 3'b110) $write("Y"); + else if (cfg[r][c] == 3'b111) $write("N"); + else $write("?"); + $write(" %b", DUT.blk.he2[c][r]); + end + $display(" "); + for (c = 15; c > 1; c = c - 1) begin // left to right + $write("%b%b| |", DUT.blk.hs[c+1][1+2*r], DUT.blk.hs[c+1][2*r]); + end + $display(" "); + for (c = 15; c > 1; c = c - 1) begin // left to right + $write(" +--%b--+", DUT.blk.ve[r+1][c]); + end + $display(" "); + end + end // increment array index and read next testvector vectornum= vectornum + 1; - $display("testing vector %d next", vectornum); end endmodule