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foss-eda-tools/third_party/shuttle/sky130/mpw-001/slot-014/7828bfebf197f7dedf496cb4a9447dc82d0cf925^!/.
commit
7828bfebf197f7dedf496cb4a9447dc82d0cf925
[log]
author
Tim Edwards <tim@opencircuitdesign.com>
Mon Oct 19 15:58:25 2020 -0400
committer
Tim Edwards <tim@opencircuitdesign.com>
Mon Oct 19 15:58:25 2020 -0400
tree
77f58827c6d18bbb87dff16e4cffc8ad415fa1c1
parent
aef447b3af603bf68b77c876219946c6cdff8849 [diff]
Updated testbenches to declare 38 bits for the user project GPIO pins.

diff --git a/verilog/dv/caravel/defs.h b/verilog/dv/caravel/defs.h
index a62d314..96630f1 100644
--- a/verilog/dv/caravel/defs.h
+++ b/verilog/dv/caravel/defs.h

@@ -83,6 +83,7 @@
 #define reg_mprj_io_34 (*(volatile uint32_t*)0x26000094)
 #define reg_mprj_io_35 (*(volatile uint32_t*)0x26000098)
 #define reg_mprj_io_36 (*(volatile uint32_t*)0x2600009c)
+#define reg_mprj_io_37 (*(volatile uint32_t*)0x260000a0)
 
 // Mega Project Slaves (0x3000_0000)
 #define reg_mprj_slave (*(volatile uint32_t*)0x30000000)

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
index 5a0c95d..49bbb0c 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
index 7932cbd..349cac9 100644
--- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v

@@ -50,7 +50,7 @@
 		$finish;
 	end
 
-	wire [36:0] mprj_io;	// Most of these are no-connects
+	wire [37:0] mprj_io;	// Most of these are no-connects
 	wire [15:0] checkbits;
 	reg  [7:0] checkbits_lo;
 	wire [7:0] checkbits_hi;

diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
index 91e36f1..4a8b066 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile

@@ -4,7 +4,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
index dd1aca2..5d7fd11 100644
--- a/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/hkspi/hkspi_tb.v

@@ -15,7 +15,7 @@
 
 	wire gpio;
 	wire [15:0] checkbits;
-	wire [36:0] mprj_io;
+	wire [37:0] mprj_io;
 	wire uart_tx;
 	wire uart_rx;
 

diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile
index 1b791ce..49a3f73 100644
--- a/verilog/dv/caravel/mgmt_soc/mem/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile

@@ -4,7 +4,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
index 8565a6b..b6c9889 100644
--- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile

@@ -4,7 +4,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
index 2d91c92..a902f21 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/Makefile

@@ -4,7 +4,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
index e741a29..ef215a2 100644
--- a/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pass_thru/pass_thru_tb.v

@@ -15,7 +15,7 @@
 
 	wire gpio;
 	wire [15:0] checkbits;
-	wire [36:0] mprj_io;
+	wire [37:0] mprj_io;
 	wire uart_tx;
 	wire uart_rx;
 

diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile
index e885eb4..4c24533 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
index c5721f9..ca86f6d 100644
--- a/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/perf/perf_tb.v

@@ -30,7 +30,7 @@
 
 	wire gpio;
 	wire [15:0] checkbits;
-	wire [36:0] mprj_io;
+	wire [37:0] mprj_io;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;

diff --git a/verilog/dv/caravel/mgmt_soc/pll/Makefile b/verilog/dv/caravel/mgmt_soc/pll/Makefile
index 31bac9e..4a5dfc8 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/pll/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
index 613364b..d9448e9 100644
--- a/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/pll/pll_tb.v

@@ -13,7 +13,7 @@
 	wire gpio;
 	wire [15:0] checkbits;
 	wire [7:0] spivalue;
-	wire [36:0] mprj_io;
+	wire [37:0] mprj_io;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;

diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
index d07464b..dd83951 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
index 6fb2f69..b22309e 100644
--- a/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/sysctrl/sysctrl_tb.v

@@ -12,7 +12,7 @@
 	wire gpio;
 	wire [15:0] checkbits;
 	wire [7:0] spivalue;
-	wire [36:0] mprj_io;
+	wire [37:0] mprj_io;
 	wire flash_csb;
 	wire flash_clk;
 	wire flash_io0;

diff --git a/verilog/dv/caravel/mgmt_soc/timer/Makefile b/verilog/dv/caravel/mgmt_soc/timer/Makefile
index 0f0bdb9..4a67c44 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer.c b/verilog/dv/caravel/mgmt_soc/timer/timer.c
index 131de72..4b49f4f 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer.c
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer.c

@@ -15,12 +15,13 @@
 	reg_mprj_datah = 0x00000000;
 	reg_mprj_datal = 0x00000000;
 
-	/* Apply all 37 bits to management standard output.	*/
+	/* Apply all 38 bits to management standard output.	*/
 
 	/* The lower 32 will be used to output the count value	*/
 	/* from the timer.  The top 5 bits will be used	to mark	*/
 	/* specific checkpoints for the testbench simulation.	*/
 
+	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index c41fb6d..5218ee3 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v

@@ -50,11 +50,11 @@
 		$finish;
 	end
 
-	wire [36:0] mprj_io;	// Most of these are no-connects
-	wire [4:0] checkbits;
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [5:0] checkbits;
 	wire [31:0] countbits;
 
-	assign checkbits = mprj_io[36:32];
+	assign checkbits = mprj_io[37:32];
 	assign countbits = mprj_io[31:0];
 
 	wire flash_csb;
@@ -64,35 +64,35 @@
 
 	// Monitor
 	initial begin
-		wait(checkbits == 5'h0a);
+		wait(checkbits == 6'h0a);
 		$display("Monitor: Test Timer (RTL) Started");
 
 		/* Add checks here */
-		wait(checkbits == 5'h01);
+		wait(checkbits == 6'h01);
 		$display("   countbits = 0x%x (should be 0xdcba7eb0)", countbits);
 		if(countbits !== 32'hdcba7eb0) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h02);
+		wait(checkbits == 6'h02);
 		$display("   countbits = 0x%x (should be 0x10)", countbits);
 		if(countbits !== 32'h10) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h03);
+		wait(checkbits == 6'h03);
 		$display("   countbits = %x (should be 0x0c)", countbits);
 		if(countbits !== 32'h0c) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h04);
+		wait(checkbits == 6'h04);
 		$display("   countbits = %x (should be 0x0c)", countbits);
 		if(countbits !== 32'h0c) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h05);
+		wait(checkbits == 6'h05);
 		$display("   countbits = %x (should be 0x117c)", countbits);
 		if(countbits !== 32'h117c) begin
 		    $display("Monitor: Test Timer (RTL) Failed");

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/Makefile b/verilog/dv/caravel/mgmt_soc/timer2/Makefile
index 9fdcf04..4255a9b 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/timer2/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2.c b/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
index 12c480f..2994082 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2.c
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2.c

@@ -16,12 +16,13 @@
 	reg_mprj_datah = 0x00000000;
 	reg_mprj_datal = 0x00000000;
 
-	/* Apply all 37 bits to management standard output.	*/
+	/* Apply all 38 bits to management standard output.	*/
 
 	/* The lower 32 will be used to output the count value	*/
 	/* from the timer.  The top 5 bits will be used	to mark	*/
 	/* specific checkpoints for the testbench simulation.	*/
 
+	reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
 	reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index cd04097..39e06cc 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v

@@ -50,11 +50,11 @@
 		$finish;
 	end
 
-	wire [36:0] mprj_io;	// Most of these are no-connects
-	wire [4:0] checkbits;
+	wire [37:0] mprj_io;	// Most of these are no-connects
+	wire [5:0] checkbits;
 	wire [31:0] countbits;
 
-	assign checkbits = mprj_io[36:32];
+	assign checkbits = mprj_io[37:32];
 	assign countbits = mprj_io[31:0];
 
 	wire flash_csb;
@@ -64,35 +64,35 @@
 
 	// Monitor
 	initial begin
-		wait(checkbits == 5'h0a);
+		wait(checkbits == 6'h0a);
 		$display("Monitor: Test Timer2 (RTL) Started");
 
 		/* Add checks here */
-		wait(checkbits == 5'h01);
+		wait(checkbits == 6'h01);
 		$display("   countbits = 0x%x (should be 0xdcba7eb0)", countbits);
 		if(countbits !== 32'hdcba7eb0) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h02);
+		wait(checkbits == 6'h02);
 		$display("   countbits = 0x%x (should be 0x10)", countbits);
 		if(countbits !== 32'h10) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h03);
+		wait(checkbits == 6'h03);
 		$display("   countbits = %x (should be 0x0c)", countbits);
 		if(countbits !== 32'h0c) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h04);
+		wait(checkbits == 6'h04);
 		$display("   countbits = %x (should be 0x0c)", countbits);
 		if(countbits !== 32'h0c) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
-		wait(checkbits == 5'h05);
+		wait(checkbits == 6'h05);
 		$display("   countbits = %x (should be 0x117c)", countbits);
 		if(countbits !== 32'h117c) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");

diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile
index e6fd284..cde1104 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/Makefile
+++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile

@@ -4,7 +4,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
index 6907155..7d4237a 100644
--- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v

@@ -34,7 +34,7 @@
 	wire flash_clk;
 	wire flash_io0;
 	wire flash_io1;
-	wire [36:0] mprj_io;
+	wire [37:0] mprj_io;
 	wire [15:0] checkbits;
 	wire uart_tx;
 	wire SDO;

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index 2d5a749..0f0482b 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 741a982..0205af3 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

@@ -11,7 +11,7 @@
 	reg power3, power4;
 
     	wire gpio;
-    	wire [36:0] mprj_io;
+    	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 
 	assign mprj_io_0 = mprj_io[7:0];

diff --git a/verilog/dv/caravel/user_proj_example/la_test1/Makefile b/verilog/dv/caravel/user_proj_example/la_test1/Makefile
index b026dbc..a258d8c 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/Makefile
+++ b/verilog/dv/caravel/user_proj_example/la_test1/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
index 9bee0a6..b378e1a 100644
--- a/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test1/la_test1_tb.v

@@ -12,7 +12,7 @@
 
     	wire gpio;
 	wire uart_tx;
-    	wire [36:0] mprj_io;
+    	wire [37:0] mprj_io;
 	wire [15:0] checkbits;
 
 	assign checkbits  = mprj_io[31:16];

diff --git a/verilog/dv/caravel/user_proj_example/la_test2/Makefile b/verilog/dv/caravel/user_proj_example/la_test2/Makefile
index 397a862..1b3823c 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/Makefile
+++ b/verilog/dv/caravel/user_proj_example/la_test2/Makefile

@@ -3,7 +3,7 @@
 IP_PATH = ../../../../ip
 BEHAVIOURAL_MODELS = ../../ 
 
-GCC_PATH=/ef/apps/bin
+GCC_PATH?=/ef/apps/bin
 PDK_PATH?=/ef/tech/SW/sky130A
 
 .SUFFIXES:

diff --git a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
index 54b671f..96833b8 100644
--- a/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v
+++ b/verilog/dv/caravel/user_proj_example/la_test2/la_test2_tb.v

@@ -10,7 +10,7 @@
 	reg power1, power2;
 
     	wire gpio;
-    	wire [36:0] mprj_io;
+    	wire [37:0] mprj_io;
 	wire [15:0] checkbits;
 
 	assign checkbits = mprj_io[31:16];

diff --git a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
index 2ec5f96..b4fc6a5 100644
--- a/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v
+++ b/verilog/dv/wb_utests/sysctrl_wb/sysctrl_wb_tb.v

@@ -18,8 +18,6 @@
 	wire wb_ack_o;
 	wire [31:0] wb_dat_o;
     
-    reg overtemp;
-
     initial begin
         wb_clk_i = 0; 
         wb_rst_i = 0;

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index b10928c..e5af073 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v

@@ -16,7 +16,7 @@
 `define USE_POWER_PINS
 `define UNIT_DELAY #1
 
-`define MPRJ_IO_PADS 37
+`define MPRJ_IO_PADS 38
 `define MPRJ_PWR_PADS 4		/* vdda1, vccd1, vdda2, vccd2 */
 
 `include "pads.v"

diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 1edc2dc..d010e77 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v

@@ -20,7 +20,7 @@
  */
 
 module user_proj_example #(
-    parameter IO_PADS = 37,
+    parameter IO_PADS = 38,
     parameter PWR_PADS = 4,
     parameter BITS = 32
 )(

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 841ef64..b37d2e5 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -14,7 +14,7 @@
  */
 
 module user_project_wrapper #(
-    parameter IO_PADS = 37,
+    parameter IO_PADS = 38,
     parameter PWR_PADS = 4,
     parameter BITS = 32
 )(