| Notice 0: Reading LEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/merged.lef |
| Notice 0: Created 13 technology layers |
| Notice 0: Created 25 technology vias |
| Notice 0: Created 437 library cells |
| Notice 0: Finished LEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/merged.lef |
| Notice 0: |
| Reading DEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/floorplan/verilog2def_openroad.def |
| Notice 0: Design: ycell |
| Notice 0: Created 26 pins. |
| Notice 0: Created 106 components and 757 component-terminals. |
| Notice 0: Created 121 nets and 333 connections. |
| Notice 0: Finished DEF file: /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/floorplan/verilog2def_openroad.def |
| Top-level design name: ycell |
| Block boundaries: 0 0 67490 78210 |
| Writing /project/openlane/morphle_ycell/runs/morphle_ycell/tmp/floorplan/ioPlacer.def |
