Some minor updates to the testbench Makefiles and verilog.
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/Makefile b/verilog/dv/caravel/mgmt_soc/gpio/Makefile index 95fcbf5..dd34c59 100644 --- a/verilog/dv/caravel/mgmt_soc/gpio/Makefile +++ b/verilog/dv/caravel/mgmt_soc/gpio/Makefile
@@ -14,7 +14,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c index 0d9caf5..4dbacc6 100644 --- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.c +++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.c
@@ -4,35 +4,35 @@ /* GPIO Test - Tests PU and PD on the lower 8 pins while being driven from outside - Tests Writing to the upper 8 pins - Tests reading from the lower 8 pins + Tests PU and PD on the lower 2 pins while being driven from outside + Tests Writing to the upper 2 pins + Tests reading from the lower 2 pins */ void main() { int i; - /* Lower 8 pins are input and upper 8 pins are o/p */ + /* Lower 2 pins are input and upper 2 pins are o/p */ reg_gpio_data = 0; - reg_gpio_ena = 0x00ff; + reg_gpio_ena = 0x0003; // change the pull up and pull down (checked by the TB) - reg_gpio_data = 0xA000; - reg_gpio_pu = 0x000f; - reg_gpio_pd = 0x00f0; + reg_gpio_data = 0x0100; + reg_gpio_pu = 0x0001; + reg_gpio_pd = 0x0002; - reg_gpio_data = 0x0B00; - reg_gpio_pu = 0x00f0; - reg_gpio_pd = 0x000f; + reg_gpio_data = 0x0300; + reg_gpio_pu = 0x0002; + reg_gpio_pd = 0x0001; - reg_gpio_pu = 0x000f; - reg_gpio_pd = 0x00f0; + reg_gpio_pu = 0x0001; + reg_gpio_pd = 0x0002; - // read the lower 8 pins, add 1 then o/p the result + // read the lower 2 pins, add 1 then o/p the result // checked by the TB - reg_gpio_data = 0xAB00; + reg_gpio_data = 0x0100; while (1){ - int x = reg_gpio_data & 0xff; + int x = reg_gpio_data & 0x03; reg_gpio_data = (x+1) << 8; } }
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex b/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex index dd2e7fe..667a214 100755 --- a/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex +++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio.hex
@@ -6,7 +6,7 @@ 13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 -13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 05 17 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 16 93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28 @@ -20,13 +20,12 @@ 23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 A3 81 62 00 82 80 01 00 00 00 01 11 22 CE 00 10 -B7 07 00 21 23 A0 07 00 B7 07 00 21 91 07 13 07 -F0 0F 98 C3 B7 07 00 21 29 67 98 C3 B7 07 00 21 -A1 07 3D 47 98 C3 B7 07 00 21 B1 07 13 07 00 0F -98 C3 B7 07 00 21 05 67 13 07 07 B0 98 C3 B7 07 -00 21 A1 07 13 07 00 0F 98 C3 B7 07 00 21 B1 07 -3D 47 98 C3 B7 07 00 21 A1 07 3D 47 98 C3 B7 07 -00 21 B1 07 13 07 00 0F 98 C3 B7 07 00 21 2D 67 -13 07 07 B0 98 C3 B7 07 00 21 9C 43 93 F7 F7 0F -23 26 F4 FE 83 27 C4 FE 85 07 13 97 87 00 B7 07 -00 21 98 C3 CD B7 00 00 +B7 07 00 21 23 A0 07 00 B7 07 00 21 91 07 0D 47 +98 C3 B7 07 00 21 13 07 00 10 98 C3 B7 07 00 21 +A1 07 05 47 98 C3 B7 07 00 21 B1 07 09 47 98 C3 +B7 07 00 21 13 07 00 30 98 C3 B7 07 00 21 A1 07 +09 47 98 C3 B7 07 00 21 B1 07 05 47 98 C3 B7 07 +00 21 A1 07 05 47 98 C3 B7 07 00 21 B1 07 09 47 +98 C3 B7 07 00 21 13 07 00 10 98 C3 B7 07 00 21 +9C 43 8D 8B 23 26 F4 FE 83 27 C4 FE 85 07 13 97 +87 00 B7 07 00 21 98 C3 D5 B7 00 00
diff --git a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v index fa095eb..41856ac 100644 --- a/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v +++ b/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v
@@ -20,8 +20,6 @@ `timescale 1 ns / 1 ps -`define FUNCTIONAL - `include "caravel.v" `include "spiflash.v" @@ -128,7 +126,7 @@ .vdd3v3 (VDD3V3), .vdd1v8 (VDD1V8), .vss (VSS), - .clock (CLOCK), + .clock (clock), .SDI (SDI), .SDO (SDO), .CSB (CSB),
diff --git a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile index 18a1606..31a859c 100644 --- a/verilog/dv/caravel/mgmt_soc/hkspi/Makefile +++ b/verilog/dv/caravel/mgmt_soc/hkspi/Makefile
@@ -14,7 +14,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/mem/Makefile b/verilog/dv/caravel/mgmt_soc/mem/Makefile index 3f25ca2..02e036b 100644 --- a/verilog/dv/caravel/mgmt_soc/mem/Makefile +++ b/verilog/dv/caravel/mgmt_soc/mem/Makefile
@@ -15,7 +15,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile index ed08e54..e60de7e 100644 --- a/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile +++ b/verilog/dv/caravel/mgmt_soc/mprj_ctrl/Makefile
@@ -14,7 +14,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/perf/Makefile b/verilog/dv/caravel/mgmt_soc/perf/Makefile index bb9c3ba..00c9aee 100644 --- a/verilog/dv/caravel/mgmt_soc/perf/Makefile +++ b/verilog/dv/caravel/mgmt_soc/perf/Makefile
@@ -14,7 +14,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile index dbd8e0d..28c604b 100644 --- a/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile +++ b/verilog/dv/caravel/mgmt_soc/sysctrl/Makefile
@@ -14,7 +14,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/uart/Makefile b/verilog/dv/caravel/mgmt_soc/uart/Makefile index 835a68f..0957ab9 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/Makefile +++ b/verilog/dv/caravel/mgmt_soc/uart/Makefile
@@ -15,7 +15,7 @@ hex: ${PATTERN:=.hex} %.vvp: %_tb.v %.hex - iverilog -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ + iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS)-I $(IP_PATH) -I $(RTL_PATH) \ $< -o $@ %.vcd: %.vvp
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.c b/verilog/dv/caravel/mgmt_soc/uart/uart.c index bf21144..bd4b67d 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/uart.c +++ b/verilog/dv/caravel/mgmt_soc/uart/uart.c
@@ -1,5 +1,5 @@ #include "../../defs.h" -#include "../stub.c" +#include "../../stub.c" // -------------------------------------------------------- @@ -12,16 +12,16 @@ // Divided by clkdiv is 64 kHz // So at this crystal rate, use clkdiv = 4167 for 9600 baud. - /* All GPIO pins are configured to be output */ + /* Both GPIO pins are configured to be output */ reg_gpio_data = 0; reg_gpio_ena = 0x0000; // start test - reg_gpio_data = 0xA000; + reg_gpio_data = 0x0001; // This should appear at the output, received by the testbench UART. print("\n"); print("Monitor: Test UART (RTL) passed\n\n"); - reg_gpio_data = 0xAB00; + reg_gpio_data = 0x0002; }
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart.hex b/verilog/dv/caravel/mgmt_soc/uart/uart.hex new file mode 100755 index 0000000..bb0c729 --- /dev/null +++ b/verilog/dv/caravel/mgmt_soc/uart/uart.hex
@@ -0,0 +1,36 @@ +@00000000 +93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00 +13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00 +13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00 +13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00 +13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 +13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 +13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 1B +93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 +11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 +63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 11 22 +01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00 +A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00 +23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3 +F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F +00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01 +93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00 +93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00 +23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC +FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08 +A3 81 62 00 82 80 01 00 00 00 01 11 06 CE 22 CC +00 10 AA 87 A3 07 F4 FE 03 47 F4 FE A9 47 63 14 +F7 00 35 45 DD 37 B7 07 00 20 91 07 03 47 F4 FE +98 C3 01 00 F2 40 62 44 05 61 82 80 01 11 06 CE +22 CC 00 10 23 26 A4 FE 19 A8 83 27 C4 FE 13 87 +17 00 23 26 E4 FE 83 C7 07 00 3E 85 7D 37 83 27 +C4 FE 83 C7 07 00 F5 F3 01 00 F2 40 62 44 05 61 +82 80 41 11 06 C6 22 C4 00 08 B7 07 00 20 13 07 +10 27 98 C3 B7 07 00 21 23 A0 07 00 B7 07 00 21 +91 07 23 A0 07 00 B7 07 00 21 05 47 98 C3 B7 07 +00 10 13 85 47 20 59 3F B7 07 00 10 13 85 87 20 +71 37 B7 07 00 21 09 47 98 C3 01 00 B2 40 22 44 +41 01 82 80 0A 00 00 00 4D 6F 6E 69 74 6F 72 3A +20 54 65 73 74 20 55 41 52 54 20 28 52 54 4C 29 +20 70 61 73 73 65 64 0A 0A 00 00 00
diff --git a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v index 80bc0b4..4f879fe 100644 --- a/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v +++ b/verilog/dv/caravel/mgmt_soc/uart/uart_tb.v
@@ -50,7 +50,7 @@ $display("Wait for UART o/p"); repeat (150) begin - repeat (10000) @(posedge XCLK); + repeat (10000) @(posedge clock); // Diagnostic. . . interrupts output pattern. end $finish;