change Morphle Logic ASCII representation to use period instead of space for blank cells
diff --git a/README.md b/README.md
index c623c10..e264dfb 100644
--- a/README.md
+++ b/README.md
@@ -39,6 +39,10 @@
make copy_config_block
+If you need a reminder of the possible targets for *make* just do:
+
+ make help
+
If the various PDK packages have been installed with the correct versions then this step can be skipped:
make pdk
diff --git a/README_MORPHLE_LOGIC.md b/README_MORPHLE_LOGIC.md
index cf76695..c140b96 100644
--- a/README_MORPHLE_LOGIC.md
+++ b/README_MORPHLE_LOGIC.md
@@ -29,7 +29,7 @@
Each cell can be configured to one of eight values, which we represent with a character:
- 0. space: the default state, it is used to isolate different circuits
+ 0. .: the default state is a blank cell used to isolate different circuits
1. +: this allows signals to cross this cell vertically and horizontally without interfering with each other
2. -: this allows signals to cross this cell horizontally
3. |: this allows signals to cross this cell vertically
@@ -42,10 +42,10 @@
Here is an example of a two bit half adder:
- ||
- 00N
+ ||..
+ 00N.
11NY
- ||
+ ..||
The first and last lines use | to make it easier to see where the two inputs are coming in from the top and the two outputs (sum and carry, respectively) are going out the bottom. In a real circuit they probably wouldn't be needed as you can normally connect two circuits by just placing them next to each other.
@@ -80,16 +80,16 @@
A two bit full adder could receive its data from the network are return its results to the network:
- ab ab
- N00 N00
- NN11 NN11
- || ||
- |0N0 |0N0
- N1N1 N1N1
- | |Y-0 ||
- | | ||
- | | ||
- t s sc
+ ..ab...ab
+ .N00..N00
+ NN11.NN11
+ ||...||..
+ |0N0.|0N0
+ N1N1.N1N1
+ |.|Y-0.||
+ |.|....||
+ |.|....||
+ t.s....sc
Note that rows and columns can easily be swapped to help match the outputs of a circuit to the inputs of the next circuit.
@@ -113,6 +113,6 @@
## Files
Besides all the files in the Caravel project, the Morphle Logic specific hardware description can
-be found in "verilog/morphle/" and that includes all tests.
+be found in "verilog/morphle/" and that includes all tests. They are explained in the [README](verilog/morphle/README.md) file in that directory.
diff --git a/verilog/morphle/README.md b/verilog/morphle/README.md
index f2ca086..b0e3e3f 100644
--- a/verilog/morphle/README.md
+++ b/verilog/morphle/README.md
@@ -17,9 +17,16 @@
--->
# Verilog files specific to Morphle Logic
+Pairs of files are used for each possible project to be included in the Caravel chip. One is a Verilog file that is used to generate *user_proj_example.gds* (the name must be this as it is what *user_project_wrapper* expects) and the other is a Tcl configuration file that must be copied to *../../openlane/user_proj_example/config.tcl* so openlane can do its job.
+
+- *user_proj_block.v* and *user_proj_block.v* connect a single 16x16 yblock cell to the Caravel logic analyzer pins. It also attaches a dummy circuit to the Wishbone interface, but leaves all io pins dangling (so ignore warnings about that).
+
## library
-The main library file *morphlelogic.v* contains the building blocks for Morphle Logic, with the basic element being *ycell* ("yellow cell", named so because of the first illustrations) and *yblock* just being an array of ycells of the specified BLOCKWIDTH and BLOCKHEIGHT. Besides connecting the ycells to each other, yblock connects the wires at the edges of the array to ports so it can be used as a component in a larger system.
+The main library contains the building blocks for Morphle Logic:
+
+- *ycell.v*: the basic element is *ycell* ("yellow cell", named so because of the first illustrations)
+- *yblock.v*: *yblock* just being an array of ycells of the specified BLOCKWIDTH and BLOCKHEIGHT. Besides connecting the ycells to each other, yblock connects the wires at the edges of the array to ports so it can be used as a component in a larger system.
## Tests
