blob: bb4477c434e931f64b19a2f27bd86db2d889e094 [file] [log] [blame]
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) gpio_control_block
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v\
$script_dir/../../verilog/rtl/gpio_control_block.v"
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(CLOCK_PORT) "serial_clock"
set ::env(CLOCK_PERIOD) "10"
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 50 125"