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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-014 / 53bee22af8a612b16be4339e2039b56d752278b9
commit53bee22af8a612b16be4339e2039b56d752278b9[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Sun Oct 11 14:52:01 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Sun Oct 11 14:52:01 2020 -0400
treef827e9686bb80664fa0e425f1e121ef33c31002e
parent514dfd83c9d8143c6fb3a0cddff9b9abee15d09e [diff]
Made a change to all of the testbench Makefiles to define PDK_PATH as the
root of the PDK, and pass this to iverilog with the -I option.  This lets
the PDK location be passed to "make" when the testbench is run, and lets
the top-level verilog not contain absolute paths to the PDK.  Also:
replaced the s8iom0s8.v with sky130_fd_io.v, which is currently just a
hack since the pad names have not changed;  I have just copied my I/O
library file to the new location and file name.
15 files changed
tree: f827e9686bb80664fa0e425f1e121ef33c31002e
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.