verilog/dv/README.md

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# DV Tests

Organized into two subdirectories:
  * caravel: contains tests for both the mangement SoC and an example user project.
  * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus

<pre>
├── caravel
│   ├── mgmt_soc
│   ├── user_proj_example
└── wb_utests
</pre>