Matt Venn | 08cd6eb | 2020-11-16 12:01:14 +0100 | [diff] [blame] | 1 | `default_nettype none |
Ahmed Ghazy | 22d29d6 | 2020-10-28 03:42:02 +0200 | [diff] [blame] | 2 | // Global parameters |
| 3 | |
| 4 | `define MPRJ_IO_PADS 38 |
| 5 | `define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */ |
| 6 | |
| 7 | // Size of soc_mem_synth |
Ahmed Ghazy | 22d29d6 | 2020-10-28 03:42:02 +0200 | [diff] [blame] | 8 | |
| 9 | // Type and size of soc_mem |
Manar | ec9b536 | 2020-10-28 22:24:06 +0200 | [diff] [blame] | 10 | // `define USE_OPENRAM |
Manar | 68e0363 | 2020-11-09 13:25:13 +0200 | [diff] [blame] | 11 | `define USE_CUSTOM_DFFRAM |
Ahmed Ghazy | 2517fa8 | 2020-11-08 23:34:41 +0200 | [diff] [blame] | 12 | // don't change the following without double checking addr widths |
Ahmed Ghazy | 22d29d6 | 2020-10-28 03:42:02 +0200 | [diff] [blame] | 13 | `define MEM_WORDS 256 |
Manar | 55ec369 | 2020-10-30 16:32:18 +0200 | [diff] [blame] | 14 | |
Manar | 8f13179 | 2020-11-11 16:38:32 +0200 | [diff] [blame] | 15 | // Number of columns in the custom memory; takes one of three values: |
| 16 | // 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB |
| 17 | `define COLS 1 |
| 18 | |
Manar | ffe6cad | 2020-11-09 19:09:04 +0200 | [diff] [blame] | 19 | // not really parameterized but just to easily keep track of the number |
| 20 | // of ram_block across different modules |
manarabdelaty | 08dd483 | 2020-12-03 19:27:08 +0200 | [diff] [blame] | 21 | `define RAM_BLOCKS 2 |
| 22 | |
| 23 | // Clock divisor default value |
manarabdelaty | 589a528 | 2020-12-05 01:06:48 +0200 | [diff] [blame] | 24 | `define CLK_DIV 3'b010 |
| 25 | |
| 26 | // GPIO conrol default mode and enable |
| 27 | `define DM_INIT 3'b110 |
| 28 | `define OENB_INIT 1'b1 |