stimulate step

rapcores

diff --git a/rapcores b/rapcores
index 803f182..83d0ccc 160000
--- a/rapcores
+++ b/rapcores
@@ -1 +1 @@
-Subproject commit 803f182e81aad5dba582ca407086309232ce0112
+Subproject commit 83d0cccd51d5a763c472f1de42092bfd3443c0b3

verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index 4725a80..362a9e8 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -186,7 +186,7 @@
             analog_cmp1 <= 1;
             analog_cmp2 <= 1;
             step <= 1;
-            //step_clock = 0;
+            step_clock <= 40'b0;
         end
         else begin
             cnt <= cnt + 1;
@@ -203,8 +203,8 @@
             else begin
                 current_abs2 = current2;
             end
-            //step_clock <= step_clock + 1;
-            //step <= step_clock[1]; //10
+            step_clock <= step_clock + 1;
+            step <= step_clock[10];
             analog_cmp1 <= (current_abs1[11:0] >= target_current1[11:0]); // compare unsigned
             analog_cmp2 <= (current_abs2[11:0] >= target_current2[11:0]);
             if (cnt <= 20'h4CA9) begin