fixes for sim

verilog/dv/caravel/user_proj_example/io_ports/Makefile

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/Makefile b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
index e19cd5e..2f91b86 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/Makefile
+++ b/verilog/dv/caravel/user_proj_example/io_ports/Makefile
@@ -26,8 +26,8 @@
 	-o $@ $<
 else
 	iverilog -DFUNCTIONAL -DSIM -DGL -I $(BEHAVIOURAL_MODELS) -I $(RAPCORES_PATH)/boards \
-	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
- 	-I $(RAPCORES_PATH)/testbench \
+	-I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) -I $(VERILOG_PATH) -I $(RAPCORES_PATH)/.. -I $(RAPCORES_PATH)/src \
+ 	-I $(RAPCORES_PATH)/testbench -I $(RAPCORES_PATH)/boards \
 	$< -o $@
 endif
 # MERGE: -I $(VERILOG_PATH) maybe needed for GL

verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v

diff --git a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
index ad1ddee..d0af590 100644
--- a/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
+++ b/verilog/dv/caravel/user_proj_example/io_ports/io_ports_tb.v
@@ -5,7 +5,7 @@
 //`define USE_POWER_PINS
 
 `ifdef GL
-  `include "gl/rapcore.v"
+  `include "gl/rapcores.v"
 `else
   `include "rapcores.v"
   `include "defines.v"