power attempt

caravel.sh

diff --git a/caravel.sh b/caravel.sh
index f5237a5..1fa93ee 100755
--- a/caravel.sh
+++ b/caravel.sh
@@ -8,6 +8,6 @@
 echo $PDK_ROOT
 echo $OPENLANE_ROOT
 cd openlane
-time make rapcore user_project_wrapper OPENLANE_IMAGE_NAME=openlane:rc6 2>&1 | tee raprc6.log
+time make rapcores user_project_wrapper OPENLANE_IMAGE_NAME=openlane:rc6 2>&1 | tee raprc6tk.log
 #cd ../
 #make ship

openlane/rapcores/config.tcl

diff --git a/openlane/rapcores/config.tcl b/openlane/rapcores/config.tcl
index 5dc2cc0..2d79ca0 100644
--- a/openlane/rapcores/config.tcl
+++ b/openlane/rapcores/config.tcl
@@ -23,7 +23,7 @@
         $script_dir/../../rapcores/src/microstepper/mytimer_8.v \
         $script_dir/../../rapcores/src/microstepper/mytimer_10.v \
         $script_dir/../../rapcores/src/rapcore.v \
-        $script_dir/../../verilog/rtl/rapcore_caravel.v"
+        $script_dir/../../verilog/rtl/rapcores.v"
 
 set ::env(CLOCK_PORT) "wb_clk_i"
 set ::env(CLOCK_PERIOD) "15"
@@ -42,8 +42,8 @@
 
 # We try to set the die size instead
 #set ::env(PL_BASIC_PLACEMENT) 40
-set ::env(PL_TARGET_DENSITY) 0.41
-set ::env(CELL_PAD) 0
+#set ::env(PL_TARGET_DENSITY) 0.41
+#set ::env(CELL_PAD) 0
 
 
 # Routing
@@ -57,16 +57,16 @@
 set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
 
 # block met5 with obstruction
-set ::env(GLB_RT_OBS) "met5 0 0 800 800"
+set ::env(GLB_RT_OBS) "met5 0 0 1000 1000"
+set ::env(GLB_RT_MAXLAYER) 5
 
-set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
-set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
+set ::env(FP_PDN_LOWER_LAYER) met1
+set ::env(FP_PDN_UPPER_LAYER) met4
 
-set ::env(FP_PDN_LOWER_LAYER) met4
-set ::env(FP_PDN_UPPER_LAYER) met5
+set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
 
-#set ::env(VDD_PIN) vccd1
-#set ::env(GND_PIN) vssd1
+set ::env(VDD_PIN) vccd1
+set ::env(GND_PIN) vssd1
 #set ::env(FP_PDN_VOFFSET) "14"
 #set ::env(FP_PDN_VPITCH) "180"
 #set ::env(FP_PDN_HOFFSET) "14"